1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * max98088.h -- MAX98088 ALSA SoC Audio driver 4 * 5 * Copyright 2010 Maxim Integrated Products 6 */ 7 8 #ifndef _MAX98088_H 9 #define _MAX98088_H 10 11 /* 12 * MAX98088 Registers Definition 13 */ 14 #define M98088_REG_00_IRQ_STATUS 0x00 15 #define M98088_REG_01_MIC_STATUS 0x01 16 #define M98088_REG_02_JACK_STATUS 0x02 17 #define M98088_REG_03_BATTERY_VOLTAGE 0x03 18 #define M98088_REG_0F_IRQ_ENABLE 0x0F 19 #define M98088_REG_10_SYS_CLK 0x10 20 #define M98088_REG_11_DAI1_CLKMODE 0x11 21 #define M98088_REG_12_DAI1_CLKCFG_HI 0x12 22 #define M98088_REG_13_DAI1_CLKCFG_LO 0x13 23 #define M98088_REG_14_DAI1_FORMAT 0x14 24 #define M98088_REG_15_DAI1_CLOCK 0x15 25 #define M98088_REG_16_DAI1_IOCFG 0x16 26 #define M98088_REG_17_DAI1_TDM 0x17 27 #define M98088_REG_18_DAI1_FILTERS 0x18 28 #define M98088_REG_19_DAI2_CLKMODE 0x19 29 #define M98088_REG_1A_DAI2_CLKCFG_HI 0x1A 30 #define M98088_REG_1B_DAI2_CLKCFG_LO 0x1B 31 #define M98088_REG_1C_DAI2_FORMAT 0x1C 32 #define M98088_REG_1D_DAI2_CLOCK 0x1D 33 #define M98088_REG_1E_DAI2_IOCFG 0x1E 34 #define M98088_REG_1F_DAI2_TDM 0x1F 35 #define M98088_REG_20_DAI2_FILTERS 0x20 36 #define M98088_REG_21_SRC 0x21 37 #define M98088_REG_22_MIX_DAC 0x22 38 #define M98088_REG_23_MIX_ADC_LEFT 0x23 39 #define M98088_REG_24_MIX_ADC_RIGHT 0x24 40 #define M98088_REG_25_MIX_HP_LEFT 0x25 41 #define M98088_REG_26_MIX_HP_RIGHT 0x26 42 #define M98088_REG_27_MIX_HP_CNTL 0x27 43 #define M98088_REG_28_MIX_REC_LEFT 0x28 44 #define M98088_REG_29_MIX_REC_RIGHT 0x29 45 #define M98088_REG_2A_MIC_REC_CNTL 0x2A 46 #define M98088_REG_2B_MIX_SPK_LEFT 0x2B 47 #define M98088_REG_2C_MIX_SPK_RIGHT 0x2C 48 #define M98088_REG_2D_MIX_SPK_CNTL 0x2D 49 #define M98088_REG_2E_LVL_SIDETONE 0x2E 50 #define M98088_REG_2F_LVL_DAI1_PLAY 0x2F 51 #define M98088_REG_30_LVL_DAI1_PLAY_EQ 0x30 52 #define M98088_REG_31_LVL_DAI2_PLAY 0x31 53 #define M98088_REG_32_LVL_DAI2_PLAY_EQ 0x32 54 #define M98088_REG_33_LVL_ADC_L 0x33 55 #define M98088_REG_34_LVL_ADC_R 0x34 56 #define M98088_REG_35_LVL_MIC1 0x35 57 #define M98088_REG_36_LVL_MIC2 0x36 58 #define M98088_REG_37_LVL_INA 0x37 59 #define M98088_REG_38_LVL_INB 0x38 60 #define M98088_REG_39_LVL_HP_L 0x39 61 #define M98088_REG_3A_LVL_HP_R 0x3A 62 #define M98088_REG_3B_LVL_REC_L 0x3B 63 #define M98088_REG_3C_LVL_REC_R 0x3C 64 #define M98088_REG_3D_LVL_SPK_L 0x3D 65 #define M98088_REG_3E_LVL_SPK_R 0x3E 66 #define M98088_REG_3F_MICAGC_CFG 0x3F 67 #define M98088_REG_40_MICAGC_THRESH 0x40 68 #define M98088_REG_41_SPKDHP 0x41 69 #define M98088_REG_42_SPKDHP_THRESH 0x42 70 #define M98088_REG_43_SPKALC_COMP 0x43 71 #define M98088_REG_44_PWRLMT_CFG 0x44 72 #define M98088_REG_45_PWRLMT_TIME 0x45 73 #define M98088_REG_46_THDLMT_CFG 0x46 74 #define M98088_REG_47_CFG_AUDIO_IN 0x47 75 #define M98088_REG_48_CFG_MIC 0x48 76 #define M98088_REG_49_CFG_LEVEL 0x49 77 #define M98088_REG_4A_CFG_BYPASS 0x4A 78 #define M98088_REG_4B_CFG_JACKDET 0x4B 79 #define M98088_REG_4C_PWR_EN_IN 0x4C 80 #define M98088_REG_4D_PWR_EN_OUT 0x4D 81 #define M98088_REG_4E_BIAS_CNTL 0x4E 82 #define M98088_REG_4F_DAC_BIAS1 0x4F 83 #define M98088_REG_50_DAC_BIAS2 0x50 84 #define M98088_REG_51_PWR_SYS 0x51 85 #define M98088_REG_52_DAI1_EQ_BASE 0x52 86 #define M98088_REG_84_DAI2_EQ_BASE 0x84 87 #define M98088_REG_B6_DAI1_BIQUAD_BASE 0xB6 88 #define M98088_REG_C0_DAI2_BIQUAD_BASE 0xC0 89 #define M98088_REG_FF_REV_ID 0xFF 90 91 #define M98088_REG_CNT (0xFF+1) 92 93 /* MAX98088 Registers Bit Fields */ 94 95 /* M98088_REG_11_DAI1_CLKMODE, M98088_REG_19_DAI2_CLKMODE */ 96 #define M98088_CLKMODE_MASK 0xFF 97 98 /* M98088_REG_14_DAI1_FORMAT, M98088_REG_1C_DAI2_FORMAT */ 99 #define M98088_DAI_MAS (1<<7) 100 #define M98088_DAI_WCI (1<<6) 101 #define M98088_DAI_BCI (1<<5) 102 #define M98088_DAI_DLY (1<<4) 103 #define M98088_DAI_TDM (1<<2) 104 #define M98088_DAI_FSW (1<<1) 105 #define M98088_DAI_WS (1<<0) 106 107 /* M98088_REG_15_DAI1_CLOCK, M98088_REG_1D_DAI2_CLOCK */ 108 #define M98088_DAI_BSEL64 (1<<0) 109 #define M98088_DAI_OSR64 (1<<6) 110 111 /* M98088_REG_16_DAI1_IOCFG, M98088_REG_1E_DAI2_IOCFG */ 112 #define M98088_S1NORMAL (1<<6) 113 #define M98088_S2NORMAL (2<<6) 114 #define M98088_SDATA (3<<0) 115 116 /* M98088_REG_18_DAI1_FILTERS, M98088_REG_20_DAI2_FILTERS */ 117 #define M98088_DAI_DHF (1<<3) 118 119 /* M98088_REG_22_MIX_DAC */ 120 #define M98088_DAI1L_TO_DACL (1<<7) 121 #define M98088_DAI1R_TO_DACL (1<<6) 122 #define M98088_DAI2L_TO_DACL (1<<5) 123 #define M98088_DAI2R_TO_DACL (1<<4) 124 #define M98088_DAI1L_TO_DACR (1<<3) 125 #define M98088_DAI1R_TO_DACR (1<<2) 126 #define M98088_DAI2L_TO_DACR (1<<1) 127 #define M98088_DAI2R_TO_DACR (1<<0) 128 129 /* M98088_REG_2A_MIC_REC_CNTL */ 130 #define M98088_REC_LINEMODE (1<<7) 131 #define M98088_REC_LINEMODE_MASK (1<<7) 132 133 /* M98088_REG_2D_MIX_SPK_CNTL */ 134 #define M98088_MIX_SPKR_GAIN_MASK (3<<2) 135 #define M98088_MIX_SPKR_GAIN_SHIFT 2 136 #define M98088_MIX_SPKL_GAIN_MASK (3<<0) 137 #define M98088_MIX_SPKL_GAIN_SHIFT 0 138 139 /* M98088_REG_2F_LVL_DAI1_PLAY, M98088_REG_31_LVL_DAI2_PLAY */ 140 #define M98088_DAI_MUTE (1<<7) 141 #define M98088_DAI_MUTE_MASK (1<<7) 142 #define M98088_DAI_VOICE_GAIN_MASK (3<<4) 143 #define M98088_DAI_ATTENUATION_MASK (0xF<<0) 144 #define M98088_DAI_ATTENUATION_SHIFT 0 145 146 /* M98088_REG_35_LVL_MIC1, M98088_REG_36_LVL_MIC2 */ 147 #define M98088_MICPRE_MASK (3<<5) 148 #define M98088_MICPRE_SHIFT 5 149 150 /* M98088_REG_3A_LVL_HP_R */ 151 #define M98088_HP_MUTE (1<<7) 152 153 /* M98088_REG_3C_LVL_REC_R */ 154 #define M98088_REC_MUTE (1<<7) 155 156 /* M98088_REG_3E_LVL_SPK_R */ 157 #define M98088_SP_MUTE (1<<7) 158 159 /* M98088_REG_48_CFG_MIC */ 160 #define M98088_EXTMIC_MASK (3<<0) 161 #define M98088_DIGMIC_L (1<<5) 162 #define M98088_DIGMIC_R (1<<4) 163 164 /* M98088_REG_49_CFG_LEVEL */ 165 #define M98088_VSEN (1<<6) 166 #define M98088_ZDEN (1<<5) 167 #define M98088_EQ2EN (1<<1) 168 #define M98088_EQ1EN (1<<0) 169 170 /* M98088_REG_4C_PWR_EN_IN */ 171 #define M98088_INAEN (1<<7) 172 #define M98088_INBEN (1<<6) 173 #define M98088_MBEN (1<<3) 174 #define M98088_ADLEN (1<<1) 175 #define M98088_ADREN (1<<0) 176 177 /* M98088_REG_4D_PWR_EN_OUT */ 178 #define M98088_HPLEN (1<<7) 179 #define M98088_HPREN (1<<6) 180 #define M98088_HPEN ((1<<7)|(1<<6)) 181 #define M98088_SPLEN (1<<5) 182 #define M98088_SPREN (1<<4) 183 #define M98088_RECEN (1<<3) 184 #define M98088_DALEN (1<<1) 185 #define M98088_DAREN (1<<0) 186 187 /* M98088_REG_51_PWR_SYS */ 188 #define M98088_SHDNRUN (1<<7) 189 #define M98088_PERFMODE (1<<3) 190 #define M98088_HPPLYBACK (1<<2) 191 #define M98088_PWRSV8K (1<<1) 192 #define M98088_PWRSV (1<<0) 193 194 /* Line inputs */ 195 #define LINE_INA 0 196 #define LINE_INB 1 197 198 #define M98088_COEFS_PER_BAND 5 199 200 #define M98088_BYTE1(w) ((w >> 8) & 0xff) 201 #define M98088_BYTE0(w) (w & 0xff) 202 203 #endif 204