1 /* 2 * max98088.c -- MAX98088 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/clk.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <linux/slab.h> 27 #include <asm/div64.h> 28 #include <sound/max98088.h> 29 #include "max98088.h" 30 31 enum max98088_type { 32 MAX98088, 33 MAX98089, 34 }; 35 36 struct max98088_cdata { 37 unsigned int rate; 38 unsigned int fmt; 39 int eq_sel; 40 }; 41 42 struct max98088_priv { 43 struct regmap *regmap; 44 enum max98088_type devtype; 45 struct max98088_pdata *pdata; 46 struct clk *mclk; 47 unsigned int sysclk; 48 struct max98088_cdata dai[2]; 49 int eq_textcnt; 50 const char **eq_texts; 51 struct soc_enum eq_enum; 52 u8 ina_state; 53 u8 inb_state; 54 unsigned int ex_mode; 55 unsigned int digmic; 56 unsigned int mic1pre; 57 unsigned int mic2pre; 58 unsigned int extmic_mode; 59 }; 60 61 static const struct reg_default max98088_reg[] = { 62 { 0xf, 0x00 }, /* 0F interrupt enable */ 63 64 { 0x10, 0x00 }, /* 10 master clock */ 65 { 0x11, 0x00 }, /* 11 DAI1 clock mode */ 66 { 0x12, 0x00 }, /* 12 DAI1 clock control */ 67 { 0x13, 0x00 }, /* 13 DAI1 clock control */ 68 { 0x14, 0x00 }, /* 14 DAI1 format */ 69 { 0x15, 0x00 }, /* 15 DAI1 clock */ 70 { 0x16, 0x00 }, /* 16 DAI1 config */ 71 { 0x17, 0x00 }, /* 17 DAI1 TDM */ 72 { 0x18, 0x00 }, /* 18 DAI1 filters */ 73 { 0x19, 0x00 }, /* 19 DAI2 clock mode */ 74 { 0x1a, 0x00 }, /* 1A DAI2 clock control */ 75 { 0x1b, 0x00 }, /* 1B DAI2 clock control */ 76 { 0x1c, 0x00 }, /* 1C DAI2 format */ 77 { 0x1d, 0x00 }, /* 1D DAI2 clock */ 78 { 0x1e, 0x00 }, /* 1E DAI2 config */ 79 { 0x1f, 0x00 }, /* 1F DAI2 TDM */ 80 81 { 0x20, 0x00 }, /* 20 DAI2 filters */ 82 { 0x21, 0x00 }, /* 21 data config */ 83 { 0x22, 0x00 }, /* 22 DAC mixer */ 84 { 0x23, 0x00 }, /* 23 left ADC mixer */ 85 { 0x24, 0x00 }, /* 24 right ADC mixer */ 86 { 0x25, 0x00 }, /* 25 left HP mixer */ 87 { 0x26, 0x00 }, /* 26 right HP mixer */ 88 { 0x27, 0x00 }, /* 27 HP control */ 89 { 0x28, 0x00 }, /* 28 left REC mixer */ 90 { 0x29, 0x00 }, /* 29 right REC mixer */ 91 { 0x2a, 0x00 }, /* 2A REC control */ 92 { 0x2b, 0x00 }, /* 2B left SPK mixer */ 93 { 0x2c, 0x00 }, /* 2C right SPK mixer */ 94 { 0x2d, 0x00 }, /* 2D SPK control */ 95 { 0x2e, 0x00 }, /* 2E sidetone */ 96 { 0x2f, 0x00 }, /* 2F DAI1 playback level */ 97 98 { 0x30, 0x00 }, /* 30 DAI1 playback level */ 99 { 0x31, 0x00 }, /* 31 DAI2 playback level */ 100 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */ 101 { 0x33, 0x00 }, /* 33 left ADC level */ 102 { 0x34, 0x00 }, /* 34 right ADC level */ 103 { 0x35, 0x00 }, /* 35 MIC1 level */ 104 { 0x36, 0x00 }, /* 36 MIC2 level */ 105 { 0x37, 0x00 }, /* 37 INA level */ 106 { 0x38, 0x00 }, /* 38 INB level */ 107 { 0x39, 0x00 }, /* 39 left HP volume */ 108 { 0x3a, 0x00 }, /* 3A right HP volume */ 109 { 0x3b, 0x00 }, /* 3B left REC volume */ 110 { 0x3c, 0x00 }, /* 3C right REC volume */ 111 { 0x3d, 0x00 }, /* 3D left SPK volume */ 112 { 0x3e, 0x00 }, /* 3E right SPK volume */ 113 { 0x3f, 0x00 }, /* 3F MIC config */ 114 115 { 0x40, 0x00 }, /* 40 MIC threshold */ 116 { 0x41, 0x00 }, /* 41 excursion limiter filter */ 117 { 0x42, 0x00 }, /* 42 excursion limiter threshold */ 118 { 0x43, 0x00 }, /* 43 ALC */ 119 { 0x44, 0x00 }, /* 44 power limiter threshold */ 120 { 0x45, 0x00 }, /* 45 power limiter config */ 121 { 0x46, 0x00 }, /* 46 distortion limiter config */ 122 { 0x47, 0x00 }, /* 47 audio input */ 123 { 0x48, 0x00 }, /* 48 microphone */ 124 { 0x49, 0x00 }, /* 49 level control */ 125 { 0x4a, 0x00 }, /* 4A bypass switches */ 126 { 0x4b, 0x00 }, /* 4B jack detect */ 127 { 0x4c, 0x00 }, /* 4C input enable */ 128 { 0x4d, 0x00 }, /* 4D output enable */ 129 { 0x4e, 0xF0 }, /* 4E bias control */ 130 { 0x4f, 0x00 }, /* 4F DAC power */ 131 132 { 0x50, 0x0F }, /* 50 DAC power */ 133 { 0x51, 0x00 }, /* 51 system */ 134 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */ 135 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */ 136 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */ 137 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */ 138 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */ 139 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */ 140 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */ 141 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */ 142 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */ 143 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */ 144 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */ 145 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */ 146 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */ 147 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */ 148 149 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */ 150 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */ 151 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */ 152 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */ 153 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */ 154 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */ 155 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */ 156 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */ 157 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */ 158 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */ 159 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */ 160 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */ 161 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */ 162 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */ 163 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */ 164 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */ 165 166 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */ 167 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */ 168 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */ 169 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */ 170 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */ 171 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */ 172 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */ 173 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */ 174 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */ 175 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */ 176 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */ 177 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */ 178 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */ 179 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */ 180 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */ 181 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */ 182 183 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */ 184 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */ 185 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */ 186 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */ 187 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */ 188 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */ 189 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */ 190 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */ 191 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */ 192 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */ 193 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */ 194 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */ 195 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */ 196 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */ 197 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */ 198 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */ 199 200 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */ 201 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */ 202 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */ 203 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */ 204 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */ 205 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */ 206 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */ 207 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */ 208 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */ 209 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */ 210 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */ 211 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */ 212 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */ 213 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */ 214 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */ 215 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */ 216 217 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */ 218 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */ 219 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */ 220 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */ 221 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */ 222 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */ 223 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */ 224 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */ 225 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */ 226 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */ 227 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */ 228 { 0xab, 0x00 }, /* AB DAI2 EQ4 */ 229 { 0xac, 0x00 }, /* AC DAI2 EQ5 */ 230 { 0xad, 0x00 }, /* AD DAI2 EQ5 */ 231 { 0xae, 0x00 }, /* AE DAI2 EQ5 */ 232 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */ 233 234 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */ 235 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */ 236 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */ 237 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */ 238 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */ 239 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */ 240 { 0xb6, 0x00 }, /* B6 DAI1 biquad */ 241 { 0xb7, 0x00 }, /* B7 DAI1 biquad */ 242 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */ 243 { 0xb9, 0x00 }, /* B9 DAI1 biquad */ 244 { 0xba, 0x00 }, /* BA DAI1 biquad */ 245 { 0xbb, 0x00 }, /* BB DAI1 biquad */ 246 { 0xbc, 0x00 }, /* BC DAI1 biquad */ 247 { 0xbd, 0x00 }, /* BD DAI1 biquad */ 248 { 0xbe, 0x00 }, /* BE DAI1 biquad */ 249 { 0xbf, 0x00 }, /* BF DAI1 biquad */ 250 251 { 0xc0, 0x00 }, /* C0 DAI2 biquad */ 252 { 0xc1, 0x00 }, /* C1 DAI2 biquad */ 253 { 0xc2, 0x00 }, /* C2 DAI2 biquad */ 254 { 0xc3, 0x00 }, /* C3 DAI2 biquad */ 255 { 0xc4, 0x00 }, /* C4 DAI2 biquad */ 256 { 0xc5, 0x00 }, /* C5 DAI2 biquad */ 257 { 0xc6, 0x00 }, /* C6 DAI2 biquad */ 258 { 0xc7, 0x00 }, /* C7 DAI2 biquad */ 259 { 0xc8, 0x00 }, /* C8 DAI2 biquad */ 260 { 0xc9, 0x00 }, /* C9 DAI2 biquad */ 261 }; 262 263 static bool max98088_readable_register(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case M98088_REG_00_IRQ_STATUS ... 0xC9: 267 case M98088_REG_FF_REV_ID: 268 return true; 269 default: 270 return false; 271 } 272 } 273 274 static bool max98088_writeable_register(struct device *dev, unsigned int reg) 275 { 276 switch (reg) { 277 case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9: 278 return true; 279 default: 280 return false; 281 } 282 } 283 284 static bool max98088_volatile_register(struct device *dev, unsigned int reg) 285 { 286 switch (reg) { 287 case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE: 288 case M98088_REG_FF_REV_ID: 289 return true; 290 default: 291 return false; 292 } 293 } 294 295 static const struct regmap_config max98088_regmap = { 296 .reg_bits = 8, 297 .val_bits = 8, 298 299 .readable_reg = max98088_readable_register, 300 .writeable_reg = max98088_writeable_register, 301 .volatile_reg = max98088_volatile_register, 302 .max_register = 0xff, 303 304 .reg_defaults = max98088_reg, 305 .num_reg_defaults = ARRAY_SIZE(max98088_reg), 306 .cache_type = REGCACHE_RBTREE, 307 }; 308 309 /* 310 * Load equalizer DSP coefficient configurations registers 311 */ 312 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai, 313 unsigned int band, u16 *coefs) 314 { 315 unsigned int eq_reg; 316 unsigned int i; 317 318 if (WARN_ON(band > 4) || 319 WARN_ON(dai > 1)) 320 return; 321 322 /* Load the base register address */ 323 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 324 325 /* Add the band address offset, note adjustment for word address */ 326 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 327 328 /* Step through the registers and coefs */ 329 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 330 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); 331 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); 332 } 333 } 334 335 /* 336 * Excursion limiter modes 337 */ 338 static const char *max98088_exmode_texts[] = { 339 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 340 "400-600Hz", "400-800Hz", 341 }; 342 343 static const unsigned int max98088_exmode_values[] = { 344 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 345 }; 346 347 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum, 348 M98088_REG_41_SPKDHP, 0, 127, 349 max98088_exmode_texts, 350 max98088_exmode_values); 351 352 static const char *max98088_ex_thresh[] = { /* volts PP */ 353 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 354 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum, 355 M98088_REG_42_SPKDHP_THRESH, 0, 356 max98088_ex_thresh); 357 358 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 359 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum, 360 M98088_REG_18_DAI1_FILTERS, 7, 361 max98088_fltr_mode); 362 363 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 364 365 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum, 366 M98088_REG_48_CFG_MIC, 0, 367 max98088_extmic_text); 368 369 static const struct snd_kcontrol_new max98088_extmic_mux = 370 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 371 372 static const char *max98088_dai1_fltr[] = { 373 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 374 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 375 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum, 376 M98088_REG_18_DAI1_FILTERS, 0, 377 max98088_dai1_fltr); 378 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum, 379 M98088_REG_18_DAI1_FILTERS, 4, 380 max98088_dai1_fltr); 381 382 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 383 struct snd_ctl_elem_value *ucontrol) 384 { 385 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 386 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 387 unsigned int sel = ucontrol->value.integer.value[0]; 388 389 max98088->mic1pre = sel; 390 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 391 (1+sel)<<M98088_MICPRE_SHIFT); 392 393 return 0; 394 } 395 396 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 397 struct snd_ctl_elem_value *ucontrol) 398 { 399 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 400 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 401 402 ucontrol->value.integer.value[0] = max98088->mic1pre; 403 return 0; 404 } 405 406 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408 { 409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 410 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 411 unsigned int sel = ucontrol->value.integer.value[0]; 412 413 max98088->mic2pre = sel; 414 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 415 (1+sel)<<M98088_MICPRE_SHIFT); 416 417 return 0; 418 } 419 420 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 421 struct snd_ctl_elem_value *ucontrol) 422 { 423 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 424 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 425 426 ucontrol->value.integer.value[0] = max98088->mic2pre; 427 return 0; 428 } 429 430 static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv, 431 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 432 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 433 ); 434 435 static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv, 436 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 437 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 438 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 439 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 440 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 441 ); 442 443 static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv, 444 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 445 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 446 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 447 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 448 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 449 ); 450 451 static const struct snd_kcontrol_new max98088_snd_controls[] = { 452 453 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L, 454 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv), 455 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 456 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv), 457 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L, 458 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv), 459 460 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 461 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 462 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 463 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 464 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 465 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 466 467 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 468 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 469 470 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 471 M98088_REG_35_LVL_MIC1, 5, 2, 0, 472 max98088_mic1pre_get, max98088_mic1pre_set, 473 max98088_micboost_tlv), 474 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 475 M98088_REG_36_LVL_MIC2, 5, 2, 0, 476 max98088_mic2pre_get, max98088_mic2pre_set, 477 max98088_micboost_tlv), 478 479 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 480 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 481 482 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 483 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 484 485 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 486 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 487 488 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 489 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 490 491 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum), 492 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 493 494 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 495 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 496 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 497 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 498 0, 1, 0), 499 500 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 501 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 502 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 503 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 504 505 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 506 4, 15, 0), 507 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 508 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 509 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 510 511 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 512 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 513 }; 514 515 /* Left speaker mixer switch */ 516 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 517 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 518 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 519 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 520 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 521 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 522 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 523 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 524 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 525 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 526 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 527 }; 528 529 /* Right speaker mixer switch */ 530 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 531 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 532 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 533 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 534 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 535 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 536 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 537 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 538 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 539 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 540 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 541 }; 542 543 /* Left headphone mixer switch */ 544 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 545 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 546 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 547 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 548 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 549 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 550 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 551 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 552 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 553 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 554 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 555 }; 556 557 /* Right headphone mixer switch */ 558 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 559 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 560 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 561 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 562 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 563 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 564 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 565 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 566 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 567 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 568 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 569 }; 570 571 /* Left earpiece/receiver mixer switch */ 572 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 573 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 574 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 575 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 576 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 577 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 578 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 579 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 580 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 581 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 582 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 583 }; 584 585 /* Right earpiece/receiver mixer switch */ 586 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 587 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 588 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 589 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 590 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 591 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 592 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 593 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 594 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 595 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 596 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 597 }; 598 599 /* Left ADC mixer switch */ 600 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 601 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 602 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 603 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 604 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 605 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 606 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 607 }; 608 609 /* Right ADC mixer switch */ 610 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 611 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 612 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 613 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 614 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 615 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 616 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 617 }; 618 619 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 620 struct snd_kcontrol *kcontrol, int event) 621 { 622 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 623 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 624 625 switch (event) { 626 case SND_SOC_DAPM_POST_PMU: 627 if (w->reg == M98088_REG_35_LVL_MIC1) { 628 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 629 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 630 } else { 631 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 632 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 633 } 634 break; 635 case SND_SOC_DAPM_POST_PMD: 636 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0); 637 break; 638 default: 639 return -EINVAL; 640 } 641 642 return 0; 643 } 644 645 /* 646 * The line inputs are 2-channel stereo inputs with the left 647 * and right channels sharing a common PGA power control signal. 648 */ 649 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 650 int event, int line, u8 channel) 651 { 652 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 653 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 654 u8 *state; 655 656 if (WARN_ON(!(channel == 1 || channel == 2))) 657 return -EINVAL; 658 659 switch (line) { 660 case LINE_INA: 661 state = &max98088->ina_state; 662 break; 663 case LINE_INB: 664 state = &max98088->inb_state; 665 break; 666 default: 667 return -EINVAL; 668 } 669 670 switch (event) { 671 case SND_SOC_DAPM_POST_PMU: 672 *state |= channel; 673 snd_soc_component_update_bits(component, w->reg, 674 (1 << w->shift), (1 << w->shift)); 675 break; 676 case SND_SOC_DAPM_POST_PMD: 677 *state &= ~channel; 678 if (*state == 0) { 679 snd_soc_component_update_bits(component, w->reg, 680 (1 << w->shift), 0); 681 } 682 break; 683 default: 684 return -EINVAL; 685 } 686 687 return 0; 688 } 689 690 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 691 struct snd_kcontrol *k, int event) 692 { 693 return max98088_line_pga(w, event, LINE_INA, 1); 694 } 695 696 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 697 struct snd_kcontrol *k, int event) 698 { 699 return max98088_line_pga(w, event, LINE_INA, 2); 700 } 701 702 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 703 struct snd_kcontrol *k, int event) 704 { 705 return max98088_line_pga(w, event, LINE_INB, 1); 706 } 707 708 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 709 struct snd_kcontrol *k, int event) 710 { 711 return max98088_line_pga(w, event, LINE_INB, 2); 712 } 713 714 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 715 716 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 717 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 718 719 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 720 M98088_REG_4D_PWR_EN_OUT, 1, 0), 721 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 722 M98088_REG_4D_PWR_EN_OUT, 0, 0), 723 SND_SOC_DAPM_DAC("DACL2", "Aux Playback", 724 M98088_REG_4D_PWR_EN_OUT, 1, 0), 725 SND_SOC_DAPM_DAC("DACR2", "Aux Playback", 726 M98088_REG_4D_PWR_EN_OUT, 0, 0), 727 728 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 729 7, 0, NULL, 0), 730 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 731 6, 0, NULL, 0), 732 733 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 734 5, 0, NULL, 0), 735 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 736 4, 0, NULL, 0), 737 738 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 739 3, 0, NULL, 0), 740 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 741 2, 0, NULL, 0), 742 743 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 744 &max98088_extmic_mux), 745 746 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 747 &max98088_left_hp_mixer_controls[0], 748 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 749 750 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 751 &max98088_right_hp_mixer_controls[0], 752 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 753 754 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 755 &max98088_left_speaker_mixer_controls[0], 756 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 757 758 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 759 &max98088_right_speaker_mixer_controls[0], 760 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 761 762 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 763 &max98088_left_rec_mixer_controls[0], 764 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 765 766 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 767 &max98088_right_rec_mixer_controls[0], 768 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 769 770 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 771 &max98088_left_ADC_mixer_controls[0], 772 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 773 774 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 775 &max98088_right_ADC_mixer_controls[0], 776 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 777 778 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 779 5, 0, NULL, 0, max98088_mic_event, 780 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 781 782 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 783 5, 0, NULL, 0, max98088_mic_event, 784 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 785 786 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 787 7, 0, NULL, 0, max98088_pga_ina1_event, 788 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 789 790 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 791 7, 0, NULL, 0, max98088_pga_ina2_event, 792 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 793 794 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 795 6, 0, NULL, 0, max98088_pga_inb1_event, 796 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 797 798 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 799 6, 0, NULL, 0, max98088_pga_inb2_event, 800 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 801 802 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 803 804 SND_SOC_DAPM_OUTPUT("HPL"), 805 SND_SOC_DAPM_OUTPUT("HPR"), 806 SND_SOC_DAPM_OUTPUT("SPKL"), 807 SND_SOC_DAPM_OUTPUT("SPKR"), 808 SND_SOC_DAPM_OUTPUT("RECL"), 809 SND_SOC_DAPM_OUTPUT("RECR"), 810 811 SND_SOC_DAPM_INPUT("MIC1"), 812 SND_SOC_DAPM_INPUT("MIC2"), 813 SND_SOC_DAPM_INPUT("INA1"), 814 SND_SOC_DAPM_INPUT("INA2"), 815 SND_SOC_DAPM_INPUT("INB1"), 816 SND_SOC_DAPM_INPUT("INB2"), 817 }; 818 819 static const struct snd_soc_dapm_route max98088_audio_map[] = { 820 /* Left headphone output mixer */ 821 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"}, 822 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"}, 823 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"}, 824 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"}, 825 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 826 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 827 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 828 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 829 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 830 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 831 832 /* Right headphone output mixer */ 833 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"}, 834 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" }, 835 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"}, 836 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"}, 837 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 838 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 839 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 840 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 841 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 842 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 843 844 /* Left speaker output mixer */ 845 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"}, 846 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"}, 847 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"}, 848 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"}, 849 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 850 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 851 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 852 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 853 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 854 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 855 856 /* Right speaker output mixer */ 857 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"}, 858 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"}, 859 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"}, 860 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"}, 861 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 862 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 863 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 864 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 865 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 866 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 867 868 /* Earpiece/Receiver output mixer */ 869 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"}, 870 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"}, 871 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"}, 872 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"}, 873 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 874 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 875 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 876 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 877 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 878 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 879 880 /* Earpiece/Receiver output mixer */ 881 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"}, 882 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"}, 883 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"}, 884 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"}, 885 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 886 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 887 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 888 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 889 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 890 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 891 892 {"HP Left Out", NULL, "Left HP Mixer"}, 893 {"HP Right Out", NULL, "Right HP Mixer"}, 894 {"SPK Left Out", NULL, "Left SPK Mixer"}, 895 {"SPK Right Out", NULL, "Right SPK Mixer"}, 896 {"REC Left Out", NULL, "Left REC Mixer"}, 897 {"REC Right Out", NULL, "Right REC Mixer"}, 898 899 {"HPL", NULL, "HP Left Out"}, 900 {"HPR", NULL, "HP Right Out"}, 901 {"SPKL", NULL, "SPK Left Out"}, 902 {"SPKR", NULL, "SPK Right Out"}, 903 {"RECL", NULL, "REC Left Out"}, 904 {"RECR", NULL, "REC Right Out"}, 905 906 /* Left ADC input mixer */ 907 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 908 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 909 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 910 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 911 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 912 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 913 914 /* Right ADC input mixer */ 915 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 916 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 917 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 918 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 919 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 920 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 921 922 /* Inputs */ 923 {"ADCL", NULL, "Left ADC Mixer"}, 924 {"ADCR", NULL, "Right ADC Mixer"}, 925 {"INA1 Input", NULL, "INA1"}, 926 {"INA2 Input", NULL, "INA2"}, 927 {"INB1 Input", NULL, "INB1"}, 928 {"INB2 Input", NULL, "INB2"}, 929 {"MIC1 Input", NULL, "MIC1"}, 930 {"MIC2 Input", NULL, "MIC2"}, 931 }; 932 933 /* codec mclk clock divider coefficients */ 934 static const struct { 935 u32 rate; 936 u8 sr; 937 } rate_table[] = { 938 {8000, 0x10}, 939 {11025, 0x20}, 940 {16000, 0x30}, 941 {22050, 0x40}, 942 {24000, 0x50}, 943 {32000, 0x60}, 944 {44100, 0x70}, 945 {48000, 0x80}, 946 {88200, 0x90}, 947 {96000, 0xA0}, 948 }; 949 950 static inline int rate_value(int rate, u8 *value) 951 { 952 int i; 953 954 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 955 if (rate_table[i].rate >= rate) { 956 *value = rate_table[i].sr; 957 return 0; 958 } 959 } 960 *value = rate_table[0].sr; 961 return -EINVAL; 962 } 963 964 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 965 struct snd_pcm_hw_params *params, 966 struct snd_soc_dai *dai) 967 { 968 struct snd_soc_component *component = dai->component; 969 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 970 struct max98088_cdata *cdata; 971 unsigned long long ni; 972 unsigned int rate; 973 u8 regval; 974 975 cdata = &max98088->dai[0]; 976 977 rate = params_rate(params); 978 979 switch (params_width(params)) { 980 case 16: 981 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 982 M98088_DAI_WS, 0); 983 break; 984 case 24: 985 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 986 M98088_DAI_WS, M98088_DAI_WS); 987 break; 988 default: 989 return -EINVAL; 990 } 991 992 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 993 994 if (rate_value(rate, ®val)) 995 return -EINVAL; 996 997 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE, 998 M98088_CLKMODE_MASK, regval); 999 cdata->rate = rate; 1000 1001 /* Configure NI when operating as master */ 1002 if (snd_soc_component_read32(component, M98088_REG_14_DAI1_FORMAT) 1003 & M98088_DAI_MAS) { 1004 if (max98088->sysclk == 0) { 1005 dev_err(component->dev, "Invalid system clock frequency\n"); 1006 return -EINVAL; 1007 } 1008 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1009 * (unsigned long long int)rate; 1010 do_div(ni, (unsigned long long int)max98088->sysclk); 1011 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 1012 (ni >> 8) & 0x7F); 1013 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 1014 ni & 0xFF); 1015 } 1016 1017 /* Update sample rate mode */ 1018 if (rate < 50000) 1019 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 1020 M98088_DAI_DHF, 0); 1021 else 1022 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 1023 M98088_DAI_DHF, M98088_DAI_DHF); 1024 1025 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1026 M98088_SHDNRUN); 1027 1028 return 0; 1029 } 1030 1031 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1032 struct snd_pcm_hw_params *params, 1033 struct snd_soc_dai *dai) 1034 { 1035 struct snd_soc_component *component = dai->component; 1036 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1037 struct max98088_cdata *cdata; 1038 unsigned long long ni; 1039 unsigned int rate; 1040 u8 regval; 1041 1042 cdata = &max98088->dai[1]; 1043 1044 rate = params_rate(params); 1045 1046 switch (params_width(params)) { 1047 case 16: 1048 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1049 M98088_DAI_WS, 0); 1050 break; 1051 case 24: 1052 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1053 M98088_DAI_WS, M98088_DAI_WS); 1054 break; 1055 default: 1056 return -EINVAL; 1057 } 1058 1059 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1060 1061 if (rate_value(rate, ®val)) 1062 return -EINVAL; 1063 1064 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE, 1065 M98088_CLKMODE_MASK, regval); 1066 cdata->rate = rate; 1067 1068 /* Configure NI when operating as master */ 1069 if (snd_soc_component_read32(component, M98088_REG_1C_DAI2_FORMAT) 1070 & M98088_DAI_MAS) { 1071 if (max98088->sysclk == 0) { 1072 dev_err(component->dev, "Invalid system clock frequency\n"); 1073 return -EINVAL; 1074 } 1075 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1076 * (unsigned long long int)rate; 1077 do_div(ni, (unsigned long long int)max98088->sysclk); 1078 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1079 (ni >> 8) & 0x7F); 1080 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1081 ni & 0xFF); 1082 } 1083 1084 /* Update sample rate mode */ 1085 if (rate < 50000) 1086 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1087 M98088_DAI_DHF, 0); 1088 else 1089 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1090 M98088_DAI_DHF, M98088_DAI_DHF); 1091 1092 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1093 M98088_SHDNRUN); 1094 1095 return 0; 1096 } 1097 1098 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1099 int clk_id, unsigned int freq, int dir) 1100 { 1101 struct snd_soc_component *component = dai->component; 1102 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1103 1104 /* Requested clock frequency is already setup */ 1105 if (freq == max98088->sysclk) 1106 return 0; 1107 1108 if (!IS_ERR(max98088->mclk)) { 1109 freq = clk_round_rate(max98088->mclk, freq); 1110 clk_set_rate(max98088->mclk, freq); 1111 } 1112 1113 /* Setup clocks for slave mode, and using the PLL 1114 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1115 * 0x02 (when master clk is 20MHz to 30MHz).. 1116 */ 1117 if ((freq >= 10000000) && (freq < 20000000)) { 1118 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); 1119 } else if ((freq >= 20000000) && (freq < 30000000)) { 1120 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); 1121 } else { 1122 dev_err(component->dev, "Invalid master clock frequency\n"); 1123 return -EINVAL; 1124 } 1125 1126 if (snd_soc_component_read32(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1127 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1128 M98088_SHDNRUN, 0); 1129 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1130 M98088_SHDNRUN, M98088_SHDNRUN); 1131 } 1132 1133 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1134 1135 max98088->sysclk = freq; 1136 return 0; 1137 } 1138 1139 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1140 unsigned int fmt) 1141 { 1142 struct snd_soc_component *component = codec_dai->component; 1143 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1144 struct max98088_cdata *cdata; 1145 u8 reg15val; 1146 u8 reg14val = 0; 1147 1148 cdata = &max98088->dai[0]; 1149 1150 if (fmt != cdata->fmt) { 1151 cdata->fmt = fmt; 1152 1153 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1154 case SND_SOC_DAIFMT_CBS_CFS: 1155 /* Slave mode PLL */ 1156 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 1157 0x80); 1158 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 1159 0x00); 1160 break; 1161 case SND_SOC_DAIFMT_CBM_CFM: 1162 /* Set to master mode */ 1163 reg14val |= M98088_DAI_MAS; 1164 break; 1165 case SND_SOC_DAIFMT_CBS_CFM: 1166 case SND_SOC_DAIFMT_CBM_CFS: 1167 default: 1168 dev_err(component->dev, "Clock mode unsupported"); 1169 return -EINVAL; 1170 } 1171 1172 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1173 case SND_SOC_DAIFMT_I2S: 1174 reg14val |= M98088_DAI_DLY; 1175 break; 1176 case SND_SOC_DAIFMT_LEFT_J: 1177 break; 1178 default: 1179 return -EINVAL; 1180 } 1181 1182 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1183 case SND_SOC_DAIFMT_NB_NF: 1184 break; 1185 case SND_SOC_DAIFMT_NB_IF: 1186 reg14val |= M98088_DAI_WCI; 1187 break; 1188 case SND_SOC_DAIFMT_IB_NF: 1189 reg14val |= M98088_DAI_BCI; 1190 break; 1191 case SND_SOC_DAIFMT_IB_IF: 1192 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1193 break; 1194 default: 1195 return -EINVAL; 1196 } 1197 1198 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 1199 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1200 M98088_DAI_WCI, reg14val); 1201 1202 reg15val = M98088_DAI_BSEL64; 1203 if (max98088->digmic) 1204 reg15val |= M98088_DAI_OSR64; 1205 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val); 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1212 unsigned int fmt) 1213 { 1214 struct snd_soc_component *component = codec_dai->component; 1215 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1216 struct max98088_cdata *cdata; 1217 u8 reg1Cval = 0; 1218 1219 cdata = &max98088->dai[1]; 1220 1221 if (fmt != cdata->fmt) { 1222 cdata->fmt = fmt; 1223 1224 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1225 case SND_SOC_DAIFMT_CBS_CFS: 1226 /* Slave mode PLL */ 1227 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1228 0x80); 1229 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1230 0x00); 1231 break; 1232 case SND_SOC_DAIFMT_CBM_CFM: 1233 /* Set to master mode */ 1234 reg1Cval |= M98088_DAI_MAS; 1235 break; 1236 case SND_SOC_DAIFMT_CBS_CFM: 1237 case SND_SOC_DAIFMT_CBM_CFS: 1238 default: 1239 dev_err(component->dev, "Clock mode unsupported"); 1240 return -EINVAL; 1241 } 1242 1243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1244 case SND_SOC_DAIFMT_I2S: 1245 reg1Cval |= M98088_DAI_DLY; 1246 break; 1247 case SND_SOC_DAIFMT_LEFT_J: 1248 break; 1249 default: 1250 return -EINVAL; 1251 } 1252 1253 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1254 case SND_SOC_DAIFMT_NB_NF: 1255 break; 1256 case SND_SOC_DAIFMT_NB_IF: 1257 reg1Cval |= M98088_DAI_WCI; 1258 break; 1259 case SND_SOC_DAIFMT_IB_NF: 1260 reg1Cval |= M98088_DAI_BCI; 1261 break; 1262 case SND_SOC_DAIFMT_IB_IF: 1263 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1264 break; 1265 default: 1266 return -EINVAL; 1267 } 1268 1269 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1270 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1271 M98088_DAI_WCI, reg1Cval); 1272 1273 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK, 1274 M98088_DAI_BSEL64); 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1281 { 1282 struct snd_soc_component *component = codec_dai->component; 1283 int reg; 1284 1285 if (mute) 1286 reg = M98088_DAI_MUTE; 1287 else 1288 reg = 0; 1289 1290 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY, 1291 M98088_DAI_MUTE_MASK, reg); 1292 return 0; 1293 } 1294 1295 static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1296 { 1297 struct snd_soc_component *component = codec_dai->component; 1298 int reg; 1299 1300 if (mute) 1301 reg = M98088_DAI_MUTE; 1302 else 1303 reg = 0; 1304 1305 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY, 1306 M98088_DAI_MUTE_MASK, reg); 1307 return 0; 1308 } 1309 1310 static int max98088_set_bias_level(struct snd_soc_component *component, 1311 enum snd_soc_bias_level level) 1312 { 1313 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1314 1315 switch (level) { 1316 case SND_SOC_BIAS_ON: 1317 break; 1318 1319 case SND_SOC_BIAS_PREPARE: 1320 /* 1321 * SND_SOC_BIAS_PREPARE is called while preparing for a 1322 * transition to ON or away from ON. If current bias_level 1323 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1324 * away from ON. Disable the clock in that case, otherwise 1325 * enable it. 1326 */ 1327 if (!IS_ERR(max98088->mclk)) { 1328 if (snd_soc_component_get_bias_level(component) == 1329 SND_SOC_BIAS_ON) 1330 clk_disable_unprepare(max98088->mclk); 1331 else 1332 clk_prepare_enable(max98088->mclk); 1333 } 1334 break; 1335 1336 case SND_SOC_BIAS_STANDBY: 1337 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1338 regcache_sync(max98088->regmap); 1339 1340 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1341 M98088_MBEN, M98088_MBEN); 1342 break; 1343 1344 case SND_SOC_BIAS_OFF: 1345 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1346 M98088_MBEN, 0); 1347 regcache_mark_dirty(max98088->regmap); 1348 break; 1349 } 1350 return 0; 1351 } 1352 1353 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1354 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1355 1356 static const struct snd_soc_dai_ops max98088_dai1_ops = { 1357 .set_sysclk = max98088_dai_set_sysclk, 1358 .set_fmt = max98088_dai1_set_fmt, 1359 .hw_params = max98088_dai1_hw_params, 1360 .digital_mute = max98088_dai1_digital_mute, 1361 }; 1362 1363 static const struct snd_soc_dai_ops max98088_dai2_ops = { 1364 .set_sysclk = max98088_dai_set_sysclk, 1365 .set_fmt = max98088_dai2_set_fmt, 1366 .hw_params = max98088_dai2_hw_params, 1367 .digital_mute = max98088_dai2_digital_mute, 1368 }; 1369 1370 static struct snd_soc_dai_driver max98088_dai[] = { 1371 { 1372 .name = "HiFi", 1373 .playback = { 1374 .stream_name = "HiFi Playback", 1375 .channels_min = 1, 1376 .channels_max = 2, 1377 .rates = MAX98088_RATES, 1378 .formats = MAX98088_FORMATS, 1379 }, 1380 .capture = { 1381 .stream_name = "HiFi Capture", 1382 .channels_min = 1, 1383 .channels_max = 2, 1384 .rates = MAX98088_RATES, 1385 .formats = MAX98088_FORMATS, 1386 }, 1387 .ops = &max98088_dai1_ops, 1388 }, 1389 { 1390 .name = "Aux", 1391 .playback = { 1392 .stream_name = "Aux Playback", 1393 .channels_min = 1, 1394 .channels_max = 2, 1395 .rates = MAX98088_RATES, 1396 .formats = MAX98088_FORMATS, 1397 }, 1398 .ops = &max98088_dai2_ops, 1399 } 1400 }; 1401 1402 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; 1403 1404 static int max98088_get_channel(struct snd_soc_component *component, const char *name) 1405 { 1406 int ret; 1407 1408 ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name); 1409 if (ret < 0) 1410 dev_err(component->dev, "Bad EQ channel name '%s'\n", name); 1411 return ret; 1412 } 1413 1414 static void max98088_setup_eq1(struct snd_soc_component *component) 1415 { 1416 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1417 struct max98088_pdata *pdata = max98088->pdata; 1418 struct max98088_eq_cfg *coef_set; 1419 int best, best_val, save, i, sel, fs; 1420 struct max98088_cdata *cdata; 1421 1422 cdata = &max98088->dai[0]; 1423 1424 if (!pdata || !max98088->eq_textcnt) 1425 return; 1426 1427 /* Find the selected configuration with nearest sample rate */ 1428 fs = cdata->rate; 1429 sel = cdata->eq_sel; 1430 1431 best = 0; 1432 best_val = INT_MAX; 1433 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1434 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1435 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1436 best = i; 1437 best_val = abs(pdata->eq_cfg[i].rate - fs); 1438 } 1439 } 1440 1441 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1442 pdata->eq_cfg[best].name, 1443 pdata->eq_cfg[best].rate, fs); 1444 1445 /* Disable EQ while configuring, and save current on/off state */ 1446 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL); 1447 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1448 1449 coef_set = &pdata->eq_cfg[sel]; 1450 1451 m98088_eq_band(component, 0, 0, coef_set->band1); 1452 m98088_eq_band(component, 0, 1, coef_set->band2); 1453 m98088_eq_band(component, 0, 2, coef_set->band3); 1454 m98088_eq_band(component, 0, 3, coef_set->band4); 1455 m98088_eq_band(component, 0, 4, coef_set->band5); 1456 1457 /* Restore the original on/off state */ 1458 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1459 } 1460 1461 static void max98088_setup_eq2(struct snd_soc_component *component) 1462 { 1463 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1464 struct max98088_pdata *pdata = max98088->pdata; 1465 struct max98088_eq_cfg *coef_set; 1466 int best, best_val, save, i, sel, fs; 1467 struct max98088_cdata *cdata; 1468 1469 cdata = &max98088->dai[1]; 1470 1471 if (!pdata || !max98088->eq_textcnt) 1472 return; 1473 1474 /* Find the selected configuration with nearest sample rate */ 1475 fs = cdata->rate; 1476 1477 sel = cdata->eq_sel; 1478 best = 0; 1479 best_val = INT_MAX; 1480 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1481 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1482 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1483 best = i; 1484 best_val = abs(pdata->eq_cfg[i].rate - fs); 1485 } 1486 } 1487 1488 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1489 pdata->eq_cfg[best].name, 1490 pdata->eq_cfg[best].rate, fs); 1491 1492 /* Disable EQ while configuring, and save current on/off state */ 1493 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL); 1494 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1495 1496 coef_set = &pdata->eq_cfg[sel]; 1497 1498 m98088_eq_band(component, 1, 0, coef_set->band1); 1499 m98088_eq_band(component, 1, 1, coef_set->band2); 1500 m98088_eq_band(component, 1, 2, coef_set->band3); 1501 m98088_eq_band(component, 1, 3, coef_set->band4); 1502 m98088_eq_band(component, 1, 4, coef_set->band5); 1503 1504 /* Restore the original on/off state */ 1505 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1506 save); 1507 } 1508 1509 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1510 struct snd_ctl_elem_value *ucontrol) 1511 { 1512 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1513 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1514 struct max98088_pdata *pdata = max98088->pdata; 1515 int channel = max98088_get_channel(component, kcontrol->id.name); 1516 struct max98088_cdata *cdata; 1517 int sel = ucontrol->value.enumerated.item[0]; 1518 1519 if (channel < 0) 1520 return channel; 1521 1522 cdata = &max98088->dai[channel]; 1523 1524 if (sel >= pdata->eq_cfgcnt) 1525 return -EINVAL; 1526 1527 cdata->eq_sel = sel; 1528 1529 switch (channel) { 1530 case 0: 1531 max98088_setup_eq1(component); 1532 break; 1533 case 1: 1534 max98088_setup_eq2(component); 1535 break; 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1542 struct snd_ctl_elem_value *ucontrol) 1543 { 1544 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1545 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1546 int channel = max98088_get_channel(component, kcontrol->id.name); 1547 struct max98088_cdata *cdata; 1548 1549 if (channel < 0) 1550 return channel; 1551 1552 cdata = &max98088->dai[channel]; 1553 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1554 return 0; 1555 } 1556 1557 static void max98088_handle_eq_pdata(struct snd_soc_component *component) 1558 { 1559 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1560 struct max98088_pdata *pdata = max98088->pdata; 1561 struct max98088_eq_cfg *cfg; 1562 unsigned int cfgcnt; 1563 int i, j; 1564 const char **t; 1565 int ret; 1566 struct snd_kcontrol_new controls[] = { 1567 SOC_ENUM_EXT((char *)eq_mode_name[0], 1568 max98088->eq_enum, 1569 max98088_get_eq_enum, 1570 max98088_put_eq_enum), 1571 SOC_ENUM_EXT((char *)eq_mode_name[1], 1572 max98088->eq_enum, 1573 max98088_get_eq_enum, 1574 max98088_put_eq_enum), 1575 }; 1576 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name)); 1577 1578 cfg = pdata->eq_cfg; 1579 cfgcnt = pdata->eq_cfgcnt; 1580 1581 /* Setup an array of texts for the equalizer enum. 1582 * This is based on Mark Brown's equalizer driver code. 1583 */ 1584 max98088->eq_textcnt = 0; 1585 max98088->eq_texts = NULL; 1586 for (i = 0; i < cfgcnt; i++) { 1587 for (j = 0; j < max98088->eq_textcnt; j++) { 1588 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1589 break; 1590 } 1591 1592 if (j != max98088->eq_textcnt) 1593 continue; 1594 1595 /* Expand the array */ 1596 t = krealloc(max98088->eq_texts, 1597 sizeof(char *) * (max98088->eq_textcnt + 1), 1598 GFP_KERNEL); 1599 if (t == NULL) 1600 continue; 1601 1602 /* Store the new entry */ 1603 t[max98088->eq_textcnt] = cfg[i].name; 1604 max98088->eq_textcnt++; 1605 max98088->eq_texts = t; 1606 } 1607 1608 /* Now point the soc_enum to .texts array items */ 1609 max98088->eq_enum.texts = max98088->eq_texts; 1610 max98088->eq_enum.items = max98088->eq_textcnt; 1611 1612 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 1613 if (ret != 0) 1614 dev_err(component->dev, "Failed to add EQ control: %d\n", ret); 1615 } 1616 1617 static void max98088_handle_pdata(struct snd_soc_component *component) 1618 { 1619 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1620 struct max98088_pdata *pdata = max98088->pdata; 1621 u8 regval = 0; 1622 1623 if (!pdata) { 1624 dev_dbg(component->dev, "No platform data\n"); 1625 return; 1626 } 1627 1628 /* Configure mic for analog/digital mic mode */ 1629 if (pdata->digmic_left_mode) 1630 regval |= M98088_DIGMIC_L; 1631 1632 if (pdata->digmic_right_mode) 1633 regval |= M98088_DIGMIC_R; 1634 1635 max98088->digmic = (regval ? 1 : 0); 1636 1637 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval); 1638 1639 /* Configure receiver output */ 1640 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1641 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL, 1642 M98088_REC_LINEMODE_MASK, regval); 1643 1644 /* Configure equalizers */ 1645 if (pdata->eq_cfgcnt) 1646 max98088_handle_eq_pdata(component); 1647 } 1648 1649 static int max98088_probe(struct snd_soc_component *component) 1650 { 1651 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1652 struct max98088_cdata *cdata; 1653 int ret = 0; 1654 1655 regcache_mark_dirty(max98088->regmap); 1656 1657 /* initialize private data */ 1658 1659 max98088->sysclk = (unsigned)-1; 1660 max98088->eq_textcnt = 0; 1661 1662 cdata = &max98088->dai[0]; 1663 cdata->rate = (unsigned)-1; 1664 cdata->fmt = (unsigned)-1; 1665 cdata->eq_sel = 0; 1666 1667 cdata = &max98088->dai[1]; 1668 cdata->rate = (unsigned)-1; 1669 cdata->fmt = (unsigned)-1; 1670 cdata->eq_sel = 0; 1671 1672 max98088->ina_state = 0; 1673 max98088->inb_state = 0; 1674 max98088->ex_mode = 0; 1675 max98088->digmic = 0; 1676 max98088->mic1pre = 0; 1677 max98088->mic2pre = 0; 1678 1679 ret = snd_soc_component_read32(component, M98088_REG_FF_REV_ID); 1680 if (ret < 0) { 1681 dev_err(component->dev, "Failed to read device revision: %d\n", 1682 ret); 1683 goto err_access; 1684 } 1685 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A'); 1686 1687 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV); 1688 1689 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00); 1690 1691 snd_soc_component_write(component, M98088_REG_22_MIX_DAC, 1692 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 1693 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 1694 1695 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0); 1696 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F); 1697 1698 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG, 1699 M98088_S1NORMAL|M98088_SDATA); 1700 1701 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG, 1702 M98088_S2NORMAL|M98088_SDATA); 1703 1704 max98088_handle_pdata(component); 1705 1706 err_access: 1707 return ret; 1708 } 1709 1710 static void max98088_remove(struct snd_soc_component *component) 1711 { 1712 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1713 1714 kfree(max98088->eq_texts); 1715 } 1716 1717 static const struct snd_soc_component_driver soc_component_dev_max98088 = { 1718 .probe = max98088_probe, 1719 .remove = max98088_remove, 1720 .set_bias_level = max98088_set_bias_level, 1721 .controls = max98088_snd_controls, 1722 .num_controls = ARRAY_SIZE(max98088_snd_controls), 1723 .dapm_widgets = max98088_dapm_widgets, 1724 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 1725 .dapm_routes = max98088_audio_map, 1726 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map), 1727 .suspend_bias_off = 1, 1728 .idle_bias_on = 1, 1729 .use_pmdown_time = 1, 1730 .endianness = 1, 1731 .non_legacy_dai_naming = 1, 1732 }; 1733 1734 static int max98088_i2c_probe(struct i2c_client *i2c, 1735 const struct i2c_device_id *id) 1736 { 1737 struct max98088_priv *max98088; 1738 int ret; 1739 1740 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv), 1741 GFP_KERNEL); 1742 if (max98088 == NULL) 1743 return -ENOMEM; 1744 1745 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap); 1746 if (IS_ERR(max98088->regmap)) 1747 return PTR_ERR(max98088->regmap); 1748 1749 max98088->mclk = devm_clk_get(&i2c->dev, "mclk"); 1750 if (IS_ERR(max98088->mclk)) 1751 if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER) 1752 return PTR_ERR(max98088->mclk); 1753 1754 max98088->devtype = id->driver_data; 1755 1756 i2c_set_clientdata(i2c, max98088); 1757 max98088->pdata = i2c->dev.platform_data; 1758 1759 ret = devm_snd_soc_register_component(&i2c->dev, 1760 &soc_component_dev_max98088, &max98088_dai[0], 2); 1761 return ret; 1762 } 1763 1764 static const struct i2c_device_id max98088_i2c_id[] = { 1765 { "max98088", MAX98088 }, 1766 { "max98089", MAX98089 }, 1767 { } 1768 }; 1769 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 1770 1771 #if defined(CONFIG_OF) 1772 static const struct of_device_id max98088_of_match[] = { 1773 { .compatible = "maxim,max98088" }, 1774 { .compatible = "maxim,max98089" }, 1775 { } 1776 }; 1777 MODULE_DEVICE_TABLE(of, max98088_of_match); 1778 #endif 1779 1780 static struct i2c_driver max98088_i2c_driver = { 1781 .driver = { 1782 .name = "max98088", 1783 .of_match_table = of_match_ptr(max98088_of_match), 1784 }, 1785 .probe = max98088_i2c_probe, 1786 .id_table = max98088_i2c_id, 1787 }; 1788 1789 module_i2c_driver(max98088_i2c_driver); 1790 1791 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 1792 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 1793 MODULE_LICENSE("GPL"); 1794