1 /* 2 * max98088.c -- MAX98088 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <linux/slab.h> 25 #include <asm/div64.h> 26 #include <sound/max98088.h> 27 #include "max98088.h" 28 29 enum max98088_type { 30 MAX98088, 31 MAX98089, 32 }; 33 34 struct max98088_cdata { 35 unsigned int rate; 36 unsigned int fmt; 37 int eq_sel; 38 }; 39 40 struct max98088_priv { 41 enum max98088_type devtype; 42 struct max98088_pdata *pdata; 43 unsigned int sysclk; 44 struct max98088_cdata dai[2]; 45 int eq_textcnt; 46 const char **eq_texts; 47 struct soc_enum eq_enum; 48 u8 ina_state; 49 u8 inb_state; 50 unsigned int ex_mode; 51 unsigned int digmic; 52 unsigned int mic1pre; 53 unsigned int mic2pre; 54 unsigned int extmic_mode; 55 }; 56 57 static const u8 max98088_reg[M98088_REG_CNT] = { 58 0x00, /* 00 IRQ status */ 59 0x00, /* 01 MIC status */ 60 0x00, /* 02 jack status */ 61 0x00, /* 03 battery voltage */ 62 0x00, /* 04 */ 63 0x00, /* 05 */ 64 0x00, /* 06 */ 65 0x00, /* 07 */ 66 0x00, /* 08 */ 67 0x00, /* 09 */ 68 0x00, /* 0A */ 69 0x00, /* 0B */ 70 0x00, /* 0C */ 71 0x00, /* 0D */ 72 0x00, /* 0E */ 73 0x00, /* 0F interrupt enable */ 74 75 0x00, /* 10 master clock */ 76 0x00, /* 11 DAI1 clock mode */ 77 0x00, /* 12 DAI1 clock control */ 78 0x00, /* 13 DAI1 clock control */ 79 0x00, /* 14 DAI1 format */ 80 0x00, /* 15 DAI1 clock */ 81 0x00, /* 16 DAI1 config */ 82 0x00, /* 17 DAI1 TDM */ 83 0x00, /* 18 DAI1 filters */ 84 0x00, /* 19 DAI2 clock mode */ 85 0x00, /* 1A DAI2 clock control */ 86 0x00, /* 1B DAI2 clock control */ 87 0x00, /* 1C DAI2 format */ 88 0x00, /* 1D DAI2 clock */ 89 0x00, /* 1E DAI2 config */ 90 0x00, /* 1F DAI2 TDM */ 91 92 0x00, /* 20 DAI2 filters */ 93 0x00, /* 21 data config */ 94 0x00, /* 22 DAC mixer */ 95 0x00, /* 23 left ADC mixer */ 96 0x00, /* 24 right ADC mixer */ 97 0x00, /* 25 left HP mixer */ 98 0x00, /* 26 right HP mixer */ 99 0x00, /* 27 HP control */ 100 0x00, /* 28 left REC mixer */ 101 0x00, /* 29 right REC mixer */ 102 0x00, /* 2A REC control */ 103 0x00, /* 2B left SPK mixer */ 104 0x00, /* 2C right SPK mixer */ 105 0x00, /* 2D SPK control */ 106 0x00, /* 2E sidetone */ 107 0x00, /* 2F DAI1 playback level */ 108 109 0x00, /* 30 DAI1 playback level */ 110 0x00, /* 31 DAI2 playback level */ 111 0x00, /* 32 DAI2 playbakc level */ 112 0x00, /* 33 left ADC level */ 113 0x00, /* 34 right ADC level */ 114 0x00, /* 35 MIC1 level */ 115 0x00, /* 36 MIC2 level */ 116 0x00, /* 37 INA level */ 117 0x00, /* 38 INB level */ 118 0x00, /* 39 left HP volume */ 119 0x00, /* 3A right HP volume */ 120 0x00, /* 3B left REC volume */ 121 0x00, /* 3C right REC volume */ 122 0x00, /* 3D left SPK volume */ 123 0x00, /* 3E right SPK volume */ 124 0x00, /* 3F MIC config */ 125 126 0x00, /* 40 MIC threshold */ 127 0x00, /* 41 excursion limiter filter */ 128 0x00, /* 42 excursion limiter threshold */ 129 0x00, /* 43 ALC */ 130 0x00, /* 44 power limiter threshold */ 131 0x00, /* 45 power limiter config */ 132 0x00, /* 46 distortion limiter config */ 133 0x00, /* 47 audio input */ 134 0x00, /* 48 microphone */ 135 0x00, /* 49 level control */ 136 0x00, /* 4A bypass switches */ 137 0x00, /* 4B jack detect */ 138 0x00, /* 4C input enable */ 139 0x00, /* 4D output enable */ 140 0xF0, /* 4E bias control */ 141 0x00, /* 4F DAC power */ 142 143 0x0F, /* 50 DAC power */ 144 0x00, /* 51 system */ 145 0x00, /* 52 DAI1 EQ1 */ 146 0x00, /* 53 DAI1 EQ1 */ 147 0x00, /* 54 DAI1 EQ1 */ 148 0x00, /* 55 DAI1 EQ1 */ 149 0x00, /* 56 DAI1 EQ1 */ 150 0x00, /* 57 DAI1 EQ1 */ 151 0x00, /* 58 DAI1 EQ1 */ 152 0x00, /* 59 DAI1 EQ1 */ 153 0x00, /* 5A DAI1 EQ1 */ 154 0x00, /* 5B DAI1 EQ1 */ 155 0x00, /* 5C DAI1 EQ2 */ 156 0x00, /* 5D DAI1 EQ2 */ 157 0x00, /* 5E DAI1 EQ2 */ 158 0x00, /* 5F DAI1 EQ2 */ 159 160 0x00, /* 60 DAI1 EQ2 */ 161 0x00, /* 61 DAI1 EQ2 */ 162 0x00, /* 62 DAI1 EQ2 */ 163 0x00, /* 63 DAI1 EQ2 */ 164 0x00, /* 64 DAI1 EQ2 */ 165 0x00, /* 65 DAI1 EQ2 */ 166 0x00, /* 66 DAI1 EQ3 */ 167 0x00, /* 67 DAI1 EQ3 */ 168 0x00, /* 68 DAI1 EQ3 */ 169 0x00, /* 69 DAI1 EQ3 */ 170 0x00, /* 6A DAI1 EQ3 */ 171 0x00, /* 6B DAI1 EQ3 */ 172 0x00, /* 6C DAI1 EQ3 */ 173 0x00, /* 6D DAI1 EQ3 */ 174 0x00, /* 6E DAI1 EQ3 */ 175 0x00, /* 6F DAI1 EQ3 */ 176 177 0x00, /* 70 DAI1 EQ4 */ 178 0x00, /* 71 DAI1 EQ4 */ 179 0x00, /* 72 DAI1 EQ4 */ 180 0x00, /* 73 DAI1 EQ4 */ 181 0x00, /* 74 DAI1 EQ4 */ 182 0x00, /* 75 DAI1 EQ4 */ 183 0x00, /* 76 DAI1 EQ4 */ 184 0x00, /* 77 DAI1 EQ4 */ 185 0x00, /* 78 DAI1 EQ4 */ 186 0x00, /* 79 DAI1 EQ4 */ 187 0x00, /* 7A DAI1 EQ5 */ 188 0x00, /* 7B DAI1 EQ5 */ 189 0x00, /* 7C DAI1 EQ5 */ 190 0x00, /* 7D DAI1 EQ5 */ 191 0x00, /* 7E DAI1 EQ5 */ 192 0x00, /* 7F DAI1 EQ5 */ 193 194 0x00, /* 80 DAI1 EQ5 */ 195 0x00, /* 81 DAI1 EQ5 */ 196 0x00, /* 82 DAI1 EQ5 */ 197 0x00, /* 83 DAI1 EQ5 */ 198 0x00, /* 84 DAI2 EQ1 */ 199 0x00, /* 85 DAI2 EQ1 */ 200 0x00, /* 86 DAI2 EQ1 */ 201 0x00, /* 87 DAI2 EQ1 */ 202 0x00, /* 88 DAI2 EQ1 */ 203 0x00, /* 89 DAI2 EQ1 */ 204 0x00, /* 8A DAI2 EQ1 */ 205 0x00, /* 8B DAI2 EQ1 */ 206 0x00, /* 8C DAI2 EQ1 */ 207 0x00, /* 8D DAI2 EQ1 */ 208 0x00, /* 8E DAI2 EQ2 */ 209 0x00, /* 8F DAI2 EQ2 */ 210 211 0x00, /* 90 DAI2 EQ2 */ 212 0x00, /* 91 DAI2 EQ2 */ 213 0x00, /* 92 DAI2 EQ2 */ 214 0x00, /* 93 DAI2 EQ2 */ 215 0x00, /* 94 DAI2 EQ2 */ 216 0x00, /* 95 DAI2 EQ2 */ 217 0x00, /* 96 DAI2 EQ2 */ 218 0x00, /* 97 DAI2 EQ2 */ 219 0x00, /* 98 DAI2 EQ3 */ 220 0x00, /* 99 DAI2 EQ3 */ 221 0x00, /* 9A DAI2 EQ3 */ 222 0x00, /* 9B DAI2 EQ3 */ 223 0x00, /* 9C DAI2 EQ3 */ 224 0x00, /* 9D DAI2 EQ3 */ 225 0x00, /* 9E DAI2 EQ3 */ 226 0x00, /* 9F DAI2 EQ3 */ 227 228 0x00, /* A0 DAI2 EQ3 */ 229 0x00, /* A1 DAI2 EQ3 */ 230 0x00, /* A2 DAI2 EQ4 */ 231 0x00, /* A3 DAI2 EQ4 */ 232 0x00, /* A4 DAI2 EQ4 */ 233 0x00, /* A5 DAI2 EQ4 */ 234 0x00, /* A6 DAI2 EQ4 */ 235 0x00, /* A7 DAI2 EQ4 */ 236 0x00, /* A8 DAI2 EQ4 */ 237 0x00, /* A9 DAI2 EQ4 */ 238 0x00, /* AA DAI2 EQ4 */ 239 0x00, /* AB DAI2 EQ4 */ 240 0x00, /* AC DAI2 EQ5 */ 241 0x00, /* AD DAI2 EQ5 */ 242 0x00, /* AE DAI2 EQ5 */ 243 0x00, /* AF DAI2 EQ5 */ 244 245 0x00, /* B0 DAI2 EQ5 */ 246 0x00, /* B1 DAI2 EQ5 */ 247 0x00, /* B2 DAI2 EQ5 */ 248 0x00, /* B3 DAI2 EQ5 */ 249 0x00, /* B4 DAI2 EQ5 */ 250 0x00, /* B5 DAI2 EQ5 */ 251 0x00, /* B6 DAI1 biquad */ 252 0x00, /* B7 DAI1 biquad */ 253 0x00, /* B8 DAI1 biquad */ 254 0x00, /* B9 DAI1 biquad */ 255 0x00, /* BA DAI1 biquad */ 256 0x00, /* BB DAI1 biquad */ 257 0x00, /* BC DAI1 biquad */ 258 0x00, /* BD DAI1 biquad */ 259 0x00, /* BE DAI1 biquad */ 260 0x00, /* BF DAI1 biquad */ 261 262 0x00, /* C0 DAI2 biquad */ 263 0x00, /* C1 DAI2 biquad */ 264 0x00, /* C2 DAI2 biquad */ 265 0x00, /* C3 DAI2 biquad */ 266 0x00, /* C4 DAI2 biquad */ 267 0x00, /* C5 DAI2 biquad */ 268 0x00, /* C6 DAI2 biquad */ 269 0x00, /* C7 DAI2 biquad */ 270 0x00, /* C8 DAI2 biquad */ 271 0x00, /* C9 DAI2 biquad */ 272 0x00, /* CA */ 273 0x00, /* CB */ 274 0x00, /* CC */ 275 0x00, /* CD */ 276 0x00, /* CE */ 277 0x00, /* CF */ 278 279 0x00, /* D0 */ 280 0x00, /* D1 */ 281 0x00, /* D2 */ 282 0x00, /* D3 */ 283 0x00, /* D4 */ 284 0x00, /* D5 */ 285 0x00, /* D6 */ 286 0x00, /* D7 */ 287 0x00, /* D8 */ 288 0x00, /* D9 */ 289 0x00, /* DA */ 290 0x70, /* DB */ 291 0x00, /* DC */ 292 0x00, /* DD */ 293 0x00, /* DE */ 294 0x00, /* DF */ 295 296 0x00, /* E0 */ 297 0x00, /* E1 */ 298 0x00, /* E2 */ 299 0x00, /* E3 */ 300 0x00, /* E4 */ 301 0x00, /* E5 */ 302 0x00, /* E6 */ 303 0x00, /* E7 */ 304 0x00, /* E8 */ 305 0x00, /* E9 */ 306 0x00, /* EA */ 307 0x00, /* EB */ 308 0x00, /* EC */ 309 0x00, /* ED */ 310 0x00, /* EE */ 311 0x00, /* EF */ 312 313 0x00, /* F0 */ 314 0x00, /* F1 */ 315 0x00, /* F2 */ 316 0x00, /* F3 */ 317 0x00, /* F4 */ 318 0x00, /* F5 */ 319 0x00, /* F6 */ 320 0x00, /* F7 */ 321 0x00, /* F8 */ 322 0x00, /* F9 */ 323 0x00, /* FA */ 324 0x00, /* FB */ 325 0x00, /* FC */ 326 0x00, /* FD */ 327 0x00, /* FE */ 328 0x00, /* FF */ 329 }; 330 331 static struct { 332 int readable; 333 int writable; 334 int vol; 335 } max98088_access[M98088_REG_CNT] = { 336 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ 337 { 0xFF, 0x00, 1 }, /* 01 MIC status */ 338 { 0xFF, 0x00, 1 }, /* 02 jack status */ 339 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ 340 { 0xFF, 0xFF, 0 }, /* 04 */ 341 { 0xFF, 0xFF, 0 }, /* 05 */ 342 { 0xFF, 0xFF, 0 }, /* 06 */ 343 { 0xFF, 0xFF, 0 }, /* 07 */ 344 { 0xFF, 0xFF, 0 }, /* 08 */ 345 { 0xFF, 0xFF, 0 }, /* 09 */ 346 { 0xFF, 0xFF, 0 }, /* 0A */ 347 { 0xFF, 0xFF, 0 }, /* 0B */ 348 { 0xFF, 0xFF, 0 }, /* 0C */ 349 { 0xFF, 0xFF, 0 }, /* 0D */ 350 { 0xFF, 0xFF, 0 }, /* 0E */ 351 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ 352 353 { 0xFF, 0xFF, 0 }, /* 10 master clock */ 354 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ 355 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ 356 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ 357 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ 358 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ 359 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ 360 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ 361 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ 362 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ 363 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ 364 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ 365 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ 366 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ 367 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ 368 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ 369 370 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ 371 { 0xFF, 0xFF, 0 }, /* 21 data config */ 372 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ 373 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ 374 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ 375 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ 376 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ 377 { 0xFF, 0xFF, 0 }, /* 27 HP control */ 378 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ 379 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ 380 { 0xFF, 0xFF, 0 }, /* 2A REC control */ 381 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ 382 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ 383 { 0xFF, 0xFF, 0 }, /* 2D SPK control */ 384 { 0xFF, 0xFF, 0 }, /* 2E sidetone */ 385 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ 386 387 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ 388 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ 389 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ 390 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ 391 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ 392 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ 393 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ 394 { 0xFF, 0xFF, 0 }, /* 37 INA level */ 395 { 0xFF, 0xFF, 0 }, /* 38 INB level */ 396 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ 397 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ 398 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ 399 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ 400 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ 401 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ 402 { 0xFF, 0xFF, 0 }, /* 3F MIC config */ 403 404 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ 405 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ 406 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ 407 { 0xFF, 0xFF, 0 }, /* 43 ALC */ 408 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ 409 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ 410 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ 411 { 0xFF, 0xFF, 0 }, /* 47 audio input */ 412 { 0xFF, 0xFF, 0 }, /* 48 microphone */ 413 { 0xFF, 0xFF, 0 }, /* 49 level control */ 414 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ 415 { 0xFF, 0xFF, 0 }, /* 4B jack detect */ 416 { 0xFF, 0xFF, 0 }, /* 4C input enable */ 417 { 0xFF, 0xFF, 0 }, /* 4D output enable */ 418 { 0xFF, 0xFF, 0 }, /* 4E bias control */ 419 { 0xFF, 0xFF, 0 }, /* 4F DAC power */ 420 421 { 0xFF, 0xFF, 0 }, /* 50 DAC power */ 422 { 0xFF, 0xFF, 0 }, /* 51 system */ 423 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ 424 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ 425 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ 426 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ 427 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ 428 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ 429 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ 430 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ 431 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ 432 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ 433 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ 434 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ 435 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ 436 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ 437 438 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ 439 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ 440 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ 441 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ 442 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ 443 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ 444 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ 445 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ 446 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ 447 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ 448 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ 449 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ 450 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ 451 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ 452 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ 453 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ 454 455 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ 456 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ 457 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ 458 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ 459 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ 460 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ 461 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ 462 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ 463 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ 464 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ 465 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ 466 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ 467 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ 468 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ 469 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ 470 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ 471 472 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ 473 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ 474 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ 475 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ 476 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ 477 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ 478 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ 479 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ 480 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ 481 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ 482 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ 483 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ 484 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ 485 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ 486 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ 487 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ 488 489 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ 490 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ 491 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ 492 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ 493 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ 494 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ 495 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ 496 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ 497 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ 498 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ 499 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ 500 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ 501 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ 502 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ 503 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ 504 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ 505 506 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ 507 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ 508 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ 509 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ 510 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ 511 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ 512 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ 513 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ 514 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ 515 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ 516 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ 517 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ 518 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ 519 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ 520 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ 521 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ 522 523 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ 524 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ 525 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ 526 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ 527 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ 528 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ 529 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ 530 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ 531 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ 532 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ 533 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ 534 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ 535 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ 536 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ 537 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ 538 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ 539 540 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ 541 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ 542 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ 543 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ 544 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ 545 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ 546 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ 547 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ 548 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ 549 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ 550 { 0x00, 0x00, 0 }, /* CA */ 551 { 0x00, 0x00, 0 }, /* CB */ 552 { 0x00, 0x00, 0 }, /* CC */ 553 { 0x00, 0x00, 0 }, /* CD */ 554 { 0x00, 0x00, 0 }, /* CE */ 555 { 0x00, 0x00, 0 }, /* CF */ 556 557 { 0x00, 0x00, 0 }, /* D0 */ 558 { 0x00, 0x00, 0 }, /* D1 */ 559 { 0x00, 0x00, 0 }, /* D2 */ 560 { 0x00, 0x00, 0 }, /* D3 */ 561 { 0x00, 0x00, 0 }, /* D4 */ 562 { 0x00, 0x00, 0 }, /* D5 */ 563 { 0x00, 0x00, 0 }, /* D6 */ 564 { 0x00, 0x00, 0 }, /* D7 */ 565 { 0x00, 0x00, 0 }, /* D8 */ 566 { 0x00, 0x00, 0 }, /* D9 */ 567 { 0x00, 0x00, 0 }, /* DA */ 568 { 0x00, 0x00, 0 }, /* DB */ 569 { 0x00, 0x00, 0 }, /* DC */ 570 { 0x00, 0x00, 0 }, /* DD */ 571 { 0x00, 0x00, 0 }, /* DE */ 572 { 0x00, 0x00, 0 }, /* DF */ 573 574 { 0x00, 0x00, 0 }, /* E0 */ 575 { 0x00, 0x00, 0 }, /* E1 */ 576 { 0x00, 0x00, 0 }, /* E2 */ 577 { 0x00, 0x00, 0 }, /* E3 */ 578 { 0x00, 0x00, 0 }, /* E4 */ 579 { 0x00, 0x00, 0 }, /* E5 */ 580 { 0x00, 0x00, 0 }, /* E6 */ 581 { 0x00, 0x00, 0 }, /* E7 */ 582 { 0x00, 0x00, 0 }, /* E8 */ 583 { 0x00, 0x00, 0 }, /* E9 */ 584 { 0x00, 0x00, 0 }, /* EA */ 585 { 0x00, 0x00, 0 }, /* EB */ 586 { 0x00, 0x00, 0 }, /* EC */ 587 { 0x00, 0x00, 0 }, /* ED */ 588 { 0x00, 0x00, 0 }, /* EE */ 589 { 0x00, 0x00, 0 }, /* EF */ 590 591 { 0x00, 0x00, 0 }, /* F0 */ 592 { 0x00, 0x00, 0 }, /* F1 */ 593 { 0x00, 0x00, 0 }, /* F2 */ 594 { 0x00, 0x00, 0 }, /* F3 */ 595 { 0x00, 0x00, 0 }, /* F4 */ 596 { 0x00, 0x00, 0 }, /* F5 */ 597 { 0x00, 0x00, 0 }, /* F6 */ 598 { 0x00, 0x00, 0 }, /* F7 */ 599 { 0x00, 0x00, 0 }, /* F8 */ 600 { 0x00, 0x00, 0 }, /* F9 */ 601 { 0x00, 0x00, 0 }, /* FA */ 602 { 0x00, 0x00, 0 }, /* FB */ 603 { 0x00, 0x00, 0 }, /* FC */ 604 { 0x00, 0x00, 0 }, /* FD */ 605 { 0x00, 0x00, 0 }, /* FE */ 606 { 0xFF, 0x00, 1 }, /* FF */ 607 }; 608 609 static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 610 { 611 return max98088_access[reg].vol; 612 } 613 614 615 /* 616 * Load equalizer DSP coefficient configurations registers 617 */ 618 static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai, 619 unsigned int band, u16 *coefs) 620 { 621 unsigned int eq_reg; 622 unsigned int i; 623 624 BUG_ON(band > 4); 625 BUG_ON(dai > 1); 626 627 /* Load the base register address */ 628 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 629 630 /* Add the band address offset, note adjustment for word address */ 631 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 632 633 /* Step through the registers and coefs */ 634 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 635 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i])); 636 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i])); 637 } 638 } 639 640 /* 641 * Excursion limiter modes 642 */ 643 static const char *max98088_exmode_texts[] = { 644 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 645 "400-600Hz", "400-800Hz", 646 }; 647 648 static const unsigned int max98088_exmode_values[] = { 649 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 650 }; 651 652 static const struct soc_enum max98088_exmode_enum = 653 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127, 654 ARRAY_SIZE(max98088_exmode_texts), 655 max98088_exmode_texts, 656 max98088_exmode_values); 657 658 static const char *max98088_ex_thresh[] = { /* volts PP */ 659 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 660 static const struct soc_enum max98088_ex_thresh_enum[] = { 661 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8, 662 max98088_ex_thresh), 663 }; 664 665 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 666 static const struct soc_enum max98088_filter_mode_enum[] = { 667 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode), 668 }; 669 670 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 671 672 static const struct soc_enum max98088_extmic_enum = 673 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text); 674 675 static const struct snd_kcontrol_new max98088_extmic_mux = 676 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 677 678 static const char *max98088_dai1_fltr[] = { 679 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 680 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 681 static const struct soc_enum max98088_dai1_dac_filter_enum[] = { 682 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr), 683 }; 684 static const struct soc_enum max98088_dai1_adc_filter_enum[] = { 685 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr), 686 }; 687 688 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 689 struct snd_ctl_elem_value *ucontrol) 690 { 691 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 692 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 693 unsigned int sel = ucontrol->value.integer.value[0]; 694 695 max98088->mic1pre = sel; 696 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 697 (1+sel)<<M98088_MICPRE_SHIFT); 698 699 return 0; 700 } 701 702 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 703 struct snd_ctl_elem_value *ucontrol) 704 { 705 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 706 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 707 708 ucontrol->value.integer.value[0] = max98088->mic1pre; 709 return 0; 710 } 711 712 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 713 struct snd_ctl_elem_value *ucontrol) 714 { 715 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 716 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 717 unsigned int sel = ucontrol->value.integer.value[0]; 718 719 max98088->mic2pre = sel; 720 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 721 (1+sel)<<M98088_MICPRE_SHIFT); 722 723 return 0; 724 } 725 726 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 727 struct snd_ctl_elem_value *ucontrol) 728 { 729 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 730 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 731 732 ucontrol->value.integer.value[0] = max98088->mic2pre; 733 return 0; 734 } 735 736 static const unsigned int max98088_micboost_tlv[] = { 737 TLV_DB_RANGE_HEAD(2), 738 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 739 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 740 }; 741 742 static const struct snd_kcontrol_new max98088_snd_controls[] = { 743 744 SOC_DOUBLE_R("Headphone Volume", M98088_REG_39_LVL_HP_L, 745 M98088_REG_3A_LVL_HP_R, 0, 31, 0), 746 SOC_DOUBLE_R("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 747 M98088_REG_3E_LVL_SPK_R, 0, 31, 0), 748 SOC_DOUBLE_R("Receiver Volume", M98088_REG_3B_LVL_REC_L, 749 M98088_REG_3C_LVL_REC_R, 0, 31, 0), 750 751 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 752 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 753 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 754 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 755 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 756 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 757 758 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 759 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 760 761 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 762 M98088_REG_35_LVL_MIC1, 5, 2, 0, 763 max98088_mic1pre_get, max98088_mic1pre_set, 764 max98088_micboost_tlv), 765 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 766 M98088_REG_36_LVL_MIC2, 5, 2, 0, 767 max98088_mic2pre_get, max98088_mic2pre_set, 768 max98088_micboost_tlv), 769 770 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 771 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 772 773 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 774 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 775 776 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 777 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 778 779 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 780 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 781 782 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum), 783 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 784 785 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 786 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 787 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 788 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 789 0, 1, 0), 790 791 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 792 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 793 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 794 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 795 796 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 797 4, 15, 0), 798 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 799 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 800 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 801 802 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 803 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 804 }; 805 806 /* Left speaker mixer switch */ 807 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 808 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 809 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 810 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 811 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 812 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 813 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 814 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 815 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 816 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 817 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 818 }; 819 820 /* Right speaker mixer switch */ 821 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 822 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 823 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 824 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 825 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 826 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 827 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 828 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 829 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 830 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 831 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 832 }; 833 834 /* Left headphone mixer switch */ 835 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 836 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 837 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 838 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 839 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 840 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 841 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 842 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 843 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 844 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 845 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 846 }; 847 848 /* Right headphone mixer switch */ 849 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 850 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 851 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 852 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 853 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 854 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 855 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 856 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 857 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 858 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 859 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 860 }; 861 862 /* Left earpiece/receiver mixer switch */ 863 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 864 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 865 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 866 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 867 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 868 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 869 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 870 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 871 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 872 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 873 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 874 }; 875 876 /* Right earpiece/receiver mixer switch */ 877 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 878 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 879 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 880 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 881 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 882 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 883 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 884 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 885 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 886 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 887 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 888 }; 889 890 /* Left ADC mixer switch */ 891 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 892 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 893 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 894 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 895 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 896 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 897 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 898 }; 899 900 /* Right ADC mixer switch */ 901 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 902 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 903 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 904 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 905 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 906 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 907 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 908 }; 909 910 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 911 struct snd_kcontrol *kcontrol, int event) 912 { 913 struct snd_soc_codec *codec = w->codec; 914 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 915 916 switch (event) { 917 case SND_SOC_DAPM_POST_PMU: 918 if (w->reg == M98088_REG_35_LVL_MIC1) { 919 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 920 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 921 } else { 922 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 923 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 924 } 925 break; 926 case SND_SOC_DAPM_POST_PMD: 927 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0); 928 break; 929 default: 930 return -EINVAL; 931 } 932 933 return 0; 934 } 935 936 /* 937 * The line inputs are 2-channel stereo inputs with the left 938 * and right channels sharing a common PGA power control signal. 939 */ 940 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 941 int event, int line, u8 channel) 942 { 943 struct snd_soc_codec *codec = w->codec; 944 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 945 u8 *state; 946 947 BUG_ON(!((channel == 1) || (channel == 2))); 948 949 switch (line) { 950 case LINE_INA: 951 state = &max98088->ina_state; 952 break; 953 case LINE_INB: 954 state = &max98088->inb_state; 955 break; 956 default: 957 return -EINVAL; 958 } 959 960 switch (event) { 961 case SND_SOC_DAPM_POST_PMU: 962 *state |= channel; 963 snd_soc_update_bits(codec, w->reg, 964 (1 << w->shift), (1 << w->shift)); 965 break; 966 case SND_SOC_DAPM_POST_PMD: 967 *state &= ~channel; 968 if (*state == 0) { 969 snd_soc_update_bits(codec, w->reg, 970 (1 << w->shift), 0); 971 } 972 break; 973 default: 974 return -EINVAL; 975 } 976 977 return 0; 978 } 979 980 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 981 struct snd_kcontrol *k, int event) 982 { 983 return max98088_line_pga(w, event, LINE_INA, 1); 984 } 985 986 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 987 struct snd_kcontrol *k, int event) 988 { 989 return max98088_line_pga(w, event, LINE_INA, 2); 990 } 991 992 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 993 struct snd_kcontrol *k, int event) 994 { 995 return max98088_line_pga(w, event, LINE_INB, 1); 996 } 997 998 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 999 struct snd_kcontrol *k, int event) 1000 { 1001 return max98088_line_pga(w, event, LINE_INB, 2); 1002 } 1003 1004 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 1005 1006 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 1007 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 1008 1009 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 1010 M98088_REG_4D_PWR_EN_OUT, 1, 0), 1011 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 1012 M98088_REG_4D_PWR_EN_OUT, 0, 0), 1013 SND_SOC_DAPM_DAC("DACL2", "Aux Playback", 1014 M98088_REG_4D_PWR_EN_OUT, 1, 0), 1015 SND_SOC_DAPM_DAC("DACR2", "Aux Playback", 1016 M98088_REG_4D_PWR_EN_OUT, 0, 0), 1017 1018 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 1019 7, 0, NULL, 0), 1020 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 1021 6, 0, NULL, 0), 1022 1023 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 1024 5, 0, NULL, 0), 1025 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 1026 4, 0, NULL, 0), 1027 1028 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 1029 3, 0, NULL, 0), 1030 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 1031 2, 0, NULL, 0), 1032 1033 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 1034 &max98088_extmic_mux), 1035 1036 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 1037 &max98088_left_hp_mixer_controls[0], 1038 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 1039 1040 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 1041 &max98088_right_hp_mixer_controls[0], 1042 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 1043 1044 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 1045 &max98088_left_speaker_mixer_controls[0], 1046 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 1047 1048 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 1049 &max98088_right_speaker_mixer_controls[0], 1050 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 1051 1052 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 1053 &max98088_left_rec_mixer_controls[0], 1054 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 1055 1056 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 1057 &max98088_right_rec_mixer_controls[0], 1058 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 1059 1060 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1061 &max98088_left_ADC_mixer_controls[0], 1062 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 1063 1064 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1065 &max98088_right_ADC_mixer_controls[0], 1066 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 1067 1068 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 1069 5, 0, NULL, 0, max98088_mic_event, 1070 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1071 1072 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 1073 5, 0, NULL, 0, max98088_mic_event, 1074 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1075 1076 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 1077 7, 0, NULL, 0, max98088_pga_ina1_event, 1078 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1079 1080 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 1081 7, 0, NULL, 0, max98088_pga_ina2_event, 1082 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1083 1084 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 1085 6, 0, NULL, 0, max98088_pga_inb1_event, 1086 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1087 1088 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 1089 6, 0, NULL, 0, max98088_pga_inb2_event, 1090 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1091 1092 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 1093 1094 SND_SOC_DAPM_OUTPUT("HPL"), 1095 SND_SOC_DAPM_OUTPUT("HPR"), 1096 SND_SOC_DAPM_OUTPUT("SPKL"), 1097 SND_SOC_DAPM_OUTPUT("SPKR"), 1098 SND_SOC_DAPM_OUTPUT("RECL"), 1099 SND_SOC_DAPM_OUTPUT("RECR"), 1100 1101 SND_SOC_DAPM_INPUT("MIC1"), 1102 SND_SOC_DAPM_INPUT("MIC2"), 1103 SND_SOC_DAPM_INPUT("INA1"), 1104 SND_SOC_DAPM_INPUT("INA2"), 1105 SND_SOC_DAPM_INPUT("INB1"), 1106 SND_SOC_DAPM_INPUT("INB2"), 1107 }; 1108 1109 static const struct snd_soc_dapm_route max98088_audio_map[] = { 1110 /* Left headphone output mixer */ 1111 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"}, 1112 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"}, 1113 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"}, 1114 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"}, 1115 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1116 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1117 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 1118 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 1119 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 1120 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 1121 1122 /* Right headphone output mixer */ 1123 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"}, 1124 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" }, 1125 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"}, 1126 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"}, 1127 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1128 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1129 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 1130 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 1131 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 1132 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 1133 1134 /* Left speaker output mixer */ 1135 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1136 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1137 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1138 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1139 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1140 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1141 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 1142 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 1143 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 1144 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 1145 1146 /* Right speaker output mixer */ 1147 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1148 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1149 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1150 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1151 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1152 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1153 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 1154 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 1155 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 1156 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 1157 1158 /* Earpiece/Receiver output mixer */ 1159 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"}, 1160 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"}, 1161 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"}, 1162 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"}, 1163 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1164 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1165 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 1166 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 1167 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 1168 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 1169 1170 /* Earpiece/Receiver output mixer */ 1171 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"}, 1172 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"}, 1173 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"}, 1174 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"}, 1175 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1176 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1177 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 1178 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 1179 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 1180 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 1181 1182 {"HP Left Out", NULL, "Left HP Mixer"}, 1183 {"HP Right Out", NULL, "Right HP Mixer"}, 1184 {"SPK Left Out", NULL, "Left SPK Mixer"}, 1185 {"SPK Right Out", NULL, "Right SPK Mixer"}, 1186 {"REC Left Out", NULL, "Left REC Mixer"}, 1187 {"REC Right Out", NULL, "Right REC Mixer"}, 1188 1189 {"HPL", NULL, "HP Left Out"}, 1190 {"HPR", NULL, "HP Right Out"}, 1191 {"SPKL", NULL, "SPK Left Out"}, 1192 {"SPKR", NULL, "SPK Right Out"}, 1193 {"RECL", NULL, "REC Left Out"}, 1194 {"RECR", NULL, "REC Right Out"}, 1195 1196 /* Left ADC input mixer */ 1197 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1198 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1199 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 1200 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 1201 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 1202 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 1203 1204 /* Right ADC input mixer */ 1205 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1206 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1207 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 1208 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 1209 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 1210 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 1211 1212 /* Inputs */ 1213 {"ADCL", NULL, "Left ADC Mixer"}, 1214 {"ADCR", NULL, "Right ADC Mixer"}, 1215 {"INA1 Input", NULL, "INA1"}, 1216 {"INA2 Input", NULL, "INA2"}, 1217 {"INB1 Input", NULL, "INB1"}, 1218 {"INB2 Input", NULL, "INB2"}, 1219 {"MIC1 Input", NULL, "MIC1"}, 1220 {"MIC2 Input", NULL, "MIC2"}, 1221 }; 1222 1223 /* codec mclk clock divider coefficients */ 1224 static const struct { 1225 u32 rate; 1226 u8 sr; 1227 } rate_table[] = { 1228 {8000, 0x10}, 1229 {11025, 0x20}, 1230 {16000, 0x30}, 1231 {22050, 0x40}, 1232 {24000, 0x50}, 1233 {32000, 0x60}, 1234 {44100, 0x70}, 1235 {48000, 0x80}, 1236 {88200, 0x90}, 1237 {96000, 0xA0}, 1238 }; 1239 1240 static inline int rate_value(int rate, u8 *value) 1241 { 1242 int i; 1243 1244 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1245 if (rate_table[i].rate >= rate) { 1246 *value = rate_table[i].sr; 1247 return 0; 1248 } 1249 } 1250 *value = rate_table[0].sr; 1251 return -EINVAL; 1252 } 1253 1254 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 1255 struct snd_pcm_hw_params *params, 1256 struct snd_soc_dai *dai) 1257 { 1258 struct snd_soc_codec *codec = dai->codec; 1259 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1260 struct max98088_cdata *cdata; 1261 unsigned long long ni; 1262 unsigned int rate; 1263 u8 regval; 1264 1265 cdata = &max98088->dai[0]; 1266 1267 rate = params_rate(params); 1268 1269 switch (params_format(params)) { 1270 case SNDRV_PCM_FORMAT_S16_LE: 1271 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1272 M98088_DAI_WS, 0); 1273 break; 1274 case SNDRV_PCM_FORMAT_S24_LE: 1275 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1276 M98088_DAI_WS, M98088_DAI_WS); 1277 break; 1278 default: 1279 return -EINVAL; 1280 } 1281 1282 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1283 1284 if (rate_value(rate, ®val)) 1285 return -EINVAL; 1286 1287 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE, 1288 M98088_CLKMODE_MASK, regval); 1289 cdata->rate = rate; 1290 1291 /* Configure NI when operating as master */ 1292 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT) 1293 & M98088_DAI_MAS) { 1294 if (max98088->sysclk == 0) { 1295 dev_err(codec->dev, "Invalid system clock frequency\n"); 1296 return -EINVAL; 1297 } 1298 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1299 * (unsigned long long int)rate; 1300 do_div(ni, (unsigned long long int)max98088->sysclk); 1301 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1302 (ni >> 8) & 0x7F); 1303 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1304 ni & 0xFF); 1305 } 1306 1307 /* Update sample rate mode */ 1308 if (rate < 50000) 1309 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1310 M98088_DAI_DHF, 0); 1311 else 1312 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1313 M98088_DAI_DHF, M98088_DAI_DHF); 1314 1315 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1316 M98088_SHDNRUN); 1317 1318 return 0; 1319 } 1320 1321 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1322 struct snd_pcm_hw_params *params, 1323 struct snd_soc_dai *dai) 1324 { 1325 struct snd_soc_codec *codec = dai->codec; 1326 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1327 struct max98088_cdata *cdata; 1328 unsigned long long ni; 1329 unsigned int rate; 1330 u8 regval; 1331 1332 cdata = &max98088->dai[1]; 1333 1334 rate = params_rate(params); 1335 1336 switch (params_format(params)) { 1337 case SNDRV_PCM_FORMAT_S16_LE: 1338 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1339 M98088_DAI_WS, 0); 1340 break; 1341 case SNDRV_PCM_FORMAT_S24_LE: 1342 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1343 M98088_DAI_WS, M98088_DAI_WS); 1344 break; 1345 default: 1346 return -EINVAL; 1347 } 1348 1349 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1350 1351 if (rate_value(rate, ®val)) 1352 return -EINVAL; 1353 1354 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE, 1355 M98088_CLKMODE_MASK, regval); 1356 cdata->rate = rate; 1357 1358 /* Configure NI when operating as master */ 1359 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT) 1360 & M98088_DAI_MAS) { 1361 if (max98088->sysclk == 0) { 1362 dev_err(codec->dev, "Invalid system clock frequency\n"); 1363 return -EINVAL; 1364 } 1365 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1366 * (unsigned long long int)rate; 1367 do_div(ni, (unsigned long long int)max98088->sysclk); 1368 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1369 (ni >> 8) & 0x7F); 1370 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1371 ni & 0xFF); 1372 } 1373 1374 /* Update sample rate mode */ 1375 if (rate < 50000) 1376 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1377 M98088_DAI_DHF, 0); 1378 else 1379 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1380 M98088_DAI_DHF, M98088_DAI_DHF); 1381 1382 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1383 M98088_SHDNRUN); 1384 1385 return 0; 1386 } 1387 1388 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1389 int clk_id, unsigned int freq, int dir) 1390 { 1391 struct snd_soc_codec *codec = dai->codec; 1392 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1393 1394 /* Requested clock frequency is already setup */ 1395 if (freq == max98088->sysclk) 1396 return 0; 1397 1398 /* Setup clocks for slave mode, and using the PLL 1399 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1400 * 0x02 (when master clk is 20MHz to 30MHz).. 1401 */ 1402 if ((freq >= 10000000) && (freq < 20000000)) { 1403 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10); 1404 } else if ((freq >= 20000000) && (freq < 30000000)) { 1405 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20); 1406 } else { 1407 dev_err(codec->dev, "Invalid master clock frequency\n"); 1408 return -EINVAL; 1409 } 1410 1411 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1412 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1413 M98088_SHDNRUN, 0); 1414 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1415 M98088_SHDNRUN, M98088_SHDNRUN); 1416 } 1417 1418 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1419 1420 max98088->sysclk = freq; 1421 return 0; 1422 } 1423 1424 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1425 unsigned int fmt) 1426 { 1427 struct snd_soc_codec *codec = codec_dai->codec; 1428 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1429 struct max98088_cdata *cdata; 1430 u8 reg15val; 1431 u8 reg14val = 0; 1432 1433 cdata = &max98088->dai[0]; 1434 1435 if (fmt != cdata->fmt) { 1436 cdata->fmt = fmt; 1437 1438 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1439 case SND_SOC_DAIFMT_CBS_CFS: 1440 /* Slave mode PLL */ 1441 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1442 0x80); 1443 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1444 0x00); 1445 break; 1446 case SND_SOC_DAIFMT_CBM_CFM: 1447 /* Set to master mode */ 1448 reg14val |= M98088_DAI_MAS; 1449 break; 1450 case SND_SOC_DAIFMT_CBS_CFM: 1451 case SND_SOC_DAIFMT_CBM_CFS: 1452 default: 1453 dev_err(codec->dev, "Clock mode unsupported"); 1454 return -EINVAL; 1455 } 1456 1457 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1458 case SND_SOC_DAIFMT_I2S: 1459 reg14val |= M98088_DAI_DLY; 1460 break; 1461 case SND_SOC_DAIFMT_LEFT_J: 1462 break; 1463 default: 1464 return -EINVAL; 1465 } 1466 1467 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1468 case SND_SOC_DAIFMT_NB_NF: 1469 break; 1470 case SND_SOC_DAIFMT_NB_IF: 1471 reg14val |= M98088_DAI_WCI; 1472 break; 1473 case SND_SOC_DAIFMT_IB_NF: 1474 reg14val |= M98088_DAI_BCI; 1475 break; 1476 case SND_SOC_DAIFMT_IB_IF: 1477 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1478 break; 1479 default: 1480 return -EINVAL; 1481 } 1482 1483 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1484 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1485 M98088_DAI_WCI, reg14val); 1486 1487 reg15val = M98088_DAI_BSEL64; 1488 if (max98088->digmic) 1489 reg15val |= M98088_DAI_OSR64; 1490 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val); 1491 } 1492 1493 return 0; 1494 } 1495 1496 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1497 unsigned int fmt) 1498 { 1499 struct snd_soc_codec *codec = codec_dai->codec; 1500 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1501 struct max98088_cdata *cdata; 1502 u8 reg1Cval = 0; 1503 1504 cdata = &max98088->dai[1]; 1505 1506 if (fmt != cdata->fmt) { 1507 cdata->fmt = fmt; 1508 1509 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1510 case SND_SOC_DAIFMT_CBS_CFS: 1511 /* Slave mode PLL */ 1512 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1513 0x80); 1514 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1515 0x00); 1516 break; 1517 case SND_SOC_DAIFMT_CBM_CFM: 1518 /* Set to master mode */ 1519 reg1Cval |= M98088_DAI_MAS; 1520 break; 1521 case SND_SOC_DAIFMT_CBS_CFM: 1522 case SND_SOC_DAIFMT_CBM_CFS: 1523 default: 1524 dev_err(codec->dev, "Clock mode unsupported"); 1525 return -EINVAL; 1526 } 1527 1528 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1529 case SND_SOC_DAIFMT_I2S: 1530 reg1Cval |= M98088_DAI_DLY; 1531 break; 1532 case SND_SOC_DAIFMT_LEFT_J: 1533 break; 1534 default: 1535 return -EINVAL; 1536 } 1537 1538 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1539 case SND_SOC_DAIFMT_NB_NF: 1540 break; 1541 case SND_SOC_DAIFMT_NB_IF: 1542 reg1Cval |= M98088_DAI_WCI; 1543 break; 1544 case SND_SOC_DAIFMT_IB_NF: 1545 reg1Cval |= M98088_DAI_BCI; 1546 break; 1547 case SND_SOC_DAIFMT_IB_IF: 1548 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1549 break; 1550 default: 1551 return -EINVAL; 1552 } 1553 1554 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1555 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1556 M98088_DAI_WCI, reg1Cval); 1557 1558 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK, 1559 M98088_DAI_BSEL64); 1560 } 1561 1562 return 0; 1563 } 1564 1565 static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1566 { 1567 struct snd_soc_codec *codec = codec_dai->codec; 1568 int reg; 1569 1570 if (mute) 1571 reg = M98088_DAI_MUTE; 1572 else 1573 reg = 0; 1574 1575 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY, 1576 M98088_DAI_MUTE_MASK, reg); 1577 return 0; 1578 } 1579 1580 static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1581 { 1582 struct snd_soc_codec *codec = codec_dai->codec; 1583 int reg; 1584 1585 if (mute) 1586 reg = M98088_DAI_MUTE; 1587 else 1588 reg = 0; 1589 1590 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY, 1591 M98088_DAI_MUTE_MASK, reg); 1592 return 0; 1593 } 1594 1595 static void max98088_sync_cache(struct snd_soc_codec *codec) 1596 { 1597 u16 *reg_cache = codec->reg_cache; 1598 int i; 1599 1600 if (!codec->cache_sync) 1601 return; 1602 1603 codec->cache_only = 0; 1604 1605 /* write back cached values if they're writeable and 1606 * different from the hardware default. 1607 */ 1608 for (i = 1; i < codec->driver->reg_cache_size; i++) { 1609 if (!max98088_access[i].writable) 1610 continue; 1611 1612 if (reg_cache[i] == max98088_reg[i]) 1613 continue; 1614 1615 snd_soc_write(codec, i, reg_cache[i]); 1616 } 1617 1618 codec->cache_sync = 0; 1619 } 1620 1621 static int max98088_set_bias_level(struct snd_soc_codec *codec, 1622 enum snd_soc_bias_level level) 1623 { 1624 switch (level) { 1625 case SND_SOC_BIAS_ON: 1626 break; 1627 1628 case SND_SOC_BIAS_PREPARE: 1629 break; 1630 1631 case SND_SOC_BIAS_STANDBY: 1632 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 1633 max98088_sync_cache(codec); 1634 1635 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1636 M98088_MBEN, M98088_MBEN); 1637 break; 1638 1639 case SND_SOC_BIAS_OFF: 1640 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1641 M98088_MBEN, 0); 1642 codec->cache_sync = 1; 1643 break; 1644 } 1645 codec->dapm.bias_level = level; 1646 return 0; 1647 } 1648 1649 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1650 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1651 1652 static const struct snd_soc_dai_ops max98088_dai1_ops = { 1653 .set_sysclk = max98088_dai_set_sysclk, 1654 .set_fmt = max98088_dai1_set_fmt, 1655 .hw_params = max98088_dai1_hw_params, 1656 .digital_mute = max98088_dai1_digital_mute, 1657 }; 1658 1659 static const struct snd_soc_dai_ops max98088_dai2_ops = { 1660 .set_sysclk = max98088_dai_set_sysclk, 1661 .set_fmt = max98088_dai2_set_fmt, 1662 .hw_params = max98088_dai2_hw_params, 1663 .digital_mute = max98088_dai2_digital_mute, 1664 }; 1665 1666 static struct snd_soc_dai_driver max98088_dai[] = { 1667 { 1668 .name = "HiFi", 1669 .playback = { 1670 .stream_name = "HiFi Playback", 1671 .channels_min = 1, 1672 .channels_max = 2, 1673 .rates = MAX98088_RATES, 1674 .formats = MAX98088_FORMATS, 1675 }, 1676 .capture = { 1677 .stream_name = "HiFi Capture", 1678 .channels_min = 1, 1679 .channels_max = 2, 1680 .rates = MAX98088_RATES, 1681 .formats = MAX98088_FORMATS, 1682 }, 1683 .ops = &max98088_dai1_ops, 1684 }, 1685 { 1686 .name = "Aux", 1687 .playback = { 1688 .stream_name = "Aux Playback", 1689 .channels_min = 1, 1690 .channels_max = 2, 1691 .rates = MAX98088_RATES, 1692 .formats = MAX98088_FORMATS, 1693 }, 1694 .ops = &max98088_dai2_ops, 1695 } 1696 }; 1697 1698 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; 1699 1700 static int max98088_get_channel(struct snd_soc_codec *codec, const char *name) 1701 { 1702 int i; 1703 1704 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++) 1705 if (strcmp(name, eq_mode_name[i]) == 0) 1706 return i; 1707 1708 /* Shouldn't happen */ 1709 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name); 1710 return -EINVAL; 1711 } 1712 1713 static void max98088_setup_eq1(struct snd_soc_codec *codec) 1714 { 1715 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1716 struct max98088_pdata *pdata = max98088->pdata; 1717 struct max98088_eq_cfg *coef_set; 1718 int best, best_val, save, i, sel, fs; 1719 struct max98088_cdata *cdata; 1720 1721 cdata = &max98088->dai[0]; 1722 1723 if (!pdata || !max98088->eq_textcnt) 1724 return; 1725 1726 /* Find the selected configuration with nearest sample rate */ 1727 fs = cdata->rate; 1728 sel = cdata->eq_sel; 1729 1730 best = 0; 1731 best_val = INT_MAX; 1732 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1733 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1734 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1735 best = i; 1736 best_val = abs(pdata->eq_cfg[i].rate - fs); 1737 } 1738 } 1739 1740 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1741 pdata->eq_cfg[best].name, 1742 pdata->eq_cfg[best].rate, fs); 1743 1744 /* Disable EQ while configuring, and save current on/off state */ 1745 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1746 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1747 1748 coef_set = &pdata->eq_cfg[sel]; 1749 1750 m98088_eq_band(codec, 0, 0, coef_set->band1); 1751 m98088_eq_band(codec, 0, 1, coef_set->band2); 1752 m98088_eq_band(codec, 0, 2, coef_set->band3); 1753 m98088_eq_band(codec, 0, 3, coef_set->band4); 1754 m98088_eq_band(codec, 0, 4, coef_set->band5); 1755 1756 /* Restore the original on/off state */ 1757 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1758 } 1759 1760 static void max98088_setup_eq2(struct snd_soc_codec *codec) 1761 { 1762 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1763 struct max98088_pdata *pdata = max98088->pdata; 1764 struct max98088_eq_cfg *coef_set; 1765 int best, best_val, save, i, sel, fs; 1766 struct max98088_cdata *cdata; 1767 1768 cdata = &max98088->dai[1]; 1769 1770 if (!pdata || !max98088->eq_textcnt) 1771 return; 1772 1773 /* Find the selected configuration with nearest sample rate */ 1774 fs = cdata->rate; 1775 1776 sel = cdata->eq_sel; 1777 best = 0; 1778 best_val = INT_MAX; 1779 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1780 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1781 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1782 best = i; 1783 best_val = abs(pdata->eq_cfg[i].rate - fs); 1784 } 1785 } 1786 1787 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1788 pdata->eq_cfg[best].name, 1789 pdata->eq_cfg[best].rate, fs); 1790 1791 /* Disable EQ while configuring, and save current on/off state */ 1792 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1793 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1794 1795 coef_set = &pdata->eq_cfg[sel]; 1796 1797 m98088_eq_band(codec, 1, 0, coef_set->band1); 1798 m98088_eq_band(codec, 1, 1, coef_set->band2); 1799 m98088_eq_band(codec, 1, 2, coef_set->band3); 1800 m98088_eq_band(codec, 1, 3, coef_set->band4); 1801 m98088_eq_band(codec, 1, 4, coef_set->band5); 1802 1803 /* Restore the original on/off state */ 1804 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1805 save); 1806 } 1807 1808 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1809 struct snd_ctl_elem_value *ucontrol) 1810 { 1811 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1812 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1813 struct max98088_pdata *pdata = max98088->pdata; 1814 int channel = max98088_get_channel(codec, kcontrol->id.name); 1815 struct max98088_cdata *cdata; 1816 int sel = ucontrol->value.integer.value[0]; 1817 1818 if (channel < 0) 1819 return channel; 1820 1821 cdata = &max98088->dai[channel]; 1822 1823 if (sel >= pdata->eq_cfgcnt) 1824 return -EINVAL; 1825 1826 cdata->eq_sel = sel; 1827 1828 switch (channel) { 1829 case 0: 1830 max98088_setup_eq1(codec); 1831 break; 1832 case 1: 1833 max98088_setup_eq2(codec); 1834 break; 1835 } 1836 1837 return 0; 1838 } 1839 1840 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1841 struct snd_ctl_elem_value *ucontrol) 1842 { 1843 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1844 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1845 int channel = max98088_get_channel(codec, kcontrol->id.name); 1846 struct max98088_cdata *cdata; 1847 1848 if (channel < 0) 1849 return channel; 1850 1851 cdata = &max98088->dai[channel]; 1852 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1853 return 0; 1854 } 1855 1856 static void max98088_handle_eq_pdata(struct snd_soc_codec *codec) 1857 { 1858 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1859 struct max98088_pdata *pdata = max98088->pdata; 1860 struct max98088_eq_cfg *cfg; 1861 unsigned int cfgcnt; 1862 int i, j; 1863 const char **t; 1864 int ret; 1865 struct snd_kcontrol_new controls[] = { 1866 SOC_ENUM_EXT((char *)eq_mode_name[0], 1867 max98088->eq_enum, 1868 max98088_get_eq_enum, 1869 max98088_put_eq_enum), 1870 SOC_ENUM_EXT((char *)eq_mode_name[1], 1871 max98088->eq_enum, 1872 max98088_get_eq_enum, 1873 max98088_put_eq_enum), 1874 }; 1875 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name)); 1876 1877 cfg = pdata->eq_cfg; 1878 cfgcnt = pdata->eq_cfgcnt; 1879 1880 /* Setup an array of texts for the equalizer enum. 1881 * This is based on Mark Brown's equalizer driver code. 1882 */ 1883 max98088->eq_textcnt = 0; 1884 max98088->eq_texts = NULL; 1885 for (i = 0; i < cfgcnt; i++) { 1886 for (j = 0; j < max98088->eq_textcnt; j++) { 1887 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1888 break; 1889 } 1890 1891 if (j != max98088->eq_textcnt) 1892 continue; 1893 1894 /* Expand the array */ 1895 t = krealloc(max98088->eq_texts, 1896 sizeof(char *) * (max98088->eq_textcnt + 1), 1897 GFP_KERNEL); 1898 if (t == NULL) 1899 continue; 1900 1901 /* Store the new entry */ 1902 t[max98088->eq_textcnt] = cfg[i].name; 1903 max98088->eq_textcnt++; 1904 max98088->eq_texts = t; 1905 } 1906 1907 /* Now point the soc_enum to .texts array items */ 1908 max98088->eq_enum.texts = max98088->eq_texts; 1909 max98088->eq_enum.max = max98088->eq_textcnt; 1910 1911 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1912 if (ret != 0) 1913 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1914 } 1915 1916 static void max98088_handle_pdata(struct snd_soc_codec *codec) 1917 { 1918 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1919 struct max98088_pdata *pdata = max98088->pdata; 1920 u8 regval = 0; 1921 1922 if (!pdata) { 1923 dev_dbg(codec->dev, "No platform data\n"); 1924 return; 1925 } 1926 1927 /* Configure mic for analog/digital mic mode */ 1928 if (pdata->digmic_left_mode) 1929 regval |= M98088_DIGMIC_L; 1930 1931 if (pdata->digmic_right_mode) 1932 regval |= M98088_DIGMIC_R; 1933 1934 max98088->digmic = (regval ? 1 : 0); 1935 1936 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval); 1937 1938 /* Configure receiver output */ 1939 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1940 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL, 1941 M98088_REC_LINEMODE_MASK, regval); 1942 1943 /* Configure equalizers */ 1944 if (pdata->eq_cfgcnt) 1945 max98088_handle_eq_pdata(codec); 1946 } 1947 1948 #ifdef CONFIG_PM 1949 static int max98088_suspend(struct snd_soc_codec *codec) 1950 { 1951 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); 1952 1953 return 0; 1954 } 1955 1956 static int max98088_resume(struct snd_soc_codec *codec) 1957 { 1958 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1959 1960 return 0; 1961 } 1962 #else 1963 #define max98088_suspend NULL 1964 #define max98088_resume NULL 1965 #endif 1966 1967 static int max98088_probe(struct snd_soc_codec *codec) 1968 { 1969 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1970 struct max98088_cdata *cdata; 1971 int ret = 0; 1972 1973 codec->cache_sync = 1; 1974 1975 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1976 if (ret != 0) { 1977 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1978 return ret; 1979 } 1980 1981 /* initialize private data */ 1982 1983 max98088->sysclk = (unsigned)-1; 1984 max98088->eq_textcnt = 0; 1985 1986 cdata = &max98088->dai[0]; 1987 cdata->rate = (unsigned)-1; 1988 cdata->fmt = (unsigned)-1; 1989 cdata->eq_sel = 0; 1990 1991 cdata = &max98088->dai[1]; 1992 cdata->rate = (unsigned)-1; 1993 cdata->fmt = (unsigned)-1; 1994 cdata->eq_sel = 0; 1995 1996 max98088->ina_state = 0; 1997 max98088->inb_state = 0; 1998 max98088->ex_mode = 0; 1999 max98088->digmic = 0; 2000 max98088->mic1pre = 0; 2001 max98088->mic2pre = 0; 2002 2003 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID); 2004 if (ret < 0) { 2005 dev_err(codec->dev, "Failed to read device revision: %d\n", 2006 ret); 2007 goto err_access; 2008 } 2009 dev_info(codec->dev, "revision %c\n", ret + 'A'); 2010 2011 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV); 2012 2013 /* initialize registers cache to hardware default */ 2014 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2015 2016 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00); 2017 2018 snd_soc_write(codec, M98088_REG_22_MIX_DAC, 2019 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 2020 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 2021 2022 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0); 2023 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F); 2024 2025 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG, 2026 M98088_S1NORMAL|M98088_SDATA); 2027 2028 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG, 2029 M98088_S2NORMAL|M98088_SDATA); 2030 2031 max98088_handle_pdata(codec); 2032 2033 snd_soc_add_codec_controls(codec, max98088_snd_controls, 2034 ARRAY_SIZE(max98088_snd_controls)); 2035 2036 err_access: 2037 return ret; 2038 } 2039 2040 static int max98088_remove(struct snd_soc_codec *codec) 2041 { 2042 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 2043 2044 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); 2045 kfree(max98088->eq_texts); 2046 2047 return 0; 2048 } 2049 2050 static struct snd_soc_codec_driver soc_codec_dev_max98088 = { 2051 .probe = max98088_probe, 2052 .remove = max98088_remove, 2053 .suspend = max98088_suspend, 2054 .resume = max98088_resume, 2055 .set_bias_level = max98088_set_bias_level, 2056 .reg_cache_size = ARRAY_SIZE(max98088_reg), 2057 .reg_word_size = sizeof(u8), 2058 .reg_cache_default = max98088_reg, 2059 .volatile_register = max98088_volatile_register, 2060 .dapm_widgets = max98088_dapm_widgets, 2061 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 2062 .dapm_routes = max98088_audio_map, 2063 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map), 2064 }; 2065 2066 static int max98088_i2c_probe(struct i2c_client *i2c, 2067 const struct i2c_device_id *id) 2068 { 2069 struct max98088_priv *max98088; 2070 int ret; 2071 2072 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv), 2073 GFP_KERNEL); 2074 if (max98088 == NULL) 2075 return -ENOMEM; 2076 2077 max98088->devtype = id->driver_data; 2078 2079 i2c_set_clientdata(i2c, max98088); 2080 max98088->pdata = i2c->dev.platform_data; 2081 2082 ret = snd_soc_register_codec(&i2c->dev, 2083 &soc_codec_dev_max98088, &max98088_dai[0], 2); 2084 return ret; 2085 } 2086 2087 static int max98088_i2c_remove(struct i2c_client *client) 2088 { 2089 snd_soc_unregister_codec(&client->dev); 2090 return 0; 2091 } 2092 2093 static const struct i2c_device_id max98088_i2c_id[] = { 2094 { "max98088", MAX98088 }, 2095 { "max98089", MAX98089 }, 2096 { } 2097 }; 2098 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 2099 2100 static struct i2c_driver max98088_i2c_driver = { 2101 .driver = { 2102 .name = "max98088", 2103 .owner = THIS_MODULE, 2104 }, 2105 .probe = max98088_i2c_probe, 2106 .remove = max98088_i2c_remove, 2107 .id_table = max98088_i2c_id, 2108 }; 2109 2110 module_i2c_driver(max98088_i2c_driver); 2111 2112 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 2113 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 2114 MODULE_LICENSE("GPL"); 2115