1 /* 2 * max98088.c -- MAX98088 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <linux/slab.h> 26 #include <asm/div64.h> 27 #include <sound/max98088.h> 28 #include "max98088.h" 29 30 enum max98088_type { 31 MAX98088, 32 MAX98089, 33 }; 34 35 struct max98088_cdata { 36 unsigned int rate; 37 unsigned int fmt; 38 int eq_sel; 39 }; 40 41 struct max98088_priv { 42 struct regmap *regmap; 43 enum max98088_type devtype; 44 struct max98088_pdata *pdata; 45 unsigned int sysclk; 46 struct max98088_cdata dai[2]; 47 int eq_textcnt; 48 const char **eq_texts; 49 struct soc_enum eq_enum; 50 u8 ina_state; 51 u8 inb_state; 52 unsigned int ex_mode; 53 unsigned int digmic; 54 unsigned int mic1pre; 55 unsigned int mic2pre; 56 unsigned int extmic_mode; 57 }; 58 59 static const struct reg_default max98088_reg[] = { 60 { 0xf, 0x00 }, /* 0F interrupt enable */ 61 62 { 0x10, 0x00 }, /* 10 master clock */ 63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */ 64 { 0x12, 0x00 }, /* 12 DAI1 clock control */ 65 { 0x13, 0x00 }, /* 13 DAI1 clock control */ 66 { 0x14, 0x00 }, /* 14 DAI1 format */ 67 { 0x15, 0x00 }, /* 15 DAI1 clock */ 68 { 0x16, 0x00 }, /* 16 DAI1 config */ 69 { 0x17, 0x00 }, /* 17 DAI1 TDM */ 70 { 0x18, 0x00 }, /* 18 DAI1 filters */ 71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */ 72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */ 73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */ 74 { 0x1c, 0x00 }, /* 1C DAI2 format */ 75 { 0x1d, 0x00 }, /* 1D DAI2 clock */ 76 { 0x1e, 0x00 }, /* 1E DAI2 config */ 77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */ 78 79 { 0x20, 0x00 }, /* 20 DAI2 filters */ 80 { 0x21, 0x00 }, /* 21 data config */ 81 { 0x22, 0x00 }, /* 22 DAC mixer */ 82 { 0x23, 0x00 }, /* 23 left ADC mixer */ 83 { 0x24, 0x00 }, /* 24 right ADC mixer */ 84 { 0x25, 0x00 }, /* 25 left HP mixer */ 85 { 0x26, 0x00 }, /* 26 right HP mixer */ 86 { 0x27, 0x00 }, /* 27 HP control */ 87 { 0x28, 0x00 }, /* 28 left REC mixer */ 88 { 0x29, 0x00 }, /* 29 right REC mixer */ 89 { 0x2a, 0x00 }, /* 2A REC control */ 90 { 0x2b, 0x00 }, /* 2B left SPK mixer */ 91 { 0x2c, 0x00 }, /* 2C right SPK mixer */ 92 { 0x2d, 0x00 }, /* 2D SPK control */ 93 { 0x2e, 0x00 }, /* 2E sidetone */ 94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */ 95 96 { 0x30, 0x00 }, /* 30 DAI1 playback level */ 97 { 0x31, 0x00 }, /* 31 DAI2 playback level */ 98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */ 99 { 0x33, 0x00 }, /* 33 left ADC level */ 100 { 0x34, 0x00 }, /* 34 right ADC level */ 101 { 0x35, 0x00 }, /* 35 MIC1 level */ 102 { 0x36, 0x00 }, /* 36 MIC2 level */ 103 { 0x37, 0x00 }, /* 37 INA level */ 104 { 0x38, 0x00 }, /* 38 INB level */ 105 { 0x39, 0x00 }, /* 39 left HP volume */ 106 { 0x3a, 0x00 }, /* 3A right HP volume */ 107 { 0x3b, 0x00 }, /* 3B left REC volume */ 108 { 0x3c, 0x00 }, /* 3C right REC volume */ 109 { 0x3d, 0x00 }, /* 3D left SPK volume */ 110 { 0x3e, 0x00 }, /* 3E right SPK volume */ 111 { 0x3f, 0x00 }, /* 3F MIC config */ 112 113 { 0x40, 0x00 }, /* 40 MIC threshold */ 114 { 0x41, 0x00 }, /* 41 excursion limiter filter */ 115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */ 116 { 0x43, 0x00 }, /* 43 ALC */ 117 { 0x44, 0x00 }, /* 44 power limiter threshold */ 118 { 0x45, 0x00 }, /* 45 power limiter config */ 119 { 0x46, 0x00 }, /* 46 distortion limiter config */ 120 { 0x47, 0x00 }, /* 47 audio input */ 121 { 0x48, 0x00 }, /* 48 microphone */ 122 { 0x49, 0x00 }, /* 49 level control */ 123 { 0x4a, 0x00 }, /* 4A bypass switches */ 124 { 0x4b, 0x00 }, /* 4B jack detect */ 125 { 0x4c, 0x00 }, /* 4C input enable */ 126 { 0x4d, 0x00 }, /* 4D output enable */ 127 { 0x4e, 0xF0 }, /* 4E bias control */ 128 { 0x4f, 0x00 }, /* 4F DAC power */ 129 130 { 0x50, 0x0F }, /* 50 DAC power */ 131 { 0x51, 0x00 }, /* 51 system */ 132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */ 133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */ 134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */ 135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */ 136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */ 137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */ 138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */ 139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */ 140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */ 141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */ 142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */ 143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */ 144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */ 145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */ 146 147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */ 148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */ 149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */ 150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */ 151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */ 152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */ 153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */ 154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */ 155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */ 156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */ 157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */ 158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */ 159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */ 160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */ 161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */ 162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */ 163 164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */ 165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */ 166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */ 167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */ 168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */ 169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */ 170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */ 171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */ 172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */ 173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */ 174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */ 175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */ 176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */ 177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */ 178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */ 179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */ 180 181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */ 182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */ 183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */ 184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */ 185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */ 186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */ 187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */ 188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */ 189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */ 190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */ 191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */ 192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */ 193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */ 194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */ 195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */ 196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */ 197 198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */ 199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */ 200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */ 201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */ 202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */ 203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */ 204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */ 205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */ 206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */ 207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */ 208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */ 209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */ 210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */ 211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */ 212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */ 213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */ 214 215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */ 216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */ 217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */ 218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */ 219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */ 220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */ 221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */ 222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */ 223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */ 224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */ 225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */ 226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */ 227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */ 228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */ 229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */ 230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */ 231 232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */ 233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */ 234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */ 235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */ 236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */ 237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */ 238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */ 239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */ 240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */ 241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */ 242 { 0xba, 0x00 }, /* BA DAI1 biquad */ 243 { 0xbb, 0x00 }, /* BB DAI1 biquad */ 244 { 0xbc, 0x00 }, /* BC DAI1 biquad */ 245 { 0xbd, 0x00 }, /* BD DAI1 biquad */ 246 { 0xbe, 0x00 }, /* BE DAI1 biquad */ 247 { 0xbf, 0x00 }, /* BF DAI1 biquad */ 248 249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */ 250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */ 251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */ 252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */ 253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */ 254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */ 255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */ 256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */ 257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */ 258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */ 259 }; 260 261 static struct { 262 int readable; 263 int writable; 264 int vol; 265 } max98088_access[M98088_REG_CNT] = { 266 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ 267 { 0xFF, 0x00, 1 }, /* 01 MIC status */ 268 { 0xFF, 0x00, 1 }, /* 02 jack status */ 269 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ 270 { 0xFF, 0xFF, 0 }, /* 04 */ 271 { 0xFF, 0xFF, 0 }, /* 05 */ 272 { 0xFF, 0xFF, 0 }, /* 06 */ 273 { 0xFF, 0xFF, 0 }, /* 07 */ 274 { 0xFF, 0xFF, 0 }, /* 08 */ 275 { 0xFF, 0xFF, 0 }, /* 09 */ 276 { 0xFF, 0xFF, 0 }, /* 0A */ 277 { 0xFF, 0xFF, 0 }, /* 0B */ 278 { 0xFF, 0xFF, 0 }, /* 0C */ 279 { 0xFF, 0xFF, 0 }, /* 0D */ 280 { 0xFF, 0xFF, 0 }, /* 0E */ 281 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ 282 283 { 0xFF, 0xFF, 0 }, /* 10 master clock */ 284 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ 285 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ 286 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ 287 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ 288 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ 289 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ 290 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ 291 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ 292 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ 293 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ 294 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ 295 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ 296 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ 297 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ 298 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ 299 300 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ 301 { 0xFF, 0xFF, 0 }, /* 21 data config */ 302 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ 303 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ 304 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ 305 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ 306 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ 307 { 0xFF, 0xFF, 0 }, /* 27 HP control */ 308 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ 309 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ 310 { 0xFF, 0xFF, 0 }, /* 2A REC control */ 311 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ 312 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ 313 { 0xFF, 0xFF, 0 }, /* 2D SPK control */ 314 { 0xFF, 0xFF, 0 }, /* 2E sidetone */ 315 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ 316 317 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ 318 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ 319 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ 320 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ 321 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ 322 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ 323 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ 324 { 0xFF, 0xFF, 0 }, /* 37 INA level */ 325 { 0xFF, 0xFF, 0 }, /* 38 INB level */ 326 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ 327 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ 328 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ 329 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ 330 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ 331 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ 332 { 0xFF, 0xFF, 0 }, /* 3F MIC config */ 333 334 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ 335 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ 336 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ 337 { 0xFF, 0xFF, 0 }, /* 43 ALC */ 338 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ 339 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ 340 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ 341 { 0xFF, 0xFF, 0 }, /* 47 audio input */ 342 { 0xFF, 0xFF, 0 }, /* 48 microphone */ 343 { 0xFF, 0xFF, 0 }, /* 49 level control */ 344 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ 345 { 0xFF, 0xFF, 0 }, /* 4B jack detect */ 346 { 0xFF, 0xFF, 0 }, /* 4C input enable */ 347 { 0xFF, 0xFF, 0 }, /* 4D output enable */ 348 { 0xFF, 0xFF, 0 }, /* 4E bias control */ 349 { 0xFF, 0xFF, 0 }, /* 4F DAC power */ 350 351 { 0xFF, 0xFF, 0 }, /* 50 DAC power */ 352 { 0xFF, 0xFF, 0 }, /* 51 system */ 353 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ 354 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ 355 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ 356 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ 357 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ 358 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ 359 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ 360 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ 361 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ 362 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ 363 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ 364 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ 365 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ 366 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ 367 368 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ 369 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ 370 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ 371 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ 372 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ 373 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ 374 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ 375 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ 376 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ 377 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ 378 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ 379 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ 380 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ 381 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ 382 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ 383 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ 384 385 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ 386 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ 387 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ 388 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ 389 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ 390 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ 391 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ 392 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ 393 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ 394 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ 395 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ 396 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ 397 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ 398 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ 399 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ 400 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ 401 402 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ 403 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ 404 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ 405 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ 406 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ 407 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ 408 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ 409 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ 410 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ 411 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ 412 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ 413 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ 414 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ 415 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ 416 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ 417 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ 418 419 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ 420 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ 421 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ 422 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ 423 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ 424 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ 425 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ 426 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ 427 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ 428 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ 429 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ 430 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ 431 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ 432 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ 433 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ 434 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ 435 436 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ 437 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ 438 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ 439 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ 440 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ 441 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ 442 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ 443 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ 444 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ 445 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ 446 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ 447 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ 448 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ 449 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ 450 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ 451 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ 452 453 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ 454 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ 455 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ 456 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ 457 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ 458 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ 459 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ 460 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ 461 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ 462 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ 463 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ 464 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ 465 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ 466 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ 467 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ 468 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ 469 470 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ 471 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ 472 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ 473 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ 474 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ 475 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ 476 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ 477 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ 478 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ 479 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ 480 { 0x00, 0x00, 0 }, /* CA */ 481 { 0x00, 0x00, 0 }, /* CB */ 482 { 0x00, 0x00, 0 }, /* CC */ 483 { 0x00, 0x00, 0 }, /* CD */ 484 { 0x00, 0x00, 0 }, /* CE */ 485 { 0x00, 0x00, 0 }, /* CF */ 486 487 { 0x00, 0x00, 0 }, /* D0 */ 488 { 0x00, 0x00, 0 }, /* D1 */ 489 { 0x00, 0x00, 0 }, /* D2 */ 490 { 0x00, 0x00, 0 }, /* D3 */ 491 { 0x00, 0x00, 0 }, /* D4 */ 492 { 0x00, 0x00, 0 }, /* D5 */ 493 { 0x00, 0x00, 0 }, /* D6 */ 494 { 0x00, 0x00, 0 }, /* D7 */ 495 { 0x00, 0x00, 0 }, /* D8 */ 496 { 0x00, 0x00, 0 }, /* D9 */ 497 { 0x00, 0x00, 0 }, /* DA */ 498 { 0x00, 0x00, 0 }, /* DB */ 499 { 0x00, 0x00, 0 }, /* DC */ 500 { 0x00, 0x00, 0 }, /* DD */ 501 { 0x00, 0x00, 0 }, /* DE */ 502 { 0x00, 0x00, 0 }, /* DF */ 503 504 { 0x00, 0x00, 0 }, /* E0 */ 505 { 0x00, 0x00, 0 }, /* E1 */ 506 { 0x00, 0x00, 0 }, /* E2 */ 507 { 0x00, 0x00, 0 }, /* E3 */ 508 { 0x00, 0x00, 0 }, /* E4 */ 509 { 0x00, 0x00, 0 }, /* E5 */ 510 { 0x00, 0x00, 0 }, /* E6 */ 511 { 0x00, 0x00, 0 }, /* E7 */ 512 { 0x00, 0x00, 0 }, /* E8 */ 513 { 0x00, 0x00, 0 }, /* E9 */ 514 { 0x00, 0x00, 0 }, /* EA */ 515 { 0x00, 0x00, 0 }, /* EB */ 516 { 0x00, 0x00, 0 }, /* EC */ 517 { 0x00, 0x00, 0 }, /* ED */ 518 { 0x00, 0x00, 0 }, /* EE */ 519 { 0x00, 0x00, 0 }, /* EF */ 520 521 { 0x00, 0x00, 0 }, /* F0 */ 522 { 0x00, 0x00, 0 }, /* F1 */ 523 { 0x00, 0x00, 0 }, /* F2 */ 524 { 0x00, 0x00, 0 }, /* F3 */ 525 { 0x00, 0x00, 0 }, /* F4 */ 526 { 0x00, 0x00, 0 }, /* F5 */ 527 { 0x00, 0x00, 0 }, /* F6 */ 528 { 0x00, 0x00, 0 }, /* F7 */ 529 { 0x00, 0x00, 0 }, /* F8 */ 530 { 0x00, 0x00, 0 }, /* F9 */ 531 { 0x00, 0x00, 0 }, /* FA */ 532 { 0x00, 0x00, 0 }, /* FB */ 533 { 0x00, 0x00, 0 }, /* FC */ 534 { 0x00, 0x00, 0 }, /* FD */ 535 { 0x00, 0x00, 0 }, /* FE */ 536 { 0xFF, 0x00, 1 }, /* FF */ 537 }; 538 539 static bool max98088_readable_register(struct device *dev, unsigned int reg) 540 { 541 return max98088_access[reg].readable; 542 } 543 544 static bool max98088_volatile_register(struct device *dev, unsigned int reg) 545 { 546 return max98088_access[reg].vol; 547 } 548 549 static const struct regmap_config max98088_regmap = { 550 .reg_bits = 8, 551 .val_bits = 8, 552 553 .readable_reg = max98088_readable_register, 554 .volatile_reg = max98088_volatile_register, 555 .max_register = 0xff, 556 557 .reg_defaults = max98088_reg, 558 .num_reg_defaults = ARRAY_SIZE(max98088_reg), 559 .cache_type = REGCACHE_RBTREE, 560 }; 561 562 /* 563 * Load equalizer DSP coefficient configurations registers 564 */ 565 static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai, 566 unsigned int band, u16 *coefs) 567 { 568 unsigned int eq_reg; 569 unsigned int i; 570 571 if (WARN_ON(band > 4) || 572 WARN_ON(dai > 1)) 573 return; 574 575 /* Load the base register address */ 576 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 577 578 /* Add the band address offset, note adjustment for word address */ 579 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 580 581 /* Step through the registers and coefs */ 582 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 583 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i])); 584 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i])); 585 } 586 } 587 588 /* 589 * Excursion limiter modes 590 */ 591 static const char *max98088_exmode_texts[] = { 592 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 593 "400-600Hz", "400-800Hz", 594 }; 595 596 static const unsigned int max98088_exmode_values[] = { 597 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 598 }; 599 600 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum, 601 M98088_REG_41_SPKDHP, 0, 127, 602 max98088_exmode_texts, 603 max98088_exmode_values); 604 605 static const char *max98088_ex_thresh[] = { /* volts PP */ 606 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 607 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum, 608 M98088_REG_42_SPKDHP_THRESH, 0, 609 max98088_ex_thresh); 610 611 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 612 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum, 613 M98088_REG_18_DAI1_FILTERS, 7, 614 max98088_fltr_mode); 615 616 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 617 618 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum, 619 M98088_REG_48_CFG_MIC, 0, 620 max98088_extmic_text); 621 622 static const struct snd_kcontrol_new max98088_extmic_mux = 623 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 624 625 static const char *max98088_dai1_fltr[] = { 626 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 627 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 628 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum, 629 M98088_REG_18_DAI1_FILTERS, 0, 630 max98088_dai1_fltr); 631 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum, 632 M98088_REG_18_DAI1_FILTERS, 4, 633 max98088_dai1_fltr); 634 635 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 636 struct snd_ctl_elem_value *ucontrol) 637 { 638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 639 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 640 unsigned int sel = ucontrol->value.integer.value[0]; 641 642 max98088->mic1pre = sel; 643 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 644 (1+sel)<<M98088_MICPRE_SHIFT); 645 646 return 0; 647 } 648 649 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 650 struct snd_ctl_elem_value *ucontrol) 651 { 652 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 653 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 654 655 ucontrol->value.integer.value[0] = max98088->mic1pre; 656 return 0; 657 } 658 659 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 660 struct snd_ctl_elem_value *ucontrol) 661 { 662 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 663 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 664 unsigned int sel = ucontrol->value.integer.value[0]; 665 666 max98088->mic2pre = sel; 667 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 668 (1+sel)<<M98088_MICPRE_SHIFT); 669 670 return 0; 671 } 672 673 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 674 struct snd_ctl_elem_value *ucontrol) 675 { 676 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 677 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 678 679 ucontrol->value.integer.value[0] = max98088->mic2pre; 680 return 0; 681 } 682 683 static const unsigned int max98088_micboost_tlv[] = { 684 TLV_DB_RANGE_HEAD(2), 685 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 686 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 687 }; 688 689 static const unsigned int max98088_hp_tlv[] = { 690 TLV_DB_RANGE_HEAD(5), 691 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 692 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 693 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 694 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 695 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 696 }; 697 698 static const unsigned int max98088_spk_tlv[] = { 699 TLV_DB_RANGE_HEAD(5), 700 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 701 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 702 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 703 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 704 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 705 }; 706 707 static const struct snd_kcontrol_new max98088_snd_controls[] = { 708 709 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L, 710 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv), 711 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 712 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv), 713 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L, 714 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv), 715 716 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 717 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 718 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 719 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 720 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 721 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 722 723 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 724 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 725 726 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 727 M98088_REG_35_LVL_MIC1, 5, 2, 0, 728 max98088_mic1pre_get, max98088_mic1pre_set, 729 max98088_micboost_tlv), 730 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 731 M98088_REG_36_LVL_MIC2, 5, 2, 0, 732 max98088_mic2pre_get, max98088_mic2pre_set, 733 max98088_micboost_tlv), 734 735 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 736 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 737 738 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 739 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 740 741 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 742 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 743 744 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 745 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 746 747 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum), 748 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 749 750 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 751 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 752 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 753 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 754 0, 1, 0), 755 756 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 757 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 758 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 759 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 760 761 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 762 4, 15, 0), 763 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 764 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 765 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 766 767 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 768 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 769 }; 770 771 /* Left speaker mixer switch */ 772 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 773 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 774 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 775 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 776 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 777 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 778 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 779 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 780 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 781 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 782 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 783 }; 784 785 /* Right speaker mixer switch */ 786 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 787 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 788 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 789 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 790 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 791 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 792 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 793 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 794 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 795 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 796 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 797 }; 798 799 /* Left headphone mixer switch */ 800 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 801 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 802 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 803 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 804 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 805 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 806 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 807 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 808 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 809 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 810 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 811 }; 812 813 /* Right headphone mixer switch */ 814 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 815 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 816 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 817 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 818 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 819 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 820 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 821 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 822 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 823 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 824 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 825 }; 826 827 /* Left earpiece/receiver mixer switch */ 828 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 829 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 830 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 831 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 832 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 833 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 834 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 835 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 836 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 837 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 838 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 839 }; 840 841 /* Right earpiece/receiver mixer switch */ 842 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 843 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 844 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 845 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 846 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 847 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 848 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 849 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 850 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 851 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 852 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 853 }; 854 855 /* Left ADC mixer switch */ 856 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 857 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 858 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 859 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 860 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 861 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 862 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 863 }; 864 865 /* Right ADC mixer switch */ 866 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 867 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 868 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 869 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 870 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 871 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 872 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 873 }; 874 875 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 876 struct snd_kcontrol *kcontrol, int event) 877 { 878 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 879 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 880 881 switch (event) { 882 case SND_SOC_DAPM_POST_PMU: 883 if (w->reg == M98088_REG_35_LVL_MIC1) { 884 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 885 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 886 } else { 887 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 888 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 889 } 890 break; 891 case SND_SOC_DAPM_POST_PMD: 892 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0); 893 break; 894 default: 895 return -EINVAL; 896 } 897 898 return 0; 899 } 900 901 /* 902 * The line inputs are 2-channel stereo inputs with the left 903 * and right channels sharing a common PGA power control signal. 904 */ 905 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 906 int event, int line, u8 channel) 907 { 908 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 909 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 910 u8 *state; 911 912 if (WARN_ON(!(channel == 1 || channel == 2))) 913 return -EINVAL; 914 915 switch (line) { 916 case LINE_INA: 917 state = &max98088->ina_state; 918 break; 919 case LINE_INB: 920 state = &max98088->inb_state; 921 break; 922 default: 923 return -EINVAL; 924 } 925 926 switch (event) { 927 case SND_SOC_DAPM_POST_PMU: 928 *state |= channel; 929 snd_soc_update_bits(codec, w->reg, 930 (1 << w->shift), (1 << w->shift)); 931 break; 932 case SND_SOC_DAPM_POST_PMD: 933 *state &= ~channel; 934 if (*state == 0) { 935 snd_soc_update_bits(codec, w->reg, 936 (1 << w->shift), 0); 937 } 938 break; 939 default: 940 return -EINVAL; 941 } 942 943 return 0; 944 } 945 946 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 947 struct snd_kcontrol *k, int event) 948 { 949 return max98088_line_pga(w, event, LINE_INA, 1); 950 } 951 952 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 953 struct snd_kcontrol *k, int event) 954 { 955 return max98088_line_pga(w, event, LINE_INA, 2); 956 } 957 958 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 959 struct snd_kcontrol *k, int event) 960 { 961 return max98088_line_pga(w, event, LINE_INB, 1); 962 } 963 964 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 965 struct snd_kcontrol *k, int event) 966 { 967 return max98088_line_pga(w, event, LINE_INB, 2); 968 } 969 970 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 971 972 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 973 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 974 975 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 976 M98088_REG_4D_PWR_EN_OUT, 1, 0), 977 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 978 M98088_REG_4D_PWR_EN_OUT, 0, 0), 979 SND_SOC_DAPM_DAC("DACL2", "Aux Playback", 980 M98088_REG_4D_PWR_EN_OUT, 1, 0), 981 SND_SOC_DAPM_DAC("DACR2", "Aux Playback", 982 M98088_REG_4D_PWR_EN_OUT, 0, 0), 983 984 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 985 7, 0, NULL, 0), 986 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 987 6, 0, NULL, 0), 988 989 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 990 5, 0, NULL, 0), 991 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 992 4, 0, NULL, 0), 993 994 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 995 3, 0, NULL, 0), 996 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 997 2, 0, NULL, 0), 998 999 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 1000 &max98088_extmic_mux), 1001 1002 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 1003 &max98088_left_hp_mixer_controls[0], 1004 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 1005 1006 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 1007 &max98088_right_hp_mixer_controls[0], 1008 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 1009 1010 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 1011 &max98088_left_speaker_mixer_controls[0], 1012 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 1013 1014 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 1015 &max98088_right_speaker_mixer_controls[0], 1016 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 1017 1018 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 1019 &max98088_left_rec_mixer_controls[0], 1020 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 1021 1022 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 1023 &max98088_right_rec_mixer_controls[0], 1024 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 1025 1026 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1027 &max98088_left_ADC_mixer_controls[0], 1028 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 1029 1030 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1031 &max98088_right_ADC_mixer_controls[0], 1032 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 1033 1034 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 1035 5, 0, NULL, 0, max98088_mic_event, 1036 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1037 1038 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 1039 5, 0, NULL, 0, max98088_mic_event, 1040 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1041 1042 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 1043 7, 0, NULL, 0, max98088_pga_ina1_event, 1044 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1045 1046 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 1047 7, 0, NULL, 0, max98088_pga_ina2_event, 1048 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1049 1050 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 1051 6, 0, NULL, 0, max98088_pga_inb1_event, 1052 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1053 1054 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 1055 6, 0, NULL, 0, max98088_pga_inb2_event, 1056 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1057 1058 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 1059 1060 SND_SOC_DAPM_OUTPUT("HPL"), 1061 SND_SOC_DAPM_OUTPUT("HPR"), 1062 SND_SOC_DAPM_OUTPUT("SPKL"), 1063 SND_SOC_DAPM_OUTPUT("SPKR"), 1064 SND_SOC_DAPM_OUTPUT("RECL"), 1065 SND_SOC_DAPM_OUTPUT("RECR"), 1066 1067 SND_SOC_DAPM_INPUT("MIC1"), 1068 SND_SOC_DAPM_INPUT("MIC2"), 1069 SND_SOC_DAPM_INPUT("INA1"), 1070 SND_SOC_DAPM_INPUT("INA2"), 1071 SND_SOC_DAPM_INPUT("INB1"), 1072 SND_SOC_DAPM_INPUT("INB2"), 1073 }; 1074 1075 static const struct snd_soc_dapm_route max98088_audio_map[] = { 1076 /* Left headphone output mixer */ 1077 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"}, 1078 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"}, 1079 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"}, 1080 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"}, 1081 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1082 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1083 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 1084 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 1085 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 1086 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 1087 1088 /* Right headphone output mixer */ 1089 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"}, 1090 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" }, 1091 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"}, 1092 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"}, 1093 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1094 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1095 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 1096 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 1097 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 1098 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 1099 1100 /* Left speaker output mixer */ 1101 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1102 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1103 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1104 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1105 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1106 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1107 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 1108 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 1109 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 1110 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 1111 1112 /* Right speaker output mixer */ 1113 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1114 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1115 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1116 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1117 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1118 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1119 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 1120 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 1121 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 1122 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 1123 1124 /* Earpiece/Receiver output mixer */ 1125 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"}, 1126 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"}, 1127 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"}, 1128 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"}, 1129 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1130 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1131 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 1132 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 1133 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 1134 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 1135 1136 /* Earpiece/Receiver output mixer */ 1137 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"}, 1138 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"}, 1139 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"}, 1140 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"}, 1141 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1142 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1143 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 1144 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 1145 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 1146 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 1147 1148 {"HP Left Out", NULL, "Left HP Mixer"}, 1149 {"HP Right Out", NULL, "Right HP Mixer"}, 1150 {"SPK Left Out", NULL, "Left SPK Mixer"}, 1151 {"SPK Right Out", NULL, "Right SPK Mixer"}, 1152 {"REC Left Out", NULL, "Left REC Mixer"}, 1153 {"REC Right Out", NULL, "Right REC Mixer"}, 1154 1155 {"HPL", NULL, "HP Left Out"}, 1156 {"HPR", NULL, "HP Right Out"}, 1157 {"SPKL", NULL, "SPK Left Out"}, 1158 {"SPKR", NULL, "SPK Right Out"}, 1159 {"RECL", NULL, "REC Left Out"}, 1160 {"RECR", NULL, "REC Right Out"}, 1161 1162 /* Left ADC input mixer */ 1163 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1164 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1165 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 1166 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 1167 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 1168 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 1169 1170 /* Right ADC input mixer */ 1171 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1172 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1173 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 1174 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 1175 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 1176 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 1177 1178 /* Inputs */ 1179 {"ADCL", NULL, "Left ADC Mixer"}, 1180 {"ADCR", NULL, "Right ADC Mixer"}, 1181 {"INA1 Input", NULL, "INA1"}, 1182 {"INA2 Input", NULL, "INA2"}, 1183 {"INB1 Input", NULL, "INB1"}, 1184 {"INB2 Input", NULL, "INB2"}, 1185 {"MIC1 Input", NULL, "MIC1"}, 1186 {"MIC2 Input", NULL, "MIC2"}, 1187 }; 1188 1189 /* codec mclk clock divider coefficients */ 1190 static const struct { 1191 u32 rate; 1192 u8 sr; 1193 } rate_table[] = { 1194 {8000, 0x10}, 1195 {11025, 0x20}, 1196 {16000, 0x30}, 1197 {22050, 0x40}, 1198 {24000, 0x50}, 1199 {32000, 0x60}, 1200 {44100, 0x70}, 1201 {48000, 0x80}, 1202 {88200, 0x90}, 1203 {96000, 0xA0}, 1204 }; 1205 1206 static inline int rate_value(int rate, u8 *value) 1207 { 1208 int i; 1209 1210 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1211 if (rate_table[i].rate >= rate) { 1212 *value = rate_table[i].sr; 1213 return 0; 1214 } 1215 } 1216 *value = rate_table[0].sr; 1217 return -EINVAL; 1218 } 1219 1220 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 1221 struct snd_pcm_hw_params *params, 1222 struct snd_soc_dai *dai) 1223 { 1224 struct snd_soc_codec *codec = dai->codec; 1225 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1226 struct max98088_cdata *cdata; 1227 unsigned long long ni; 1228 unsigned int rate; 1229 u8 regval; 1230 1231 cdata = &max98088->dai[0]; 1232 1233 rate = params_rate(params); 1234 1235 switch (params_width(params)) { 1236 case 16: 1237 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1238 M98088_DAI_WS, 0); 1239 break; 1240 case 24: 1241 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1242 M98088_DAI_WS, M98088_DAI_WS); 1243 break; 1244 default: 1245 return -EINVAL; 1246 } 1247 1248 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1249 1250 if (rate_value(rate, ®val)) 1251 return -EINVAL; 1252 1253 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE, 1254 M98088_CLKMODE_MASK, regval); 1255 cdata->rate = rate; 1256 1257 /* Configure NI when operating as master */ 1258 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT) 1259 & M98088_DAI_MAS) { 1260 if (max98088->sysclk == 0) { 1261 dev_err(codec->dev, "Invalid system clock frequency\n"); 1262 return -EINVAL; 1263 } 1264 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1265 * (unsigned long long int)rate; 1266 do_div(ni, (unsigned long long int)max98088->sysclk); 1267 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1268 (ni >> 8) & 0x7F); 1269 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1270 ni & 0xFF); 1271 } 1272 1273 /* Update sample rate mode */ 1274 if (rate < 50000) 1275 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1276 M98088_DAI_DHF, 0); 1277 else 1278 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1279 M98088_DAI_DHF, M98088_DAI_DHF); 1280 1281 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1282 M98088_SHDNRUN); 1283 1284 return 0; 1285 } 1286 1287 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1288 struct snd_pcm_hw_params *params, 1289 struct snd_soc_dai *dai) 1290 { 1291 struct snd_soc_codec *codec = dai->codec; 1292 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1293 struct max98088_cdata *cdata; 1294 unsigned long long ni; 1295 unsigned int rate; 1296 u8 regval; 1297 1298 cdata = &max98088->dai[1]; 1299 1300 rate = params_rate(params); 1301 1302 switch (params_width(params)) { 1303 case 16: 1304 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1305 M98088_DAI_WS, 0); 1306 break; 1307 case 24: 1308 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1309 M98088_DAI_WS, M98088_DAI_WS); 1310 break; 1311 default: 1312 return -EINVAL; 1313 } 1314 1315 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1316 1317 if (rate_value(rate, ®val)) 1318 return -EINVAL; 1319 1320 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE, 1321 M98088_CLKMODE_MASK, regval); 1322 cdata->rate = rate; 1323 1324 /* Configure NI when operating as master */ 1325 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT) 1326 & M98088_DAI_MAS) { 1327 if (max98088->sysclk == 0) { 1328 dev_err(codec->dev, "Invalid system clock frequency\n"); 1329 return -EINVAL; 1330 } 1331 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1332 * (unsigned long long int)rate; 1333 do_div(ni, (unsigned long long int)max98088->sysclk); 1334 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1335 (ni >> 8) & 0x7F); 1336 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1337 ni & 0xFF); 1338 } 1339 1340 /* Update sample rate mode */ 1341 if (rate < 50000) 1342 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1343 M98088_DAI_DHF, 0); 1344 else 1345 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1346 M98088_DAI_DHF, M98088_DAI_DHF); 1347 1348 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1349 M98088_SHDNRUN); 1350 1351 return 0; 1352 } 1353 1354 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1355 int clk_id, unsigned int freq, int dir) 1356 { 1357 struct snd_soc_codec *codec = dai->codec; 1358 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1359 1360 /* Requested clock frequency is already setup */ 1361 if (freq == max98088->sysclk) 1362 return 0; 1363 1364 /* Setup clocks for slave mode, and using the PLL 1365 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1366 * 0x02 (when master clk is 20MHz to 30MHz).. 1367 */ 1368 if ((freq >= 10000000) && (freq < 20000000)) { 1369 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10); 1370 } else if ((freq >= 20000000) && (freq < 30000000)) { 1371 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20); 1372 } else { 1373 dev_err(codec->dev, "Invalid master clock frequency\n"); 1374 return -EINVAL; 1375 } 1376 1377 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1378 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1379 M98088_SHDNRUN, 0); 1380 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1381 M98088_SHDNRUN, M98088_SHDNRUN); 1382 } 1383 1384 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1385 1386 max98088->sysclk = freq; 1387 return 0; 1388 } 1389 1390 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1391 unsigned int fmt) 1392 { 1393 struct snd_soc_codec *codec = codec_dai->codec; 1394 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1395 struct max98088_cdata *cdata; 1396 u8 reg15val; 1397 u8 reg14val = 0; 1398 1399 cdata = &max98088->dai[0]; 1400 1401 if (fmt != cdata->fmt) { 1402 cdata->fmt = fmt; 1403 1404 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1405 case SND_SOC_DAIFMT_CBS_CFS: 1406 /* Slave mode PLL */ 1407 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1408 0x80); 1409 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1410 0x00); 1411 break; 1412 case SND_SOC_DAIFMT_CBM_CFM: 1413 /* Set to master mode */ 1414 reg14val |= M98088_DAI_MAS; 1415 break; 1416 case SND_SOC_DAIFMT_CBS_CFM: 1417 case SND_SOC_DAIFMT_CBM_CFS: 1418 default: 1419 dev_err(codec->dev, "Clock mode unsupported"); 1420 return -EINVAL; 1421 } 1422 1423 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1424 case SND_SOC_DAIFMT_I2S: 1425 reg14val |= M98088_DAI_DLY; 1426 break; 1427 case SND_SOC_DAIFMT_LEFT_J: 1428 break; 1429 default: 1430 return -EINVAL; 1431 } 1432 1433 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1434 case SND_SOC_DAIFMT_NB_NF: 1435 break; 1436 case SND_SOC_DAIFMT_NB_IF: 1437 reg14val |= M98088_DAI_WCI; 1438 break; 1439 case SND_SOC_DAIFMT_IB_NF: 1440 reg14val |= M98088_DAI_BCI; 1441 break; 1442 case SND_SOC_DAIFMT_IB_IF: 1443 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1444 break; 1445 default: 1446 return -EINVAL; 1447 } 1448 1449 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1450 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1451 M98088_DAI_WCI, reg14val); 1452 1453 reg15val = M98088_DAI_BSEL64; 1454 if (max98088->digmic) 1455 reg15val |= M98088_DAI_OSR64; 1456 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val); 1457 } 1458 1459 return 0; 1460 } 1461 1462 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1463 unsigned int fmt) 1464 { 1465 struct snd_soc_codec *codec = codec_dai->codec; 1466 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1467 struct max98088_cdata *cdata; 1468 u8 reg1Cval = 0; 1469 1470 cdata = &max98088->dai[1]; 1471 1472 if (fmt != cdata->fmt) { 1473 cdata->fmt = fmt; 1474 1475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1476 case SND_SOC_DAIFMT_CBS_CFS: 1477 /* Slave mode PLL */ 1478 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1479 0x80); 1480 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1481 0x00); 1482 break; 1483 case SND_SOC_DAIFMT_CBM_CFM: 1484 /* Set to master mode */ 1485 reg1Cval |= M98088_DAI_MAS; 1486 break; 1487 case SND_SOC_DAIFMT_CBS_CFM: 1488 case SND_SOC_DAIFMT_CBM_CFS: 1489 default: 1490 dev_err(codec->dev, "Clock mode unsupported"); 1491 return -EINVAL; 1492 } 1493 1494 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1495 case SND_SOC_DAIFMT_I2S: 1496 reg1Cval |= M98088_DAI_DLY; 1497 break; 1498 case SND_SOC_DAIFMT_LEFT_J: 1499 break; 1500 default: 1501 return -EINVAL; 1502 } 1503 1504 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1505 case SND_SOC_DAIFMT_NB_NF: 1506 break; 1507 case SND_SOC_DAIFMT_NB_IF: 1508 reg1Cval |= M98088_DAI_WCI; 1509 break; 1510 case SND_SOC_DAIFMT_IB_NF: 1511 reg1Cval |= M98088_DAI_BCI; 1512 break; 1513 case SND_SOC_DAIFMT_IB_IF: 1514 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1515 break; 1516 default: 1517 return -EINVAL; 1518 } 1519 1520 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1521 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1522 M98088_DAI_WCI, reg1Cval); 1523 1524 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK, 1525 M98088_DAI_BSEL64); 1526 } 1527 1528 return 0; 1529 } 1530 1531 static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1532 { 1533 struct snd_soc_codec *codec = codec_dai->codec; 1534 int reg; 1535 1536 if (mute) 1537 reg = M98088_DAI_MUTE; 1538 else 1539 reg = 0; 1540 1541 snd_soc_update_bits(codec, M98088_REG_2F_LVL_DAI1_PLAY, 1542 M98088_DAI_MUTE_MASK, reg); 1543 return 0; 1544 } 1545 1546 static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1547 { 1548 struct snd_soc_codec *codec = codec_dai->codec; 1549 int reg; 1550 1551 if (mute) 1552 reg = M98088_DAI_MUTE; 1553 else 1554 reg = 0; 1555 1556 snd_soc_update_bits(codec, M98088_REG_31_LVL_DAI2_PLAY, 1557 M98088_DAI_MUTE_MASK, reg); 1558 return 0; 1559 } 1560 1561 static int max98088_set_bias_level(struct snd_soc_codec *codec, 1562 enum snd_soc_bias_level level) 1563 { 1564 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1565 1566 switch (level) { 1567 case SND_SOC_BIAS_ON: 1568 break; 1569 1570 case SND_SOC_BIAS_PREPARE: 1571 break; 1572 1573 case SND_SOC_BIAS_STANDBY: 1574 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 1575 regcache_sync(max98088->regmap); 1576 1577 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1578 M98088_MBEN, M98088_MBEN); 1579 break; 1580 1581 case SND_SOC_BIAS_OFF: 1582 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1583 M98088_MBEN, 0); 1584 regcache_mark_dirty(max98088->regmap); 1585 break; 1586 } 1587 codec->dapm.bias_level = level; 1588 return 0; 1589 } 1590 1591 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1592 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1593 1594 static const struct snd_soc_dai_ops max98088_dai1_ops = { 1595 .set_sysclk = max98088_dai_set_sysclk, 1596 .set_fmt = max98088_dai1_set_fmt, 1597 .hw_params = max98088_dai1_hw_params, 1598 .digital_mute = max98088_dai1_digital_mute, 1599 }; 1600 1601 static const struct snd_soc_dai_ops max98088_dai2_ops = { 1602 .set_sysclk = max98088_dai_set_sysclk, 1603 .set_fmt = max98088_dai2_set_fmt, 1604 .hw_params = max98088_dai2_hw_params, 1605 .digital_mute = max98088_dai2_digital_mute, 1606 }; 1607 1608 static struct snd_soc_dai_driver max98088_dai[] = { 1609 { 1610 .name = "HiFi", 1611 .playback = { 1612 .stream_name = "HiFi Playback", 1613 .channels_min = 1, 1614 .channels_max = 2, 1615 .rates = MAX98088_RATES, 1616 .formats = MAX98088_FORMATS, 1617 }, 1618 .capture = { 1619 .stream_name = "HiFi Capture", 1620 .channels_min = 1, 1621 .channels_max = 2, 1622 .rates = MAX98088_RATES, 1623 .formats = MAX98088_FORMATS, 1624 }, 1625 .ops = &max98088_dai1_ops, 1626 }, 1627 { 1628 .name = "Aux", 1629 .playback = { 1630 .stream_name = "Aux Playback", 1631 .channels_min = 1, 1632 .channels_max = 2, 1633 .rates = MAX98088_RATES, 1634 .formats = MAX98088_FORMATS, 1635 }, 1636 .ops = &max98088_dai2_ops, 1637 } 1638 }; 1639 1640 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; 1641 1642 static int max98088_get_channel(struct snd_soc_codec *codec, const char *name) 1643 { 1644 int i; 1645 1646 for (i = 0; i < ARRAY_SIZE(eq_mode_name); i++) 1647 if (strcmp(name, eq_mode_name[i]) == 0) 1648 return i; 1649 1650 /* Shouldn't happen */ 1651 dev_err(codec->dev, "Bad EQ channel name '%s'\n", name); 1652 return -EINVAL; 1653 } 1654 1655 static void max98088_setup_eq1(struct snd_soc_codec *codec) 1656 { 1657 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1658 struct max98088_pdata *pdata = max98088->pdata; 1659 struct max98088_eq_cfg *coef_set; 1660 int best, best_val, save, i, sel, fs; 1661 struct max98088_cdata *cdata; 1662 1663 cdata = &max98088->dai[0]; 1664 1665 if (!pdata || !max98088->eq_textcnt) 1666 return; 1667 1668 /* Find the selected configuration with nearest sample rate */ 1669 fs = cdata->rate; 1670 sel = cdata->eq_sel; 1671 1672 best = 0; 1673 best_val = INT_MAX; 1674 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1675 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1676 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1677 best = i; 1678 best_val = abs(pdata->eq_cfg[i].rate - fs); 1679 } 1680 } 1681 1682 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1683 pdata->eq_cfg[best].name, 1684 pdata->eq_cfg[best].rate, fs); 1685 1686 /* Disable EQ while configuring, and save current on/off state */ 1687 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1688 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1689 1690 coef_set = &pdata->eq_cfg[sel]; 1691 1692 m98088_eq_band(codec, 0, 0, coef_set->band1); 1693 m98088_eq_band(codec, 0, 1, coef_set->band2); 1694 m98088_eq_band(codec, 0, 2, coef_set->band3); 1695 m98088_eq_band(codec, 0, 3, coef_set->band4); 1696 m98088_eq_band(codec, 0, 4, coef_set->band5); 1697 1698 /* Restore the original on/off state */ 1699 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1700 } 1701 1702 static void max98088_setup_eq2(struct snd_soc_codec *codec) 1703 { 1704 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1705 struct max98088_pdata *pdata = max98088->pdata; 1706 struct max98088_eq_cfg *coef_set; 1707 int best, best_val, save, i, sel, fs; 1708 struct max98088_cdata *cdata; 1709 1710 cdata = &max98088->dai[1]; 1711 1712 if (!pdata || !max98088->eq_textcnt) 1713 return; 1714 1715 /* Find the selected configuration with nearest sample rate */ 1716 fs = cdata->rate; 1717 1718 sel = cdata->eq_sel; 1719 best = 0; 1720 best_val = INT_MAX; 1721 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1722 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1723 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1724 best = i; 1725 best_val = abs(pdata->eq_cfg[i].rate - fs); 1726 } 1727 } 1728 1729 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1730 pdata->eq_cfg[best].name, 1731 pdata->eq_cfg[best].rate, fs); 1732 1733 /* Disable EQ while configuring, and save current on/off state */ 1734 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1735 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1736 1737 coef_set = &pdata->eq_cfg[sel]; 1738 1739 m98088_eq_band(codec, 1, 0, coef_set->band1); 1740 m98088_eq_band(codec, 1, 1, coef_set->band2); 1741 m98088_eq_band(codec, 1, 2, coef_set->band3); 1742 m98088_eq_band(codec, 1, 3, coef_set->band4); 1743 m98088_eq_band(codec, 1, 4, coef_set->band5); 1744 1745 /* Restore the original on/off state */ 1746 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1747 save); 1748 } 1749 1750 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1751 struct snd_ctl_elem_value *ucontrol) 1752 { 1753 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1754 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1755 struct max98088_pdata *pdata = max98088->pdata; 1756 int channel = max98088_get_channel(codec, kcontrol->id.name); 1757 struct max98088_cdata *cdata; 1758 int sel = ucontrol->value.integer.value[0]; 1759 1760 if (channel < 0) 1761 return channel; 1762 1763 cdata = &max98088->dai[channel]; 1764 1765 if (sel >= pdata->eq_cfgcnt) 1766 return -EINVAL; 1767 1768 cdata->eq_sel = sel; 1769 1770 switch (channel) { 1771 case 0: 1772 max98088_setup_eq1(codec); 1773 break; 1774 case 1: 1775 max98088_setup_eq2(codec); 1776 break; 1777 } 1778 1779 return 0; 1780 } 1781 1782 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1783 struct snd_ctl_elem_value *ucontrol) 1784 { 1785 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1786 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1787 int channel = max98088_get_channel(codec, kcontrol->id.name); 1788 struct max98088_cdata *cdata; 1789 1790 if (channel < 0) 1791 return channel; 1792 1793 cdata = &max98088->dai[channel]; 1794 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1795 return 0; 1796 } 1797 1798 static void max98088_handle_eq_pdata(struct snd_soc_codec *codec) 1799 { 1800 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1801 struct max98088_pdata *pdata = max98088->pdata; 1802 struct max98088_eq_cfg *cfg; 1803 unsigned int cfgcnt; 1804 int i, j; 1805 const char **t; 1806 int ret; 1807 struct snd_kcontrol_new controls[] = { 1808 SOC_ENUM_EXT((char *)eq_mode_name[0], 1809 max98088->eq_enum, 1810 max98088_get_eq_enum, 1811 max98088_put_eq_enum), 1812 SOC_ENUM_EXT((char *)eq_mode_name[1], 1813 max98088->eq_enum, 1814 max98088_get_eq_enum, 1815 max98088_put_eq_enum), 1816 }; 1817 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name)); 1818 1819 cfg = pdata->eq_cfg; 1820 cfgcnt = pdata->eq_cfgcnt; 1821 1822 /* Setup an array of texts for the equalizer enum. 1823 * This is based on Mark Brown's equalizer driver code. 1824 */ 1825 max98088->eq_textcnt = 0; 1826 max98088->eq_texts = NULL; 1827 for (i = 0; i < cfgcnt; i++) { 1828 for (j = 0; j < max98088->eq_textcnt; j++) { 1829 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1830 break; 1831 } 1832 1833 if (j != max98088->eq_textcnt) 1834 continue; 1835 1836 /* Expand the array */ 1837 t = krealloc(max98088->eq_texts, 1838 sizeof(char *) * (max98088->eq_textcnt + 1), 1839 GFP_KERNEL); 1840 if (t == NULL) 1841 continue; 1842 1843 /* Store the new entry */ 1844 t[max98088->eq_textcnt] = cfg[i].name; 1845 max98088->eq_textcnt++; 1846 max98088->eq_texts = t; 1847 } 1848 1849 /* Now point the soc_enum to .texts array items */ 1850 max98088->eq_enum.texts = max98088->eq_texts; 1851 max98088->eq_enum.items = max98088->eq_textcnt; 1852 1853 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1854 if (ret != 0) 1855 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1856 } 1857 1858 static void max98088_handle_pdata(struct snd_soc_codec *codec) 1859 { 1860 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1861 struct max98088_pdata *pdata = max98088->pdata; 1862 u8 regval = 0; 1863 1864 if (!pdata) { 1865 dev_dbg(codec->dev, "No platform data\n"); 1866 return; 1867 } 1868 1869 /* Configure mic for analog/digital mic mode */ 1870 if (pdata->digmic_left_mode) 1871 regval |= M98088_DIGMIC_L; 1872 1873 if (pdata->digmic_right_mode) 1874 regval |= M98088_DIGMIC_R; 1875 1876 max98088->digmic = (regval ? 1 : 0); 1877 1878 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval); 1879 1880 /* Configure receiver output */ 1881 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1882 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL, 1883 M98088_REC_LINEMODE_MASK, regval); 1884 1885 /* Configure equalizers */ 1886 if (pdata->eq_cfgcnt) 1887 max98088_handle_eq_pdata(codec); 1888 } 1889 1890 static int max98088_probe(struct snd_soc_codec *codec) 1891 { 1892 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1893 struct max98088_cdata *cdata; 1894 int ret = 0; 1895 1896 regcache_mark_dirty(max98088->regmap); 1897 1898 /* initialize private data */ 1899 1900 max98088->sysclk = (unsigned)-1; 1901 max98088->eq_textcnt = 0; 1902 1903 cdata = &max98088->dai[0]; 1904 cdata->rate = (unsigned)-1; 1905 cdata->fmt = (unsigned)-1; 1906 cdata->eq_sel = 0; 1907 1908 cdata = &max98088->dai[1]; 1909 cdata->rate = (unsigned)-1; 1910 cdata->fmt = (unsigned)-1; 1911 cdata->eq_sel = 0; 1912 1913 max98088->ina_state = 0; 1914 max98088->inb_state = 0; 1915 max98088->ex_mode = 0; 1916 max98088->digmic = 0; 1917 max98088->mic1pre = 0; 1918 max98088->mic2pre = 0; 1919 1920 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID); 1921 if (ret < 0) { 1922 dev_err(codec->dev, "Failed to read device revision: %d\n", 1923 ret); 1924 goto err_access; 1925 } 1926 dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A'); 1927 1928 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV); 1929 1930 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00); 1931 1932 snd_soc_write(codec, M98088_REG_22_MIX_DAC, 1933 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 1934 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 1935 1936 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0); 1937 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F); 1938 1939 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG, 1940 M98088_S1NORMAL|M98088_SDATA); 1941 1942 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG, 1943 M98088_S2NORMAL|M98088_SDATA); 1944 1945 max98088_handle_pdata(codec); 1946 1947 err_access: 1948 return ret; 1949 } 1950 1951 static int max98088_remove(struct snd_soc_codec *codec) 1952 { 1953 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1954 1955 kfree(max98088->eq_texts); 1956 1957 return 0; 1958 } 1959 1960 static struct snd_soc_codec_driver soc_codec_dev_max98088 = { 1961 .probe = max98088_probe, 1962 .remove = max98088_remove, 1963 .set_bias_level = max98088_set_bias_level, 1964 .suspend_bias_off = true, 1965 1966 .controls = max98088_snd_controls, 1967 .num_controls = ARRAY_SIZE(max98088_snd_controls), 1968 .dapm_widgets = max98088_dapm_widgets, 1969 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 1970 .dapm_routes = max98088_audio_map, 1971 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map), 1972 }; 1973 1974 static int max98088_i2c_probe(struct i2c_client *i2c, 1975 const struct i2c_device_id *id) 1976 { 1977 struct max98088_priv *max98088; 1978 int ret; 1979 1980 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv), 1981 GFP_KERNEL); 1982 if (max98088 == NULL) 1983 return -ENOMEM; 1984 1985 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap); 1986 if (IS_ERR(max98088->regmap)) 1987 return PTR_ERR(max98088->regmap); 1988 1989 max98088->devtype = id->driver_data; 1990 1991 i2c_set_clientdata(i2c, max98088); 1992 max98088->pdata = i2c->dev.platform_data; 1993 1994 ret = snd_soc_register_codec(&i2c->dev, 1995 &soc_codec_dev_max98088, &max98088_dai[0], 2); 1996 return ret; 1997 } 1998 1999 static int max98088_i2c_remove(struct i2c_client *client) 2000 { 2001 snd_soc_unregister_codec(&client->dev); 2002 return 0; 2003 } 2004 2005 static const struct i2c_device_id max98088_i2c_id[] = { 2006 { "max98088", MAX98088 }, 2007 { "max98089", MAX98089 }, 2008 { } 2009 }; 2010 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 2011 2012 static struct i2c_driver max98088_i2c_driver = { 2013 .driver = { 2014 .name = "max98088", 2015 .owner = THIS_MODULE, 2016 }, 2017 .probe = max98088_i2c_probe, 2018 .remove = max98088_i2c_remove, 2019 .id_table = max98088_i2c_id, 2020 }; 2021 2022 module_i2c_driver(max98088_i2c_driver); 2023 2024 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 2025 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 2026 MODULE_LICENSE("GPL"); 2027