1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98088.c -- MAX98088 ALSA SoC Audio driver 4 * 5 * Copyright 2010 Maxim Integrated Products 6 */ 7 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/initval.h> 22 #include <sound/tlv.h> 23 #include <linux/slab.h> 24 #include <asm/div64.h> 25 #include <sound/max98088.h> 26 #include "max98088.h" 27 28 enum max98088_type { 29 MAX98088, 30 MAX98089, 31 }; 32 33 struct max98088_cdata { 34 unsigned int rate; 35 unsigned int fmt; 36 int eq_sel; 37 }; 38 39 struct max98088_priv { 40 struct regmap *regmap; 41 enum max98088_type devtype; 42 struct max98088_pdata *pdata; 43 struct clk *mclk; 44 unsigned char mclk_prescaler; 45 unsigned int sysclk; 46 struct max98088_cdata dai[2]; 47 int eq_textcnt; 48 const char **eq_texts; 49 struct soc_enum eq_enum; 50 u8 ina_state; 51 u8 inb_state; 52 unsigned int ex_mode; 53 unsigned int digmic; 54 unsigned int mic1pre; 55 unsigned int mic2pre; 56 unsigned int extmic_mode; 57 }; 58 59 static const struct reg_default max98088_reg[] = { 60 { 0xf, 0x00 }, /* 0F interrupt enable */ 61 62 { 0x10, 0x00 }, /* 10 master clock */ 63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */ 64 { 0x12, 0x00 }, /* 12 DAI1 clock control */ 65 { 0x13, 0x00 }, /* 13 DAI1 clock control */ 66 { 0x14, 0x00 }, /* 14 DAI1 format */ 67 { 0x15, 0x00 }, /* 15 DAI1 clock */ 68 { 0x16, 0x00 }, /* 16 DAI1 config */ 69 { 0x17, 0x00 }, /* 17 DAI1 TDM */ 70 { 0x18, 0x00 }, /* 18 DAI1 filters */ 71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */ 72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */ 73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */ 74 { 0x1c, 0x00 }, /* 1C DAI2 format */ 75 { 0x1d, 0x00 }, /* 1D DAI2 clock */ 76 { 0x1e, 0x00 }, /* 1E DAI2 config */ 77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */ 78 79 { 0x20, 0x00 }, /* 20 DAI2 filters */ 80 { 0x21, 0x00 }, /* 21 data config */ 81 { 0x22, 0x00 }, /* 22 DAC mixer */ 82 { 0x23, 0x00 }, /* 23 left ADC mixer */ 83 { 0x24, 0x00 }, /* 24 right ADC mixer */ 84 { 0x25, 0x00 }, /* 25 left HP mixer */ 85 { 0x26, 0x00 }, /* 26 right HP mixer */ 86 { 0x27, 0x00 }, /* 27 HP control */ 87 { 0x28, 0x00 }, /* 28 left REC mixer */ 88 { 0x29, 0x00 }, /* 29 right REC mixer */ 89 { 0x2a, 0x00 }, /* 2A REC control */ 90 { 0x2b, 0x00 }, /* 2B left SPK mixer */ 91 { 0x2c, 0x00 }, /* 2C right SPK mixer */ 92 { 0x2d, 0x00 }, /* 2D SPK control */ 93 { 0x2e, 0x00 }, /* 2E sidetone */ 94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */ 95 96 { 0x30, 0x00 }, /* 30 DAI1 playback level */ 97 { 0x31, 0x00 }, /* 31 DAI2 playback level */ 98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */ 99 { 0x33, 0x00 }, /* 33 left ADC level */ 100 { 0x34, 0x00 }, /* 34 right ADC level */ 101 { 0x35, 0x00 }, /* 35 MIC1 level */ 102 { 0x36, 0x00 }, /* 36 MIC2 level */ 103 { 0x37, 0x00 }, /* 37 INA level */ 104 { 0x38, 0x00 }, /* 38 INB level */ 105 { 0x39, 0x00 }, /* 39 left HP volume */ 106 { 0x3a, 0x00 }, /* 3A right HP volume */ 107 { 0x3b, 0x00 }, /* 3B left REC volume */ 108 { 0x3c, 0x00 }, /* 3C right REC volume */ 109 { 0x3d, 0x00 }, /* 3D left SPK volume */ 110 { 0x3e, 0x00 }, /* 3E right SPK volume */ 111 { 0x3f, 0x00 }, /* 3F MIC config */ 112 113 { 0x40, 0x00 }, /* 40 MIC threshold */ 114 { 0x41, 0x00 }, /* 41 excursion limiter filter */ 115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */ 116 { 0x43, 0x00 }, /* 43 ALC */ 117 { 0x44, 0x00 }, /* 44 power limiter threshold */ 118 { 0x45, 0x00 }, /* 45 power limiter config */ 119 { 0x46, 0x00 }, /* 46 distortion limiter config */ 120 { 0x47, 0x00 }, /* 47 audio input */ 121 { 0x48, 0x00 }, /* 48 microphone */ 122 { 0x49, 0x00 }, /* 49 level control */ 123 { 0x4a, 0x00 }, /* 4A bypass switches */ 124 { 0x4b, 0x00 }, /* 4B jack detect */ 125 { 0x4c, 0x00 }, /* 4C input enable */ 126 { 0x4d, 0x00 }, /* 4D output enable */ 127 { 0x4e, 0xF0 }, /* 4E bias control */ 128 { 0x4f, 0x00 }, /* 4F DAC power */ 129 130 { 0x50, 0x0F }, /* 50 DAC power */ 131 { 0x51, 0x00 }, /* 51 system */ 132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */ 133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */ 134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */ 135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */ 136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */ 137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */ 138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */ 139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */ 140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */ 141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */ 142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */ 143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */ 144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */ 145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */ 146 147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */ 148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */ 149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */ 150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */ 151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */ 152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */ 153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */ 154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */ 155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */ 156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */ 157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */ 158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */ 159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */ 160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */ 161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */ 162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */ 163 164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */ 165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */ 166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */ 167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */ 168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */ 169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */ 170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */ 171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */ 172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */ 173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */ 174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */ 175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */ 176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */ 177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */ 178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */ 179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */ 180 181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */ 182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */ 183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */ 184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */ 185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */ 186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */ 187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */ 188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */ 189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */ 190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */ 191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */ 192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */ 193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */ 194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */ 195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */ 196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */ 197 198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */ 199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */ 200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */ 201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */ 202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */ 203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */ 204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */ 205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */ 206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */ 207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */ 208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */ 209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */ 210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */ 211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */ 212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */ 213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */ 214 215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */ 216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */ 217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */ 218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */ 219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */ 220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */ 221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */ 222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */ 223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */ 224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */ 225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */ 226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */ 227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */ 228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */ 229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */ 230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */ 231 232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */ 233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */ 234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */ 235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */ 236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */ 237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */ 238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */ 239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */ 240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */ 241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */ 242 { 0xba, 0x00 }, /* BA DAI1 biquad */ 243 { 0xbb, 0x00 }, /* BB DAI1 biquad */ 244 { 0xbc, 0x00 }, /* BC DAI1 biquad */ 245 { 0xbd, 0x00 }, /* BD DAI1 biquad */ 246 { 0xbe, 0x00 }, /* BE DAI1 biquad */ 247 { 0xbf, 0x00 }, /* BF DAI1 biquad */ 248 249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */ 250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */ 251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */ 252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */ 253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */ 254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */ 255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */ 256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */ 257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */ 258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */ 259 }; 260 261 static bool max98088_readable_register(struct device *dev, unsigned int reg) 262 { 263 switch (reg) { 264 case M98088_REG_00_IRQ_STATUS ... 0xC9: 265 case M98088_REG_FF_REV_ID: 266 return true; 267 default: 268 return false; 269 } 270 } 271 272 static bool max98088_writeable_register(struct device *dev, unsigned int reg) 273 { 274 switch (reg) { 275 case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool max98088_volatile_register(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE: 286 case M98088_REG_FF_REV_ID: 287 return true; 288 default: 289 return false; 290 } 291 } 292 293 static const struct regmap_config max98088_regmap = { 294 .reg_bits = 8, 295 .val_bits = 8, 296 297 .readable_reg = max98088_readable_register, 298 .writeable_reg = max98088_writeable_register, 299 .volatile_reg = max98088_volatile_register, 300 .max_register = 0xff, 301 302 .reg_defaults = max98088_reg, 303 .num_reg_defaults = ARRAY_SIZE(max98088_reg), 304 .cache_type = REGCACHE_RBTREE, 305 }; 306 307 /* 308 * Load equalizer DSP coefficient configurations registers 309 */ 310 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai, 311 unsigned int band, u16 *coefs) 312 { 313 unsigned int eq_reg; 314 unsigned int i; 315 316 if (WARN_ON(band > 4) || 317 WARN_ON(dai > 1)) 318 return; 319 320 /* Load the base register address */ 321 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 322 323 /* Add the band address offset, note adjustment for word address */ 324 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 325 326 /* Step through the registers and coefs */ 327 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 328 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); 329 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); 330 } 331 } 332 333 /* 334 * Excursion limiter modes 335 */ 336 static const char *max98088_exmode_texts[] = { 337 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 338 "400-600Hz", "400-800Hz", 339 }; 340 341 static const unsigned int max98088_exmode_values[] = { 342 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 343 }; 344 345 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum, 346 M98088_REG_41_SPKDHP, 0, 127, 347 max98088_exmode_texts, 348 max98088_exmode_values); 349 350 static const char *max98088_ex_thresh[] = { /* volts PP */ 351 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 352 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum, 353 M98088_REG_42_SPKDHP_THRESH, 0, 354 max98088_ex_thresh); 355 356 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 357 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum, 358 M98088_REG_18_DAI1_FILTERS, 7, 359 max98088_fltr_mode); 360 361 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 362 363 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum, 364 M98088_REG_48_CFG_MIC, 0, 365 max98088_extmic_text); 366 367 static const struct snd_kcontrol_new max98088_extmic_mux = 368 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 369 370 static const char *max98088_dai1_fltr[] = { 371 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 372 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 373 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum, 374 M98088_REG_18_DAI1_FILTERS, 0, 375 max98088_dai1_fltr); 376 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum, 377 M98088_REG_18_DAI1_FILTERS, 4, 378 max98088_dai1_fltr); 379 380 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 381 struct snd_ctl_elem_value *ucontrol) 382 { 383 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 384 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 385 unsigned int sel = ucontrol->value.integer.value[0]; 386 387 max98088->mic1pre = sel; 388 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 389 (1+sel)<<M98088_MICPRE_SHIFT); 390 391 return 0; 392 } 393 394 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 395 struct snd_ctl_elem_value *ucontrol) 396 { 397 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 398 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 399 400 ucontrol->value.integer.value[0] = max98088->mic1pre; 401 return 0; 402 } 403 404 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 405 struct snd_ctl_elem_value *ucontrol) 406 { 407 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 408 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 409 unsigned int sel = ucontrol->value.integer.value[0]; 410 411 max98088->mic2pre = sel; 412 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 413 (1+sel)<<M98088_MICPRE_SHIFT); 414 415 return 0; 416 } 417 418 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 419 struct snd_ctl_elem_value *ucontrol) 420 { 421 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 422 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 423 424 ucontrol->value.integer.value[0] = max98088->mic2pre; 425 return 0; 426 } 427 428 static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv, 429 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 430 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 431 ); 432 433 static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv, 434 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 435 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 436 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 437 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 438 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 439 ); 440 441 static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv, 442 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 443 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 444 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 445 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 446 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 447 ); 448 449 static const struct snd_kcontrol_new max98088_snd_controls[] = { 450 451 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L, 452 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv), 453 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 454 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv), 455 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L, 456 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv), 457 458 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 459 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 460 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 461 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 462 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 463 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 464 465 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 466 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 467 468 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 469 M98088_REG_35_LVL_MIC1, 5, 2, 0, 470 max98088_mic1pre_get, max98088_mic1pre_set, 471 max98088_micboost_tlv), 472 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 473 M98088_REG_36_LVL_MIC2, 5, 2, 0, 474 max98088_mic2pre_get, max98088_mic2pre_set, 475 max98088_micboost_tlv), 476 477 SOC_SINGLE("Noise Gate Threshold", M98088_REG_40_MICAGC_THRESH, 478 4, 15, 0), 479 480 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 481 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 482 483 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 484 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 485 486 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 487 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 488 489 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 490 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 491 492 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum), 493 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 494 495 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 496 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 497 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 498 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 499 0, 1, 0), 500 501 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 502 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 503 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 504 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 505 506 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 507 4, 15, 0), 508 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 509 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 510 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 511 512 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 513 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 514 }; 515 516 /* Left speaker mixer switch */ 517 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 518 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 519 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 520 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 521 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 522 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 523 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 524 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 525 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 526 }; 527 528 /* Right speaker mixer switch */ 529 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 530 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 531 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 532 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 533 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 534 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 535 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 536 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 537 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 538 }; 539 540 /* Left headphone mixer switch */ 541 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 542 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 543 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 544 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 545 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 546 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 547 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 548 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 549 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 550 }; 551 552 /* Right headphone mixer switch */ 553 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 554 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 555 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 556 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 557 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 558 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 559 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 560 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 561 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 562 }; 563 564 /* Left earpiece/receiver mixer switch */ 565 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 566 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 567 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 568 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 569 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 570 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 571 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 572 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 573 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 574 }; 575 576 /* Right earpiece/receiver mixer switch */ 577 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 578 SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 579 SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 580 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 581 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 582 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 583 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 584 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 585 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 586 }; 587 588 /* Left ADC mixer switch */ 589 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 590 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 591 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 592 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 593 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 594 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 595 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 596 }; 597 598 /* Right ADC mixer switch */ 599 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 600 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 601 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 602 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 603 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 604 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 605 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 606 }; 607 608 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 609 struct snd_kcontrol *kcontrol, int event) 610 { 611 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 612 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 613 614 switch (event) { 615 case SND_SOC_DAPM_POST_PMU: 616 if (w->reg == M98088_REG_35_LVL_MIC1) { 617 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 618 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 619 } else { 620 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 621 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 622 } 623 break; 624 case SND_SOC_DAPM_POST_PMD: 625 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0); 626 break; 627 default: 628 return -EINVAL; 629 } 630 631 return 0; 632 } 633 634 /* 635 * The line inputs are 2-channel stereo inputs with the left 636 * and right channels sharing a common PGA power control signal. 637 */ 638 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 639 int event, int line, u8 channel) 640 { 641 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 642 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 643 u8 *state; 644 645 if (WARN_ON(!(channel == 1 || channel == 2))) 646 return -EINVAL; 647 648 switch (line) { 649 case LINE_INA: 650 state = &max98088->ina_state; 651 break; 652 case LINE_INB: 653 state = &max98088->inb_state; 654 break; 655 default: 656 return -EINVAL; 657 } 658 659 switch (event) { 660 case SND_SOC_DAPM_POST_PMU: 661 *state |= channel; 662 snd_soc_component_update_bits(component, w->reg, 663 (1 << w->shift), (1 << w->shift)); 664 break; 665 case SND_SOC_DAPM_POST_PMD: 666 *state &= ~channel; 667 if (*state == 0) { 668 snd_soc_component_update_bits(component, w->reg, 669 (1 << w->shift), 0); 670 } 671 break; 672 default: 673 return -EINVAL; 674 } 675 676 return 0; 677 } 678 679 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 680 struct snd_kcontrol *k, int event) 681 { 682 return max98088_line_pga(w, event, LINE_INA, 1); 683 } 684 685 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 686 struct snd_kcontrol *k, int event) 687 { 688 return max98088_line_pga(w, event, LINE_INA, 2); 689 } 690 691 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 692 struct snd_kcontrol *k, int event) 693 { 694 return max98088_line_pga(w, event, LINE_INB, 1); 695 } 696 697 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 698 struct snd_kcontrol *k, int event) 699 { 700 return max98088_line_pga(w, event, LINE_INB, 2); 701 } 702 703 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 704 705 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 706 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 707 708 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", 709 M98088_REG_4D_PWR_EN_OUT, 1, 0), 710 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", 711 M98088_REG_4D_PWR_EN_OUT, 0, 0), 712 713 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 714 7, 0, NULL, 0), 715 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 716 6, 0, NULL, 0), 717 718 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 719 5, 0, NULL, 0), 720 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 721 4, 0, NULL, 0), 722 723 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 724 3, 0, NULL, 0), 725 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 726 2, 0, NULL, 0), 727 728 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 729 &max98088_extmic_mux), 730 731 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 732 &max98088_left_hp_mixer_controls[0], 733 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 734 735 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 736 &max98088_right_hp_mixer_controls[0], 737 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 738 739 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 740 &max98088_left_speaker_mixer_controls[0], 741 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 742 743 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 744 &max98088_right_speaker_mixer_controls[0], 745 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 746 747 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 748 &max98088_left_rec_mixer_controls[0], 749 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 750 751 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 752 &max98088_right_rec_mixer_controls[0], 753 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 754 755 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 756 &max98088_left_ADC_mixer_controls[0], 757 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 758 759 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 760 &max98088_right_ADC_mixer_controls[0], 761 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 762 763 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 764 5, 0, NULL, 0, max98088_mic_event, 765 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 766 767 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 768 5, 0, NULL, 0, max98088_mic_event, 769 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 770 771 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 772 7, 0, NULL, 0, max98088_pga_ina1_event, 773 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 774 775 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 776 7, 0, NULL, 0, max98088_pga_ina2_event, 777 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 778 779 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 780 6, 0, NULL, 0, max98088_pga_inb1_event, 781 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 782 783 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 784 6, 0, NULL, 0, max98088_pga_inb2_event, 785 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 786 787 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 788 789 SND_SOC_DAPM_OUTPUT("HPL"), 790 SND_SOC_DAPM_OUTPUT("HPR"), 791 SND_SOC_DAPM_OUTPUT("SPKL"), 792 SND_SOC_DAPM_OUTPUT("SPKR"), 793 SND_SOC_DAPM_OUTPUT("RECL"), 794 SND_SOC_DAPM_OUTPUT("RECR"), 795 796 SND_SOC_DAPM_INPUT("MIC1"), 797 SND_SOC_DAPM_INPUT("MIC2"), 798 SND_SOC_DAPM_INPUT("INA1"), 799 SND_SOC_DAPM_INPUT("INA2"), 800 SND_SOC_DAPM_INPUT("INB1"), 801 SND_SOC_DAPM_INPUT("INB2"), 802 }; 803 804 static const struct snd_soc_dapm_route max98088_audio_map[] = { 805 /* Left headphone output mixer */ 806 {"Left HP Mixer", "Left DAC Switch", "DACL"}, 807 {"Left HP Mixer", "Right DAC Switch", "DACR"}, 808 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 809 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 810 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 811 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 812 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 813 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 814 815 /* Right headphone output mixer */ 816 {"Right HP Mixer", "Left DAC Switch", "DACL"}, 817 {"Right HP Mixer", "Right DAC Switch", "DACR"}, 818 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 819 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 820 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 821 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 822 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 823 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 824 825 /* Left speaker output mixer */ 826 {"Left SPK Mixer", "Left DAC Switch", "DACL"}, 827 {"Left SPK Mixer", "Right DAC Switch", "DACR"}, 828 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 829 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 830 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 831 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 832 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 833 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 834 835 /* Right speaker output mixer */ 836 {"Right SPK Mixer", "Left DAC Switch", "DACL"}, 837 {"Right SPK Mixer", "Right DAC Switch", "DACR"}, 838 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 839 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 840 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 841 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 842 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 843 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 844 845 /* Earpiece/Receiver output mixer */ 846 {"Left REC Mixer", "Left DAC Switch", "DACL"}, 847 {"Left REC Mixer", "Right DAC Switch", "DACR"}, 848 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 849 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 850 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 851 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 852 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 853 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 854 855 /* Earpiece/Receiver output mixer */ 856 {"Right REC Mixer", "Left DAC Switch", "DACL"}, 857 {"Right REC Mixer", "Right DAC Switch", "DACR"}, 858 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 859 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 860 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 861 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 862 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 863 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 864 865 {"HP Left Out", NULL, "Left HP Mixer"}, 866 {"HP Right Out", NULL, "Right HP Mixer"}, 867 {"SPK Left Out", NULL, "Left SPK Mixer"}, 868 {"SPK Right Out", NULL, "Right SPK Mixer"}, 869 {"REC Left Out", NULL, "Left REC Mixer"}, 870 {"REC Right Out", NULL, "Right REC Mixer"}, 871 872 {"HPL", NULL, "HP Left Out"}, 873 {"HPR", NULL, "HP Right Out"}, 874 {"SPKL", NULL, "SPK Left Out"}, 875 {"SPKR", NULL, "SPK Right Out"}, 876 {"RECL", NULL, "REC Left Out"}, 877 {"RECR", NULL, "REC Right Out"}, 878 879 /* Left ADC input mixer */ 880 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 881 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 882 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 883 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 884 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 885 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 886 887 /* Right ADC input mixer */ 888 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 889 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 890 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 891 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 892 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 893 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 894 895 /* Inputs */ 896 {"ADCL", NULL, "Left ADC Mixer"}, 897 {"ADCR", NULL, "Right ADC Mixer"}, 898 {"INA1 Input", NULL, "INA1"}, 899 {"INA2 Input", NULL, "INA2"}, 900 {"INB1 Input", NULL, "INB1"}, 901 {"INB2 Input", NULL, "INB2"}, 902 {"MIC1 Input", NULL, "MIC1"}, 903 {"MIC2 Input", NULL, "MIC2"}, 904 }; 905 906 /* codec mclk clock divider coefficients */ 907 static const struct { 908 u32 rate; 909 u8 sr; 910 } rate_table[] = { 911 {8000, 0x10}, 912 {11025, 0x20}, 913 {16000, 0x30}, 914 {22050, 0x40}, 915 {24000, 0x50}, 916 {32000, 0x60}, 917 {44100, 0x70}, 918 {48000, 0x80}, 919 {88200, 0x90}, 920 {96000, 0xA0}, 921 }; 922 923 static inline int rate_value(int rate, u8 *value) 924 { 925 int i; 926 927 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 928 if (rate_table[i].rate >= rate) { 929 *value = rate_table[i].sr; 930 return 0; 931 } 932 } 933 *value = rate_table[0].sr; 934 return -EINVAL; 935 } 936 937 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 938 struct snd_pcm_hw_params *params, 939 struct snd_soc_dai *dai) 940 { 941 struct snd_soc_component *component = dai->component; 942 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 943 struct max98088_cdata *cdata; 944 unsigned long long ni; 945 unsigned int rate; 946 u8 regval; 947 948 cdata = &max98088->dai[0]; 949 950 rate = params_rate(params); 951 952 switch (params_width(params)) { 953 case 16: 954 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 955 M98088_DAI_WS, 0); 956 break; 957 case 24: 958 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 959 M98088_DAI_WS, M98088_DAI_WS); 960 break; 961 default: 962 return -EINVAL; 963 } 964 965 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 966 967 if (rate_value(rate, ®val)) 968 return -EINVAL; 969 970 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE, 971 M98088_CLKMODE_MASK, regval); 972 cdata->rate = rate; 973 974 /* Configure NI when operating as master */ 975 if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT) 976 & M98088_DAI_MAS) { 977 unsigned long pclk; 978 979 if (max98088->sysclk == 0) { 980 dev_err(component->dev, "Invalid system clock frequency\n"); 981 return -EINVAL; 982 } 983 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 984 * (unsigned long long int)rate; 985 pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler); 986 ni = DIV_ROUND_CLOSEST_ULL(ni, pclk); 987 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 988 (ni >> 8) & 0x7F); 989 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 990 ni & 0xFF); 991 } 992 993 /* Update sample rate mode */ 994 if (rate < 50000) 995 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 996 M98088_DAI_DHF, 0); 997 else 998 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 999 M98088_DAI_DHF, M98088_DAI_DHF); 1000 1001 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1002 M98088_SHDNRUN); 1003 1004 return 0; 1005 } 1006 1007 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1008 struct snd_pcm_hw_params *params, 1009 struct snd_soc_dai *dai) 1010 { 1011 struct snd_soc_component *component = dai->component; 1012 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1013 struct max98088_cdata *cdata; 1014 unsigned long long ni; 1015 unsigned int rate; 1016 u8 regval; 1017 1018 cdata = &max98088->dai[1]; 1019 1020 rate = params_rate(params); 1021 1022 switch (params_width(params)) { 1023 case 16: 1024 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1025 M98088_DAI_WS, 0); 1026 break; 1027 case 24: 1028 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1029 M98088_DAI_WS, M98088_DAI_WS); 1030 break; 1031 default: 1032 return -EINVAL; 1033 } 1034 1035 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1036 1037 if (rate_value(rate, ®val)) 1038 return -EINVAL; 1039 1040 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE, 1041 M98088_CLKMODE_MASK, regval); 1042 cdata->rate = rate; 1043 1044 /* Configure NI when operating as master */ 1045 if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT) 1046 & M98088_DAI_MAS) { 1047 unsigned long pclk; 1048 1049 if (max98088->sysclk == 0) { 1050 dev_err(component->dev, "Invalid system clock frequency\n"); 1051 return -EINVAL; 1052 } 1053 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1054 * (unsigned long long int)rate; 1055 pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler); 1056 ni = DIV_ROUND_CLOSEST_ULL(ni, pclk); 1057 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1058 (ni >> 8) & 0x7F); 1059 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1060 ni & 0xFF); 1061 } 1062 1063 /* Update sample rate mode */ 1064 if (rate < 50000) 1065 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1066 M98088_DAI_DHF, 0); 1067 else 1068 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1069 M98088_DAI_DHF, M98088_DAI_DHF); 1070 1071 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1072 M98088_SHDNRUN); 1073 1074 return 0; 1075 } 1076 1077 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1078 int clk_id, unsigned int freq, int dir) 1079 { 1080 struct snd_soc_component *component = dai->component; 1081 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1082 1083 /* Requested clock frequency is already setup */ 1084 if (freq == max98088->sysclk) 1085 return 0; 1086 1087 if (!IS_ERR(max98088->mclk)) { 1088 freq = clk_round_rate(max98088->mclk, freq); 1089 clk_set_rate(max98088->mclk, freq); 1090 } 1091 1092 /* Setup clocks for slave mode, and using the PLL 1093 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1094 * 0x02 (when master clk is 20MHz to 30MHz).. 1095 */ 1096 if ((freq >= 10000000) && (freq < 20000000)) { 1097 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); 1098 max98088->mclk_prescaler = 1; 1099 } else if ((freq >= 20000000) && (freq < 30000000)) { 1100 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); 1101 max98088->mclk_prescaler = 2; 1102 } else { 1103 dev_err(component->dev, "Invalid master clock frequency\n"); 1104 return -EINVAL; 1105 } 1106 1107 if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1108 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1109 M98088_SHDNRUN, 0); 1110 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1111 M98088_SHDNRUN, M98088_SHDNRUN); 1112 } 1113 1114 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1115 1116 max98088->sysclk = freq; 1117 return 0; 1118 } 1119 1120 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1121 unsigned int fmt) 1122 { 1123 struct snd_soc_component *component = codec_dai->component; 1124 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1125 struct max98088_cdata *cdata; 1126 u8 reg15val; 1127 u8 reg14val = 0; 1128 1129 cdata = &max98088->dai[0]; 1130 1131 if (fmt != cdata->fmt) { 1132 cdata->fmt = fmt; 1133 1134 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1135 case SND_SOC_DAIFMT_CBC_CFC: 1136 /* Consumer mode PLL */ 1137 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 1138 0x80); 1139 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 1140 0x00); 1141 break; 1142 case SND_SOC_DAIFMT_CBP_CFP: 1143 /* Set to provider mode */ 1144 reg14val |= M98088_DAI_MAS; 1145 break; 1146 default: 1147 dev_err(component->dev, "Clock mode unsupported"); 1148 return -EINVAL; 1149 } 1150 1151 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1152 case SND_SOC_DAIFMT_I2S: 1153 reg14val |= M98088_DAI_DLY; 1154 break; 1155 case SND_SOC_DAIFMT_LEFT_J: 1156 break; 1157 default: 1158 return -EINVAL; 1159 } 1160 1161 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1162 case SND_SOC_DAIFMT_NB_NF: 1163 break; 1164 case SND_SOC_DAIFMT_NB_IF: 1165 reg14val |= M98088_DAI_WCI; 1166 break; 1167 case SND_SOC_DAIFMT_IB_NF: 1168 reg14val |= M98088_DAI_BCI; 1169 break; 1170 case SND_SOC_DAIFMT_IB_IF: 1171 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1172 break; 1173 default: 1174 return -EINVAL; 1175 } 1176 1177 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 1178 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1179 M98088_DAI_WCI, reg14val); 1180 1181 reg15val = M98088_DAI_BSEL64; 1182 if (max98088->digmic) 1183 reg15val |= M98088_DAI_OSR64; 1184 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val); 1185 } 1186 1187 return 0; 1188 } 1189 1190 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1191 unsigned int fmt) 1192 { 1193 struct snd_soc_component *component = codec_dai->component; 1194 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1195 struct max98088_cdata *cdata; 1196 u8 reg1Cval = 0; 1197 1198 cdata = &max98088->dai[1]; 1199 1200 if (fmt != cdata->fmt) { 1201 cdata->fmt = fmt; 1202 1203 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1204 case SND_SOC_DAIFMT_CBC_CFC: 1205 /* Consumer mode PLL */ 1206 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1207 0x80); 1208 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1209 0x00); 1210 break; 1211 case SND_SOC_DAIFMT_CBP_CFP: 1212 /* Set to provider mode */ 1213 reg1Cval |= M98088_DAI_MAS; 1214 break; 1215 default: 1216 dev_err(component->dev, "Clock mode unsupported"); 1217 return -EINVAL; 1218 } 1219 1220 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1221 case SND_SOC_DAIFMT_I2S: 1222 reg1Cval |= M98088_DAI_DLY; 1223 break; 1224 case SND_SOC_DAIFMT_LEFT_J: 1225 break; 1226 default: 1227 return -EINVAL; 1228 } 1229 1230 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1231 case SND_SOC_DAIFMT_NB_NF: 1232 break; 1233 case SND_SOC_DAIFMT_NB_IF: 1234 reg1Cval |= M98088_DAI_WCI; 1235 break; 1236 case SND_SOC_DAIFMT_IB_NF: 1237 reg1Cval |= M98088_DAI_BCI; 1238 break; 1239 case SND_SOC_DAIFMT_IB_IF: 1240 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1241 break; 1242 default: 1243 return -EINVAL; 1244 } 1245 1246 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1247 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1248 M98088_DAI_WCI, reg1Cval); 1249 1250 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK, 1251 M98088_DAI_BSEL64); 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute, 1258 int direction) 1259 { 1260 struct snd_soc_component *component = codec_dai->component; 1261 int reg; 1262 1263 if (mute) 1264 reg = M98088_DAI_MUTE; 1265 else 1266 reg = 0; 1267 1268 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY, 1269 M98088_DAI_MUTE_MASK, reg); 1270 return 0; 1271 } 1272 1273 static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute, 1274 int direction) 1275 { 1276 struct snd_soc_component *component = codec_dai->component; 1277 int reg; 1278 1279 if (mute) 1280 reg = M98088_DAI_MUTE; 1281 else 1282 reg = 0; 1283 1284 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY, 1285 M98088_DAI_MUTE_MASK, reg); 1286 return 0; 1287 } 1288 1289 static int max98088_set_bias_level(struct snd_soc_component *component, 1290 enum snd_soc_bias_level level) 1291 { 1292 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1293 int ret; 1294 1295 switch (level) { 1296 case SND_SOC_BIAS_ON: 1297 break; 1298 1299 case SND_SOC_BIAS_PREPARE: 1300 /* 1301 * SND_SOC_BIAS_PREPARE is called while preparing for a 1302 * transition to ON or away from ON. If current bias_level 1303 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1304 * away from ON. Disable the clock in that case, otherwise 1305 * enable it. 1306 */ 1307 if (!IS_ERR(max98088->mclk)) { 1308 if (snd_soc_component_get_bias_level(component) == 1309 SND_SOC_BIAS_ON) { 1310 clk_disable_unprepare(max98088->mclk); 1311 } else { 1312 ret = clk_prepare_enable(max98088->mclk); 1313 if (ret) 1314 return ret; 1315 } 1316 } 1317 break; 1318 1319 case SND_SOC_BIAS_STANDBY: 1320 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1321 regcache_sync(max98088->regmap); 1322 1323 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1324 M98088_MBEN, M98088_MBEN); 1325 break; 1326 1327 case SND_SOC_BIAS_OFF: 1328 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1329 M98088_MBEN, 0); 1330 regcache_mark_dirty(max98088->regmap); 1331 break; 1332 } 1333 return 0; 1334 } 1335 1336 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1337 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1338 1339 static const struct snd_soc_dai_ops max98088_dai1_ops = { 1340 .set_sysclk = max98088_dai_set_sysclk, 1341 .set_fmt = max98088_dai1_set_fmt, 1342 .hw_params = max98088_dai1_hw_params, 1343 .mute_stream = max98088_dai1_mute, 1344 .no_capture_mute = 1, 1345 }; 1346 1347 static const struct snd_soc_dai_ops max98088_dai2_ops = { 1348 .set_sysclk = max98088_dai_set_sysclk, 1349 .set_fmt = max98088_dai2_set_fmt, 1350 .hw_params = max98088_dai2_hw_params, 1351 .mute_stream = max98088_dai2_mute, 1352 .no_capture_mute = 1, 1353 }; 1354 1355 static struct snd_soc_dai_driver max98088_dai[] = { 1356 { 1357 .name = "HiFi", 1358 .playback = { 1359 .stream_name = "HiFi Playback", 1360 .channels_min = 1, 1361 .channels_max = 2, 1362 .rates = MAX98088_RATES, 1363 .formats = MAX98088_FORMATS, 1364 }, 1365 .capture = { 1366 .stream_name = "HiFi Capture", 1367 .channels_min = 1, 1368 .channels_max = 2, 1369 .rates = MAX98088_RATES, 1370 .formats = MAX98088_FORMATS, 1371 }, 1372 .ops = &max98088_dai1_ops, 1373 }, 1374 { 1375 .name = "Aux", 1376 .playback = { 1377 .stream_name = "Aux Playback", 1378 .channels_min = 1, 1379 .channels_max = 2, 1380 .rates = MAX98088_RATES, 1381 .formats = MAX98088_FORMATS, 1382 }, 1383 .ops = &max98088_dai2_ops, 1384 } 1385 }; 1386 1387 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; 1388 1389 static int max98088_get_channel(struct snd_soc_component *component, const char *name) 1390 { 1391 int ret; 1392 1393 ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name); 1394 if (ret < 0) 1395 dev_err(component->dev, "Bad EQ channel name '%s'\n", name); 1396 return ret; 1397 } 1398 1399 static void max98088_setup_eq1(struct snd_soc_component *component) 1400 { 1401 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1402 struct max98088_pdata *pdata = max98088->pdata; 1403 struct max98088_eq_cfg *coef_set; 1404 int best, best_val, save, i, sel, fs; 1405 struct max98088_cdata *cdata; 1406 1407 cdata = &max98088->dai[0]; 1408 1409 if (!pdata || !max98088->eq_textcnt) 1410 return; 1411 1412 /* Find the selected configuration with nearest sample rate */ 1413 fs = cdata->rate; 1414 sel = cdata->eq_sel; 1415 1416 best = 0; 1417 best_val = INT_MAX; 1418 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1419 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1420 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1421 best = i; 1422 best_val = abs(pdata->eq_cfg[i].rate - fs); 1423 } 1424 } 1425 1426 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1427 pdata->eq_cfg[best].name, 1428 pdata->eq_cfg[best].rate, fs); 1429 1430 /* Disable EQ while configuring, and save current on/off state */ 1431 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL); 1432 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1433 1434 coef_set = &pdata->eq_cfg[sel]; 1435 1436 m98088_eq_band(component, 0, 0, coef_set->band1); 1437 m98088_eq_band(component, 0, 1, coef_set->band2); 1438 m98088_eq_band(component, 0, 2, coef_set->band3); 1439 m98088_eq_band(component, 0, 3, coef_set->band4); 1440 m98088_eq_band(component, 0, 4, coef_set->band5); 1441 1442 /* Restore the original on/off state */ 1443 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1444 } 1445 1446 static void max98088_setup_eq2(struct snd_soc_component *component) 1447 { 1448 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1449 struct max98088_pdata *pdata = max98088->pdata; 1450 struct max98088_eq_cfg *coef_set; 1451 int best, best_val, save, i, sel, fs; 1452 struct max98088_cdata *cdata; 1453 1454 cdata = &max98088->dai[1]; 1455 1456 if (!pdata || !max98088->eq_textcnt) 1457 return; 1458 1459 /* Find the selected configuration with nearest sample rate */ 1460 fs = cdata->rate; 1461 1462 sel = cdata->eq_sel; 1463 best = 0; 1464 best_val = INT_MAX; 1465 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1466 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1467 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1468 best = i; 1469 best_val = abs(pdata->eq_cfg[i].rate - fs); 1470 } 1471 } 1472 1473 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1474 pdata->eq_cfg[best].name, 1475 pdata->eq_cfg[best].rate, fs); 1476 1477 /* Disable EQ while configuring, and save current on/off state */ 1478 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL); 1479 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1480 1481 coef_set = &pdata->eq_cfg[sel]; 1482 1483 m98088_eq_band(component, 1, 0, coef_set->band1); 1484 m98088_eq_band(component, 1, 1, coef_set->band2); 1485 m98088_eq_band(component, 1, 2, coef_set->band3); 1486 m98088_eq_band(component, 1, 3, coef_set->band4); 1487 m98088_eq_band(component, 1, 4, coef_set->band5); 1488 1489 /* Restore the original on/off state */ 1490 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1491 save); 1492 } 1493 1494 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1495 struct snd_ctl_elem_value *ucontrol) 1496 { 1497 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1498 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1499 struct max98088_pdata *pdata = max98088->pdata; 1500 int channel = max98088_get_channel(component, kcontrol->id.name); 1501 struct max98088_cdata *cdata; 1502 int sel = ucontrol->value.enumerated.item[0]; 1503 1504 if (channel < 0) 1505 return channel; 1506 1507 cdata = &max98088->dai[channel]; 1508 1509 if (sel >= pdata->eq_cfgcnt) 1510 return -EINVAL; 1511 1512 cdata->eq_sel = sel; 1513 1514 switch (channel) { 1515 case 0: 1516 max98088_setup_eq1(component); 1517 break; 1518 case 1: 1519 max98088_setup_eq2(component); 1520 break; 1521 } 1522 1523 return 0; 1524 } 1525 1526 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1527 struct snd_ctl_elem_value *ucontrol) 1528 { 1529 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1530 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1531 int channel = max98088_get_channel(component, kcontrol->id.name); 1532 struct max98088_cdata *cdata; 1533 1534 if (channel < 0) 1535 return channel; 1536 1537 cdata = &max98088->dai[channel]; 1538 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1539 return 0; 1540 } 1541 1542 static void max98088_handle_eq_pdata(struct snd_soc_component *component) 1543 { 1544 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1545 struct max98088_pdata *pdata = max98088->pdata; 1546 struct max98088_eq_cfg *cfg; 1547 unsigned int cfgcnt; 1548 int i, j; 1549 const char **t; 1550 int ret; 1551 struct snd_kcontrol_new controls[] = { 1552 SOC_ENUM_EXT((char *)eq_mode_name[0], 1553 max98088->eq_enum, 1554 max98088_get_eq_enum, 1555 max98088_put_eq_enum), 1556 SOC_ENUM_EXT((char *)eq_mode_name[1], 1557 max98088->eq_enum, 1558 max98088_get_eq_enum, 1559 max98088_put_eq_enum), 1560 }; 1561 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name)); 1562 1563 cfg = pdata->eq_cfg; 1564 cfgcnt = pdata->eq_cfgcnt; 1565 1566 /* Setup an array of texts for the equalizer enum. 1567 * This is based on Mark Brown's equalizer driver code. 1568 */ 1569 max98088->eq_textcnt = 0; 1570 max98088->eq_texts = NULL; 1571 for (i = 0; i < cfgcnt; i++) { 1572 for (j = 0; j < max98088->eq_textcnt; j++) { 1573 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1574 break; 1575 } 1576 1577 if (j != max98088->eq_textcnt) 1578 continue; 1579 1580 /* Expand the array */ 1581 t = krealloc(max98088->eq_texts, 1582 sizeof(char *) * (max98088->eq_textcnt + 1), 1583 GFP_KERNEL); 1584 if (t == NULL) 1585 continue; 1586 1587 /* Store the new entry */ 1588 t[max98088->eq_textcnt] = cfg[i].name; 1589 max98088->eq_textcnt++; 1590 max98088->eq_texts = t; 1591 } 1592 1593 /* Now point the soc_enum to .texts array items */ 1594 max98088->eq_enum.texts = max98088->eq_texts; 1595 max98088->eq_enum.items = max98088->eq_textcnt; 1596 1597 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 1598 if (ret != 0) 1599 dev_err(component->dev, "Failed to add EQ control: %d\n", ret); 1600 } 1601 1602 static void max98088_handle_pdata(struct snd_soc_component *component) 1603 { 1604 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1605 struct max98088_pdata *pdata = max98088->pdata; 1606 u8 regval = 0; 1607 1608 if (!pdata) { 1609 dev_dbg(component->dev, "No platform data\n"); 1610 return; 1611 } 1612 1613 /* Configure mic for analog/digital mic mode */ 1614 if (pdata->digmic_left_mode) 1615 regval |= M98088_DIGMIC_L; 1616 1617 if (pdata->digmic_right_mode) 1618 regval |= M98088_DIGMIC_R; 1619 1620 max98088->digmic = (regval ? 1 : 0); 1621 1622 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval); 1623 1624 /* Configure receiver output */ 1625 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1626 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL, 1627 M98088_REC_LINEMODE_MASK, regval); 1628 1629 /* Configure equalizers */ 1630 if (pdata->eq_cfgcnt) 1631 max98088_handle_eq_pdata(component); 1632 } 1633 1634 static int max98088_probe(struct snd_soc_component *component) 1635 { 1636 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1637 struct max98088_cdata *cdata; 1638 int ret = 0; 1639 1640 regcache_mark_dirty(max98088->regmap); 1641 1642 /* initialize private data */ 1643 1644 max98088->sysclk = (unsigned)-1; 1645 max98088->eq_textcnt = 0; 1646 1647 cdata = &max98088->dai[0]; 1648 cdata->rate = (unsigned)-1; 1649 cdata->fmt = (unsigned)-1; 1650 cdata->eq_sel = 0; 1651 1652 cdata = &max98088->dai[1]; 1653 cdata->rate = (unsigned)-1; 1654 cdata->fmt = (unsigned)-1; 1655 cdata->eq_sel = 0; 1656 1657 max98088->ina_state = 0; 1658 max98088->inb_state = 0; 1659 max98088->ex_mode = 0; 1660 max98088->digmic = 0; 1661 max98088->mic1pre = 0; 1662 max98088->mic2pre = 0; 1663 1664 ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID); 1665 if (ret < 0) { 1666 dev_err(component->dev, "Failed to read device revision: %d\n", 1667 ret); 1668 goto err_access; 1669 } 1670 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A'); 1671 1672 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV); 1673 1674 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00); 1675 1676 snd_soc_component_write(component, M98088_REG_22_MIX_DAC, 1677 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 1678 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 1679 1680 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0); 1681 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F); 1682 1683 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG, 1684 M98088_S1NORMAL|M98088_SDATA); 1685 1686 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG, 1687 M98088_S2NORMAL|M98088_SDATA); 1688 1689 max98088_handle_pdata(component); 1690 1691 err_access: 1692 return ret; 1693 } 1694 1695 static void max98088_remove(struct snd_soc_component *component) 1696 { 1697 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1698 1699 kfree(max98088->eq_texts); 1700 } 1701 1702 static const struct snd_soc_component_driver soc_component_dev_max98088 = { 1703 .probe = max98088_probe, 1704 .remove = max98088_remove, 1705 .set_bias_level = max98088_set_bias_level, 1706 .controls = max98088_snd_controls, 1707 .num_controls = ARRAY_SIZE(max98088_snd_controls), 1708 .dapm_widgets = max98088_dapm_widgets, 1709 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 1710 .dapm_routes = max98088_audio_map, 1711 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map), 1712 .suspend_bias_off = 1, 1713 .idle_bias_on = 1, 1714 .use_pmdown_time = 1, 1715 .endianness = 1, 1716 }; 1717 1718 static const struct i2c_device_id max98088_i2c_id[] = { 1719 { "max98088", MAX98088 }, 1720 { "max98089", MAX98089 }, 1721 { } 1722 }; 1723 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 1724 1725 static int max98088_i2c_probe(struct i2c_client *i2c) 1726 { 1727 struct max98088_priv *max98088; 1728 const struct i2c_device_id *id; 1729 1730 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv), 1731 GFP_KERNEL); 1732 if (max98088 == NULL) 1733 return -ENOMEM; 1734 1735 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap); 1736 if (IS_ERR(max98088->regmap)) 1737 return PTR_ERR(max98088->regmap); 1738 1739 max98088->mclk = devm_clk_get(&i2c->dev, "mclk"); 1740 if (IS_ERR(max98088->mclk)) 1741 if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER) 1742 return PTR_ERR(max98088->mclk); 1743 1744 id = i2c_match_id(max98088_i2c_id, i2c); 1745 max98088->devtype = id->driver_data; 1746 1747 i2c_set_clientdata(i2c, max98088); 1748 max98088->pdata = i2c->dev.platform_data; 1749 1750 return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_max98088, 1751 &max98088_dai[0], 2); 1752 } 1753 1754 #if defined(CONFIG_OF) 1755 static const struct of_device_id max98088_of_match[] = { 1756 { .compatible = "maxim,max98088" }, 1757 { .compatible = "maxim,max98089" }, 1758 { } 1759 }; 1760 MODULE_DEVICE_TABLE(of, max98088_of_match); 1761 #endif 1762 1763 static struct i2c_driver max98088_i2c_driver = { 1764 .driver = { 1765 .name = "max98088", 1766 .of_match_table = of_match_ptr(max98088_of_match), 1767 }, 1768 .probe = max98088_i2c_probe, 1769 .id_table = max98088_i2c_id, 1770 }; 1771 1772 module_i2c_driver(max98088_i2c_driver); 1773 1774 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 1775 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 1776 MODULE_LICENSE("GPL"); 1777