1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of_clk.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <sound/soc.h> 16 #include <sound/soc-dapm.h> 17 #include <sound/tlv.h> 18 19 #include "lpass-macro-common.h" 20 21 /* VA macro registers */ 22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 23 #define CDC_VA_MCLK_CONTROL_EN BIT(0) 24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 25 #define CDC_VA_FS_CONTROL_EN BIT(0) 26 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 27 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080) 28 #define CDC_VA_FS_BROADCAST_EN BIT(1) 29 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) 30 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) 31 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) 32 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) 33 #define CDC_VA_DMIC_EN_MASK BIT(0) 34 #define CDC_VA_DMIC_ENABLE BIT(0) 35 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) 36 #define CDC_VA_DMIC_CLK_SEL_SHFT 1 37 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 38 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 39 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 40 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 41 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 42 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa 43 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094) 44 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7) 45 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) 46 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0 47 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) 48 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3) 49 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) 50 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2) 51 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) 52 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1) 53 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) 54 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0) 55 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0 56 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) 57 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0) 58 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) 59 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) 60 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) 61 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) 62 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) 63 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) 64 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) 65 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0) 66 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4) 67 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8) 68 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC) 69 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) 70 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) 71 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108) 72 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C) 73 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110) 74 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114) 75 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118) 76 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C) 77 #define CDC_VA_TX0_TX_PATH_CTL (0x0400) 78 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5) 79 #define CDC_VA_TX_PATH_CLK_EN BIT(5) 80 #define CDC_VA_TX_PATH_CLK_DISABLE 0 81 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4) 82 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4) 83 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0 84 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404) 85 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1) 86 #define CDC_VA_ADC_MODE_SHIFT 1 87 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5) 88 #define CF_MIN_3DB_4HZ 0x0 89 #define CF_MIN_3DB_75HZ 0x1 90 #define CF_MIN_3DB_150HZ 0x2 91 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408) 92 #define CDC_VA_TX0_TX_VOL_CTL (0x040C) 93 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410) 94 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414) 95 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418) 96 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1) 97 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1) 98 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0) 99 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0) 100 #define CDC_VA_TX_HPF_ZERO_GATE 0 101 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C) 102 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420) 103 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424) 104 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428) 105 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C) 106 #define CDC_VA_TX1_TX_PATH_CTL (0x0480) 107 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484) 108 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488) 109 #define CDC_VA_TX1_TX_VOL_CTL (0x048C) 110 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490) 111 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494) 112 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498) 113 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C) 114 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0) 115 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4) 116 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8) 117 #define CDC_VA_TX2_TX_PATH_CTL (0x0500) 118 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504) 119 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508) 120 #define CDC_VA_TX2_TX_VOL_CTL (0x050C) 121 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510) 122 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514) 123 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518) 124 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C) 125 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520) 126 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524) 127 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528) 128 #define CDC_VA_TX3_TX_PATH_CTL (0x0580) 129 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584) 130 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7) 131 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7) 132 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0 133 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588) 134 #define CDC_VA_TX3_TX_VOL_CTL (0x058C) 135 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590) 136 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594) 137 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598) 138 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C) 139 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0) 140 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) 141 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) 142 143 #define VA_MAX_OFFSET (0x07A8) 144 145 #define VA_MACRO_NUM_DECIMATORS 4 146 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 147 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 148 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 149 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 150 SNDRV_PCM_FMTBIT_S24_LE |\ 151 SNDRV_PCM_FMTBIT_S24_3LE) 152 153 #define VA_MACRO_MCLK_FREQ 9600000 154 #define VA_MACRO_TX_PATH_OFFSET 0x80 155 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF 156 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8 157 158 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 159 160 enum { 161 VA_MACRO_AIF_INVALID = 0, 162 VA_MACRO_AIF1_CAP, 163 VA_MACRO_AIF2_CAP, 164 VA_MACRO_AIF3_CAP, 165 VA_MACRO_MAX_DAIS, 166 }; 167 168 enum { 169 VA_MACRO_DEC0, 170 VA_MACRO_DEC1, 171 VA_MACRO_DEC2, 172 VA_MACRO_DEC3, 173 VA_MACRO_DEC4, 174 VA_MACRO_DEC5, 175 VA_MACRO_DEC6, 176 VA_MACRO_DEC7, 177 VA_MACRO_DEC_MAX, 178 }; 179 180 enum { 181 VA_MACRO_CLK_DIV_2, 182 VA_MACRO_CLK_DIV_3, 183 VA_MACRO_CLK_DIV_4, 184 VA_MACRO_CLK_DIV_6, 185 VA_MACRO_CLK_DIV_8, 186 VA_MACRO_CLK_DIV_16, 187 }; 188 189 #define VA_NUM_CLKS_MAX 3 190 191 struct va_macro { 192 struct device *dev; 193 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS]; 194 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS]; 195 u16 dmic_clk_div; 196 197 int dec_mode[VA_MACRO_NUM_DECIMATORS]; 198 struct regmap *regmap; 199 struct clk *mclk; 200 struct clk *macro; 201 struct clk *dcodec; 202 struct clk_hw hw; 203 struct lpass_macro *pds; 204 205 s32 dmic_0_1_clk_cnt; 206 s32 dmic_2_3_clk_cnt; 207 s32 dmic_4_5_clk_cnt; 208 s32 dmic_6_7_clk_cnt; 209 u8 dmic_0_1_clk_div; 210 u8 dmic_2_3_clk_div; 211 u8 dmic_4_5_clk_div; 212 u8 dmic_6_7_clk_div; 213 }; 214 215 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw) 216 217 static bool va_is_volatile_register(struct device *dev, unsigned int reg) 218 { 219 switch (reg) { 220 case CDC_VA_TOP_CSR_CORE_ID_0: 221 case CDC_VA_TOP_CSR_CORE_ID_1: 222 case CDC_VA_TOP_CSR_CORE_ID_2: 223 case CDC_VA_TOP_CSR_CORE_ID_3: 224 case CDC_VA_TOP_CSR_DMIC0_CTL: 225 case CDC_VA_TOP_CSR_DMIC1_CTL: 226 case CDC_VA_TOP_CSR_DMIC2_CTL: 227 case CDC_VA_TOP_CSR_DMIC3_CTL: 228 return true; 229 } 230 return false; 231 } 232 233 static const struct reg_default va_defaults[] = { 234 /* VA macro */ 235 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 236 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 237 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 238 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, 239 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, 240 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, 241 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, 242 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, 243 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, 244 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, 245 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, 246 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, 247 { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, 248 { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, 249 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, 250 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, 251 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, 252 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, 253 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, 254 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, 255 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, 256 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, 257 258 /* VA core */ 259 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, 260 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, 261 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, 262 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, 263 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, 264 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, 265 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, 266 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, 267 { CDC_VA_TX0_TX_PATH_CTL, 0x04}, 268 { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, 269 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, 270 { CDC_VA_TX0_TX_VOL_CTL, 0x00}, 271 { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, 272 { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, 273 { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, 274 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, 275 { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, 276 { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, 277 { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, 278 { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, 279 { CDC_VA_TX1_TX_PATH_CTL, 0x04}, 280 { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, 281 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, 282 { CDC_VA_TX1_TX_VOL_CTL, 0x00}, 283 { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, 284 { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, 285 { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, 286 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, 287 { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, 288 { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, 289 { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, 290 { CDC_VA_TX2_TX_PATH_CTL, 0x04}, 291 { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, 292 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, 293 { CDC_VA_TX2_TX_VOL_CTL, 0x00}, 294 { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, 295 { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, 296 { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, 297 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, 298 { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, 299 { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, 300 { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, 301 { CDC_VA_TX3_TX_PATH_CTL, 0x04}, 302 { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, 303 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, 304 { CDC_VA_TX3_TX_VOL_CTL, 0x00}, 305 { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, 306 { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, 307 { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, 308 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, 309 { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, 310 { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, 311 { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, 312 }; 313 314 static bool va_is_rw_register(struct device *dev, unsigned int reg) 315 { 316 switch (reg) { 317 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL: 318 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL: 319 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL: 320 case CDC_VA_TOP_CSR_TOP_CFG0: 321 case CDC_VA_TOP_CSR_DMIC0_CTL: 322 case CDC_VA_TOP_CSR_DMIC1_CTL: 323 case CDC_VA_TOP_CSR_DMIC2_CTL: 324 case CDC_VA_TOP_CSR_DMIC3_CTL: 325 case CDC_VA_TOP_CSR_DMIC_CFG: 326 case CDC_VA_TOP_CSR_DEBUG_BUS: 327 case CDC_VA_TOP_CSR_DEBUG_EN: 328 case CDC_VA_TOP_CSR_TX_I2S_CTL: 329 case CDC_VA_TOP_CSR_I2S_CLK: 330 case CDC_VA_TOP_CSR_I2S_RESET: 331 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 332 case CDC_VA_INP_MUX_ADC_MUX0_CFG1: 333 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 334 case CDC_VA_INP_MUX_ADC_MUX1_CFG1: 335 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 336 case CDC_VA_INP_MUX_ADC_MUX2_CFG1: 337 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 338 case CDC_VA_INP_MUX_ADC_MUX3_CFG1: 339 case CDC_VA_TX0_TX_PATH_CTL: 340 case CDC_VA_TX0_TX_PATH_CFG0: 341 case CDC_VA_TX0_TX_PATH_CFG1: 342 case CDC_VA_TX0_TX_VOL_CTL: 343 case CDC_VA_TX0_TX_PATH_SEC0: 344 case CDC_VA_TX0_TX_PATH_SEC1: 345 case CDC_VA_TX0_TX_PATH_SEC2: 346 case CDC_VA_TX0_TX_PATH_SEC3: 347 case CDC_VA_TX0_TX_PATH_SEC4: 348 case CDC_VA_TX0_TX_PATH_SEC5: 349 case CDC_VA_TX0_TX_PATH_SEC6: 350 case CDC_VA_TX0_TX_PATH_SEC7: 351 case CDC_VA_TX1_TX_PATH_CTL: 352 case CDC_VA_TX1_TX_PATH_CFG0: 353 case CDC_VA_TX1_TX_PATH_CFG1: 354 case CDC_VA_TX1_TX_VOL_CTL: 355 case CDC_VA_TX1_TX_PATH_SEC0: 356 case CDC_VA_TX1_TX_PATH_SEC1: 357 case CDC_VA_TX1_TX_PATH_SEC2: 358 case CDC_VA_TX1_TX_PATH_SEC3: 359 case CDC_VA_TX1_TX_PATH_SEC4: 360 case CDC_VA_TX1_TX_PATH_SEC5: 361 case CDC_VA_TX1_TX_PATH_SEC6: 362 case CDC_VA_TX2_TX_PATH_CTL: 363 case CDC_VA_TX2_TX_PATH_CFG0: 364 case CDC_VA_TX2_TX_PATH_CFG1: 365 case CDC_VA_TX2_TX_VOL_CTL: 366 case CDC_VA_TX2_TX_PATH_SEC0: 367 case CDC_VA_TX2_TX_PATH_SEC1: 368 case CDC_VA_TX2_TX_PATH_SEC2: 369 case CDC_VA_TX2_TX_PATH_SEC3: 370 case CDC_VA_TX2_TX_PATH_SEC4: 371 case CDC_VA_TX2_TX_PATH_SEC5: 372 case CDC_VA_TX2_TX_PATH_SEC6: 373 case CDC_VA_TX3_TX_PATH_CTL: 374 case CDC_VA_TX3_TX_PATH_CFG0: 375 case CDC_VA_TX3_TX_PATH_CFG1: 376 case CDC_VA_TX3_TX_VOL_CTL: 377 case CDC_VA_TX3_TX_PATH_SEC0: 378 case CDC_VA_TX3_TX_PATH_SEC1: 379 case CDC_VA_TX3_TX_PATH_SEC2: 380 case CDC_VA_TX3_TX_PATH_SEC3: 381 case CDC_VA_TX3_TX_PATH_SEC4: 382 case CDC_VA_TX3_TX_PATH_SEC5: 383 case CDC_VA_TX3_TX_PATH_SEC6: 384 return true; 385 } 386 387 return false; 388 } 389 390 static bool va_is_readable_register(struct device *dev, unsigned int reg) 391 { 392 switch (reg) { 393 case CDC_VA_TOP_CSR_CORE_ID_0: 394 case CDC_VA_TOP_CSR_CORE_ID_1: 395 case CDC_VA_TOP_CSR_CORE_ID_2: 396 case CDC_VA_TOP_CSR_CORE_ID_3: 397 return true; 398 } 399 400 return va_is_rw_register(dev, reg); 401 } 402 403 static const struct regmap_config va_regmap_config = { 404 .name = "va_macro", 405 .reg_bits = 32, 406 .val_bits = 32, 407 .reg_stride = 4, 408 .cache_type = REGCACHE_FLAT, 409 .reg_defaults = va_defaults, 410 .num_reg_defaults = ARRAY_SIZE(va_defaults), 411 .max_register = VA_MAX_OFFSET, 412 .volatile_reg = va_is_volatile_register, 413 .readable_reg = va_is_readable_register, 414 .writeable_reg = va_is_rw_register, 415 }; 416 417 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) 418 { 419 struct regmap *regmap = va->regmap; 420 421 if (enable) { 422 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 423 CDC_VA_MCLK_CONTROL_EN, 424 CDC_VA_MCLK_CONTROL_EN); 425 426 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 427 CDC_VA_FS_CONTROL_EN, 428 CDC_VA_FS_CONTROL_EN); 429 430 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 431 CDC_VA_FS_BROADCAST_EN, 432 CDC_VA_FS_BROADCAST_EN); 433 } else { 434 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 435 CDC_VA_MCLK_CONTROL_EN, 0x0); 436 437 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 438 CDC_VA_FS_CONTROL_EN, 0x0); 439 440 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 441 CDC_VA_FS_BROADCAST_EN, 0x0); 442 } 443 444 return 0; 445 } 446 447 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable) 448 { 449 struct regmap *regmap = va->regmap; 450 451 if (mclk_enable) { 452 va_clk_rsc_fs_gen_request(va, true); 453 regcache_mark_dirty(regmap); 454 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); 455 } else { 456 va_clk_rsc_fs_gen_request(va, false); 457 } 458 459 return 0; 460 } 461 462 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, 463 struct snd_kcontrol *kcontrol, int event) 464 { 465 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 466 struct va_macro *va = snd_soc_component_get_drvdata(comp); 467 468 switch (event) { 469 case SND_SOC_DAPM_PRE_PMU: 470 return va_macro_mclk_enable(va, true); 471 case SND_SOC_DAPM_POST_PMD: 472 return va_macro_mclk_enable(va, false); 473 } 474 475 return 0; 476 } 477 478 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 479 struct snd_ctl_elem_value *ucontrol) 480 { 481 struct snd_soc_dapm_widget *widget = 482 snd_soc_dapm_kcontrol_widget(kcontrol); 483 struct snd_soc_component *component = 484 snd_soc_dapm_to_component(widget->dapm); 485 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 486 unsigned int val; 487 u16 mic_sel_reg; 488 489 val = ucontrol->value.enumerated.item[0]; 490 491 switch (e->reg) { 492 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 493 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0; 494 break; 495 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 496 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0; 497 break; 498 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 499 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0; 500 break; 501 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 502 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0; 503 break; 504 default: 505 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", 506 __func__, e->reg); 507 return -EINVAL; 508 } 509 510 if (val != 0) 511 snd_soc_component_update_bits(component, mic_sel_reg, 512 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, 513 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); 514 515 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 516 } 517 518 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 519 struct snd_ctl_elem_value *ucontrol) 520 { 521 struct snd_soc_dapm_widget *widget = 522 snd_soc_dapm_kcontrol_widget(kcontrol); 523 struct snd_soc_component *component = 524 snd_soc_dapm_to_component(widget->dapm); 525 struct soc_mixer_control *mc = 526 (struct soc_mixer_control *)kcontrol->private_value; 527 u32 dai_id = widget->shift; 528 u32 dec_id = mc->shift; 529 struct va_macro *va = snd_soc_component_get_drvdata(component); 530 531 if (test_bit(dec_id, &va->active_ch_mask[dai_id])) 532 ucontrol->value.integer.value[0] = 1; 533 else 534 ucontrol->value.integer.value[0] = 0; 535 536 return 0; 537 } 538 539 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 540 struct snd_ctl_elem_value *ucontrol) 541 { 542 struct snd_soc_dapm_widget *widget = 543 snd_soc_dapm_kcontrol_widget(kcontrol); 544 struct snd_soc_component *component = 545 snd_soc_dapm_to_component(widget->dapm); 546 struct snd_soc_dapm_update *update = NULL; 547 struct soc_mixer_control *mc = 548 (struct soc_mixer_control *)kcontrol->private_value; 549 u32 dai_id = widget->shift; 550 u32 dec_id = mc->shift; 551 u32 enable = ucontrol->value.integer.value[0]; 552 struct va_macro *va = snd_soc_component_get_drvdata(component); 553 554 if (enable) { 555 set_bit(dec_id, &va->active_ch_mask[dai_id]); 556 va->active_ch_cnt[dai_id]++; 557 } else { 558 clear_bit(dec_id, &va->active_ch_mask[dai_id]); 559 va->active_ch_cnt[dai_id]--; 560 } 561 562 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 563 564 return 0; 565 } 566 567 static int va_dmic_clk_enable(struct snd_soc_component *component, 568 u32 dmic, bool enable) 569 { 570 struct va_macro *va = snd_soc_component_get_drvdata(component); 571 u16 dmic_clk_reg; 572 s32 *dmic_clk_cnt; 573 u8 *dmic_clk_div; 574 u8 freq_change_mask; 575 u8 clk_div; 576 577 switch (dmic) { 578 case 0: 579 case 1: 580 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt); 581 dmic_clk_div = &(va->dmic_0_1_clk_div); 582 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL; 583 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK; 584 break; 585 case 2: 586 case 3: 587 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt); 588 dmic_clk_div = &(va->dmic_2_3_clk_div); 589 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL; 590 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK; 591 break; 592 case 4: 593 case 5: 594 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt); 595 dmic_clk_div = &(va->dmic_4_5_clk_div); 596 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL; 597 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK; 598 break; 599 case 6: 600 case 7: 601 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt); 602 dmic_clk_div = &(va->dmic_6_7_clk_div); 603 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL; 604 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK; 605 break; 606 default: 607 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 608 __func__); 609 return -EINVAL; 610 } 611 612 if (enable) { 613 clk_div = va->dmic_clk_div; 614 (*dmic_clk_cnt)++; 615 if (*dmic_clk_cnt == 1) { 616 snd_soc_component_update_bits(component, 617 CDC_VA_TOP_CSR_DMIC_CFG, 618 CDC_VA_RESET_ALL_DMICS_MASK, 619 CDC_VA_RESET_ALL_DMICS_DISABLE); 620 snd_soc_component_update_bits(component, dmic_clk_reg, 621 CDC_VA_DMIC_CLK_SEL_MASK, 622 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 623 snd_soc_component_update_bits(component, dmic_clk_reg, 624 CDC_VA_DMIC_EN_MASK, 625 CDC_VA_DMIC_ENABLE); 626 } else { 627 if (*dmic_clk_div > clk_div) { 628 snd_soc_component_update_bits(component, 629 CDC_VA_TOP_CSR_DMIC_CFG, 630 freq_change_mask, 631 freq_change_mask); 632 snd_soc_component_update_bits(component, dmic_clk_reg, 633 CDC_VA_DMIC_CLK_SEL_MASK, 634 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 635 snd_soc_component_update_bits(component, 636 CDC_VA_TOP_CSR_DMIC_CFG, 637 freq_change_mask, 638 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 639 } else { 640 clk_div = *dmic_clk_div; 641 } 642 } 643 *dmic_clk_div = clk_div; 644 } else { 645 (*dmic_clk_cnt)--; 646 if (*dmic_clk_cnt == 0) { 647 snd_soc_component_update_bits(component, dmic_clk_reg, 648 CDC_VA_DMIC_EN_MASK, 0); 649 clk_div = 0; 650 snd_soc_component_update_bits(component, dmic_clk_reg, 651 CDC_VA_DMIC_CLK_SEL_MASK, 652 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 653 } else { 654 clk_div = va->dmic_clk_div; 655 if (*dmic_clk_div > clk_div) { 656 clk_div = va->dmic_clk_div; 657 snd_soc_component_update_bits(component, 658 CDC_VA_TOP_CSR_DMIC_CFG, 659 freq_change_mask, 660 freq_change_mask); 661 snd_soc_component_update_bits(component, dmic_clk_reg, 662 CDC_VA_DMIC_CLK_SEL_MASK, 663 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 664 snd_soc_component_update_bits(component, 665 CDC_VA_TOP_CSR_DMIC_CFG, 666 freq_change_mask, 667 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 668 } else { 669 clk_div = *dmic_clk_div; 670 } 671 } 672 *dmic_clk_div = clk_div; 673 } 674 675 return 0; 676 } 677 678 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w, 679 struct snd_kcontrol *kcontrol, int event) 680 { 681 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 682 unsigned int dmic = w->shift; 683 684 switch (event) { 685 case SND_SOC_DAPM_PRE_PMU: 686 va_dmic_clk_enable(comp, dmic, true); 687 break; 688 case SND_SOC_DAPM_POST_PMD: 689 va_dmic_clk_enable(comp, dmic, false); 690 break; 691 } 692 693 return 0; 694 } 695 696 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 697 struct snd_kcontrol *kcontrol, int event) 698 { 699 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 700 unsigned int decimator; 701 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; 702 u16 tx_gain_ctl_reg; 703 u8 hpf_cut_off_freq; 704 705 struct va_macro *va = snd_soc_component_get_drvdata(comp); 706 707 decimator = w->shift; 708 709 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 710 VA_MACRO_TX_PATH_OFFSET * decimator; 711 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 + 712 VA_MACRO_TX_PATH_OFFSET * decimator; 713 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 + 714 VA_MACRO_TX_PATH_OFFSET * decimator; 715 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL + 716 VA_MACRO_TX_PATH_OFFSET * decimator; 717 718 switch (event) { 719 case SND_SOC_DAPM_PRE_PMU: 720 snd_soc_component_update_bits(comp, 721 dec_cfg_reg, CDC_VA_ADC_MODE_MASK, 722 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); 723 /* Enable TX PGA Mute */ 724 break; 725 case SND_SOC_DAPM_POST_PMU: 726 /* Enable TX CLK */ 727 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 728 CDC_VA_TX_PATH_CLK_EN_MASK, 729 CDC_VA_TX_PATH_CLK_EN); 730 snd_soc_component_update_bits(comp, hpf_gate_reg, 731 CDC_VA_TX_HPF_ZERO_GATE_MASK, 732 CDC_VA_TX_HPF_ZERO_GATE); 733 734 usleep_range(1000, 1010); 735 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 736 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 737 738 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 739 snd_soc_component_update_bits(comp, dec_cfg_reg, 740 TX_HPF_CUT_OFF_FREQ_MASK, 741 CF_MIN_3DB_150HZ << 5); 742 743 snd_soc_component_update_bits(comp, hpf_gate_reg, 744 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 745 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ); 746 747 /* 748 * Minimum 1 clk cycle delay is required as per HW spec 749 */ 750 usleep_range(1000, 1010); 751 752 snd_soc_component_update_bits(comp, 753 hpf_gate_reg, 754 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 755 0x0); 756 } 757 758 759 usleep_range(1000, 1010); 760 snd_soc_component_update_bits(comp, hpf_gate_reg, 761 CDC_VA_TX_HPF_ZERO_GATE_MASK, 762 CDC_VA_TX_HPF_ZERO_NO_GATE); 763 /* 764 * 6ms delay is required as per HW spec 765 */ 766 usleep_range(6000, 6010); 767 /* apply gain after decimator is enabled */ 768 snd_soc_component_write(comp, tx_gain_ctl_reg, 769 snd_soc_component_read(comp, tx_gain_ctl_reg)); 770 break; 771 case SND_SOC_DAPM_POST_PMD: 772 /* Disable TX CLK */ 773 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 774 CDC_VA_TX_PATH_CLK_EN_MASK, 775 CDC_VA_TX_PATH_CLK_DISABLE); 776 break; 777 } 778 return 0; 779 } 780 781 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 782 struct snd_ctl_elem_value *ucontrol) 783 { 784 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 785 struct va_macro *va = snd_soc_component_get_drvdata(comp); 786 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 787 int path = e->shift_l; 788 789 ucontrol->value.enumerated.item[0] = va->dec_mode[path]; 790 791 return 0; 792 } 793 794 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 795 struct snd_ctl_elem_value *ucontrol) 796 { 797 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 798 int value = ucontrol->value.enumerated.item[0]; 799 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 800 int path = e->shift_l; 801 struct va_macro *va = snd_soc_component_get_drvdata(comp); 802 803 va->dec_mode[path] = value; 804 805 return 0; 806 } 807 808 static int va_macro_hw_params(struct snd_pcm_substream *substream, 809 struct snd_pcm_hw_params *params, 810 struct snd_soc_dai *dai) 811 { 812 int tx_fs_rate; 813 struct snd_soc_component *component = dai->component; 814 u32 decimator, sample_rate; 815 u16 tx_fs_reg; 816 struct device *va_dev = component->dev; 817 struct va_macro *va = snd_soc_component_get_drvdata(component); 818 819 sample_rate = params_rate(params); 820 switch (sample_rate) { 821 case 8000: 822 tx_fs_rate = 0; 823 break; 824 case 16000: 825 tx_fs_rate = 1; 826 break; 827 case 32000: 828 tx_fs_rate = 3; 829 break; 830 case 48000: 831 tx_fs_rate = 4; 832 break; 833 case 96000: 834 tx_fs_rate = 5; 835 break; 836 case 192000: 837 tx_fs_rate = 6; 838 break; 839 case 384000: 840 tx_fs_rate = 7; 841 break; 842 default: 843 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n", 844 __func__, params_rate(params)); 845 return -EINVAL; 846 } 847 848 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 849 VA_MACRO_DEC_MAX) { 850 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL + 851 VA_MACRO_TX_PATH_OFFSET * decimator; 852 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F, 853 tx_fs_rate); 854 } 855 return 0; 856 } 857 858 static int va_macro_get_channel_map(struct snd_soc_dai *dai, 859 unsigned int *tx_num, unsigned int *tx_slot, 860 unsigned int *rx_num, unsigned int *rx_slot) 861 { 862 struct snd_soc_component *component = dai->component; 863 struct device *va_dev = component->dev; 864 struct va_macro *va = snd_soc_component_get_drvdata(component); 865 866 switch (dai->id) { 867 case VA_MACRO_AIF1_CAP: 868 case VA_MACRO_AIF2_CAP: 869 case VA_MACRO_AIF3_CAP: 870 *tx_slot = va->active_ch_mask[dai->id]; 871 *tx_num = va->active_ch_cnt[dai->id]; 872 break; 873 default: 874 dev_err(va_dev, "%s: Invalid AIF\n", __func__); 875 break; 876 } 877 return 0; 878 } 879 880 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 881 { 882 struct snd_soc_component *component = dai->component; 883 struct va_macro *va = snd_soc_component_get_drvdata(component); 884 u16 tx_vol_ctl_reg, decimator; 885 886 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 887 VA_MACRO_DEC_MAX) { 888 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 889 VA_MACRO_TX_PATH_OFFSET * decimator; 890 if (mute) 891 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 892 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 893 CDC_VA_TX_PATH_PGA_MUTE_EN); 894 else 895 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 896 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 897 CDC_VA_TX_PATH_PGA_MUTE_DISABLE); 898 } 899 900 return 0; 901 } 902 903 static const struct snd_soc_dai_ops va_macro_dai_ops = { 904 .hw_params = va_macro_hw_params, 905 .get_channel_map = va_macro_get_channel_map, 906 .mute_stream = va_macro_digital_mute, 907 }; 908 909 static struct snd_soc_dai_driver va_macro_dais[] = { 910 { 911 .name = "va_macro_tx1", 912 .id = VA_MACRO_AIF1_CAP, 913 .capture = { 914 .stream_name = "VA_AIF1 Capture", 915 .rates = VA_MACRO_RATES, 916 .formats = VA_MACRO_FORMATS, 917 .rate_max = 192000, 918 .rate_min = 8000, 919 .channels_min = 1, 920 .channels_max = 8, 921 }, 922 .ops = &va_macro_dai_ops, 923 }, 924 { 925 .name = "va_macro_tx2", 926 .id = VA_MACRO_AIF2_CAP, 927 .capture = { 928 .stream_name = "VA_AIF2 Capture", 929 .rates = VA_MACRO_RATES, 930 .formats = VA_MACRO_FORMATS, 931 .rate_max = 192000, 932 .rate_min = 8000, 933 .channels_min = 1, 934 .channels_max = 8, 935 }, 936 .ops = &va_macro_dai_ops, 937 }, 938 { 939 .name = "va_macro_tx3", 940 .id = VA_MACRO_AIF3_CAP, 941 .capture = { 942 .stream_name = "VA_AIF3 Capture", 943 .rates = VA_MACRO_RATES, 944 .formats = VA_MACRO_FORMATS, 945 .rate_max = 192000, 946 .rate_min = 8000, 947 .channels_min = 1, 948 .channels_max = 8, 949 }, 950 .ops = &va_macro_dai_ops, 951 }, 952 }; 953 954 static const char * const adc_mux_text[] = { 955 "VA_DMIC", "SWR_MIC" 956 }; 957 958 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 959 0, adc_mux_text); 960 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, 961 0, adc_mux_text); 962 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1, 963 0, adc_mux_text); 964 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1, 965 0, adc_mux_text); 966 967 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0", 968 va_dec0_enum); 969 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1", 970 va_dec1_enum); 971 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2", 972 va_dec2_enum); 973 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3", 974 va_dec3_enum); 975 976 static const char * const dmic_mux_text[] = { 977 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 978 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 979 }; 980 981 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, 982 4, dmic_mux_text); 983 984 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, 985 4, dmic_mux_text); 986 987 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, 988 4, dmic_mux_text); 989 990 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, 991 4, dmic_mux_text); 992 993 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0", 994 va_dmic0_enum, snd_soc_dapm_get_enum_double, 995 va_macro_put_dec_enum); 996 997 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1", 998 va_dmic1_enum, snd_soc_dapm_get_enum_double, 999 va_macro_put_dec_enum); 1000 1001 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2", 1002 va_dmic2_enum, snd_soc_dapm_get_enum_double, 1003 va_macro_put_dec_enum); 1004 1005 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3", 1006 va_dmic3_enum, snd_soc_dapm_get_enum_double, 1007 va_macro_put_dec_enum); 1008 1009 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { 1010 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1011 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1012 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1013 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1014 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1015 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1016 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1017 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1018 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1019 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1020 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1021 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1022 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1023 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1024 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1025 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1026 }; 1027 1028 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { 1029 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1030 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1031 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1032 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1033 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1034 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1035 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1036 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1037 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1038 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1039 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1040 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1041 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1042 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1043 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1044 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1045 }; 1046 1047 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { 1048 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1049 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1050 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1051 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1052 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1053 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1054 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1055 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1056 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1058 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1059 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1060 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1061 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1062 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1063 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1064 }; 1065 1066 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = { 1067 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0, 1068 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0), 1069 1070 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0, 1071 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0), 1072 1073 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0, 1074 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0), 1075 1076 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, 1077 VA_MACRO_AIF1_CAP, 0, 1078 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)), 1079 1080 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, 1081 VA_MACRO_AIF2_CAP, 0, 1082 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)), 1083 1084 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, 1085 VA_MACRO_AIF3_CAP, 0, 1086 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)), 1087 1088 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux), 1089 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux), 1090 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), 1091 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), 1092 1093 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), 1094 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 1095 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 1096 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 1097 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 1098 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 1099 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 1100 SND_SOC_DAPM_INPUT("DMIC6 Pin"), 1101 SND_SOC_DAPM_INPUT("DMIC7 Pin"), 1102 1103 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0, 1104 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1105 SND_SOC_DAPM_POST_PMD), 1106 1107 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0, 1108 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1109 SND_SOC_DAPM_POST_PMD), 1110 1111 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0, 1112 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1113 SND_SOC_DAPM_POST_PMD), 1114 1115 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0, 1116 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1117 SND_SOC_DAPM_POST_PMD), 1118 1119 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0, 1120 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1121 SND_SOC_DAPM_POST_PMD), 1122 1123 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0, 1124 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1125 SND_SOC_DAPM_POST_PMD), 1126 1127 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0, 1128 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1129 SND_SOC_DAPM_POST_PMD), 1130 1131 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0, 1132 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1133 SND_SOC_DAPM_POST_PMD), 1134 1135 SND_SOC_DAPM_INPUT("VA SWR_ADC0"), 1136 SND_SOC_DAPM_INPUT("VA SWR_ADC1"), 1137 SND_SOC_DAPM_INPUT("VA SWR_ADC2"), 1138 SND_SOC_DAPM_INPUT("VA SWR_ADC3"), 1139 SND_SOC_DAPM_INPUT("VA SWR_MIC0"), 1140 SND_SOC_DAPM_INPUT("VA SWR_MIC1"), 1141 SND_SOC_DAPM_INPUT("VA SWR_MIC2"), 1142 SND_SOC_DAPM_INPUT("VA SWR_MIC3"), 1143 SND_SOC_DAPM_INPUT("VA SWR_MIC4"), 1144 SND_SOC_DAPM_INPUT("VA SWR_MIC5"), 1145 SND_SOC_DAPM_INPUT("VA SWR_MIC6"), 1146 SND_SOC_DAPM_INPUT("VA SWR_MIC7"), 1147 1148 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0, 1149 &va_dec0_mux, va_macro_enable_dec, 1150 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1151 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1152 1153 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0, 1154 &va_dec1_mux, va_macro_enable_dec, 1155 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1156 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1157 1158 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0, 1159 &va_dec2_mux, va_macro_enable_dec, 1160 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1161 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1162 1163 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0, 1164 &va_dec3_mux, va_macro_enable_dec, 1165 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1166 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1167 1168 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, 1169 va_macro_mclk_event, 1170 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1171 }; 1172 1173 static const struct snd_soc_dapm_route va_audio_map[] = { 1174 {"VA_AIF1 CAP", NULL, "VA_MCLK"}, 1175 {"VA_AIF2 CAP", NULL, "VA_MCLK"}, 1176 {"VA_AIF3 CAP", NULL, "VA_MCLK"}, 1177 1178 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"}, 1179 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"}, 1180 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"}, 1181 1182 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1183 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1184 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1185 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1186 1187 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1188 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1189 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1190 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1191 1192 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1193 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1194 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1195 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1196 1197 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"}, 1198 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, 1199 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"}, 1200 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"}, 1201 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"}, 1202 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"}, 1203 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"}, 1204 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"}, 1205 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"}, 1206 1207 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"}, 1208 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"}, 1209 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"}, 1210 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"}, 1211 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"}, 1212 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"}, 1213 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"}, 1214 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"}, 1215 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"}, 1216 1217 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"}, 1218 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, 1219 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, 1220 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"}, 1221 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"}, 1222 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"}, 1223 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"}, 1224 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"}, 1225 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"}, 1226 1227 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"}, 1228 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"}, 1229 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"}, 1230 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"}, 1231 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"}, 1232 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"}, 1233 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"}, 1234 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, 1235 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, 1236 1237 { "VA DMIC0", NULL, "DMIC0 Pin" }, 1238 { "VA DMIC1", NULL, "DMIC1 Pin" }, 1239 { "VA DMIC2", NULL, "DMIC2 Pin" }, 1240 { "VA DMIC3", NULL, "DMIC3 Pin" }, 1241 { "VA DMIC4", NULL, "DMIC4 Pin" }, 1242 { "VA DMIC5", NULL, "DMIC5 Pin" }, 1243 { "VA DMIC6", NULL, "DMIC6 Pin" }, 1244 { "VA DMIC7", NULL, "DMIC7 Pin" }, 1245 }; 1246 1247 static const char * const dec_mode_mux_text[] = { 1248 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1249 }; 1250 1251 static const struct soc_enum dec_mode_mux_enum[] = { 1252 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1253 dec_mode_mux_text), 1254 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1255 dec_mode_mux_text), 1256 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1257 dec_mode_mux_text), 1258 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1259 dec_mode_mux_text), 1260 }; 1261 1262 static const struct snd_kcontrol_new va_macro_snd_controls[] = { 1263 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL, 1264 -84, 40, digital_gain), 1265 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL, 1266 -84, 40, digital_gain), 1267 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL, 1268 -84, 40, digital_gain), 1269 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL, 1270 -84, 40, digital_gain), 1271 1272 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0], 1273 va_macro_dec_mode_get, va_macro_dec_mode_put), 1274 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1], 1275 va_macro_dec_mode_get, va_macro_dec_mode_put), 1276 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2], 1277 va_macro_dec_mode_get, va_macro_dec_mode_put), 1278 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3], 1279 va_macro_dec_mode_get, va_macro_dec_mode_put), 1280 }; 1281 1282 static int va_macro_component_probe(struct snd_soc_component *component) 1283 { 1284 struct va_macro *va = snd_soc_component_get_drvdata(component); 1285 1286 snd_soc_component_init_regmap(component, va->regmap); 1287 1288 return 0; 1289 } 1290 1291 static const struct snd_soc_component_driver va_macro_component_drv = { 1292 .name = "VA MACRO", 1293 .probe = va_macro_component_probe, 1294 .controls = va_macro_snd_controls, 1295 .num_controls = ARRAY_SIZE(va_macro_snd_controls), 1296 .dapm_widgets = va_macro_dapm_widgets, 1297 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets), 1298 .dapm_routes = va_audio_map, 1299 .num_dapm_routes = ARRAY_SIZE(va_audio_map), 1300 }; 1301 1302 static int fsgen_gate_enable(struct clk_hw *hw) 1303 { 1304 return va_macro_mclk_enable(to_va_macro(hw), true); 1305 } 1306 1307 static void fsgen_gate_disable(struct clk_hw *hw) 1308 { 1309 va_macro_mclk_enable(to_va_macro(hw), false); 1310 } 1311 1312 static int fsgen_gate_is_enabled(struct clk_hw *hw) 1313 { 1314 struct va_macro *va = to_va_macro(hw); 1315 int val; 1316 1317 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val); 1318 1319 return !!(val & CDC_VA_FS_BROADCAST_EN); 1320 } 1321 1322 static const struct clk_ops fsgen_gate_ops = { 1323 .prepare = fsgen_gate_enable, 1324 .unprepare = fsgen_gate_disable, 1325 .is_enabled = fsgen_gate_is_enabled, 1326 }; 1327 1328 static int va_macro_register_fsgen_output(struct va_macro *va) 1329 { 1330 struct clk *parent = va->mclk; 1331 struct device *dev = va->dev; 1332 struct device_node *np = dev->of_node; 1333 const char *parent_clk_name; 1334 const char *clk_name = "fsgen"; 1335 struct clk_init_data init; 1336 int ret; 1337 1338 parent_clk_name = __clk_get_name(parent); 1339 1340 of_property_read_string(np, "clock-output-names", &clk_name); 1341 1342 init.name = clk_name; 1343 init.ops = &fsgen_gate_ops; 1344 init.flags = 0; 1345 init.parent_names = &parent_clk_name; 1346 init.num_parents = 1; 1347 va->hw.init = &init; 1348 ret = devm_clk_hw_register(va->dev, &va->hw); 1349 if (ret) 1350 return ret; 1351 1352 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw); 1353 } 1354 1355 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, 1356 struct va_macro *va) 1357 { 1358 u32 div_factor; 1359 u32 mclk_rate = VA_MACRO_MCLK_FREQ; 1360 1361 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0) 1362 goto undefined_rate; 1363 1364 div_factor = mclk_rate / dmic_sample_rate; 1365 1366 switch (div_factor) { 1367 case 2: 1368 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1369 break; 1370 case 3: 1371 va->dmic_clk_div = VA_MACRO_CLK_DIV_3; 1372 break; 1373 case 4: 1374 va->dmic_clk_div = VA_MACRO_CLK_DIV_4; 1375 break; 1376 case 6: 1377 va->dmic_clk_div = VA_MACRO_CLK_DIV_6; 1378 break; 1379 case 8: 1380 va->dmic_clk_div = VA_MACRO_CLK_DIV_8; 1381 break; 1382 case 16: 1383 va->dmic_clk_div = VA_MACRO_CLK_DIV_16; 1384 break; 1385 default: 1386 /* Any other DIV factor is invalid */ 1387 goto undefined_rate; 1388 } 1389 1390 return dmic_sample_rate; 1391 1392 undefined_rate: 1393 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n", 1394 __func__, dmic_sample_rate, mclk_rate); 1395 dmic_sample_rate = 0; 1396 1397 return dmic_sample_rate; 1398 } 1399 1400 static int va_macro_probe(struct platform_device *pdev) 1401 { 1402 struct device *dev = &pdev->dev; 1403 struct va_macro *va; 1404 void __iomem *base; 1405 u32 sample_rate = 0; 1406 int ret; 1407 1408 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); 1409 if (!va) 1410 return -ENOMEM; 1411 1412 va->dev = dev; 1413 1414 va->macro = devm_clk_get_optional(dev, "macro"); 1415 if (IS_ERR(va->macro)) 1416 return PTR_ERR(va->macro); 1417 1418 va->dcodec = devm_clk_get_optional(dev, "dcodec"); 1419 if (IS_ERR(va->dcodec)) 1420 return PTR_ERR(va->dcodec); 1421 1422 va->mclk = devm_clk_get(dev, "mclk"); 1423 if (IS_ERR(va->mclk)) 1424 return PTR_ERR(va->mclk); 1425 1426 va->pds = lpass_macro_pds_init(dev); 1427 if (IS_ERR(va->pds)) 1428 return PTR_ERR(va->pds); 1429 1430 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate", 1431 &sample_rate); 1432 if (ret) { 1433 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n"); 1434 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1435 } else { 1436 ret = va_macro_validate_dmic_sample_rate(sample_rate, va); 1437 if (!ret) { 1438 ret = -EINVAL; 1439 goto err; 1440 } 1441 } 1442 1443 base = devm_platform_ioremap_resource(pdev, 0); 1444 if (IS_ERR(base)) { 1445 ret = PTR_ERR(base); 1446 goto err; 1447 } 1448 1449 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); 1450 if (IS_ERR(va->regmap)) { 1451 ret = -EINVAL; 1452 goto err; 1453 } 1454 1455 dev_set_drvdata(dev, va); 1456 1457 /* mclk rate */ 1458 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ); 1459 1460 ret = clk_prepare_enable(va->macro); 1461 if (ret) 1462 goto err; 1463 1464 ret = clk_prepare_enable(va->dcodec); 1465 if (ret) 1466 goto err_dcodec; 1467 1468 ret = clk_prepare_enable(va->mclk); 1469 if (ret) 1470 goto err_mclk; 1471 1472 ret = va_macro_register_fsgen_output(va); 1473 if (ret) 1474 goto err_clkout; 1475 1476 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv, 1477 va_macro_dais, 1478 ARRAY_SIZE(va_macro_dais)); 1479 if (ret) 1480 goto err_clkout; 1481 1482 pm_runtime_set_autosuspend_delay(dev, 3000); 1483 pm_runtime_use_autosuspend(dev); 1484 pm_runtime_mark_last_busy(dev); 1485 pm_runtime_set_active(dev); 1486 pm_runtime_enable(dev); 1487 1488 return 0; 1489 1490 err_clkout: 1491 clk_disable_unprepare(va->mclk); 1492 err_mclk: 1493 clk_disable_unprepare(va->dcodec); 1494 err_dcodec: 1495 clk_disable_unprepare(va->macro); 1496 err: 1497 lpass_macro_pds_exit(va->pds); 1498 1499 return ret; 1500 } 1501 1502 static int va_macro_remove(struct platform_device *pdev) 1503 { 1504 struct va_macro *va = dev_get_drvdata(&pdev->dev); 1505 1506 clk_disable_unprepare(va->mclk); 1507 clk_disable_unprepare(va->dcodec); 1508 clk_disable_unprepare(va->macro); 1509 1510 lpass_macro_pds_exit(va->pds); 1511 1512 return 0; 1513 } 1514 1515 static int __maybe_unused va_macro_runtime_suspend(struct device *dev) 1516 { 1517 struct va_macro *va = dev_get_drvdata(dev); 1518 1519 regcache_cache_only(va->regmap, true); 1520 regcache_mark_dirty(va->regmap); 1521 1522 clk_disable_unprepare(va->mclk); 1523 1524 return 0; 1525 } 1526 1527 static int __maybe_unused va_macro_runtime_resume(struct device *dev) 1528 { 1529 struct va_macro *va = dev_get_drvdata(dev); 1530 int ret; 1531 1532 ret = clk_prepare_enable(va->mclk); 1533 if (ret) { 1534 dev_err(va->dev, "unable to prepare mclk\n"); 1535 return ret; 1536 } 1537 1538 regcache_cache_only(va->regmap, false); 1539 regcache_sync(va->regmap); 1540 1541 return 0; 1542 } 1543 1544 1545 static const struct dev_pm_ops va_macro_pm_ops = { 1546 SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL) 1547 }; 1548 1549 static const struct of_device_id va_macro_dt_match[] = { 1550 { .compatible = "qcom,sc7280-lpass-va-macro" }, 1551 { .compatible = "qcom,sm8250-lpass-va-macro" }, 1552 {} 1553 }; 1554 MODULE_DEVICE_TABLE(of, va_macro_dt_match); 1555 1556 static struct platform_driver va_macro_driver = { 1557 .driver = { 1558 .name = "va_macro", 1559 .of_match_table = va_macro_dt_match, 1560 .suppress_bind_attrs = true, 1561 .pm = &va_macro_pm_ops, 1562 }, 1563 .probe = va_macro_probe, 1564 .remove = va_macro_remove, 1565 }; 1566 1567 module_platform_driver(va_macro_driver); 1568 MODULE_DESCRIPTION("VA macro driver"); 1569 MODULE_LICENSE("GPL"); 1570