1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/clk.h> 7 #include <linux/io.h> 8 #include <linux/platform_device.h> 9 #include <linux/regmap.h> 10 #include <sound/soc.h> 11 #include <sound/soc-dapm.h> 12 #include <sound/tlv.h> 13 #include <linux/of_clk.h> 14 #include <linux/clk-provider.h> 15 16 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 17 #define CDC_TX_MCLK_EN_MASK BIT(0) 18 #define CDC_TX_MCLK_ENABLE BIT(0) 19 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 20 #define CDC_TX_FS_CNT_EN_MASK BIT(0) 21 #define CDC_TX_FS_CNT_ENABLE BIT(0) 22 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008) 23 #define CDC_TX_SWR_RESET_MASK BIT(1) 24 #define CDC_TX_SWR_RESET_ENABLE BIT(1) 25 #define CDC_TX_SWR_CLK_EN_MASK BIT(0) 26 #define CDC_TX_SWR_CLK_ENABLE BIT(0) 27 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080) 28 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084) 29 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088) 30 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090) 31 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094) 32 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098) 33 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4) 34 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8) 35 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) 36 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) 37 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) 38 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) 39 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) 40 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) 41 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC) 42 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0) 43 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4) 44 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n) 45 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0) 46 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100) 47 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n) 48 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104) 49 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108) 50 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C) 51 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110) 52 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114) 53 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118) 54 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C) 55 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120) 56 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124) 57 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128) 58 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C) 59 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130) 60 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) 61 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) 62 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) 63 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) 64 #define CDC_TX_ANC0_MODE_1_CTL (0x0204) 65 #define CDC_TX_ANC0_MODE_2_CTL (0x0208) 66 #define CDC_TX_ANC0_FF_SHIFT (0x020C) 67 #define CDC_TX_ANC0_FB_SHIFT (0x0210) 68 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214) 69 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218) 70 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C) 71 #define CDC_TX_ANC0_SMLPF_CTL (0x0220) 72 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224) 73 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228) 74 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C) 75 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230) 76 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234) 77 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238) 78 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C) 79 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n) 80 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0) 81 #define CDC_TXn_PGA_MUTE_MASK BIT(4) 82 #define CDC_TXn_CLK_EN_MASK BIT(5) 83 #define CDC_TX0_TX_PATH_CTL (0x0400) 84 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n) 85 #define CDC_TX0_TX_PATH_CFG0 (0x0404) 86 #define CDC_TXn_PH_EN_MASK BIT(0) 87 #define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1) 88 #define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5) 89 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7) 90 #define CDC_TX0_TX_PATH_CFG1 (0x0408) 91 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n) 92 #define CDC_TX0_TX_VOL_CTL (0x040C) 93 #define CDC_TX0_TX_PATH_SEC0 (0x0410) 94 #define CDC_TX0_TX_PATH_SEC1 (0x0414) 95 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n) 96 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1) 97 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0) 98 #define CDC_TX0_TX_PATH_SEC2 (0x0418) 99 #define CDC_TX0_TX_PATH_SEC3 (0x041C) 100 #define CDC_TX0_TX_PATH_SEC4 (0x0420) 101 #define CDC_TX0_TX_PATH_SEC5 (0x0424) 102 #define CDC_TX0_TX_PATH_SEC6 (0x0428) 103 #define CDC_TX0_TX_PATH_SEC7 (0x042C) 104 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) 105 #define CDC_TX1_TX_PATH_CTL (0x0480) 106 #define CDC_TX1_TX_PATH_CFG0 (0x0484) 107 #define CDC_TX1_TX_PATH_CFG1 (0x0488) 108 #define CDC_TX1_TX_VOL_CTL (0x048C) 109 #define CDC_TX1_TX_PATH_SEC0 (0x0490) 110 #define CDC_TX1_TX_PATH_SEC1 (0x0494) 111 #define CDC_TX1_TX_PATH_SEC2 (0x0498) 112 #define CDC_TX1_TX_PATH_SEC3 (0x049C) 113 #define CDC_TX1_TX_PATH_SEC4 (0x04A0) 114 #define CDC_TX1_TX_PATH_SEC5 (0x04A4) 115 #define CDC_TX1_TX_PATH_SEC6 (0x04A8) 116 #define CDC_TX2_TX_PATH_CTL (0x0500) 117 #define CDC_TX2_TX_PATH_CFG0 (0x0504) 118 #define CDC_TX2_TX_PATH_CFG1 (0x0508) 119 #define CDC_TX2_TX_VOL_CTL (0x050C) 120 #define CDC_TX2_TX_PATH_SEC0 (0x0510) 121 #define CDC_TX2_TX_PATH_SEC1 (0x0514) 122 #define CDC_TX2_TX_PATH_SEC2 (0x0518) 123 #define CDC_TX2_TX_PATH_SEC3 (0x051C) 124 #define CDC_TX2_TX_PATH_SEC4 (0x0520) 125 #define CDC_TX2_TX_PATH_SEC5 (0x0524) 126 #define CDC_TX2_TX_PATH_SEC6 (0x0528) 127 #define CDC_TX3_TX_PATH_CTL (0x0580) 128 #define CDC_TX3_TX_PATH_CFG0 (0x0584) 129 #define CDC_TX3_TX_PATH_CFG1 (0x0588) 130 #define CDC_TX3_TX_VOL_CTL (0x058C) 131 #define CDC_TX3_TX_PATH_SEC0 (0x0590) 132 #define CDC_TX3_TX_PATH_SEC1 (0x0594) 133 #define CDC_TX3_TX_PATH_SEC2 (0x0598) 134 #define CDC_TX3_TX_PATH_SEC3 (0x059C) 135 #define CDC_TX3_TX_PATH_SEC4 (0x05A0) 136 #define CDC_TX3_TX_PATH_SEC5 (0x05A4) 137 #define CDC_TX3_TX_PATH_SEC6 (0x05A8) 138 #define CDC_TX4_TX_PATH_CTL (0x0600) 139 #define CDC_TX4_TX_PATH_CFG0 (0x0604) 140 #define CDC_TX4_TX_PATH_CFG1 (0x0608) 141 #define CDC_TX4_TX_VOL_CTL (0x060C) 142 #define CDC_TX4_TX_PATH_SEC0 (0x0610) 143 #define CDC_TX4_TX_PATH_SEC1 (0x0614) 144 #define CDC_TX4_TX_PATH_SEC2 (0x0618) 145 #define CDC_TX4_TX_PATH_SEC3 (0x061C) 146 #define CDC_TX4_TX_PATH_SEC4 (0x0620) 147 #define CDC_TX4_TX_PATH_SEC5 (0x0624) 148 #define CDC_TX4_TX_PATH_SEC6 (0x0628) 149 #define CDC_TX5_TX_PATH_CTL (0x0680) 150 #define CDC_TX5_TX_PATH_CFG0 (0x0684) 151 #define CDC_TX5_TX_PATH_CFG1 (0x0688) 152 #define CDC_TX5_TX_VOL_CTL (0x068C) 153 #define CDC_TX5_TX_PATH_SEC0 (0x0690) 154 #define CDC_TX5_TX_PATH_SEC1 (0x0694) 155 #define CDC_TX5_TX_PATH_SEC2 (0x0698) 156 #define CDC_TX5_TX_PATH_SEC3 (0x069C) 157 #define CDC_TX5_TX_PATH_SEC4 (0x06A0) 158 #define CDC_TX5_TX_PATH_SEC5 (0x06A4) 159 #define CDC_TX5_TX_PATH_SEC6 (0x06A8) 160 #define CDC_TX6_TX_PATH_CTL (0x0700) 161 #define CDC_TX6_TX_PATH_CFG0 (0x0704) 162 #define CDC_TX6_TX_PATH_CFG1 (0x0708) 163 #define CDC_TX6_TX_VOL_CTL (0x070C) 164 #define CDC_TX6_TX_PATH_SEC0 (0x0710) 165 #define CDC_TX6_TX_PATH_SEC1 (0x0714) 166 #define CDC_TX6_TX_PATH_SEC2 (0x0718) 167 #define CDC_TX6_TX_PATH_SEC3 (0x071C) 168 #define CDC_TX6_TX_PATH_SEC4 (0x0720) 169 #define CDC_TX6_TX_PATH_SEC5 (0x0724) 170 #define CDC_TX6_TX_PATH_SEC6 (0x0728) 171 #define CDC_TX7_TX_PATH_CTL (0x0780) 172 #define CDC_TX7_TX_PATH_CFG0 (0x0784) 173 #define CDC_TX7_TX_PATH_CFG1 (0x0788) 174 #define CDC_TX7_TX_VOL_CTL (0x078C) 175 #define CDC_TX7_TX_PATH_SEC0 (0x0790) 176 #define CDC_TX7_TX_PATH_SEC1 (0x0794) 177 #define CDC_TX7_TX_PATH_SEC2 (0x0798) 178 #define CDC_TX7_TX_PATH_SEC3 (0x079C) 179 #define CDC_TX7_TX_PATH_SEC4 (0x07A0) 180 #define CDC_TX7_TX_PATH_SEC5 (0x07A4) 181 #define CDC_TX7_TX_PATH_SEC6 (0x07A8) 182 #define TX_MAX_OFFSET (0x07A8) 183 184 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 185 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 186 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 187 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 188 SNDRV_PCM_FMTBIT_S24_LE |\ 189 SNDRV_PCM_FMTBIT_S24_3LE) 190 191 #define CF_MIN_3DB_4HZ 0x0 192 #define CF_MIN_3DB_75HZ 0x1 193 #define CF_MIN_3DB_150HZ 0x2 194 #define TX_ADC_MAX 5 195 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2) 196 #define NUM_DECIMATORS 8 197 #define TX_NUM_CLKS_MAX 5 198 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40 199 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100 200 #define TX_MACRO_DMIC_HPF_DELAY_MS 300 201 #define TX_MACRO_AMIC_HPF_DELAY_MS 300 202 #define MCLK_FREQ 9600000 203 204 enum { 205 TX_MACRO_AIF_INVALID = 0, 206 TX_MACRO_AIF1_CAP, 207 TX_MACRO_AIF2_CAP, 208 TX_MACRO_AIF3_CAP, 209 TX_MACRO_MAX_DAIS 210 }; 211 212 enum { 213 TX_MACRO_DEC0, 214 TX_MACRO_DEC1, 215 TX_MACRO_DEC2, 216 TX_MACRO_DEC3, 217 TX_MACRO_DEC4, 218 TX_MACRO_DEC5, 219 TX_MACRO_DEC6, 220 TX_MACRO_DEC7, 221 TX_MACRO_DEC_MAX, 222 }; 223 224 enum { 225 TX_MACRO_CLK_DIV_2, 226 TX_MACRO_CLK_DIV_3, 227 TX_MACRO_CLK_DIV_4, 228 TX_MACRO_CLK_DIV_6, 229 TX_MACRO_CLK_DIV_8, 230 TX_MACRO_CLK_DIV_16, 231 }; 232 233 enum { 234 MSM_DMIC, 235 SWR_MIC, 236 ANC_FB_TUNE1 237 }; 238 239 struct tx_mute_work { 240 struct tx_macro *tx; 241 u32 decimator; 242 struct delayed_work dwork; 243 }; 244 245 struct hpf_work { 246 struct tx_macro *tx; 247 u8 decimator; 248 u8 hpf_cut_off_freq; 249 struct delayed_work dwork; 250 }; 251 252 struct tx_macro { 253 struct device *dev; 254 struct snd_soc_component *component; 255 struct hpf_work tx_hpf_work[NUM_DECIMATORS]; 256 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; 257 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; 258 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; 259 unsigned long active_decimator[TX_MACRO_MAX_DAIS]; 260 struct regmap *regmap; 261 struct clk_bulk_data clks[TX_NUM_CLKS_MAX]; 262 struct clk_hw hw; 263 bool dec_active[NUM_DECIMATORS]; 264 bool reset_swr; 265 int tx_mclk_users; 266 u16 dmic_clk_div; 267 bool bcs_enable; 268 int dec_mode[NUM_DECIMATORS]; 269 bool bcs_clk_en; 270 }; 271 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw) 272 273 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 274 275 static struct reg_default tx_defaults[] = { 276 /* TX Macro */ 277 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 278 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 279 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 280 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, 281 { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, 282 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, 283 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, 284 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, 285 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, 286 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, 287 { CDC_TX_TOP_CSR_I2S_CLK, 0x00}, 288 { CDC_TX_TOP_CSR_I2S_RESET, 0x00}, 289 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, 290 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, 291 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, 292 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, 293 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, 294 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, 295 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, 296 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, 297 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, 298 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00}, 299 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00}, 300 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00}, 301 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00}, 302 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00}, 303 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00}, 304 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00}, 305 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00}, 306 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00}, 307 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00}, 308 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, 309 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, 310 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, 311 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, 312 { CDC_TX_ANC0_MODE_1_CTL, 0x00}, 313 { CDC_TX_ANC0_MODE_2_CTL, 0x00}, 314 { CDC_TX_ANC0_FF_SHIFT, 0x00}, 315 { CDC_TX_ANC0_FB_SHIFT, 0x00}, 316 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00}, 317 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00}, 318 { CDC_TX_ANC0_LPF_FB_CTL, 0x00}, 319 { CDC_TX_ANC0_SMLPF_CTL, 0x00}, 320 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00}, 321 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00}, 322 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00}, 323 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00}, 324 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00}, 325 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00}, 326 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00}, 327 { CDC_TX0_TX_PATH_CTL, 0x04}, 328 { CDC_TX0_TX_PATH_CFG0, 0x10}, 329 { CDC_TX0_TX_PATH_CFG1, 0x0B}, 330 { CDC_TX0_TX_VOL_CTL, 0x00}, 331 { CDC_TX0_TX_PATH_SEC0, 0x00}, 332 { CDC_TX0_TX_PATH_SEC1, 0x00}, 333 { CDC_TX0_TX_PATH_SEC2, 0x01}, 334 { CDC_TX0_TX_PATH_SEC3, 0x3C}, 335 { CDC_TX0_TX_PATH_SEC4, 0x20}, 336 { CDC_TX0_TX_PATH_SEC5, 0x00}, 337 { CDC_TX0_TX_PATH_SEC6, 0x00}, 338 { CDC_TX0_TX_PATH_SEC7, 0x25}, 339 { CDC_TX1_TX_PATH_CTL, 0x04}, 340 { CDC_TX1_TX_PATH_CFG0, 0x10}, 341 { CDC_TX1_TX_PATH_CFG1, 0x0B}, 342 { CDC_TX1_TX_VOL_CTL, 0x00}, 343 { CDC_TX1_TX_PATH_SEC0, 0x00}, 344 { CDC_TX1_TX_PATH_SEC1, 0x00}, 345 { CDC_TX1_TX_PATH_SEC2, 0x01}, 346 { CDC_TX1_TX_PATH_SEC3, 0x3C}, 347 { CDC_TX1_TX_PATH_SEC4, 0x20}, 348 { CDC_TX1_TX_PATH_SEC5, 0x00}, 349 { CDC_TX1_TX_PATH_SEC6, 0x00}, 350 { CDC_TX2_TX_PATH_CTL, 0x04}, 351 { CDC_TX2_TX_PATH_CFG0, 0x10}, 352 { CDC_TX2_TX_PATH_CFG1, 0x0B}, 353 { CDC_TX2_TX_VOL_CTL, 0x00}, 354 { CDC_TX2_TX_PATH_SEC0, 0x00}, 355 { CDC_TX2_TX_PATH_SEC1, 0x00}, 356 { CDC_TX2_TX_PATH_SEC2, 0x01}, 357 { CDC_TX2_TX_PATH_SEC3, 0x3C}, 358 { CDC_TX2_TX_PATH_SEC4, 0x20}, 359 { CDC_TX2_TX_PATH_SEC5, 0x00}, 360 { CDC_TX2_TX_PATH_SEC6, 0x00}, 361 { CDC_TX3_TX_PATH_CTL, 0x04}, 362 { CDC_TX3_TX_PATH_CFG0, 0x10}, 363 { CDC_TX3_TX_PATH_CFG1, 0x0B}, 364 { CDC_TX3_TX_VOL_CTL, 0x00}, 365 { CDC_TX3_TX_PATH_SEC0, 0x00}, 366 { CDC_TX3_TX_PATH_SEC1, 0x00}, 367 { CDC_TX3_TX_PATH_SEC2, 0x01}, 368 { CDC_TX3_TX_PATH_SEC3, 0x3C}, 369 { CDC_TX3_TX_PATH_SEC4, 0x20}, 370 { CDC_TX3_TX_PATH_SEC5, 0x00}, 371 { CDC_TX3_TX_PATH_SEC6, 0x00}, 372 { CDC_TX4_TX_PATH_CTL, 0x04}, 373 { CDC_TX4_TX_PATH_CFG0, 0x10}, 374 { CDC_TX4_TX_PATH_CFG1, 0x0B}, 375 { CDC_TX4_TX_VOL_CTL, 0x00}, 376 { CDC_TX4_TX_PATH_SEC0, 0x00}, 377 { CDC_TX4_TX_PATH_SEC1, 0x00}, 378 { CDC_TX4_TX_PATH_SEC2, 0x01}, 379 { CDC_TX4_TX_PATH_SEC3, 0x3C}, 380 { CDC_TX4_TX_PATH_SEC4, 0x20}, 381 { CDC_TX4_TX_PATH_SEC5, 0x00}, 382 { CDC_TX4_TX_PATH_SEC6, 0x00}, 383 { CDC_TX5_TX_PATH_CTL, 0x04}, 384 { CDC_TX5_TX_PATH_CFG0, 0x10}, 385 { CDC_TX5_TX_PATH_CFG1, 0x0B}, 386 { CDC_TX5_TX_VOL_CTL, 0x00}, 387 { CDC_TX5_TX_PATH_SEC0, 0x00}, 388 { CDC_TX5_TX_PATH_SEC1, 0x00}, 389 { CDC_TX5_TX_PATH_SEC2, 0x01}, 390 { CDC_TX5_TX_PATH_SEC3, 0x3C}, 391 { CDC_TX5_TX_PATH_SEC4, 0x20}, 392 { CDC_TX5_TX_PATH_SEC5, 0x00}, 393 { CDC_TX5_TX_PATH_SEC6, 0x00}, 394 { CDC_TX6_TX_PATH_CTL, 0x04}, 395 { CDC_TX6_TX_PATH_CFG0, 0x10}, 396 { CDC_TX6_TX_PATH_CFG1, 0x0B}, 397 { CDC_TX6_TX_VOL_CTL, 0x00}, 398 { CDC_TX6_TX_PATH_SEC0, 0x00}, 399 { CDC_TX6_TX_PATH_SEC1, 0x00}, 400 { CDC_TX6_TX_PATH_SEC2, 0x01}, 401 { CDC_TX6_TX_PATH_SEC3, 0x3C}, 402 { CDC_TX6_TX_PATH_SEC4, 0x20}, 403 { CDC_TX6_TX_PATH_SEC5, 0x00}, 404 { CDC_TX6_TX_PATH_SEC6, 0x00}, 405 { CDC_TX7_TX_PATH_CTL, 0x04}, 406 { CDC_TX7_TX_PATH_CFG0, 0x10}, 407 { CDC_TX7_TX_PATH_CFG1, 0x0B}, 408 { CDC_TX7_TX_VOL_CTL, 0x00}, 409 { CDC_TX7_TX_PATH_SEC0, 0x00}, 410 { CDC_TX7_TX_PATH_SEC1, 0x00}, 411 { CDC_TX7_TX_PATH_SEC2, 0x01}, 412 { CDC_TX7_TX_PATH_SEC3, 0x3C}, 413 { CDC_TX7_TX_PATH_SEC4, 0x20}, 414 { CDC_TX7_TX_PATH_SEC5, 0x00}, 415 { CDC_TX7_TX_PATH_SEC6, 0x00}, 416 }; 417 418 static bool tx_is_volatile_register(struct device *dev, unsigned int reg) 419 { 420 /* Update volatile list for tx/tx macros */ 421 switch (reg) { 422 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 423 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 424 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 425 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 426 return true; 427 } 428 return false; 429 } 430 431 static bool tx_is_rw_register(struct device *dev, unsigned int reg) 432 { 433 switch (reg) { 434 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL: 435 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL: 436 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL: 437 case CDC_TX_TOP_CSR_TOP_CFG0: 438 case CDC_TX_TOP_CSR_ANC_CFG: 439 case CDC_TX_TOP_CSR_SWR_CTRL: 440 case CDC_TX_TOP_CSR_FREQ_MCLK: 441 case CDC_TX_TOP_CSR_DEBUG_BUS: 442 case CDC_TX_TOP_CSR_DEBUG_EN: 443 case CDC_TX_TOP_CSR_TX_I2S_CTL: 444 case CDC_TX_TOP_CSR_I2S_CLK: 445 case CDC_TX_TOP_CSR_I2S_RESET: 446 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 447 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 448 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 449 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 450 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 451 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 452 case CDC_TX_ANC0_CLK_RESET_CTL: 453 case CDC_TX_ANC0_MODE_1_CTL: 454 case CDC_TX_ANC0_MODE_2_CTL: 455 case CDC_TX_ANC0_FF_SHIFT: 456 case CDC_TX_ANC0_FB_SHIFT: 457 case CDC_TX_ANC0_LPF_FF_A_CTL: 458 case CDC_TX_ANC0_LPF_FF_B_CTL: 459 case CDC_TX_ANC0_LPF_FB_CTL: 460 case CDC_TX_ANC0_SMLPF_CTL: 461 case CDC_TX_ANC0_DCFLT_SHIFT_CTL: 462 case CDC_TX_ANC0_IIR_ADAPT_CTL: 463 case CDC_TX_ANC0_IIR_COEFF_1_CTL: 464 case CDC_TX_ANC0_IIR_COEFF_2_CTL: 465 case CDC_TX_ANC0_FF_A_GAIN_CTL: 466 case CDC_TX_ANC0_FF_B_GAIN_CTL: 467 case CDC_TX_ANC0_FB_GAIN_CTL: 468 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 469 case CDC_TX_INP_MUX_ADC_MUX0_CFG1: 470 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 471 case CDC_TX_INP_MUX_ADC_MUX1_CFG1: 472 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 473 case CDC_TX_INP_MUX_ADC_MUX2_CFG1: 474 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 475 case CDC_TX_INP_MUX_ADC_MUX3_CFG1: 476 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 477 case CDC_TX_INP_MUX_ADC_MUX4_CFG1: 478 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 479 case CDC_TX_INP_MUX_ADC_MUX5_CFG1: 480 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 481 case CDC_TX_INP_MUX_ADC_MUX6_CFG1: 482 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 483 case CDC_TX_INP_MUX_ADC_MUX7_CFG1: 484 case CDC_TX0_TX_PATH_CTL: 485 case CDC_TX0_TX_PATH_CFG0: 486 case CDC_TX0_TX_PATH_CFG1: 487 case CDC_TX0_TX_VOL_CTL: 488 case CDC_TX0_TX_PATH_SEC0: 489 case CDC_TX0_TX_PATH_SEC1: 490 case CDC_TX0_TX_PATH_SEC2: 491 case CDC_TX0_TX_PATH_SEC3: 492 case CDC_TX0_TX_PATH_SEC4: 493 case CDC_TX0_TX_PATH_SEC5: 494 case CDC_TX0_TX_PATH_SEC6: 495 case CDC_TX0_TX_PATH_SEC7: 496 case CDC_TX1_TX_PATH_CTL: 497 case CDC_TX1_TX_PATH_CFG0: 498 case CDC_TX1_TX_PATH_CFG1: 499 case CDC_TX1_TX_VOL_CTL: 500 case CDC_TX1_TX_PATH_SEC0: 501 case CDC_TX1_TX_PATH_SEC1: 502 case CDC_TX1_TX_PATH_SEC2: 503 case CDC_TX1_TX_PATH_SEC3: 504 case CDC_TX1_TX_PATH_SEC4: 505 case CDC_TX1_TX_PATH_SEC5: 506 case CDC_TX1_TX_PATH_SEC6: 507 case CDC_TX2_TX_PATH_CTL: 508 case CDC_TX2_TX_PATH_CFG0: 509 case CDC_TX2_TX_PATH_CFG1: 510 case CDC_TX2_TX_VOL_CTL: 511 case CDC_TX2_TX_PATH_SEC0: 512 case CDC_TX2_TX_PATH_SEC1: 513 case CDC_TX2_TX_PATH_SEC2: 514 case CDC_TX2_TX_PATH_SEC3: 515 case CDC_TX2_TX_PATH_SEC4: 516 case CDC_TX2_TX_PATH_SEC5: 517 case CDC_TX2_TX_PATH_SEC6: 518 case CDC_TX3_TX_PATH_CTL: 519 case CDC_TX3_TX_PATH_CFG0: 520 case CDC_TX3_TX_PATH_CFG1: 521 case CDC_TX3_TX_VOL_CTL: 522 case CDC_TX3_TX_PATH_SEC0: 523 case CDC_TX3_TX_PATH_SEC1: 524 case CDC_TX3_TX_PATH_SEC2: 525 case CDC_TX3_TX_PATH_SEC3: 526 case CDC_TX3_TX_PATH_SEC4: 527 case CDC_TX3_TX_PATH_SEC5: 528 case CDC_TX3_TX_PATH_SEC6: 529 case CDC_TX4_TX_PATH_CTL: 530 case CDC_TX4_TX_PATH_CFG0: 531 case CDC_TX4_TX_PATH_CFG1: 532 case CDC_TX4_TX_VOL_CTL: 533 case CDC_TX4_TX_PATH_SEC0: 534 case CDC_TX4_TX_PATH_SEC1: 535 case CDC_TX4_TX_PATH_SEC2: 536 case CDC_TX4_TX_PATH_SEC3: 537 case CDC_TX4_TX_PATH_SEC4: 538 case CDC_TX4_TX_PATH_SEC5: 539 case CDC_TX4_TX_PATH_SEC6: 540 case CDC_TX5_TX_PATH_CTL: 541 case CDC_TX5_TX_PATH_CFG0: 542 case CDC_TX5_TX_PATH_CFG1: 543 case CDC_TX5_TX_VOL_CTL: 544 case CDC_TX5_TX_PATH_SEC0: 545 case CDC_TX5_TX_PATH_SEC1: 546 case CDC_TX5_TX_PATH_SEC2: 547 case CDC_TX5_TX_PATH_SEC3: 548 case CDC_TX5_TX_PATH_SEC4: 549 case CDC_TX5_TX_PATH_SEC5: 550 case CDC_TX5_TX_PATH_SEC6: 551 case CDC_TX6_TX_PATH_CTL: 552 case CDC_TX6_TX_PATH_CFG0: 553 case CDC_TX6_TX_PATH_CFG1: 554 case CDC_TX6_TX_VOL_CTL: 555 case CDC_TX6_TX_PATH_SEC0: 556 case CDC_TX6_TX_PATH_SEC1: 557 case CDC_TX6_TX_PATH_SEC2: 558 case CDC_TX6_TX_PATH_SEC3: 559 case CDC_TX6_TX_PATH_SEC4: 560 case CDC_TX6_TX_PATH_SEC5: 561 case CDC_TX6_TX_PATH_SEC6: 562 case CDC_TX7_TX_PATH_CTL: 563 case CDC_TX7_TX_PATH_CFG0: 564 case CDC_TX7_TX_PATH_CFG1: 565 case CDC_TX7_TX_VOL_CTL: 566 case CDC_TX7_TX_PATH_SEC0: 567 case CDC_TX7_TX_PATH_SEC1: 568 case CDC_TX7_TX_PATH_SEC2: 569 case CDC_TX7_TX_PATH_SEC3: 570 case CDC_TX7_TX_PATH_SEC4: 571 case CDC_TX7_TX_PATH_SEC5: 572 case CDC_TX7_TX_PATH_SEC6: 573 return true; 574 } 575 576 return false; 577 } 578 579 static const struct regmap_config tx_regmap_config = { 580 .name = "tx_macro", 581 .reg_bits = 16, 582 .val_bits = 32, 583 .reg_stride = 4, 584 .cache_type = REGCACHE_FLAT, 585 .max_register = TX_MAX_OFFSET, 586 .reg_defaults = tx_defaults, 587 .num_reg_defaults = ARRAY_SIZE(tx_defaults), 588 .writeable_reg = tx_is_rw_register, 589 .volatile_reg = tx_is_volatile_register, 590 .readable_reg = tx_is_rw_register, 591 }; 592 593 static int tx_macro_mclk_enable(struct tx_macro *tx, 594 bool mclk_enable) 595 { 596 struct regmap *regmap = tx->regmap; 597 598 if (mclk_enable) { 599 if (tx->tx_mclk_users == 0) { 600 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 601 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); 602 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 603 CDC_TX_MCLK_EN_MASK, 604 CDC_TX_MCLK_ENABLE); 605 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 606 CDC_TX_FS_CNT_EN_MASK, 607 CDC_TX_FS_CNT_ENABLE); 608 regcache_mark_dirty(regmap); 609 regcache_sync(regmap); 610 } 611 tx->tx_mclk_users++; 612 } else { 613 if (tx->tx_mclk_users <= 0) { 614 dev_err(tx->dev, "clock already disabled\n"); 615 tx->tx_mclk_users = 0; 616 goto exit; 617 } 618 tx->tx_mclk_users--; 619 if (tx->tx_mclk_users == 0) { 620 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 621 CDC_TX_FS_CNT_EN_MASK, 0x0); 622 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 623 CDC_TX_MCLK_EN_MASK, 0x0); 624 } 625 } 626 exit: 627 return 0; 628 } 629 630 static bool is_amic_enabled(struct snd_soc_component *component, int decimator) 631 { 632 u16 adc_mux_reg, adc_reg, adc_n; 633 634 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 635 636 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 637 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 638 adc_n = snd_soc_component_read_field(component, adc_reg, 639 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK); 640 if (adc_n < TX_ADC_MAX) 641 return true; 642 } 643 644 return false; 645 } 646 647 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 648 { 649 struct delayed_work *hpf_delayed_work; 650 struct hpf_work *hpf_work; 651 struct tx_macro *tx; 652 struct snd_soc_component *component; 653 u16 dec_cfg_reg, hpf_gate_reg; 654 u8 hpf_cut_off_freq; 655 656 hpf_delayed_work = to_delayed_work(work); 657 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); 658 tx = hpf_work->tx; 659 component = tx->component; 660 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; 661 662 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator); 663 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator); 664 665 if (is_amic_enabled(component, hpf_work->decimator)) { 666 snd_soc_component_write_field(component, 667 dec_cfg_reg, 668 CDC_TXn_HPF_CUT_FREQ_MASK, 669 hpf_cut_off_freq); 670 snd_soc_component_update_bits(component, hpf_gate_reg, 671 CDC_TXn_HPF_F_CHANGE_MASK | 672 CDC_TXn_HPF_ZERO_GATE_MASK, 673 0x02); 674 snd_soc_component_update_bits(component, hpf_gate_reg, 675 CDC_TXn_HPF_F_CHANGE_MASK | 676 CDC_TXn_HPF_ZERO_GATE_MASK, 677 0x01); 678 } else { 679 snd_soc_component_write_field(component, dec_cfg_reg, 680 CDC_TXn_HPF_CUT_FREQ_MASK, 681 hpf_cut_off_freq); 682 snd_soc_component_write_field(component, hpf_gate_reg, 683 CDC_TXn_HPF_F_CHANGE_MASK, 0x1); 684 /* Minimum 1 clk cycle delay is required as per HW spec */ 685 usleep_range(1000, 1010); 686 snd_soc_component_write_field(component, hpf_gate_reg, 687 CDC_TXn_HPF_F_CHANGE_MASK, 0x0); 688 } 689 } 690 691 static void tx_macro_mute_update_callback(struct work_struct *work) 692 { 693 struct tx_mute_work *tx_mute_dwork; 694 struct snd_soc_component *component; 695 struct tx_macro *tx; 696 struct delayed_work *delayed_work; 697 u8 decimator; 698 699 delayed_work = to_delayed_work(work); 700 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); 701 tx = tx_mute_dwork->tx; 702 component = tx->component; 703 decimator = tx_mute_dwork->decimator; 704 705 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator), 706 CDC_TXn_PGA_MUTE_MASK, 0x0); 707 } 708 709 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, 710 struct snd_kcontrol *kcontrol, int event) 711 { 712 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 713 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 714 715 switch (event) { 716 case SND_SOC_DAPM_PRE_PMU: 717 tx_macro_mclk_enable(tx, true); 718 break; 719 case SND_SOC_DAPM_POST_PMD: 720 tx_macro_mclk_enable(tx, false); 721 break; 722 default: 723 break; 724 } 725 726 return 0; 727 } 728 729 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 730 struct snd_ctl_elem_value *ucontrol) 731 { 732 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 733 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 734 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 735 unsigned int val, dmic; 736 u16 mic_sel_reg; 737 u16 dmic_clk_reg; 738 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 739 740 val = ucontrol->value.enumerated.item[0]; 741 742 switch (e->reg) { 743 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 744 mic_sel_reg = CDC_TX0_TX_PATH_CFG0; 745 break; 746 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 747 mic_sel_reg = CDC_TX1_TX_PATH_CFG0; 748 break; 749 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 750 mic_sel_reg = CDC_TX2_TX_PATH_CFG0; 751 break; 752 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 753 mic_sel_reg = CDC_TX3_TX_PATH_CFG0; 754 break; 755 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 756 mic_sel_reg = CDC_TX4_TX_PATH_CFG0; 757 break; 758 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 759 mic_sel_reg = CDC_TX5_TX_PATH_CFG0; 760 break; 761 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 762 mic_sel_reg = CDC_TX6_TX_PATH_CFG0; 763 break; 764 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 765 mic_sel_reg = CDC_TX7_TX_PATH_CFG0; 766 break; 767 } 768 769 if (val != 0) { 770 if (val < 5) { 771 snd_soc_component_write_field(component, mic_sel_reg, 772 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 773 } else { 774 snd_soc_component_write_field(component, mic_sel_reg, 775 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 776 dmic = TX_ADC_TO_DMIC(val); 777 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 778 snd_soc_component_write_field(component, dmic_clk_reg, 779 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 780 tx->dmic_clk_div); 781 } 782 } 783 784 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 785 } 786 787 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 788 struct snd_ctl_elem_value *ucontrol) 789 { 790 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 791 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 792 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 793 u32 dai_id = widget->shift; 794 u32 dec_id = mc->shift; 795 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 796 797 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) 798 ucontrol->value.integer.value[0] = 1; 799 else 800 ucontrol->value.integer.value[0] = 0; 801 802 return 0; 803 } 804 805 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 806 struct snd_ctl_elem_value *ucontrol) 807 { 808 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 809 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 810 struct snd_soc_dapm_update *update = NULL; 811 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 812 u32 dai_id = widget->shift; 813 u32 dec_id = mc->shift; 814 u32 enable = ucontrol->value.integer.value[0]; 815 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 816 817 if (enable) { 818 set_bit(dec_id, &tx->active_ch_mask[dai_id]); 819 tx->active_ch_cnt[dai_id]++; 820 tx->active_decimator[dai_id] = dec_id; 821 } else { 822 tx->active_ch_cnt[dai_id]--; 823 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); 824 tx->active_decimator[dai_id] = -1; 825 } 826 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 827 828 return 0; 829 } 830 831 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 832 struct snd_kcontrol *kcontrol, int event) 833 { 834 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 835 unsigned int decimator; 836 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg; 837 u8 hpf_cut_off_freq; 838 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; 839 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; 840 u16 adc_mux_reg, adc_reg, adc_n, dmic; 841 u16 dmic_clk_reg; 842 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 843 844 decimator = w->shift; 845 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator); 846 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator); 847 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator); 848 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator); 849 850 switch (event) { 851 case SND_SOC_DAPM_PRE_PMU: 852 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 853 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 854 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 855 adc_n = snd_soc_component_read(component, adc_reg) & 856 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK; 857 if (adc_n >= TX_ADC_MAX) { 858 dmic = TX_ADC_TO_DMIC(adc_n); 859 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 860 861 snd_soc_component_write_field(component, dmic_clk_reg, 862 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 863 tx->dmic_clk_div); 864 } 865 } 866 snd_soc_component_write_field(component, dec_cfg_reg, 867 CDC_TXn_ADC_MODE_MASK, 868 tx->dec_mode[decimator]); 869 /* Enable TX PGA Mute */ 870 snd_soc_component_write_field(component, tx_vol_ctl_reg, 871 CDC_TXn_PGA_MUTE_MASK, 0x1); 872 break; 873 case SND_SOC_DAPM_POST_PMU: 874 snd_soc_component_write_field(component, tx_vol_ctl_reg, 875 CDC_TXn_CLK_EN_MASK, 0x1); 876 if (!is_amic_enabled(component, decimator)) { 877 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); 878 /* Minimum 1 clk cycle delay is required as per HW spec */ 879 usleep_range(1000, 1010); 880 } 881 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg, 882 CDC_TXn_HPF_CUT_FREQ_MASK); 883 884 tx->tx_hpf_work[decimator].hpf_cut_off_freq = 885 hpf_cut_off_freq; 886 887 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) 888 snd_soc_component_write_field(component, dec_cfg_reg, 889 CDC_TXn_HPF_CUT_FREQ_MASK, 890 CF_MIN_3DB_150HZ); 891 892 if (is_amic_enabled(component, decimator)) { 893 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS; 894 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS; 895 } 896 /* schedule work queue to Remove Mute */ 897 queue_delayed_work(system_freezable_wq, 898 &tx->tx_mute_dwork[decimator].dwork, 899 msecs_to_jiffies(unmute_delay)); 900 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 901 queue_delayed_work(system_freezable_wq, 902 &tx->tx_hpf_work[decimator].dwork, 903 msecs_to_jiffies(hpf_delay)); 904 snd_soc_component_update_bits(component, hpf_gate_reg, 905 CDC_TXn_HPF_F_CHANGE_MASK | 906 CDC_TXn_HPF_ZERO_GATE_MASK, 907 0x02); 908 if (!is_amic_enabled(component, decimator)) 909 snd_soc_component_update_bits(component, hpf_gate_reg, 910 CDC_TXn_HPF_F_CHANGE_MASK | 911 CDC_TXn_HPF_ZERO_GATE_MASK, 912 0x00); 913 snd_soc_component_update_bits(component, hpf_gate_reg, 914 CDC_TXn_HPF_F_CHANGE_MASK | 915 CDC_TXn_HPF_ZERO_GATE_MASK, 916 0x01); 917 918 /* 919 * 6ms delay is required as per HW spec 920 */ 921 usleep_range(6000, 6010); 922 } 923 /* apply gain after decimator is enabled */ 924 snd_soc_component_write(component, tx_gain_ctl_reg, 925 snd_soc_component_read(component, 926 tx_gain_ctl_reg)); 927 if (tx->bcs_enable) { 928 snd_soc_component_update_bits(component, dec_cfg_reg, 929 0x01, 0x01); 930 tx->bcs_clk_en = true; 931 } 932 break; 933 case SND_SOC_DAPM_PRE_PMD: 934 hpf_cut_off_freq = 935 tx->tx_hpf_work[decimator].hpf_cut_off_freq; 936 snd_soc_component_write_field(component, tx_vol_ctl_reg, 937 CDC_TXn_PGA_MUTE_MASK, 0x1); 938 if (cancel_delayed_work_sync( 939 &tx->tx_hpf_work[decimator].dwork)) { 940 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 941 snd_soc_component_write_field( 942 component, dec_cfg_reg, 943 CDC_TXn_HPF_CUT_FREQ_MASK, 944 hpf_cut_off_freq); 945 if (is_amic_enabled(component, decimator)) 946 snd_soc_component_update_bits(component, 947 hpf_gate_reg, 948 CDC_TXn_HPF_F_CHANGE_MASK | 949 CDC_TXn_HPF_ZERO_GATE_MASK, 950 0x02); 951 else 952 snd_soc_component_update_bits(component, 953 hpf_gate_reg, 954 CDC_TXn_HPF_F_CHANGE_MASK | 955 CDC_TXn_HPF_ZERO_GATE_MASK, 956 0x03); 957 958 /* 959 * Minimum 1 clk cycle delay is required 960 * as per HW spec 961 */ 962 usleep_range(1000, 1010); 963 snd_soc_component_update_bits(component, hpf_gate_reg, 964 CDC_TXn_HPF_F_CHANGE_MASK | 965 CDC_TXn_HPF_ZERO_GATE_MASK, 966 0x1); 967 } 968 } 969 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); 970 break; 971 case SND_SOC_DAPM_POST_PMD: 972 snd_soc_component_write_field(component, tx_vol_ctl_reg, 973 CDC_TXn_CLK_EN_MASK, 0x0); 974 snd_soc_component_write_field(component, dec_cfg_reg, 975 CDC_TXn_ADC_MODE_MASK, 0x0); 976 snd_soc_component_write_field(component, tx_vol_ctl_reg, 977 CDC_TXn_PGA_MUTE_MASK, 0x0); 978 if (tx->bcs_enable) { 979 snd_soc_component_write_field(component, dec_cfg_reg, 980 CDC_TXn_PH_EN_MASK, 0x0); 981 snd_soc_component_write_field(component, 982 CDC_TX0_TX_PATH_SEC7, 983 CDC_TX0_MBHC_CTL_EN_MASK, 984 0x0); 985 tx->bcs_clk_en = false; 986 } 987 break; 988 } 989 return 0; 990 } 991 992 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 993 struct snd_ctl_elem_value *ucontrol) 994 { 995 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 996 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 997 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 998 int path = e->shift_l; 999 1000 ucontrol->value.integer.value[0] = tx->dec_mode[path]; 1001 1002 return 0; 1003 } 1004 1005 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 1006 struct snd_ctl_elem_value *ucontrol) 1007 { 1008 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1009 int value = ucontrol->value.integer.value[0]; 1010 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1011 int path = e->shift_l; 1012 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1013 1014 tx->dec_mode[path] = value; 1015 1016 return 0; 1017 } 1018 1019 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol, 1020 struct snd_ctl_elem_value *ucontrol) 1021 { 1022 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1023 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1024 1025 ucontrol->value.integer.value[0] = tx->bcs_enable; 1026 1027 return 0; 1028 } 1029 1030 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol, 1031 struct snd_ctl_elem_value *ucontrol) 1032 { 1033 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1034 int value = ucontrol->value.integer.value[0]; 1035 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1036 1037 tx->bcs_enable = value; 1038 1039 return 0; 1040 } 1041 1042 static int tx_macro_hw_params(struct snd_pcm_substream *substream, 1043 struct snd_pcm_hw_params *params, 1044 struct snd_soc_dai *dai) 1045 { 1046 struct snd_soc_component *component = dai->component; 1047 u32 decimator, sample_rate; 1048 int tx_fs_rate; 1049 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1050 1051 sample_rate = params_rate(params); 1052 switch (sample_rate) { 1053 case 8000: 1054 tx_fs_rate = 0; 1055 break; 1056 case 16000: 1057 tx_fs_rate = 1; 1058 break; 1059 case 32000: 1060 tx_fs_rate = 3; 1061 break; 1062 case 48000: 1063 tx_fs_rate = 4; 1064 break; 1065 case 96000: 1066 tx_fs_rate = 5; 1067 break; 1068 case 192000: 1069 tx_fs_rate = 6; 1070 break; 1071 case 384000: 1072 tx_fs_rate = 7; 1073 break; 1074 default: 1075 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", 1076 __func__, params_rate(params)); 1077 return -EINVAL; 1078 } 1079 1080 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) 1081 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator), 1082 CDC_TXn_PCM_RATE_MASK, 1083 tx_fs_rate); 1084 return 0; 1085 } 1086 1087 static int tx_macro_get_channel_map(struct snd_soc_dai *dai, 1088 unsigned int *tx_num, unsigned int *tx_slot, 1089 unsigned int *rx_num, unsigned int *rx_slot) 1090 { 1091 struct snd_soc_component *component = dai->component; 1092 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1093 1094 switch (dai->id) { 1095 case TX_MACRO_AIF1_CAP: 1096 case TX_MACRO_AIF2_CAP: 1097 case TX_MACRO_AIF3_CAP: 1098 *tx_slot = tx->active_ch_mask[dai->id]; 1099 *tx_num = tx->active_ch_cnt[dai->id]; 1100 break; 1101 default: 1102 break; 1103 } 1104 return 0; 1105 } 1106 1107 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1108 { 1109 struct snd_soc_component *component = dai->component; 1110 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1111 u16 decimator; 1112 1113 decimator = tx->active_decimator[dai->id]; 1114 1115 if (mute) 1116 snd_soc_component_write_field(component, 1117 CDC_TXn_TX_PATH_CTL(decimator), 1118 CDC_TXn_PGA_MUTE_MASK, 0x1); 1119 else 1120 snd_soc_component_update_bits(component, 1121 CDC_TXn_TX_PATH_CTL(decimator), 1122 CDC_TXn_PGA_MUTE_MASK, 0x0); 1123 1124 return 0; 1125 } 1126 1127 static const struct snd_soc_dai_ops tx_macro_dai_ops = { 1128 .hw_params = tx_macro_hw_params, 1129 .get_channel_map = tx_macro_get_channel_map, 1130 .mute_stream = tx_macro_digital_mute, 1131 }; 1132 1133 static struct snd_soc_dai_driver tx_macro_dai[] = { 1134 { 1135 .name = "tx_macro_tx1", 1136 .id = TX_MACRO_AIF1_CAP, 1137 .capture = { 1138 .stream_name = "TX_AIF1 Capture", 1139 .rates = TX_MACRO_RATES, 1140 .formats = TX_MACRO_FORMATS, 1141 .rate_max = 192000, 1142 .rate_min = 8000, 1143 .channels_min = 1, 1144 .channels_max = 8, 1145 }, 1146 .ops = &tx_macro_dai_ops, 1147 }, 1148 { 1149 .name = "tx_macro_tx2", 1150 .id = TX_MACRO_AIF2_CAP, 1151 .capture = { 1152 .stream_name = "TX_AIF2 Capture", 1153 .rates = TX_MACRO_RATES, 1154 .formats = TX_MACRO_FORMATS, 1155 .rate_max = 192000, 1156 .rate_min = 8000, 1157 .channels_min = 1, 1158 .channels_max = 8, 1159 }, 1160 .ops = &tx_macro_dai_ops, 1161 }, 1162 { 1163 .name = "tx_macro_tx3", 1164 .id = TX_MACRO_AIF3_CAP, 1165 .capture = { 1166 .stream_name = "TX_AIF3 Capture", 1167 .rates = TX_MACRO_RATES, 1168 .formats = TX_MACRO_FORMATS, 1169 .rate_max = 192000, 1170 .rate_min = 8000, 1171 .channels_min = 1, 1172 .channels_max = 8, 1173 }, 1174 .ops = &tx_macro_dai_ops, 1175 }, 1176 }; 1177 1178 static const char * const adc_mux_text[] = { 1179 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" 1180 }; 1181 1182 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, 1183 0, adc_mux_text); 1184 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, 1185 0, adc_mux_text); 1186 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, 1187 0, adc_mux_text); 1188 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, 1189 0, adc_mux_text); 1190 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, 1191 0, adc_mux_text); 1192 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, 1193 0, adc_mux_text); 1194 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, 1195 0, adc_mux_text); 1196 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, 1197 0, adc_mux_text); 1198 1199 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum); 1200 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum); 1201 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum); 1202 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum); 1203 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum); 1204 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum); 1205 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum); 1206 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum); 1207 1208 static const char * const smic_mux_text[] = { 1209 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", 1210 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", 1211 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" 1212 }; 1213 1214 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1215 0, smic_mux_text); 1216 1217 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1218 0, smic_mux_text); 1219 1220 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1221 0, smic_mux_text); 1222 1223 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1224 0, smic_mux_text); 1225 1226 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1227 0, smic_mux_text); 1228 1229 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1230 0, smic_mux_text); 1231 1232 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1233 0, smic_mux_text); 1234 1235 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1236 0, smic_mux_text); 1237 1238 static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum, 1239 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1240 static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum, 1241 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1242 static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum, 1243 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1244 static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum, 1245 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1246 static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum, 1247 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1248 static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum, 1249 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1250 static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum, 1251 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1252 static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum, 1253 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1254 1255 static const char * const dec_mode_mux_text[] = { 1256 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1257 }; 1258 1259 static const struct soc_enum dec_mode_mux_enum[] = { 1260 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1261 dec_mode_mux_text), 1262 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1263 dec_mode_mux_text), 1264 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1265 dec_mode_mux_text), 1266 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1267 dec_mode_mux_text), 1268 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text), 1269 dec_mode_mux_text), 1270 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text), 1271 dec_mode_mux_text), 1272 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text), 1273 dec_mode_mux_text), 1274 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text), 1275 dec_mode_mux_text), 1276 }; 1277 1278 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { 1279 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1280 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1281 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1282 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1283 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1284 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1285 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1286 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1287 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1288 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1289 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1290 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1291 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1292 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1293 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1294 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1295 }; 1296 1297 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { 1298 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1299 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1300 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1301 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1302 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1303 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1304 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1305 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1306 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1307 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1308 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1309 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1310 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1311 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1312 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1313 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1314 }; 1315 1316 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { 1317 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1318 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1319 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1320 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1321 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1322 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1323 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1324 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1325 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1326 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1327 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1328 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1329 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1330 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1331 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1332 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1333 }; 1334 1335 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { 1336 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, 1337 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), 1338 1339 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, 1340 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), 1341 1342 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, 1343 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), 1344 1345 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, 1346 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), 1347 1348 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, 1349 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), 1350 1351 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0, 1352 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), 1353 1354 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux), 1355 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux), 1356 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux), 1357 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux), 1358 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux), 1359 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux), 1360 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux), 1361 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux), 1362 1363 SND_SOC_DAPM_INPUT("TX SWR_ADC0"), 1364 SND_SOC_DAPM_INPUT("TX SWR_ADC1"), 1365 SND_SOC_DAPM_INPUT("TX SWR_ADC2"), 1366 SND_SOC_DAPM_INPUT("TX SWR_ADC3"), 1367 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), 1368 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), 1369 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), 1370 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), 1371 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), 1372 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), 1373 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), 1374 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), 1375 1376 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, 1377 TX_MACRO_DEC0, 0, 1378 &tx_dec0_mux, tx_macro_enable_dec, 1379 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1380 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1381 1382 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, 1383 TX_MACRO_DEC1, 0, 1384 &tx_dec1_mux, tx_macro_enable_dec, 1385 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1386 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1387 1388 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, 1389 TX_MACRO_DEC2, 0, 1390 &tx_dec2_mux, tx_macro_enable_dec, 1391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1392 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1393 1394 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, 1395 TX_MACRO_DEC3, 0, 1396 &tx_dec3_mux, tx_macro_enable_dec, 1397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1398 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1399 1400 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, 1401 TX_MACRO_DEC4, 0, 1402 &tx_dec4_mux, tx_macro_enable_dec, 1403 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1404 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1405 1406 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, 1407 TX_MACRO_DEC5, 0, 1408 &tx_dec5_mux, tx_macro_enable_dec, 1409 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1410 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1411 1412 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, 1413 TX_MACRO_DEC6, 0, 1414 &tx_dec6_mux, tx_macro_enable_dec, 1415 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1416 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1417 1418 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, 1419 TX_MACRO_DEC7, 0, 1420 &tx_dec7_mux, tx_macro_enable_dec, 1421 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1422 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1423 1424 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, 1425 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1426 1427 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), 1428 1429 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, 1430 NULL, 0), 1431 }; 1432 1433 static const struct snd_soc_dapm_route tx_audio_map[] = { 1434 {"TX_AIF1 CAP", NULL, "TX_MCLK"}, 1435 {"TX_AIF2 CAP", NULL, "TX_MCLK"}, 1436 {"TX_AIF3 CAP", NULL, "TX_MCLK"}, 1437 1438 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, 1439 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, 1440 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, 1441 1442 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1443 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1444 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1445 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1446 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1447 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1448 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1449 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1450 1451 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1452 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1453 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1454 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1455 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1456 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1457 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1458 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1459 1460 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1461 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1462 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1463 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1464 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1465 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1466 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1467 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1468 1469 {"TX DEC0 MUX", NULL, "TX_MCLK"}, 1470 {"TX DEC1 MUX", NULL, "TX_MCLK"}, 1471 {"TX DEC2 MUX", NULL, "TX_MCLK"}, 1472 {"TX DEC3 MUX", NULL, "TX_MCLK"}, 1473 {"TX DEC4 MUX", NULL, "TX_MCLK"}, 1474 {"TX DEC5 MUX", NULL, "TX_MCLK"}, 1475 {"TX DEC6 MUX", NULL, "TX_MCLK"}, 1476 {"TX DEC7 MUX", NULL, "TX_MCLK"}, 1477 1478 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1479 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1480 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, 1481 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, 1482 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, 1483 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, 1484 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, 1485 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, 1486 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, 1487 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, 1488 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, 1489 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, 1490 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, 1491 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, 1492 1493 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1494 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1495 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, 1496 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, 1497 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, 1498 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, 1499 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, 1500 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, 1501 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, 1502 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, 1503 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, 1504 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, 1505 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, 1506 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, 1507 1508 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1509 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1510 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, 1511 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, 1512 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, 1513 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, 1514 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, 1515 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, 1516 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, 1517 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, 1518 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, 1519 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, 1520 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, 1521 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, 1522 1523 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1524 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1525 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, 1526 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, 1527 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, 1528 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, 1529 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, 1530 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, 1531 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, 1532 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, 1533 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, 1534 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, 1535 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, 1536 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, 1537 1538 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1539 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1540 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, 1541 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, 1542 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, 1543 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, 1544 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, 1545 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, 1546 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, 1547 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, 1548 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, 1549 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, 1550 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, 1551 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, 1552 1553 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1554 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1555 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, 1556 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, 1557 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, 1558 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, 1559 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, 1560 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, 1561 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, 1562 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, 1563 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, 1564 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, 1565 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, 1566 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, 1567 1568 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1569 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 1570 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, 1571 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, 1572 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, 1573 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, 1574 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, 1575 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, 1576 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, 1577 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, 1578 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, 1579 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, 1580 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, 1581 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, 1582 1583 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 1584 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 1585 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, 1586 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, 1587 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, 1588 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, 1589 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, 1590 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, 1591 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, 1592 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, 1593 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, 1594 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, 1595 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, 1596 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, 1597 }; 1598 1599 static const struct snd_kcontrol_new tx_macro_snd_controls[] = { 1600 SOC_SINGLE_S8_TLV("TX_DEC0 Volume", 1601 CDC_TX0_TX_VOL_CTL, 1602 -84, 40, digital_gain), 1603 SOC_SINGLE_S8_TLV("TX_DEC1 Volume", 1604 CDC_TX1_TX_VOL_CTL, 1605 -84, 40, digital_gain), 1606 SOC_SINGLE_S8_TLV("TX_DEC2 Volume", 1607 CDC_TX2_TX_VOL_CTL, 1608 -84, 40, digital_gain), 1609 SOC_SINGLE_S8_TLV("TX_DEC3 Volume", 1610 CDC_TX3_TX_VOL_CTL, 1611 -84, 40, digital_gain), 1612 SOC_SINGLE_S8_TLV("TX_DEC4 Volume", 1613 CDC_TX4_TX_VOL_CTL, 1614 -84, 40, digital_gain), 1615 SOC_SINGLE_S8_TLV("TX_DEC5 Volume", 1616 CDC_TX5_TX_VOL_CTL, 1617 -84, 40, digital_gain), 1618 SOC_SINGLE_S8_TLV("TX_DEC6 Volume", 1619 CDC_TX6_TX_VOL_CTL, 1620 -84, 40, digital_gain), 1621 SOC_SINGLE_S8_TLV("TX_DEC7 Volume", 1622 CDC_TX7_TX_VOL_CTL, 1623 -84, 40, digital_gain), 1624 1625 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0], 1626 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1627 1628 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1], 1629 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1630 1631 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2], 1632 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1633 1634 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3], 1635 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1636 1637 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4], 1638 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1639 1640 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5], 1641 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1642 1643 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6], 1644 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1645 1646 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7], 1647 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1648 1649 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, 1650 tx_macro_get_bcs, tx_macro_set_bcs), 1651 }; 1652 1653 static int tx_macro_component_probe(struct snd_soc_component *comp) 1654 { 1655 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 1656 int i; 1657 1658 snd_soc_component_init_regmap(comp, tx->regmap); 1659 1660 for (i = 0; i < NUM_DECIMATORS; i++) { 1661 tx->tx_hpf_work[i].tx = tx; 1662 tx->tx_hpf_work[i].decimator = i; 1663 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, 1664 tx_macro_tx_hpf_corner_freq_callback); 1665 } 1666 1667 for (i = 0; i < NUM_DECIMATORS; i++) { 1668 tx->tx_mute_dwork[i].tx = tx; 1669 tx->tx_mute_dwork[i].decimator = i; 1670 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, 1671 tx_macro_mute_update_callback); 1672 } 1673 tx->component = comp; 1674 1675 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 1676 0x0A); 1677 /* Enable swr mic0 and mic1 clock */ 1678 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00); 1679 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00); 1680 1681 return 0; 1682 } 1683 1684 static int swclk_gate_enable(struct clk_hw *hw) 1685 { 1686 struct tx_macro *tx = to_tx_macro(hw); 1687 struct regmap *regmap = tx->regmap; 1688 1689 tx_macro_mclk_enable(tx, true); 1690 if (tx->reset_swr) 1691 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1692 CDC_TX_SWR_RESET_MASK, 1693 CDC_TX_SWR_RESET_ENABLE); 1694 1695 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1696 CDC_TX_SWR_CLK_EN_MASK, 1697 CDC_TX_SWR_CLK_ENABLE); 1698 if (tx->reset_swr) 1699 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1700 CDC_TX_SWR_RESET_MASK, 0x0); 1701 tx->reset_swr = false; 1702 1703 return 0; 1704 } 1705 1706 static void swclk_gate_disable(struct clk_hw *hw) 1707 { 1708 struct tx_macro *tx = to_tx_macro(hw); 1709 struct regmap *regmap = tx->regmap; 1710 1711 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1712 CDC_TX_SWR_CLK_EN_MASK, 0x0); 1713 1714 tx_macro_mclk_enable(tx, false); 1715 } 1716 1717 static int swclk_gate_is_enabled(struct clk_hw *hw) 1718 { 1719 struct tx_macro *tx = to_tx_macro(hw); 1720 int ret, val; 1721 1722 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); 1723 ret = val & BIT(0); 1724 1725 return ret; 1726 } 1727 1728 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 1729 unsigned long parent_rate) 1730 { 1731 return parent_rate / 2; 1732 } 1733 1734 static const struct clk_ops swclk_gate_ops = { 1735 .prepare = swclk_gate_enable, 1736 .unprepare = swclk_gate_disable, 1737 .is_enabled = swclk_gate_is_enabled, 1738 .recalc_rate = swclk_recalc_rate, 1739 1740 }; 1741 1742 static struct clk *tx_macro_register_mclk_output(struct tx_macro *tx) 1743 { 1744 struct device *dev = tx->dev; 1745 struct device_node *np = dev->of_node; 1746 const char *parent_clk_name = NULL; 1747 const char *clk_name = "lpass-tx-mclk"; 1748 struct clk_hw *hw; 1749 struct clk_init_data init; 1750 int ret; 1751 1752 parent_clk_name = __clk_get_name(tx->clks[2].clk); 1753 1754 init.name = clk_name; 1755 init.ops = &swclk_gate_ops; 1756 init.flags = 0; 1757 init.parent_names = &parent_clk_name; 1758 init.num_parents = 1; 1759 tx->hw.init = &init; 1760 hw = &tx->hw; 1761 ret = clk_hw_register(tx->dev, hw); 1762 if (ret) 1763 return ERR_PTR(ret); 1764 1765 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); 1766 1767 return NULL; 1768 } 1769 1770 static const struct snd_soc_component_driver tx_macro_component_drv = { 1771 .name = "RX-MACRO", 1772 .probe = tx_macro_component_probe, 1773 .controls = tx_macro_snd_controls, 1774 .num_controls = ARRAY_SIZE(tx_macro_snd_controls), 1775 .dapm_widgets = tx_macro_dapm_widgets, 1776 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets), 1777 .dapm_routes = tx_audio_map, 1778 .num_dapm_routes = ARRAY_SIZE(tx_audio_map), 1779 }; 1780 1781 static int tx_macro_probe(struct platform_device *pdev) 1782 { 1783 struct device *dev = &pdev->dev; 1784 struct device_node *np = dev->of_node; 1785 struct tx_macro *tx; 1786 void __iomem *base; 1787 int ret, reg; 1788 1789 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); 1790 if (!tx) 1791 return -ENOMEM; 1792 1793 tx->clks[0].id = "macro"; 1794 tx->clks[1].id = "dcodec"; 1795 tx->clks[2].id = "mclk"; 1796 tx->clks[3].id = "npl"; 1797 tx->clks[4].id = "fsgen"; 1798 1799 ret = devm_clk_bulk_get_optional(dev, TX_NUM_CLKS_MAX, tx->clks); 1800 if (ret) { 1801 dev_err(dev, "Error getting RX Clocks (%d)\n", ret); 1802 return ret; 1803 } 1804 1805 base = devm_platform_ioremap_resource(pdev, 0); 1806 if (IS_ERR(base)) 1807 return PTR_ERR(base); 1808 1809 /* Update defaults for lpass sc7280 */ 1810 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { 1811 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) { 1812 switch (tx_defaults[reg].reg) { 1813 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 1814 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 1815 tx_defaults[reg].def = 0x0E; 1816 break; 1817 default: 1818 break; 1819 } 1820 } 1821 } 1822 1823 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); 1824 1825 dev_set_drvdata(dev, tx); 1826 1827 tx->reset_swr = true; 1828 tx->dev = dev; 1829 1830 /* set MCLK and NPL rates */ 1831 clk_set_rate(tx->clks[2].clk, MCLK_FREQ); 1832 clk_set_rate(tx->clks[3].clk, 2 * MCLK_FREQ); 1833 1834 ret = clk_bulk_prepare_enable(TX_NUM_CLKS_MAX, tx->clks); 1835 if (ret) 1836 return ret; 1837 1838 tx_macro_register_mclk_output(tx); 1839 1840 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv, 1841 tx_macro_dai, 1842 ARRAY_SIZE(tx_macro_dai)); 1843 if (ret) 1844 goto err; 1845 return ret; 1846 err: 1847 clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks); 1848 1849 return ret; 1850 } 1851 1852 static int tx_macro_remove(struct platform_device *pdev) 1853 { 1854 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); 1855 1856 of_clk_del_provider(pdev->dev.of_node); 1857 1858 clk_bulk_disable_unprepare(TX_NUM_CLKS_MAX, tx->clks); 1859 1860 return 0; 1861 } 1862 1863 static const struct of_device_id tx_macro_dt_match[] = { 1864 { .compatible = "qcom,sc7280-lpass-tx-macro" }, 1865 { .compatible = "qcom,sm8250-lpass-tx-macro" }, 1866 { } 1867 }; 1868 MODULE_DEVICE_TABLE(of, tx_macro_dt_match); 1869 static struct platform_driver tx_macro_driver = { 1870 .driver = { 1871 .name = "tx_macro", 1872 .of_match_table = tx_macro_dt_match, 1873 .suppress_bind_attrs = true, 1874 }, 1875 .probe = tx_macro_probe, 1876 .remove = tx_macro_remove, 1877 }; 1878 1879 module_platform_driver(tx_macro_driver); 1880 1881 MODULE_DESCRIPTION("TX macro driver"); 1882 MODULE_LICENSE("GPL"); 1883