1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/clk.h> 7 #include <linux/io.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regmap.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dapm.h> 13 #include <sound/tlv.h> 14 #include <linux/of_clk.h> 15 #include <linux/clk-provider.h> 16 17 #include "lpass-macro-common.h" 18 19 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 20 #define CDC_TX_MCLK_EN_MASK BIT(0) 21 #define CDC_TX_MCLK_ENABLE BIT(0) 22 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 23 #define CDC_TX_FS_CNT_EN_MASK BIT(0) 24 #define CDC_TX_FS_CNT_ENABLE BIT(0) 25 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26 #define CDC_TX_SWR_RESET_MASK BIT(1) 27 #define CDC_TX_SWR_RESET_ENABLE BIT(1) 28 #define CDC_TX_SWR_CLK_EN_MASK BIT(0) 29 #define CDC_TX_SWR_CLK_ENABLE BIT(0) 30 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080) 31 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084) 32 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088) 33 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090) 34 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094) 35 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098) 36 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4) 37 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8) 38 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC) 39 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4) 40 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0) 41 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1) 42 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4) 43 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8) 44 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC) 45 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0) 46 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4) 47 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n) 48 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0) 49 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100) 50 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n) 51 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104) 52 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108) 53 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C) 54 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110) 55 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114) 56 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118) 57 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C) 58 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120) 59 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124) 60 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128) 61 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C) 62 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130) 63 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) 64 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) 65 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) 66 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) 67 #define CDC_TX_ANC0_MODE_1_CTL (0x0204) 68 #define CDC_TX_ANC0_MODE_2_CTL (0x0208) 69 #define CDC_TX_ANC0_FF_SHIFT (0x020C) 70 #define CDC_TX_ANC0_FB_SHIFT (0x0210) 71 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214) 72 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218) 73 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C) 74 #define CDC_TX_ANC0_SMLPF_CTL (0x0220) 75 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224) 76 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228) 77 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C) 78 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230) 79 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234) 80 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238) 81 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C) 82 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n) 83 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0) 84 #define CDC_TXn_PGA_MUTE_MASK BIT(4) 85 #define CDC_TXn_CLK_EN_MASK BIT(5) 86 #define CDC_TX0_TX_PATH_CTL (0x0400) 87 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n) 88 #define CDC_TX0_TX_PATH_CFG0 (0x0404) 89 #define CDC_TXn_PH_EN_MASK BIT(0) 90 #define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1) 91 #define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5) 92 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7) 93 #define CDC_TX0_TX_PATH_CFG1 (0x0408) 94 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n) 95 #define CDC_TX0_TX_VOL_CTL (0x040C) 96 #define CDC_TX0_TX_PATH_SEC0 (0x0410) 97 #define CDC_TX0_TX_PATH_SEC1 (0x0414) 98 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n) 99 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1) 100 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0) 101 #define CDC_TX0_TX_PATH_SEC2 (0x0418) 102 #define CDC_TX0_TX_PATH_SEC3 (0x041C) 103 #define CDC_TX0_TX_PATH_SEC4 (0x0420) 104 #define CDC_TX0_TX_PATH_SEC5 (0x0424) 105 #define CDC_TX0_TX_PATH_SEC6 (0x0428) 106 #define CDC_TX0_TX_PATH_SEC7 (0x042C) 107 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) 108 #define CDC_TX1_TX_PATH_CTL (0x0480) 109 #define CDC_TX1_TX_PATH_CFG0 (0x0484) 110 #define CDC_TX1_TX_PATH_CFG1 (0x0488) 111 #define CDC_TX1_TX_VOL_CTL (0x048C) 112 #define CDC_TX1_TX_PATH_SEC0 (0x0490) 113 #define CDC_TX1_TX_PATH_SEC1 (0x0494) 114 #define CDC_TX1_TX_PATH_SEC2 (0x0498) 115 #define CDC_TX1_TX_PATH_SEC3 (0x049C) 116 #define CDC_TX1_TX_PATH_SEC4 (0x04A0) 117 #define CDC_TX1_TX_PATH_SEC5 (0x04A4) 118 #define CDC_TX1_TX_PATH_SEC6 (0x04A8) 119 #define CDC_TX2_TX_PATH_CTL (0x0500) 120 #define CDC_TX2_TX_PATH_CFG0 (0x0504) 121 #define CDC_TX2_TX_PATH_CFG1 (0x0508) 122 #define CDC_TX2_TX_VOL_CTL (0x050C) 123 #define CDC_TX2_TX_PATH_SEC0 (0x0510) 124 #define CDC_TX2_TX_PATH_SEC1 (0x0514) 125 #define CDC_TX2_TX_PATH_SEC2 (0x0518) 126 #define CDC_TX2_TX_PATH_SEC3 (0x051C) 127 #define CDC_TX2_TX_PATH_SEC4 (0x0520) 128 #define CDC_TX2_TX_PATH_SEC5 (0x0524) 129 #define CDC_TX2_TX_PATH_SEC6 (0x0528) 130 #define CDC_TX3_TX_PATH_CTL (0x0580) 131 #define CDC_TX3_TX_PATH_CFG0 (0x0584) 132 #define CDC_TX3_TX_PATH_CFG1 (0x0588) 133 #define CDC_TX3_TX_VOL_CTL (0x058C) 134 #define CDC_TX3_TX_PATH_SEC0 (0x0590) 135 #define CDC_TX3_TX_PATH_SEC1 (0x0594) 136 #define CDC_TX3_TX_PATH_SEC2 (0x0598) 137 #define CDC_TX3_TX_PATH_SEC3 (0x059C) 138 #define CDC_TX3_TX_PATH_SEC4 (0x05A0) 139 #define CDC_TX3_TX_PATH_SEC5 (0x05A4) 140 #define CDC_TX3_TX_PATH_SEC6 (0x05A8) 141 #define CDC_TX4_TX_PATH_CTL (0x0600) 142 #define CDC_TX4_TX_PATH_CFG0 (0x0604) 143 #define CDC_TX4_TX_PATH_CFG1 (0x0608) 144 #define CDC_TX4_TX_VOL_CTL (0x060C) 145 #define CDC_TX4_TX_PATH_SEC0 (0x0610) 146 #define CDC_TX4_TX_PATH_SEC1 (0x0614) 147 #define CDC_TX4_TX_PATH_SEC2 (0x0618) 148 #define CDC_TX4_TX_PATH_SEC3 (0x061C) 149 #define CDC_TX4_TX_PATH_SEC4 (0x0620) 150 #define CDC_TX4_TX_PATH_SEC5 (0x0624) 151 #define CDC_TX4_TX_PATH_SEC6 (0x0628) 152 #define CDC_TX5_TX_PATH_CTL (0x0680) 153 #define CDC_TX5_TX_PATH_CFG0 (0x0684) 154 #define CDC_TX5_TX_PATH_CFG1 (0x0688) 155 #define CDC_TX5_TX_VOL_CTL (0x068C) 156 #define CDC_TX5_TX_PATH_SEC0 (0x0690) 157 #define CDC_TX5_TX_PATH_SEC1 (0x0694) 158 #define CDC_TX5_TX_PATH_SEC2 (0x0698) 159 #define CDC_TX5_TX_PATH_SEC3 (0x069C) 160 #define CDC_TX5_TX_PATH_SEC4 (0x06A0) 161 #define CDC_TX5_TX_PATH_SEC5 (0x06A4) 162 #define CDC_TX5_TX_PATH_SEC6 (0x06A8) 163 #define CDC_TX6_TX_PATH_CTL (0x0700) 164 #define CDC_TX6_TX_PATH_CFG0 (0x0704) 165 #define CDC_TX6_TX_PATH_CFG1 (0x0708) 166 #define CDC_TX6_TX_VOL_CTL (0x070C) 167 #define CDC_TX6_TX_PATH_SEC0 (0x0710) 168 #define CDC_TX6_TX_PATH_SEC1 (0x0714) 169 #define CDC_TX6_TX_PATH_SEC2 (0x0718) 170 #define CDC_TX6_TX_PATH_SEC3 (0x071C) 171 #define CDC_TX6_TX_PATH_SEC4 (0x0720) 172 #define CDC_TX6_TX_PATH_SEC5 (0x0724) 173 #define CDC_TX6_TX_PATH_SEC6 (0x0728) 174 #define CDC_TX7_TX_PATH_CTL (0x0780) 175 #define CDC_TX7_TX_PATH_CFG0 (0x0784) 176 #define CDC_TX7_TX_PATH_CFG1 (0x0788) 177 #define CDC_TX7_TX_VOL_CTL (0x078C) 178 #define CDC_TX7_TX_PATH_SEC0 (0x0790) 179 #define CDC_TX7_TX_PATH_SEC1 (0x0794) 180 #define CDC_TX7_TX_PATH_SEC2 (0x0798) 181 #define CDC_TX7_TX_PATH_SEC3 (0x079C) 182 #define CDC_TX7_TX_PATH_SEC4 (0x07A0) 183 #define CDC_TX7_TX_PATH_SEC5 (0x07A4) 184 #define CDC_TX7_TX_PATH_SEC6 (0x07A8) 185 #define TX_MAX_OFFSET (0x07A8) 186 187 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 188 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 189 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 190 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 191 SNDRV_PCM_FMTBIT_S24_LE |\ 192 SNDRV_PCM_FMTBIT_S24_3LE) 193 194 #define CF_MIN_3DB_4HZ 0x0 195 #define CF_MIN_3DB_75HZ 0x1 196 #define CF_MIN_3DB_150HZ 0x2 197 #define TX_ADC_MAX 5 198 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2) 199 #define NUM_DECIMATORS 8 200 #define TX_NUM_CLKS_MAX 5 201 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40 202 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100 203 #define TX_MACRO_DMIC_HPF_DELAY_MS 300 204 #define TX_MACRO_AMIC_HPF_DELAY_MS 300 205 #define MCLK_FREQ 9600000 206 207 enum { 208 TX_MACRO_AIF_INVALID = 0, 209 TX_MACRO_AIF1_CAP, 210 TX_MACRO_AIF2_CAP, 211 TX_MACRO_AIF3_CAP, 212 TX_MACRO_MAX_DAIS 213 }; 214 215 enum { 216 TX_MACRO_DEC0, 217 TX_MACRO_DEC1, 218 TX_MACRO_DEC2, 219 TX_MACRO_DEC3, 220 TX_MACRO_DEC4, 221 TX_MACRO_DEC5, 222 TX_MACRO_DEC6, 223 TX_MACRO_DEC7, 224 TX_MACRO_DEC_MAX, 225 }; 226 227 enum { 228 TX_MACRO_CLK_DIV_2, 229 TX_MACRO_CLK_DIV_3, 230 TX_MACRO_CLK_DIV_4, 231 TX_MACRO_CLK_DIV_6, 232 TX_MACRO_CLK_DIV_8, 233 TX_MACRO_CLK_DIV_16, 234 }; 235 236 enum { 237 MSM_DMIC, 238 SWR_MIC, 239 ANC_FB_TUNE1 240 }; 241 242 struct tx_mute_work { 243 struct tx_macro *tx; 244 u32 decimator; 245 struct delayed_work dwork; 246 }; 247 248 struct hpf_work { 249 struct tx_macro *tx; 250 u8 decimator; 251 u8 hpf_cut_off_freq; 252 struct delayed_work dwork; 253 }; 254 255 struct tx_macro { 256 struct device *dev; 257 struct snd_soc_component *component; 258 struct hpf_work tx_hpf_work[NUM_DECIMATORS]; 259 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; 260 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; 261 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; 262 unsigned long active_decimator[TX_MACRO_MAX_DAIS]; 263 struct regmap *regmap; 264 struct clk *mclk; 265 struct clk *npl; 266 struct clk *macro; 267 struct clk *dcodec; 268 struct clk *fsgen; 269 struct clk_hw hw; 270 bool dec_active[NUM_DECIMATORS]; 271 bool reset_swr; 272 int tx_mclk_users; 273 u16 dmic_clk_div; 274 bool bcs_enable; 275 int dec_mode[NUM_DECIMATORS]; 276 struct lpass_macro *pds; 277 bool bcs_clk_en; 278 }; 279 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw) 280 281 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 282 283 static struct reg_default tx_defaults[] = { 284 /* TX Macro */ 285 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 286 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 287 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 288 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, 289 { CDC_TX_TOP_CSR_ANC_CFG, 0x00}, 290 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, 291 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, 292 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, 293 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, 294 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, 295 { CDC_TX_TOP_CSR_I2S_CLK, 0x00}, 296 { CDC_TX_TOP_CSR_I2S_RESET, 0x00}, 297 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, 298 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, 299 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, 300 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, 301 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, 302 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, 303 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, 304 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, 305 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, 306 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00}, 307 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00}, 308 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00}, 309 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00}, 310 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00}, 311 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00}, 312 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00}, 313 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00}, 314 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00}, 315 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00}, 316 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, 317 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, 318 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, 319 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, 320 { CDC_TX_ANC0_MODE_1_CTL, 0x00}, 321 { CDC_TX_ANC0_MODE_2_CTL, 0x00}, 322 { CDC_TX_ANC0_FF_SHIFT, 0x00}, 323 { CDC_TX_ANC0_FB_SHIFT, 0x00}, 324 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00}, 325 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00}, 326 { CDC_TX_ANC0_LPF_FB_CTL, 0x00}, 327 { CDC_TX_ANC0_SMLPF_CTL, 0x00}, 328 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00}, 329 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00}, 330 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00}, 331 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00}, 332 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00}, 333 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00}, 334 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00}, 335 { CDC_TX0_TX_PATH_CTL, 0x04}, 336 { CDC_TX0_TX_PATH_CFG0, 0x10}, 337 { CDC_TX0_TX_PATH_CFG1, 0x0B}, 338 { CDC_TX0_TX_VOL_CTL, 0x00}, 339 { CDC_TX0_TX_PATH_SEC0, 0x00}, 340 { CDC_TX0_TX_PATH_SEC1, 0x00}, 341 { CDC_TX0_TX_PATH_SEC2, 0x01}, 342 { CDC_TX0_TX_PATH_SEC3, 0x3C}, 343 { CDC_TX0_TX_PATH_SEC4, 0x20}, 344 { CDC_TX0_TX_PATH_SEC5, 0x00}, 345 { CDC_TX0_TX_PATH_SEC6, 0x00}, 346 { CDC_TX0_TX_PATH_SEC7, 0x25}, 347 { CDC_TX1_TX_PATH_CTL, 0x04}, 348 { CDC_TX1_TX_PATH_CFG0, 0x10}, 349 { CDC_TX1_TX_PATH_CFG1, 0x0B}, 350 { CDC_TX1_TX_VOL_CTL, 0x00}, 351 { CDC_TX1_TX_PATH_SEC0, 0x00}, 352 { CDC_TX1_TX_PATH_SEC1, 0x00}, 353 { CDC_TX1_TX_PATH_SEC2, 0x01}, 354 { CDC_TX1_TX_PATH_SEC3, 0x3C}, 355 { CDC_TX1_TX_PATH_SEC4, 0x20}, 356 { CDC_TX1_TX_PATH_SEC5, 0x00}, 357 { CDC_TX1_TX_PATH_SEC6, 0x00}, 358 { CDC_TX2_TX_PATH_CTL, 0x04}, 359 { CDC_TX2_TX_PATH_CFG0, 0x10}, 360 { CDC_TX2_TX_PATH_CFG1, 0x0B}, 361 { CDC_TX2_TX_VOL_CTL, 0x00}, 362 { CDC_TX2_TX_PATH_SEC0, 0x00}, 363 { CDC_TX2_TX_PATH_SEC1, 0x00}, 364 { CDC_TX2_TX_PATH_SEC2, 0x01}, 365 { CDC_TX2_TX_PATH_SEC3, 0x3C}, 366 { CDC_TX2_TX_PATH_SEC4, 0x20}, 367 { CDC_TX2_TX_PATH_SEC5, 0x00}, 368 { CDC_TX2_TX_PATH_SEC6, 0x00}, 369 { CDC_TX3_TX_PATH_CTL, 0x04}, 370 { CDC_TX3_TX_PATH_CFG0, 0x10}, 371 { CDC_TX3_TX_PATH_CFG1, 0x0B}, 372 { CDC_TX3_TX_VOL_CTL, 0x00}, 373 { CDC_TX3_TX_PATH_SEC0, 0x00}, 374 { CDC_TX3_TX_PATH_SEC1, 0x00}, 375 { CDC_TX3_TX_PATH_SEC2, 0x01}, 376 { CDC_TX3_TX_PATH_SEC3, 0x3C}, 377 { CDC_TX3_TX_PATH_SEC4, 0x20}, 378 { CDC_TX3_TX_PATH_SEC5, 0x00}, 379 { CDC_TX3_TX_PATH_SEC6, 0x00}, 380 { CDC_TX4_TX_PATH_CTL, 0x04}, 381 { CDC_TX4_TX_PATH_CFG0, 0x10}, 382 { CDC_TX4_TX_PATH_CFG1, 0x0B}, 383 { CDC_TX4_TX_VOL_CTL, 0x00}, 384 { CDC_TX4_TX_PATH_SEC0, 0x00}, 385 { CDC_TX4_TX_PATH_SEC1, 0x00}, 386 { CDC_TX4_TX_PATH_SEC2, 0x01}, 387 { CDC_TX4_TX_PATH_SEC3, 0x3C}, 388 { CDC_TX4_TX_PATH_SEC4, 0x20}, 389 { CDC_TX4_TX_PATH_SEC5, 0x00}, 390 { CDC_TX4_TX_PATH_SEC6, 0x00}, 391 { CDC_TX5_TX_PATH_CTL, 0x04}, 392 { CDC_TX5_TX_PATH_CFG0, 0x10}, 393 { CDC_TX5_TX_PATH_CFG1, 0x0B}, 394 { CDC_TX5_TX_VOL_CTL, 0x00}, 395 { CDC_TX5_TX_PATH_SEC0, 0x00}, 396 { CDC_TX5_TX_PATH_SEC1, 0x00}, 397 { CDC_TX5_TX_PATH_SEC2, 0x01}, 398 { CDC_TX5_TX_PATH_SEC3, 0x3C}, 399 { CDC_TX5_TX_PATH_SEC4, 0x20}, 400 { CDC_TX5_TX_PATH_SEC5, 0x00}, 401 { CDC_TX5_TX_PATH_SEC6, 0x00}, 402 { CDC_TX6_TX_PATH_CTL, 0x04}, 403 { CDC_TX6_TX_PATH_CFG0, 0x10}, 404 { CDC_TX6_TX_PATH_CFG1, 0x0B}, 405 { CDC_TX6_TX_VOL_CTL, 0x00}, 406 { CDC_TX6_TX_PATH_SEC0, 0x00}, 407 { CDC_TX6_TX_PATH_SEC1, 0x00}, 408 { CDC_TX6_TX_PATH_SEC2, 0x01}, 409 { CDC_TX6_TX_PATH_SEC3, 0x3C}, 410 { CDC_TX6_TX_PATH_SEC4, 0x20}, 411 { CDC_TX6_TX_PATH_SEC5, 0x00}, 412 { CDC_TX6_TX_PATH_SEC6, 0x00}, 413 { CDC_TX7_TX_PATH_CTL, 0x04}, 414 { CDC_TX7_TX_PATH_CFG0, 0x10}, 415 { CDC_TX7_TX_PATH_CFG1, 0x0B}, 416 { CDC_TX7_TX_VOL_CTL, 0x00}, 417 { CDC_TX7_TX_PATH_SEC0, 0x00}, 418 { CDC_TX7_TX_PATH_SEC1, 0x00}, 419 { CDC_TX7_TX_PATH_SEC2, 0x01}, 420 { CDC_TX7_TX_PATH_SEC3, 0x3C}, 421 { CDC_TX7_TX_PATH_SEC4, 0x20}, 422 { CDC_TX7_TX_PATH_SEC5, 0x00}, 423 { CDC_TX7_TX_PATH_SEC6, 0x00}, 424 }; 425 426 static bool tx_is_volatile_register(struct device *dev, unsigned int reg) 427 { 428 /* Update volatile list for tx/tx macros */ 429 switch (reg) { 430 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 431 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 432 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 433 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 434 return true; 435 } 436 return false; 437 } 438 439 static bool tx_is_rw_register(struct device *dev, unsigned int reg) 440 { 441 switch (reg) { 442 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL: 443 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL: 444 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL: 445 case CDC_TX_TOP_CSR_TOP_CFG0: 446 case CDC_TX_TOP_CSR_ANC_CFG: 447 case CDC_TX_TOP_CSR_SWR_CTRL: 448 case CDC_TX_TOP_CSR_FREQ_MCLK: 449 case CDC_TX_TOP_CSR_DEBUG_BUS: 450 case CDC_TX_TOP_CSR_DEBUG_EN: 451 case CDC_TX_TOP_CSR_TX_I2S_CTL: 452 case CDC_TX_TOP_CSR_I2S_CLK: 453 case CDC_TX_TOP_CSR_I2S_RESET: 454 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL: 455 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL: 456 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL: 457 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL: 458 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 459 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 460 case CDC_TX_ANC0_CLK_RESET_CTL: 461 case CDC_TX_ANC0_MODE_1_CTL: 462 case CDC_TX_ANC0_MODE_2_CTL: 463 case CDC_TX_ANC0_FF_SHIFT: 464 case CDC_TX_ANC0_FB_SHIFT: 465 case CDC_TX_ANC0_LPF_FF_A_CTL: 466 case CDC_TX_ANC0_LPF_FF_B_CTL: 467 case CDC_TX_ANC0_LPF_FB_CTL: 468 case CDC_TX_ANC0_SMLPF_CTL: 469 case CDC_TX_ANC0_DCFLT_SHIFT_CTL: 470 case CDC_TX_ANC0_IIR_ADAPT_CTL: 471 case CDC_TX_ANC0_IIR_COEFF_1_CTL: 472 case CDC_TX_ANC0_IIR_COEFF_2_CTL: 473 case CDC_TX_ANC0_FF_A_GAIN_CTL: 474 case CDC_TX_ANC0_FF_B_GAIN_CTL: 475 case CDC_TX_ANC0_FB_GAIN_CTL: 476 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 477 case CDC_TX_INP_MUX_ADC_MUX0_CFG1: 478 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 479 case CDC_TX_INP_MUX_ADC_MUX1_CFG1: 480 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 481 case CDC_TX_INP_MUX_ADC_MUX2_CFG1: 482 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 483 case CDC_TX_INP_MUX_ADC_MUX3_CFG1: 484 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 485 case CDC_TX_INP_MUX_ADC_MUX4_CFG1: 486 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 487 case CDC_TX_INP_MUX_ADC_MUX5_CFG1: 488 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 489 case CDC_TX_INP_MUX_ADC_MUX6_CFG1: 490 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 491 case CDC_TX_INP_MUX_ADC_MUX7_CFG1: 492 case CDC_TX0_TX_PATH_CTL: 493 case CDC_TX0_TX_PATH_CFG0: 494 case CDC_TX0_TX_PATH_CFG1: 495 case CDC_TX0_TX_VOL_CTL: 496 case CDC_TX0_TX_PATH_SEC0: 497 case CDC_TX0_TX_PATH_SEC1: 498 case CDC_TX0_TX_PATH_SEC2: 499 case CDC_TX0_TX_PATH_SEC3: 500 case CDC_TX0_TX_PATH_SEC4: 501 case CDC_TX0_TX_PATH_SEC5: 502 case CDC_TX0_TX_PATH_SEC6: 503 case CDC_TX0_TX_PATH_SEC7: 504 case CDC_TX1_TX_PATH_CTL: 505 case CDC_TX1_TX_PATH_CFG0: 506 case CDC_TX1_TX_PATH_CFG1: 507 case CDC_TX1_TX_VOL_CTL: 508 case CDC_TX1_TX_PATH_SEC0: 509 case CDC_TX1_TX_PATH_SEC1: 510 case CDC_TX1_TX_PATH_SEC2: 511 case CDC_TX1_TX_PATH_SEC3: 512 case CDC_TX1_TX_PATH_SEC4: 513 case CDC_TX1_TX_PATH_SEC5: 514 case CDC_TX1_TX_PATH_SEC6: 515 case CDC_TX2_TX_PATH_CTL: 516 case CDC_TX2_TX_PATH_CFG0: 517 case CDC_TX2_TX_PATH_CFG1: 518 case CDC_TX2_TX_VOL_CTL: 519 case CDC_TX2_TX_PATH_SEC0: 520 case CDC_TX2_TX_PATH_SEC1: 521 case CDC_TX2_TX_PATH_SEC2: 522 case CDC_TX2_TX_PATH_SEC3: 523 case CDC_TX2_TX_PATH_SEC4: 524 case CDC_TX2_TX_PATH_SEC5: 525 case CDC_TX2_TX_PATH_SEC6: 526 case CDC_TX3_TX_PATH_CTL: 527 case CDC_TX3_TX_PATH_CFG0: 528 case CDC_TX3_TX_PATH_CFG1: 529 case CDC_TX3_TX_VOL_CTL: 530 case CDC_TX3_TX_PATH_SEC0: 531 case CDC_TX3_TX_PATH_SEC1: 532 case CDC_TX3_TX_PATH_SEC2: 533 case CDC_TX3_TX_PATH_SEC3: 534 case CDC_TX3_TX_PATH_SEC4: 535 case CDC_TX3_TX_PATH_SEC5: 536 case CDC_TX3_TX_PATH_SEC6: 537 case CDC_TX4_TX_PATH_CTL: 538 case CDC_TX4_TX_PATH_CFG0: 539 case CDC_TX4_TX_PATH_CFG1: 540 case CDC_TX4_TX_VOL_CTL: 541 case CDC_TX4_TX_PATH_SEC0: 542 case CDC_TX4_TX_PATH_SEC1: 543 case CDC_TX4_TX_PATH_SEC2: 544 case CDC_TX4_TX_PATH_SEC3: 545 case CDC_TX4_TX_PATH_SEC4: 546 case CDC_TX4_TX_PATH_SEC5: 547 case CDC_TX4_TX_PATH_SEC6: 548 case CDC_TX5_TX_PATH_CTL: 549 case CDC_TX5_TX_PATH_CFG0: 550 case CDC_TX5_TX_PATH_CFG1: 551 case CDC_TX5_TX_VOL_CTL: 552 case CDC_TX5_TX_PATH_SEC0: 553 case CDC_TX5_TX_PATH_SEC1: 554 case CDC_TX5_TX_PATH_SEC2: 555 case CDC_TX5_TX_PATH_SEC3: 556 case CDC_TX5_TX_PATH_SEC4: 557 case CDC_TX5_TX_PATH_SEC5: 558 case CDC_TX5_TX_PATH_SEC6: 559 case CDC_TX6_TX_PATH_CTL: 560 case CDC_TX6_TX_PATH_CFG0: 561 case CDC_TX6_TX_PATH_CFG1: 562 case CDC_TX6_TX_VOL_CTL: 563 case CDC_TX6_TX_PATH_SEC0: 564 case CDC_TX6_TX_PATH_SEC1: 565 case CDC_TX6_TX_PATH_SEC2: 566 case CDC_TX6_TX_PATH_SEC3: 567 case CDC_TX6_TX_PATH_SEC4: 568 case CDC_TX6_TX_PATH_SEC5: 569 case CDC_TX6_TX_PATH_SEC6: 570 case CDC_TX7_TX_PATH_CTL: 571 case CDC_TX7_TX_PATH_CFG0: 572 case CDC_TX7_TX_PATH_CFG1: 573 case CDC_TX7_TX_VOL_CTL: 574 case CDC_TX7_TX_PATH_SEC0: 575 case CDC_TX7_TX_PATH_SEC1: 576 case CDC_TX7_TX_PATH_SEC2: 577 case CDC_TX7_TX_PATH_SEC3: 578 case CDC_TX7_TX_PATH_SEC4: 579 case CDC_TX7_TX_PATH_SEC5: 580 case CDC_TX7_TX_PATH_SEC6: 581 return true; 582 } 583 584 return false; 585 } 586 587 static const struct regmap_config tx_regmap_config = { 588 .name = "tx_macro", 589 .reg_bits = 16, 590 .val_bits = 32, 591 .reg_stride = 4, 592 .cache_type = REGCACHE_FLAT, 593 .max_register = TX_MAX_OFFSET, 594 .reg_defaults = tx_defaults, 595 .num_reg_defaults = ARRAY_SIZE(tx_defaults), 596 .writeable_reg = tx_is_rw_register, 597 .volatile_reg = tx_is_volatile_register, 598 .readable_reg = tx_is_rw_register, 599 }; 600 601 static int tx_macro_mclk_enable(struct tx_macro *tx, 602 bool mclk_enable) 603 { 604 struct regmap *regmap = tx->regmap; 605 606 if (mclk_enable) { 607 if (tx->tx_mclk_users == 0) { 608 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 609 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); 610 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 611 CDC_TX_MCLK_EN_MASK, 612 CDC_TX_MCLK_ENABLE); 613 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 614 CDC_TX_FS_CNT_EN_MASK, 615 CDC_TX_FS_CNT_ENABLE); 616 regcache_mark_dirty(regmap); 617 regcache_sync(regmap); 618 } 619 tx->tx_mclk_users++; 620 } else { 621 if (tx->tx_mclk_users <= 0) { 622 dev_err(tx->dev, "clock already disabled\n"); 623 tx->tx_mclk_users = 0; 624 goto exit; 625 } 626 tx->tx_mclk_users--; 627 if (tx->tx_mclk_users == 0) { 628 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 629 CDC_TX_FS_CNT_EN_MASK, 0x0); 630 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 631 CDC_TX_MCLK_EN_MASK, 0x0); 632 } 633 } 634 exit: 635 return 0; 636 } 637 638 static bool is_amic_enabled(struct snd_soc_component *component, int decimator) 639 { 640 u16 adc_mux_reg, adc_reg, adc_n; 641 642 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 643 644 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 645 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 646 adc_n = snd_soc_component_read_field(component, adc_reg, 647 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK); 648 if (adc_n < TX_ADC_MAX) 649 return true; 650 } 651 652 return false; 653 } 654 655 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 656 { 657 struct delayed_work *hpf_delayed_work; 658 struct hpf_work *hpf_work; 659 struct tx_macro *tx; 660 struct snd_soc_component *component; 661 u16 dec_cfg_reg, hpf_gate_reg; 662 u8 hpf_cut_off_freq; 663 664 hpf_delayed_work = to_delayed_work(work); 665 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); 666 tx = hpf_work->tx; 667 component = tx->component; 668 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; 669 670 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator); 671 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator); 672 673 if (is_amic_enabled(component, hpf_work->decimator)) { 674 snd_soc_component_write_field(component, 675 dec_cfg_reg, 676 CDC_TXn_HPF_CUT_FREQ_MASK, 677 hpf_cut_off_freq); 678 snd_soc_component_update_bits(component, hpf_gate_reg, 679 CDC_TXn_HPF_F_CHANGE_MASK | 680 CDC_TXn_HPF_ZERO_GATE_MASK, 681 0x02); 682 snd_soc_component_update_bits(component, hpf_gate_reg, 683 CDC_TXn_HPF_F_CHANGE_MASK | 684 CDC_TXn_HPF_ZERO_GATE_MASK, 685 0x01); 686 } else { 687 snd_soc_component_write_field(component, dec_cfg_reg, 688 CDC_TXn_HPF_CUT_FREQ_MASK, 689 hpf_cut_off_freq); 690 snd_soc_component_write_field(component, hpf_gate_reg, 691 CDC_TXn_HPF_F_CHANGE_MASK, 0x1); 692 /* Minimum 1 clk cycle delay is required as per HW spec */ 693 usleep_range(1000, 1010); 694 snd_soc_component_write_field(component, hpf_gate_reg, 695 CDC_TXn_HPF_F_CHANGE_MASK, 0x0); 696 } 697 } 698 699 static void tx_macro_mute_update_callback(struct work_struct *work) 700 { 701 struct tx_mute_work *tx_mute_dwork; 702 struct snd_soc_component *component; 703 struct tx_macro *tx; 704 struct delayed_work *delayed_work; 705 u8 decimator; 706 707 delayed_work = to_delayed_work(work); 708 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); 709 tx = tx_mute_dwork->tx; 710 component = tx->component; 711 decimator = tx_mute_dwork->decimator; 712 713 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator), 714 CDC_TXn_PGA_MUTE_MASK, 0x0); 715 } 716 717 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, 718 struct snd_kcontrol *kcontrol, int event) 719 { 720 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 721 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 722 723 switch (event) { 724 case SND_SOC_DAPM_PRE_PMU: 725 tx_macro_mclk_enable(tx, true); 726 break; 727 case SND_SOC_DAPM_POST_PMD: 728 tx_macro_mclk_enable(tx, false); 729 break; 730 default: 731 break; 732 } 733 734 return 0; 735 } 736 737 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 738 struct snd_ctl_elem_value *ucontrol) 739 { 740 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 741 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 742 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 743 unsigned int val, dmic; 744 u16 mic_sel_reg; 745 u16 dmic_clk_reg; 746 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 747 748 val = ucontrol->value.enumerated.item[0]; 749 750 switch (e->reg) { 751 case CDC_TX_INP_MUX_ADC_MUX0_CFG0: 752 mic_sel_reg = CDC_TX0_TX_PATH_CFG0; 753 break; 754 case CDC_TX_INP_MUX_ADC_MUX1_CFG0: 755 mic_sel_reg = CDC_TX1_TX_PATH_CFG0; 756 break; 757 case CDC_TX_INP_MUX_ADC_MUX2_CFG0: 758 mic_sel_reg = CDC_TX2_TX_PATH_CFG0; 759 break; 760 case CDC_TX_INP_MUX_ADC_MUX3_CFG0: 761 mic_sel_reg = CDC_TX3_TX_PATH_CFG0; 762 break; 763 case CDC_TX_INP_MUX_ADC_MUX4_CFG0: 764 mic_sel_reg = CDC_TX4_TX_PATH_CFG0; 765 break; 766 case CDC_TX_INP_MUX_ADC_MUX5_CFG0: 767 mic_sel_reg = CDC_TX5_TX_PATH_CFG0; 768 break; 769 case CDC_TX_INP_MUX_ADC_MUX6_CFG0: 770 mic_sel_reg = CDC_TX6_TX_PATH_CFG0; 771 break; 772 case CDC_TX_INP_MUX_ADC_MUX7_CFG0: 773 mic_sel_reg = CDC_TX7_TX_PATH_CFG0; 774 break; 775 } 776 777 if (val != 0) { 778 if (val < 5) { 779 snd_soc_component_write_field(component, mic_sel_reg, 780 CDC_TXn_ADC_DMIC_SEL_MASK, 0); 781 } else { 782 snd_soc_component_write_field(component, mic_sel_reg, 783 CDC_TXn_ADC_DMIC_SEL_MASK, 1); 784 dmic = TX_ADC_TO_DMIC(val); 785 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 786 snd_soc_component_write_field(component, dmic_clk_reg, 787 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 788 tx->dmic_clk_div); 789 } 790 } 791 792 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 793 } 794 795 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 796 struct snd_ctl_elem_value *ucontrol) 797 { 798 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 799 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 800 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 801 u32 dai_id = widget->shift; 802 u32 dec_id = mc->shift; 803 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 804 805 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) 806 ucontrol->value.integer.value[0] = 1; 807 else 808 ucontrol->value.integer.value[0] = 0; 809 810 return 0; 811 } 812 813 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 814 struct snd_ctl_elem_value *ucontrol) 815 { 816 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 817 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 818 struct snd_soc_dapm_update *update = NULL; 819 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; 820 u32 dai_id = widget->shift; 821 u32 dec_id = mc->shift; 822 u32 enable = ucontrol->value.integer.value[0]; 823 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 824 825 if (enable) { 826 set_bit(dec_id, &tx->active_ch_mask[dai_id]); 827 tx->active_ch_cnt[dai_id]++; 828 tx->active_decimator[dai_id] = dec_id; 829 } else { 830 tx->active_ch_cnt[dai_id]--; 831 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); 832 tx->active_decimator[dai_id] = -1; 833 } 834 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 835 836 return 0; 837 } 838 839 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 840 struct snd_kcontrol *kcontrol, int event) 841 { 842 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 843 unsigned int decimator; 844 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg; 845 u8 hpf_cut_off_freq; 846 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; 847 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; 848 u16 adc_mux_reg, adc_reg, adc_n, dmic; 849 u16 dmic_clk_reg; 850 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 851 852 decimator = w->shift; 853 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator); 854 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator); 855 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator); 856 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator); 857 858 switch (event) { 859 case SND_SOC_DAPM_PRE_PMU: 860 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); 861 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { 862 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); 863 adc_n = snd_soc_component_read(component, adc_reg) & 864 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK; 865 if (adc_n >= TX_ADC_MAX) { 866 dmic = TX_ADC_TO_DMIC(adc_n); 867 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); 868 869 snd_soc_component_write_field(component, dmic_clk_reg, 870 CDC_TX_SWR_DMIC_CLK_SEL_MASK, 871 tx->dmic_clk_div); 872 } 873 } 874 snd_soc_component_write_field(component, dec_cfg_reg, 875 CDC_TXn_ADC_MODE_MASK, 876 tx->dec_mode[decimator]); 877 /* Enable TX PGA Mute */ 878 snd_soc_component_write_field(component, tx_vol_ctl_reg, 879 CDC_TXn_PGA_MUTE_MASK, 0x1); 880 break; 881 case SND_SOC_DAPM_POST_PMU: 882 snd_soc_component_write_field(component, tx_vol_ctl_reg, 883 CDC_TXn_CLK_EN_MASK, 0x1); 884 if (!is_amic_enabled(component, decimator)) { 885 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); 886 /* Minimum 1 clk cycle delay is required as per HW spec */ 887 usleep_range(1000, 1010); 888 } 889 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg, 890 CDC_TXn_HPF_CUT_FREQ_MASK); 891 892 tx->tx_hpf_work[decimator].hpf_cut_off_freq = 893 hpf_cut_off_freq; 894 895 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) 896 snd_soc_component_write_field(component, dec_cfg_reg, 897 CDC_TXn_HPF_CUT_FREQ_MASK, 898 CF_MIN_3DB_150HZ); 899 900 if (is_amic_enabled(component, decimator)) { 901 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS; 902 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS; 903 } 904 /* schedule work queue to Remove Mute */ 905 queue_delayed_work(system_freezable_wq, 906 &tx->tx_mute_dwork[decimator].dwork, 907 msecs_to_jiffies(unmute_delay)); 908 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 909 queue_delayed_work(system_freezable_wq, 910 &tx->tx_hpf_work[decimator].dwork, 911 msecs_to_jiffies(hpf_delay)); 912 snd_soc_component_update_bits(component, hpf_gate_reg, 913 CDC_TXn_HPF_F_CHANGE_MASK | 914 CDC_TXn_HPF_ZERO_GATE_MASK, 915 0x02); 916 if (!is_amic_enabled(component, decimator)) 917 snd_soc_component_update_bits(component, hpf_gate_reg, 918 CDC_TXn_HPF_F_CHANGE_MASK | 919 CDC_TXn_HPF_ZERO_GATE_MASK, 920 0x00); 921 snd_soc_component_update_bits(component, hpf_gate_reg, 922 CDC_TXn_HPF_F_CHANGE_MASK | 923 CDC_TXn_HPF_ZERO_GATE_MASK, 924 0x01); 925 926 /* 927 * 6ms delay is required as per HW spec 928 */ 929 usleep_range(6000, 6010); 930 } 931 /* apply gain after decimator is enabled */ 932 snd_soc_component_write(component, tx_gain_ctl_reg, 933 snd_soc_component_read(component, 934 tx_gain_ctl_reg)); 935 if (tx->bcs_enable) { 936 snd_soc_component_update_bits(component, dec_cfg_reg, 937 0x01, 0x01); 938 tx->bcs_clk_en = true; 939 } 940 break; 941 case SND_SOC_DAPM_PRE_PMD: 942 hpf_cut_off_freq = 943 tx->tx_hpf_work[decimator].hpf_cut_off_freq; 944 snd_soc_component_write_field(component, tx_vol_ctl_reg, 945 CDC_TXn_PGA_MUTE_MASK, 0x1); 946 if (cancel_delayed_work_sync( 947 &tx->tx_hpf_work[decimator].dwork)) { 948 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 949 snd_soc_component_write_field( 950 component, dec_cfg_reg, 951 CDC_TXn_HPF_CUT_FREQ_MASK, 952 hpf_cut_off_freq); 953 if (is_amic_enabled(component, decimator)) 954 snd_soc_component_update_bits(component, 955 hpf_gate_reg, 956 CDC_TXn_HPF_F_CHANGE_MASK | 957 CDC_TXn_HPF_ZERO_GATE_MASK, 958 0x02); 959 else 960 snd_soc_component_update_bits(component, 961 hpf_gate_reg, 962 CDC_TXn_HPF_F_CHANGE_MASK | 963 CDC_TXn_HPF_ZERO_GATE_MASK, 964 0x03); 965 966 /* 967 * Minimum 1 clk cycle delay is required 968 * as per HW spec 969 */ 970 usleep_range(1000, 1010); 971 snd_soc_component_update_bits(component, hpf_gate_reg, 972 CDC_TXn_HPF_F_CHANGE_MASK | 973 CDC_TXn_HPF_ZERO_GATE_MASK, 974 0x1); 975 } 976 } 977 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); 978 break; 979 case SND_SOC_DAPM_POST_PMD: 980 snd_soc_component_write_field(component, tx_vol_ctl_reg, 981 CDC_TXn_CLK_EN_MASK, 0x0); 982 snd_soc_component_write_field(component, dec_cfg_reg, 983 CDC_TXn_ADC_MODE_MASK, 0x0); 984 snd_soc_component_write_field(component, tx_vol_ctl_reg, 985 CDC_TXn_PGA_MUTE_MASK, 0x0); 986 if (tx->bcs_enable) { 987 snd_soc_component_write_field(component, dec_cfg_reg, 988 CDC_TXn_PH_EN_MASK, 0x0); 989 snd_soc_component_write_field(component, 990 CDC_TX0_TX_PATH_SEC7, 991 CDC_TX0_MBHC_CTL_EN_MASK, 992 0x0); 993 tx->bcs_clk_en = false; 994 } 995 break; 996 } 997 return 0; 998 } 999 1000 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 1001 struct snd_ctl_elem_value *ucontrol) 1002 { 1003 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1004 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1005 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1006 int path = e->shift_l; 1007 1008 ucontrol->value.integer.value[0] = tx->dec_mode[path]; 1009 1010 return 0; 1011 } 1012 1013 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 1014 struct snd_ctl_elem_value *ucontrol) 1015 { 1016 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1017 int value = ucontrol->value.integer.value[0]; 1018 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1019 int path = e->shift_l; 1020 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1021 1022 tx->dec_mode[path] = value; 1023 1024 return 0; 1025 } 1026 1027 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol, 1028 struct snd_ctl_elem_value *ucontrol) 1029 { 1030 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1031 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1032 1033 ucontrol->value.integer.value[0] = tx->bcs_enable; 1034 1035 return 0; 1036 } 1037 1038 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol, 1039 struct snd_ctl_elem_value *ucontrol) 1040 { 1041 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1042 int value = ucontrol->value.integer.value[0]; 1043 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1044 1045 tx->bcs_enable = value; 1046 1047 return 0; 1048 } 1049 1050 static int tx_macro_hw_params(struct snd_pcm_substream *substream, 1051 struct snd_pcm_hw_params *params, 1052 struct snd_soc_dai *dai) 1053 { 1054 struct snd_soc_component *component = dai->component; 1055 u32 decimator, sample_rate; 1056 int tx_fs_rate; 1057 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1058 1059 sample_rate = params_rate(params); 1060 switch (sample_rate) { 1061 case 8000: 1062 tx_fs_rate = 0; 1063 break; 1064 case 16000: 1065 tx_fs_rate = 1; 1066 break; 1067 case 32000: 1068 tx_fs_rate = 3; 1069 break; 1070 case 48000: 1071 tx_fs_rate = 4; 1072 break; 1073 case 96000: 1074 tx_fs_rate = 5; 1075 break; 1076 case 192000: 1077 tx_fs_rate = 6; 1078 break; 1079 case 384000: 1080 tx_fs_rate = 7; 1081 break; 1082 default: 1083 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", 1084 __func__, params_rate(params)); 1085 return -EINVAL; 1086 } 1087 1088 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) 1089 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator), 1090 CDC_TXn_PCM_RATE_MASK, 1091 tx_fs_rate); 1092 return 0; 1093 } 1094 1095 static int tx_macro_get_channel_map(struct snd_soc_dai *dai, 1096 unsigned int *tx_num, unsigned int *tx_slot, 1097 unsigned int *rx_num, unsigned int *rx_slot) 1098 { 1099 struct snd_soc_component *component = dai->component; 1100 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1101 1102 switch (dai->id) { 1103 case TX_MACRO_AIF1_CAP: 1104 case TX_MACRO_AIF2_CAP: 1105 case TX_MACRO_AIF3_CAP: 1106 *tx_slot = tx->active_ch_mask[dai->id]; 1107 *tx_num = tx->active_ch_cnt[dai->id]; 1108 break; 1109 default: 1110 break; 1111 } 1112 return 0; 1113 } 1114 1115 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1116 { 1117 struct snd_soc_component *component = dai->component; 1118 struct tx_macro *tx = snd_soc_component_get_drvdata(component); 1119 u16 decimator; 1120 1121 decimator = tx->active_decimator[dai->id]; 1122 1123 if (mute) 1124 snd_soc_component_write_field(component, 1125 CDC_TXn_TX_PATH_CTL(decimator), 1126 CDC_TXn_PGA_MUTE_MASK, 0x1); 1127 else 1128 snd_soc_component_update_bits(component, 1129 CDC_TXn_TX_PATH_CTL(decimator), 1130 CDC_TXn_PGA_MUTE_MASK, 0x0); 1131 1132 return 0; 1133 } 1134 1135 static const struct snd_soc_dai_ops tx_macro_dai_ops = { 1136 .hw_params = tx_macro_hw_params, 1137 .get_channel_map = tx_macro_get_channel_map, 1138 .mute_stream = tx_macro_digital_mute, 1139 }; 1140 1141 static struct snd_soc_dai_driver tx_macro_dai[] = { 1142 { 1143 .name = "tx_macro_tx1", 1144 .id = TX_MACRO_AIF1_CAP, 1145 .capture = { 1146 .stream_name = "TX_AIF1 Capture", 1147 .rates = TX_MACRO_RATES, 1148 .formats = TX_MACRO_FORMATS, 1149 .rate_max = 192000, 1150 .rate_min = 8000, 1151 .channels_min = 1, 1152 .channels_max = 8, 1153 }, 1154 .ops = &tx_macro_dai_ops, 1155 }, 1156 { 1157 .name = "tx_macro_tx2", 1158 .id = TX_MACRO_AIF2_CAP, 1159 .capture = { 1160 .stream_name = "TX_AIF2 Capture", 1161 .rates = TX_MACRO_RATES, 1162 .formats = TX_MACRO_FORMATS, 1163 .rate_max = 192000, 1164 .rate_min = 8000, 1165 .channels_min = 1, 1166 .channels_max = 8, 1167 }, 1168 .ops = &tx_macro_dai_ops, 1169 }, 1170 { 1171 .name = "tx_macro_tx3", 1172 .id = TX_MACRO_AIF3_CAP, 1173 .capture = { 1174 .stream_name = "TX_AIF3 Capture", 1175 .rates = TX_MACRO_RATES, 1176 .formats = TX_MACRO_FORMATS, 1177 .rate_max = 192000, 1178 .rate_min = 8000, 1179 .channels_min = 1, 1180 .channels_max = 8, 1181 }, 1182 .ops = &tx_macro_dai_ops, 1183 }, 1184 }; 1185 1186 static const char * const adc_mux_text[] = { 1187 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" 1188 }; 1189 1190 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, 1191 0, adc_mux_text); 1192 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, 1193 0, adc_mux_text); 1194 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, 1195 0, adc_mux_text); 1196 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, 1197 0, adc_mux_text); 1198 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, 1199 0, adc_mux_text); 1200 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, 1201 0, adc_mux_text); 1202 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, 1203 0, adc_mux_text); 1204 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, 1205 0, adc_mux_text); 1206 1207 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum); 1208 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum); 1209 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum); 1210 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum); 1211 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum); 1212 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum); 1213 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum); 1214 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum); 1215 1216 static const char * const smic_mux_text[] = { 1217 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", 1218 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", 1219 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" 1220 }; 1221 1222 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0, 1223 0, smic_mux_text); 1224 1225 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0, 1226 0, smic_mux_text); 1227 1228 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0, 1229 0, smic_mux_text); 1230 1231 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0, 1232 0, smic_mux_text); 1233 1234 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0, 1235 0, smic_mux_text); 1236 1237 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0, 1238 0, smic_mux_text); 1239 1240 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0, 1241 0, smic_mux_text); 1242 1243 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0, 1244 0, smic_mux_text); 1245 1246 static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum, 1247 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1248 static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum, 1249 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1250 static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum, 1251 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1252 static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum, 1253 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1254 static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum, 1255 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1256 static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum, 1257 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1258 static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum, 1259 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1260 static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum, 1261 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); 1262 1263 static const char * const dec_mode_mux_text[] = { 1264 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1265 }; 1266 1267 static const struct soc_enum dec_mode_mux_enum[] = { 1268 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1269 dec_mode_mux_text), 1270 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1271 dec_mode_mux_text), 1272 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1273 dec_mode_mux_text), 1274 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1275 dec_mode_mux_text), 1276 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text), 1277 dec_mode_mux_text), 1278 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text), 1279 dec_mode_mux_text), 1280 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text), 1281 dec_mode_mux_text), 1282 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text), 1283 dec_mode_mux_text), 1284 }; 1285 1286 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { 1287 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1288 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1289 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1290 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1291 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1292 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1293 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1294 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1295 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1296 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1297 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1298 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1299 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1300 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1301 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1302 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1303 }; 1304 1305 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { 1306 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1307 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1308 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1309 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1310 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1311 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1312 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1313 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1314 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1315 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1316 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1317 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1318 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1319 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1320 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1321 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1322 }; 1323 1324 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { 1325 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, 1326 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1327 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, 1328 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1329 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, 1330 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1331 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, 1332 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1333 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, 1334 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1335 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, 1336 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1337 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, 1338 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1339 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, 1340 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), 1341 }; 1342 1343 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { 1344 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, 1345 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), 1346 1347 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, 1348 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), 1349 1350 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, 1351 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), 1352 1353 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, 1354 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), 1355 1356 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, 1357 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), 1358 1359 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0, 1360 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), 1361 1362 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux), 1363 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux), 1364 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux), 1365 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux), 1366 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux), 1367 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux), 1368 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux), 1369 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux), 1370 1371 SND_SOC_DAPM_INPUT("TX SWR_ADC0"), 1372 SND_SOC_DAPM_INPUT("TX SWR_ADC1"), 1373 SND_SOC_DAPM_INPUT("TX SWR_ADC2"), 1374 SND_SOC_DAPM_INPUT("TX SWR_ADC3"), 1375 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), 1376 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), 1377 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), 1378 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), 1379 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), 1380 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), 1381 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), 1382 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), 1383 1384 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, 1385 TX_MACRO_DEC0, 0, 1386 &tx_dec0_mux, tx_macro_enable_dec, 1387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1388 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1389 1390 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, 1391 TX_MACRO_DEC1, 0, 1392 &tx_dec1_mux, tx_macro_enable_dec, 1393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1394 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1395 1396 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, 1397 TX_MACRO_DEC2, 0, 1398 &tx_dec2_mux, tx_macro_enable_dec, 1399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1400 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1401 1402 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, 1403 TX_MACRO_DEC3, 0, 1404 &tx_dec3_mux, tx_macro_enable_dec, 1405 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1406 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1407 1408 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, 1409 TX_MACRO_DEC4, 0, 1410 &tx_dec4_mux, tx_macro_enable_dec, 1411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1412 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1413 1414 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, 1415 TX_MACRO_DEC5, 0, 1416 &tx_dec5_mux, tx_macro_enable_dec, 1417 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1418 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1419 1420 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, 1421 TX_MACRO_DEC6, 0, 1422 &tx_dec6_mux, tx_macro_enable_dec, 1423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1424 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1425 1426 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, 1427 TX_MACRO_DEC7, 0, 1428 &tx_dec7_mux, tx_macro_enable_dec, 1429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1430 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1431 1432 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, 1433 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1434 1435 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), 1436 1437 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, 1438 NULL, 0), 1439 }; 1440 1441 static const struct snd_soc_dapm_route tx_audio_map[] = { 1442 {"TX_AIF1 CAP", NULL, "TX_MCLK"}, 1443 {"TX_AIF2 CAP", NULL, "TX_MCLK"}, 1444 {"TX_AIF3 CAP", NULL, "TX_MCLK"}, 1445 1446 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, 1447 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, 1448 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, 1449 1450 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1451 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1452 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1453 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1454 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1455 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1456 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1457 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1458 1459 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1460 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1461 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1462 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1463 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1464 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1465 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1466 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1467 1468 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, 1469 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, 1470 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, 1471 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, 1472 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, 1473 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, 1474 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, 1475 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, 1476 1477 {"TX DEC0 MUX", NULL, "TX_MCLK"}, 1478 {"TX DEC1 MUX", NULL, "TX_MCLK"}, 1479 {"TX DEC2 MUX", NULL, "TX_MCLK"}, 1480 {"TX DEC3 MUX", NULL, "TX_MCLK"}, 1481 {"TX DEC4 MUX", NULL, "TX_MCLK"}, 1482 {"TX DEC5 MUX", NULL, "TX_MCLK"}, 1483 {"TX DEC6 MUX", NULL, "TX_MCLK"}, 1484 {"TX DEC7 MUX", NULL, "TX_MCLK"}, 1485 1486 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, 1487 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, 1488 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, 1489 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, 1490 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, 1491 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, 1492 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, 1493 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, 1494 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, 1495 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, 1496 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, 1497 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, 1498 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, 1499 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, 1500 1501 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, 1502 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, 1503 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, 1504 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, 1505 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, 1506 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, 1507 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, 1508 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, 1509 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, 1510 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, 1511 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, 1512 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, 1513 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, 1514 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, 1515 1516 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, 1517 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, 1518 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, 1519 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, 1520 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, 1521 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, 1522 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, 1523 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, 1524 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, 1525 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, 1526 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, 1527 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, 1528 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, 1529 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, 1530 1531 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, 1532 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, 1533 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, 1534 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, 1535 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, 1536 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, 1537 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, 1538 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, 1539 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, 1540 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, 1541 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, 1542 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, 1543 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, 1544 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, 1545 1546 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, 1547 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, 1548 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, 1549 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, 1550 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, 1551 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, 1552 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, 1553 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, 1554 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, 1555 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, 1556 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, 1557 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, 1558 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, 1559 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, 1560 1561 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, 1562 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, 1563 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, 1564 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, 1565 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, 1566 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, 1567 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, 1568 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, 1569 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, 1570 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, 1571 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, 1572 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, 1573 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, 1574 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, 1575 1576 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, 1577 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, 1578 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, 1579 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, 1580 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, 1581 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, 1582 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, 1583 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, 1584 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, 1585 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, 1586 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, 1587 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, 1588 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, 1589 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, 1590 1591 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, 1592 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, 1593 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, 1594 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, 1595 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, 1596 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, 1597 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, 1598 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, 1599 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, 1600 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, 1601 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, 1602 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, 1603 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, 1604 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, 1605 }; 1606 1607 static const struct snd_kcontrol_new tx_macro_snd_controls[] = { 1608 SOC_SINGLE_S8_TLV("TX_DEC0 Volume", 1609 CDC_TX0_TX_VOL_CTL, 1610 -84, 40, digital_gain), 1611 SOC_SINGLE_S8_TLV("TX_DEC1 Volume", 1612 CDC_TX1_TX_VOL_CTL, 1613 -84, 40, digital_gain), 1614 SOC_SINGLE_S8_TLV("TX_DEC2 Volume", 1615 CDC_TX2_TX_VOL_CTL, 1616 -84, 40, digital_gain), 1617 SOC_SINGLE_S8_TLV("TX_DEC3 Volume", 1618 CDC_TX3_TX_VOL_CTL, 1619 -84, 40, digital_gain), 1620 SOC_SINGLE_S8_TLV("TX_DEC4 Volume", 1621 CDC_TX4_TX_VOL_CTL, 1622 -84, 40, digital_gain), 1623 SOC_SINGLE_S8_TLV("TX_DEC5 Volume", 1624 CDC_TX5_TX_VOL_CTL, 1625 -84, 40, digital_gain), 1626 SOC_SINGLE_S8_TLV("TX_DEC6 Volume", 1627 CDC_TX6_TX_VOL_CTL, 1628 -84, 40, digital_gain), 1629 SOC_SINGLE_S8_TLV("TX_DEC7 Volume", 1630 CDC_TX7_TX_VOL_CTL, 1631 -84, 40, digital_gain), 1632 1633 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0], 1634 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1635 1636 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1], 1637 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1638 1639 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2], 1640 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1641 1642 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3], 1643 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1644 1645 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4], 1646 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1647 1648 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5], 1649 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1650 1651 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6], 1652 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1653 1654 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7], 1655 tx_macro_dec_mode_get, tx_macro_dec_mode_put), 1656 1657 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, 1658 tx_macro_get_bcs, tx_macro_set_bcs), 1659 }; 1660 1661 static int tx_macro_component_probe(struct snd_soc_component *comp) 1662 { 1663 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); 1664 int i; 1665 1666 snd_soc_component_init_regmap(comp, tx->regmap); 1667 1668 for (i = 0; i < NUM_DECIMATORS; i++) { 1669 tx->tx_hpf_work[i].tx = tx; 1670 tx->tx_hpf_work[i].decimator = i; 1671 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, 1672 tx_macro_tx_hpf_corner_freq_callback); 1673 } 1674 1675 for (i = 0; i < NUM_DECIMATORS; i++) { 1676 tx->tx_mute_dwork[i].tx = tx; 1677 tx->tx_mute_dwork[i].decimator = i; 1678 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, 1679 tx_macro_mute_update_callback); 1680 } 1681 tx->component = comp; 1682 1683 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, 1684 0x0A); 1685 /* Enable swr mic0 and mic1 clock */ 1686 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00); 1687 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00); 1688 1689 return 0; 1690 } 1691 1692 static int swclk_gate_enable(struct clk_hw *hw) 1693 { 1694 struct tx_macro *tx = to_tx_macro(hw); 1695 struct regmap *regmap = tx->regmap; 1696 int ret; 1697 1698 ret = clk_prepare_enable(tx->mclk); 1699 if (ret) { 1700 dev_err(tx->dev, "failed to enable mclk\n"); 1701 return ret; 1702 } 1703 1704 tx_macro_mclk_enable(tx, true); 1705 if (tx->reset_swr) 1706 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1707 CDC_TX_SWR_RESET_MASK, 1708 CDC_TX_SWR_RESET_ENABLE); 1709 1710 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1711 CDC_TX_SWR_CLK_EN_MASK, 1712 CDC_TX_SWR_CLK_ENABLE); 1713 if (tx->reset_swr) 1714 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1715 CDC_TX_SWR_RESET_MASK, 0x0); 1716 tx->reset_swr = false; 1717 1718 return 0; 1719 } 1720 1721 static void swclk_gate_disable(struct clk_hw *hw) 1722 { 1723 struct tx_macro *tx = to_tx_macro(hw); 1724 struct regmap *regmap = tx->regmap; 1725 1726 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 1727 CDC_TX_SWR_CLK_EN_MASK, 0x0); 1728 1729 tx_macro_mclk_enable(tx, false); 1730 clk_disable_unprepare(tx->mclk); 1731 } 1732 1733 static int swclk_gate_is_enabled(struct clk_hw *hw) 1734 { 1735 struct tx_macro *tx = to_tx_macro(hw); 1736 int ret, val; 1737 1738 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); 1739 ret = val & BIT(0); 1740 1741 return ret; 1742 } 1743 1744 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 1745 unsigned long parent_rate) 1746 { 1747 return parent_rate / 2; 1748 } 1749 1750 static const struct clk_ops swclk_gate_ops = { 1751 .prepare = swclk_gate_enable, 1752 .unprepare = swclk_gate_disable, 1753 .is_enabled = swclk_gate_is_enabled, 1754 .recalc_rate = swclk_recalc_rate, 1755 1756 }; 1757 1758 static int tx_macro_register_mclk_output(struct tx_macro *tx) 1759 { 1760 struct device *dev = tx->dev; 1761 const char *parent_clk_name = NULL; 1762 const char *clk_name = "lpass-tx-mclk"; 1763 struct clk_hw *hw; 1764 struct clk_init_data init; 1765 int ret; 1766 1767 parent_clk_name = __clk_get_name(tx->npl); 1768 1769 init.name = clk_name; 1770 init.ops = &swclk_gate_ops; 1771 init.flags = 0; 1772 init.parent_names = &parent_clk_name; 1773 init.num_parents = 1; 1774 tx->hw.init = &init; 1775 hw = &tx->hw; 1776 ret = devm_clk_hw_register(dev, hw); 1777 if (ret) 1778 return ret; 1779 1780 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 1781 } 1782 1783 static const struct snd_soc_component_driver tx_macro_component_drv = { 1784 .name = "RX-MACRO", 1785 .probe = tx_macro_component_probe, 1786 .controls = tx_macro_snd_controls, 1787 .num_controls = ARRAY_SIZE(tx_macro_snd_controls), 1788 .dapm_widgets = tx_macro_dapm_widgets, 1789 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets), 1790 .dapm_routes = tx_audio_map, 1791 .num_dapm_routes = ARRAY_SIZE(tx_audio_map), 1792 }; 1793 1794 static int tx_macro_probe(struct platform_device *pdev) 1795 { 1796 struct device *dev = &pdev->dev; 1797 struct device_node *np = dev->of_node; 1798 struct tx_macro *tx; 1799 void __iomem *base; 1800 int ret, reg; 1801 1802 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); 1803 if (!tx) 1804 return -ENOMEM; 1805 1806 tx->macro = devm_clk_get_optional(dev, "macro"); 1807 if (IS_ERR(tx->macro)) 1808 return PTR_ERR(tx->macro); 1809 1810 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); 1811 if (IS_ERR(tx->dcodec)) 1812 return PTR_ERR(tx->dcodec); 1813 1814 tx->mclk = devm_clk_get(dev, "mclk"); 1815 if (IS_ERR(tx->mclk)) 1816 return PTR_ERR(tx->mclk); 1817 1818 tx->npl = devm_clk_get(dev, "npl"); 1819 if (IS_ERR(tx->npl)) 1820 return PTR_ERR(tx->npl); 1821 1822 tx->fsgen = devm_clk_get(dev, "fsgen"); 1823 if (IS_ERR(tx->fsgen)) 1824 return PTR_ERR(tx->fsgen); 1825 1826 tx->pds = lpass_macro_pds_init(dev); 1827 if (IS_ERR(tx->pds)) 1828 return PTR_ERR(tx->pds); 1829 1830 base = devm_platform_ioremap_resource(pdev, 0); 1831 if (IS_ERR(base)) { 1832 ret = PTR_ERR(base); 1833 goto err; 1834 } 1835 1836 /* Update defaults for lpass sc7280 */ 1837 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { 1838 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) { 1839 switch (tx_defaults[reg].reg) { 1840 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL: 1841 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL: 1842 tx_defaults[reg].def = 0x0E; 1843 break; 1844 default: 1845 break; 1846 } 1847 } 1848 } 1849 1850 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); 1851 if (IS_ERR(tx->regmap)) { 1852 ret = PTR_ERR(tx->regmap); 1853 goto err; 1854 } 1855 1856 dev_set_drvdata(dev, tx); 1857 1858 tx->reset_swr = true; 1859 tx->dev = dev; 1860 1861 /* set MCLK and NPL rates */ 1862 clk_set_rate(tx->mclk, MCLK_FREQ); 1863 clk_set_rate(tx->npl, 2 * MCLK_FREQ); 1864 1865 ret = clk_prepare_enable(tx->macro); 1866 if (ret) 1867 goto err; 1868 1869 ret = clk_prepare_enable(tx->dcodec); 1870 if (ret) 1871 goto err_dcodec; 1872 1873 ret = clk_prepare_enable(tx->mclk); 1874 if (ret) 1875 goto err_mclk; 1876 1877 ret = clk_prepare_enable(tx->npl); 1878 if (ret) 1879 goto err_npl; 1880 1881 ret = clk_prepare_enable(tx->fsgen); 1882 if (ret) 1883 goto err_fsgen; 1884 1885 ret = tx_macro_register_mclk_output(tx); 1886 if (ret) 1887 goto err_clkout; 1888 1889 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv, 1890 tx_macro_dai, 1891 ARRAY_SIZE(tx_macro_dai)); 1892 if (ret) 1893 goto err_clkout; 1894 1895 pm_runtime_set_autosuspend_delay(dev, 3000); 1896 pm_runtime_use_autosuspend(dev); 1897 pm_runtime_mark_last_busy(dev); 1898 pm_runtime_set_active(dev); 1899 pm_runtime_enable(dev); 1900 1901 return 0; 1902 1903 err_clkout: 1904 clk_disable_unprepare(tx->fsgen); 1905 err_fsgen: 1906 clk_disable_unprepare(tx->npl); 1907 err_npl: 1908 clk_disable_unprepare(tx->mclk); 1909 err_mclk: 1910 clk_disable_unprepare(tx->dcodec); 1911 err_dcodec: 1912 clk_disable_unprepare(tx->macro); 1913 err: 1914 lpass_macro_pds_exit(tx->pds); 1915 1916 return ret; 1917 } 1918 1919 static int tx_macro_remove(struct platform_device *pdev) 1920 { 1921 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); 1922 1923 clk_disable_unprepare(tx->macro); 1924 clk_disable_unprepare(tx->dcodec); 1925 clk_disable_unprepare(tx->mclk); 1926 clk_disable_unprepare(tx->npl); 1927 clk_disable_unprepare(tx->fsgen); 1928 1929 lpass_macro_pds_exit(tx->pds); 1930 1931 return 0; 1932 } 1933 1934 static int __maybe_unused tx_macro_runtime_suspend(struct device *dev) 1935 { 1936 struct tx_macro *tx = dev_get_drvdata(dev); 1937 1938 regcache_cache_only(tx->regmap, true); 1939 regcache_mark_dirty(tx->regmap); 1940 1941 clk_disable_unprepare(tx->mclk); 1942 clk_disable_unprepare(tx->npl); 1943 clk_disable_unprepare(tx->fsgen); 1944 1945 return 0; 1946 } 1947 1948 static int __maybe_unused tx_macro_runtime_resume(struct device *dev) 1949 { 1950 struct tx_macro *tx = dev_get_drvdata(dev); 1951 int ret; 1952 1953 ret = clk_prepare_enable(tx->mclk); 1954 if (ret) { 1955 dev_err(dev, "unable to prepare mclk\n"); 1956 return ret; 1957 } 1958 1959 ret = clk_prepare_enable(tx->npl); 1960 if (ret) { 1961 dev_err(dev, "unable to prepare npl\n"); 1962 goto err_npl; 1963 } 1964 1965 ret = clk_prepare_enable(tx->fsgen); 1966 if (ret) { 1967 dev_err(dev, "unable to prepare fsgen\n"); 1968 goto err_fsgen; 1969 } 1970 1971 regcache_cache_only(tx->regmap, false); 1972 regcache_sync(tx->regmap); 1973 tx->reset_swr = true; 1974 1975 return 0; 1976 err_fsgen: 1977 clk_disable_unprepare(tx->npl); 1978 err_npl: 1979 clk_disable_unprepare(tx->mclk); 1980 1981 return ret; 1982 } 1983 1984 static const struct dev_pm_ops tx_macro_pm_ops = { 1985 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL) 1986 }; 1987 1988 static const struct of_device_id tx_macro_dt_match[] = { 1989 { .compatible = "qcom,sc7280-lpass-tx-macro" }, 1990 { .compatible = "qcom,sm8250-lpass-tx-macro" }, 1991 { } 1992 }; 1993 MODULE_DEVICE_TABLE(of, tx_macro_dt_match); 1994 static struct platform_driver tx_macro_driver = { 1995 .driver = { 1996 .name = "tx_macro", 1997 .of_match_table = tx_macro_dt_match, 1998 .suppress_bind_attrs = true, 1999 .pm = &tx_macro_pm_ops, 2000 }, 2001 .probe = tx_macro_probe, 2002 .remove = tx_macro_remove, 2003 }; 2004 2005 module_platform_driver(tx_macro_driver); 2006 2007 MODULE_DESCRIPTION("TX macro driver"); 2008 MODULE_LICENSE("GPL"); 2009