1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/platform_device.h> 8 #include <linux/clk.h> 9 #include <sound/soc.h> 10 #include <sound/pcm.h> 11 #include <sound/pcm_params.h> 12 #include <sound/soc-dapm.h> 13 #include <sound/tlv.h> 14 #include <linux/of_clk.h> 15 #include <linux/clk-provider.h> 16 17 #define CDC_RX_TOP_TOP_CFG0 (0x0000) 18 #define CDC_RX_TOP_SWR_CTRL (0x0008) 19 #define CDC_RX_TOP_DEBUG (0x000C) 20 #define CDC_RX_TOP_DEBUG_BUS (0x0010) 21 #define CDC_RX_TOP_DEBUG_EN0 (0x0014) 22 #define CDC_RX_TOP_DEBUG_EN1 (0x0018) 23 #define CDC_RX_TOP_DEBUG_EN2 (0x001C) 24 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020) 25 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024) 26 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028) 27 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7) 28 #define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C) 29 #define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030) 30 #define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034) 31 #define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038) 32 #define CDC_RX_TOP_HPHR_COMP_LUT (0x003C) 33 #define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040) 34 #define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044) 35 #define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070) 36 #define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074) 37 #define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078) 38 #define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C) 39 #define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080) 40 #define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084) 41 #define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088) 42 #define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C) 43 #define CDC_RX_TOP_RX_I2S_CTL (0x0090) 44 #define CDC_RX_TOP_TX_I2S2_CTL (0x0094) 45 #define CDC_RX_TOP_I2S_CLK (0x0098) 46 #define CDC_RX_TOP_I2S_RESET (0x009C) 47 #define CDC_RX_TOP_I2S_MUX (0x00A0) 48 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100) 49 #define CDC_RX_CLK_MCLK_EN_MASK BIT(0) 50 #define CDC_RX_CLK_MCLK_ENABLE BIT(0) 51 #define CDC_RX_CLK_MCLK2_EN_MASK BIT(1) 52 #define CDC_RX_CLK_MCLK2_ENABLE BIT(1) 53 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104) 54 #define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0) 55 #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0) 56 #define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1) 57 #define CDC_RX_FS_MCLK_CNT_CLR BIT(1) 58 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108) 59 #define CDC_RX_SWR_CLK_EN_MASK BIT(0) 60 #define CDC_RX_SWR_RESET_MASK BIT(1) 61 #define CDC_RX_SWR_RESET BIT(1) 62 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C) 63 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110) 64 #define CDC_RX_SOFTCLIP_CRC (0x0140) 65 #define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0) 66 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144) 67 #define CDC_RX_SOFTCLIP_EN_MASK BIT(0) 68 #define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180) 69 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0) 70 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4) 71 #define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184) 72 #define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0) 73 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4) 74 #define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188) 75 #define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C) 76 #define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190) 77 #define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194) 78 #define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198) 79 #define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C) 80 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0) 81 #define CDC_RX_CLSH_CRC (0x0200) 82 #define CDC_RX_CLSH_CLK_EN_MASK BIT(0) 83 #define CDC_RX_CLSH_DLY_CTRL (0x0204) 84 #define CDC_RX_CLSH_DECAY_CTRL (0x0208) 85 #define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0) 86 #define CDC_RX_CLSH_HPH_V_PA (0x020C) 87 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0) 88 #define CDC_RX_CLSH_EAR_V_PA (0x0210) 89 #define CDC_RX_CLSH_HPH_V_HD (0x0214) 90 #define CDC_RX_CLSH_EAR_V_HD (0x0218) 91 #define CDC_RX_CLSH_K1_MSB (0x021C) 92 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0) 93 #define CDC_RX_CLSH_K1_LSB (0x0220) 94 #define CDC_RX_CLSH_K2_MSB (0x0224) 95 #define CDC_RX_CLSH_K2_LSB (0x0228) 96 #define CDC_RX_CLSH_IDLE_CTRL (0x022C) 97 #define CDC_RX_CLSH_IDLE_HPH (0x0230) 98 #define CDC_RX_CLSH_IDLE_EAR (0x0234) 99 #define CDC_RX_CLSH_TEST0 (0x0238) 100 #define CDC_RX_CLSH_TEST1 (0x023C) 101 #define CDC_RX_CLSH_OVR_VREF (0x0240) 102 #define CDC_RX_CLSH_CLSG_CTL (0x0244) 103 #define CDC_RX_CLSH_CLSG_CFG1 (0x0248) 104 #define CDC_RX_CLSH_CLSG_CFG2 (0x024C) 105 #define CDC_RX_BCL_VBAT_PATH_CTL (0x0280) 106 #define CDC_RX_BCL_VBAT_CFG (0x0284) 107 #define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288) 108 #define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C) 109 #define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290) 110 #define CDC_RX_BCL_VBAT_PK_EST1 (0x0294) 111 #define CDC_RX_BCL_VBAT_PK_EST2 (0x0298) 112 #define CDC_RX_BCL_VBAT_PK_EST3 (0x029C) 113 #define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0) 114 #define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4) 115 #define CDC_RX_BCL_VBAT_TAC1 (0x02A8) 116 #define CDC_RX_BCL_VBAT_TAC2 (0x02AC) 117 #define CDC_RX_BCL_VBAT_TAC3 (0x02B0) 118 #define CDC_RX_BCL_VBAT_TAC4 (0x02B4) 119 #define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8) 120 #define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC) 121 #define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0) 122 #define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4) 123 #define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8) 124 #define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC) 125 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0) 126 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4) 127 #define CDC_RX_BCL_VBAT_BAN (0x02D8) 128 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC) 129 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0) 130 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4) 131 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8) 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC) 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0) 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4) 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8) 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC) 137 #define CDC_RX_BCL_VBAT_ATTN1 (0x0300) 138 #define CDC_RX_BCL_VBAT_ATTN2 (0x0304) 139 #define CDC_RX_BCL_VBAT_ATTN3 (0x0308) 140 #define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C) 141 #define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310) 142 #define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314) 143 #define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318) 144 #define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C) 145 #define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320) 146 #define CDC_RX_BCL_VBAT_DECODE_ST (0x0324) 147 #define CDC_RX_INTR_CTRL_CFG (0x0340) 148 #define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344) 149 #define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360) 150 #define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368) 151 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370) 152 #define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380) 153 #define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388) 154 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390) 155 #define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0) 156 #define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8) 157 #define CDC_RX_INTR_CTRL_SET0 (0x03D0) 158 #define CDC_RX_RXn_RX_PATH_CTL(n) (0x0400 + 0x80 * n) 159 #define CDC_RX_RX0_RX_PATH_CTL (0x0400) 160 #define CDC_RX_PATH_RESET_EN_MASK BIT(6) 161 #define CDC_RX_PATH_CLK_EN_MASK BIT(5) 162 #define CDC_RX_PATH_CLK_ENABLE BIT(5) 163 #define CDC_RX_PATH_PGA_MUTE_MASK BIT(4) 164 #define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4) 165 #define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0) 166 #define CDC_RX_RXn_RX_PATH_CFG0(n) (0x0404 + 0x80 * n) 167 #define CDC_RX_RXn_COMP_EN_MASK BIT(1) 168 #define CDC_RX_RX0_RX_PATH_CFG0 (0x0404) 169 #define CDC_RX_RXn_CLSH_EN_MASK BIT(6) 170 #define CDC_RX_DLY_ZN_EN_MASK BIT(3) 171 #define CDC_RX_DLY_ZN_ENABLE BIT(3) 172 #define CDC_RX_RXn_HD2_EN_MASK BIT(2) 173 #define CDC_RX_RXn_RX_PATH_CFG1(n) (0x0408 + 0x80 * n) 174 #define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4) 175 #define CDC_RX_RX0_RX_PATH_CFG1 (0x0408) 176 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1) 177 #define CDC_RX_RXn_RX_PATH_CFG2(n) (0x040C + 0x80 * n) 178 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0) 179 #define CDC_RX_RX0_RX_PATH_CFG2 (0x040C) 180 #define CDC_RX_RXn_RX_PATH_CFG3(n) (0x0410 + 0x80 * n) 181 #define CDC_RX_RX0_RX_PATH_CFG3 (0x0410) 182 #define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0) 183 #define CDC_RX_DC_COEFF_SEL_TWO 0x2 184 #define CDC_RX_RXn_RX_VOL_CTL(n) (0x0414 + 0x80 * n) 185 #define CDC_RX_RX0_RX_VOL_CTL (0x0414) 186 #define CDC_RX_RXn_RX_PATH_MIX_CTL(n) (0x0418 + 0x80 * n) 187 #define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0) 188 #define CDC_RX_RXn_MIX_RESET_MASK BIT(6) 189 #define CDC_RX_RXn_MIX_RESET BIT(6) 190 #define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5) 191 #define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418) 192 #define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C) 193 #define CDC_RX_RXn_RX_VOL_MIX_CTL(n) (0x0420 + 0x80 * n) 194 #define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420) 195 #define CDC_RX_RX0_RX_PATH_SEC1 (0x0424) 196 #define CDC_RX_RX0_RX_PATH_SEC2 (0x0428) 197 #define CDC_RX_RX0_RX_PATH_SEC3 (0x042C) 198 #define CDC_RX_RX0_RX_PATH_SEC4 (0x0430) 199 #define CDC_RX_RX0_RX_PATH_SEC7 (0x0434) 200 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0) 201 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2 202 #define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438) 203 #define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C) 204 #define CDC_RX_RXn_RX_PATH_DSM_CTL(n) (0x0440 + 0x80 * n) 205 #define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0) 206 #define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440) 207 #define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444) 208 #define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448) 209 #define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C) 210 #define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450) 211 #define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454) 212 #define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458) 213 #define CDC_RX_RX1_RX_PATH_CTL (0x0480) 214 #define CDC_RX_RX1_RX_PATH_CFG0 (0x0484) 215 #define CDC_RX_RX1_RX_PATH_CFG1 (0x0488) 216 #define CDC_RX_RX1_RX_PATH_CFG2 (0x048C) 217 #define CDC_RX_RX1_RX_PATH_CFG3 (0x0490) 218 #define CDC_RX_RX1_RX_VOL_CTL (0x0494) 219 #define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498) 220 #define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C) 221 #define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0) 222 #define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4) 223 #define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8) 224 #define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC) 225 #define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2) 226 #define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0) 227 #define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4) 228 #define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8) 229 #define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC) 230 #define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0) 231 #define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4) 232 #define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8) 233 #define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC) 234 #define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0) 235 #define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4) 236 #define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8) 237 #define CDC_RX_RX2_RX_PATH_CTL (0x0500) 238 #define CDC_RX_RX2_RX_PATH_CFG0 (0x0504) 239 #define CDC_RX_RX2_CLSH_EN_MASK BIT(4) 240 #define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3) 241 #define CDC_RX_RX2_RX_PATH_CFG1 (0x0508) 242 #define CDC_RX_RX2_RX_PATH_CFG2 (0x050C) 243 #define CDC_RX_RX2_RX_PATH_CFG3 (0x0510) 244 #define CDC_RX_RX2_RX_VOL_CTL (0x0514) 245 #define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518) 246 #define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C) 247 #define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520) 248 #define CDC_RX_RX2_RX_PATH_SEC0 (0x0524) 249 #define CDC_RX_RX2_RX_PATH_SEC1 (0x0528) 250 #define CDC_RX_RX2_RX_PATH_SEC2 (0x052C) 251 #define CDC_RX_RX2_RX_PATH_SEC3 (0x0530) 252 #define CDC_RX_RX2_RX_PATH_SEC4 (0x0534) 253 #define CDC_RX_RX2_RX_PATH_SEC5 (0x0538) 254 #define CDC_RX_RX2_RX_PATH_SEC6 (0x053C) 255 #define CDC_RX_RX2_RX_PATH_SEC7 (0x0540) 256 #define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544) 257 #define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548) 258 #define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C) 259 #define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780) 260 #define CDC_RX_IDLE_DETECT_CFG0 (0x0784) 261 #define CDC_RX_IDLE_DETECT_CFG1 (0x0788) 262 #define CDC_RX_IDLE_DETECT_CFG2 (0x078C) 263 #define CDC_RX_IDLE_DETECT_CFG3 (0x0790) 264 #define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n) 265 #define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0) 266 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1) 267 #define CDC_RX_COMPANDERn_HALT_MASK BIT(2) 268 #define CDC_RX_COMPANDER0_CTL0 (0x0800) 269 #define CDC_RX_COMPANDER0_CTL1 (0x0804) 270 #define CDC_RX_COMPANDER0_CTL2 (0x0808) 271 #define CDC_RX_COMPANDER0_CTL3 (0x080C) 272 #define CDC_RX_COMPANDER0_CTL4 (0x0810) 273 #define CDC_RX_COMPANDER0_CTL5 (0x0814) 274 #define CDC_RX_COMPANDER0_CTL6 (0x0818) 275 #define CDC_RX_COMPANDER0_CTL7 (0x081C) 276 #define CDC_RX_COMPANDER1_CTL0 (0x0840) 277 #define CDC_RX_COMPANDER1_CTL1 (0x0844) 278 #define CDC_RX_COMPANDER1_CTL2 (0x0848) 279 #define CDC_RX_COMPANDER1_CTL3 (0x084C) 280 #define CDC_RX_COMPANDER1_CTL4 (0x0850) 281 #define CDC_RX_COMPANDER1_CTL5 (0x0854) 282 #define CDC_RX_COMPANDER1_CTL6 (0x0858) 283 #define CDC_RX_COMPANDER1_CTL7 (0x085C) 284 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5) 285 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00) 286 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04) 287 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08) 288 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C) 289 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10) 290 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14) 291 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18) 292 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C) 293 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20) 294 #define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24) 295 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28) 296 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C) 297 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30) 298 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80) 299 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84) 300 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88) 301 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C) 302 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90) 303 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94) 304 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98) 305 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C) 306 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0) 307 #define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4) 308 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8) 309 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC) 310 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0) 311 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00) 312 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04) 313 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08) 314 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C) 315 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10) 316 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14) 317 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18) 318 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C) 319 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40) 320 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44) 321 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50) 322 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54) 323 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00) 324 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04) 325 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40) 326 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44) 327 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80) 328 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84) 329 #define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00) 330 #define CDC_RX_EC_ASRC0_CTL0 (0x0D04) 331 #define CDC_RX_EC_ASRC0_CTL1 (0x0D08) 332 #define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C) 333 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10) 334 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14) 335 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18) 336 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C) 337 #define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20) 338 #define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40) 339 #define CDC_RX_EC_ASRC1_CTL0 (0x0D44) 340 #define CDC_RX_EC_ASRC1_CTL1 (0x0D48) 341 #define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C) 342 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50) 343 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54) 344 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58) 345 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C) 346 #define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60) 347 #define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80) 348 #define CDC_RX_EC_ASRC2_CTL0 (0x0D84) 349 #define CDC_RX_EC_ASRC2_CTL1 (0x0D88) 350 #define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C) 351 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90) 352 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94) 353 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98) 354 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C) 355 #define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0) 356 #define CDC_RX_DSD0_PATH_CTL (0x0F00) 357 #define CDC_RX_DSD0_CFG0 (0x0F04) 358 #define CDC_RX_DSD0_CFG1 (0x0F08) 359 #define CDC_RX_DSD0_CFG2 (0x0F0C) 360 #define CDC_RX_DSD1_PATH_CTL (0x0F80) 361 #define CDC_RX_DSD1_CFG0 (0x0F84) 362 #define CDC_RX_DSD1_CFG1 (0x0F88) 363 #define CDC_RX_DSD1_CFG2 (0x0F8C) 364 #define RX_MAX_OFFSET (0x0F8C) 365 366 #define MCLK_FREQ 9600000 367 368 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 369 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 370 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 371 SNDRV_PCM_RATE_384000) 372 /* Fractional Rates */ 373 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 374 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 375 376 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 377 SNDRV_PCM_FMTBIT_S24_LE |\ 378 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 379 380 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 381 SNDRV_PCM_RATE_48000) 382 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 383 SNDRV_PCM_FMTBIT_S24_LE |\ 384 SNDRV_PCM_FMTBIT_S24_3LE) 385 386 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2 387 388 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0 389 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f 390 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f 391 392 #define COMP_MAX_COEFF 25 393 #define RX_NUM_CLKS_MAX 5 394 395 struct comp_coeff_val { 396 u8 lsb; 397 u8 msb; 398 }; 399 400 enum { 401 HPH_ULP, 402 HPH_LOHIFI, 403 HPH_MODE_MAX, 404 }; 405 406 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = { 407 { 408 {0x40, 0x00}, 409 {0x4C, 0x00}, 410 {0x5A, 0x00}, 411 {0x6B, 0x00}, 412 {0x7F, 0x00}, 413 {0x97, 0x00}, 414 {0xB3, 0x00}, 415 {0xD5, 0x00}, 416 {0xFD, 0x00}, 417 {0x2D, 0x01}, 418 {0x66, 0x01}, 419 {0xA7, 0x01}, 420 {0xF8, 0x01}, 421 {0x57, 0x02}, 422 {0xC7, 0x02}, 423 {0x4B, 0x03}, 424 {0xE9, 0x03}, 425 {0xA3, 0x04}, 426 {0x7D, 0x05}, 427 {0x90, 0x06}, 428 {0xD1, 0x07}, 429 {0x49, 0x09}, 430 {0x00, 0x0B}, 431 {0x01, 0x0D}, 432 {0x59, 0x0F}, 433 }, 434 { 435 {0x40, 0x00}, 436 {0x4C, 0x00}, 437 {0x5A, 0x00}, 438 {0x6B, 0x00}, 439 {0x80, 0x00}, 440 {0x98, 0x00}, 441 {0xB4, 0x00}, 442 {0xD5, 0x00}, 443 {0xFE, 0x00}, 444 {0x2E, 0x01}, 445 {0x66, 0x01}, 446 {0xA9, 0x01}, 447 {0xF8, 0x01}, 448 {0x56, 0x02}, 449 {0xC4, 0x02}, 450 {0x4F, 0x03}, 451 {0xF0, 0x03}, 452 {0xAE, 0x04}, 453 {0x8B, 0x05}, 454 {0x8E, 0x06}, 455 {0xBC, 0x07}, 456 {0x56, 0x09}, 457 {0x0F, 0x0B}, 458 {0x13, 0x0D}, 459 {0x6F, 0x0F}, 460 }, 461 }; 462 463 struct rx_macro_reg_mask_val { 464 u16 reg; 465 u8 mask; 466 u8 val; 467 }; 468 469 enum { 470 INTERP_HPHL, 471 INTERP_HPHR, 472 INTERP_AUX, 473 INTERP_MAX 474 }; 475 476 enum { 477 RX_MACRO_RX0, 478 RX_MACRO_RX1, 479 RX_MACRO_RX2, 480 RX_MACRO_RX3, 481 RX_MACRO_RX4, 482 RX_MACRO_RX5, 483 RX_MACRO_PORTS_MAX 484 }; 485 486 enum { 487 RX_MACRO_COMP1, /* HPH_L */ 488 RX_MACRO_COMP2, /* HPH_R */ 489 RX_MACRO_COMP_MAX 490 }; 491 492 enum { 493 RX_MACRO_EC0_MUX = 0, 494 RX_MACRO_EC1_MUX, 495 RX_MACRO_EC2_MUX, 496 RX_MACRO_EC_MUX_MAX, 497 }; 498 499 enum { 500 INTn_1_INP_SEL_ZERO = 0, 501 INTn_1_INP_SEL_DEC0, 502 INTn_1_INP_SEL_DEC1, 503 INTn_1_INP_SEL_IIR0, 504 INTn_1_INP_SEL_IIR1, 505 INTn_1_INP_SEL_RX0, 506 INTn_1_INP_SEL_RX1, 507 INTn_1_INP_SEL_RX2, 508 INTn_1_INP_SEL_RX3, 509 INTn_1_INP_SEL_RX4, 510 INTn_1_INP_SEL_RX5, 511 }; 512 513 enum { 514 INTn_2_INP_SEL_ZERO = 0, 515 INTn_2_INP_SEL_RX0, 516 INTn_2_INP_SEL_RX1, 517 INTn_2_INP_SEL_RX2, 518 INTn_2_INP_SEL_RX3, 519 INTn_2_INP_SEL_RX4, 520 INTn_2_INP_SEL_RX5, 521 }; 522 523 enum { 524 INTERP_MAIN_PATH, 525 INTERP_MIX_PATH, 526 }; 527 528 /* Codec supports 2 IIR filters */ 529 enum { 530 IIR0 = 0, 531 IIR1, 532 IIR_MAX, 533 }; 534 535 /* Each IIR has 5 Filter Stages */ 536 enum { 537 BAND1 = 0, 538 BAND2, 539 BAND3, 540 BAND4, 541 BAND5, 542 BAND_MAX, 543 }; 544 545 #define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 546 547 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \ 548 { \ 549 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 550 .info = rx_macro_iir_filter_info, \ 551 .get = rx_macro_get_iir_band_audio_mixer, \ 552 .put = rx_macro_put_iir_band_audio_mixer, \ 553 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 554 .iir_idx = iidx, \ 555 .band_idx = bidx, \ 556 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \ 557 } \ 558 } 559 560 struct interp_sample_rate { 561 int sample_rate; 562 int rate_val; 563 }; 564 565 static struct interp_sample_rate sr_val_tbl[] = { 566 {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, 567 {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA}, 568 {176400, 0xB}, {352800, 0xC}, 569 }; 570 571 enum { 572 RX_MACRO_AIF_INVALID = 0, 573 RX_MACRO_AIF1_PB, 574 RX_MACRO_AIF2_PB, 575 RX_MACRO_AIF3_PB, 576 RX_MACRO_AIF4_PB, 577 RX_MACRO_AIF_ECHO, 578 RX_MACRO_MAX_DAIS, 579 }; 580 581 enum { 582 RX_MACRO_AIF1_CAP = 0, 583 RX_MACRO_AIF2_CAP, 584 RX_MACRO_AIF3_CAP, 585 RX_MACRO_MAX_AIF_CAP_DAIS 586 }; 587 588 struct rx_macro { 589 struct device *dev; 590 int comp_enabled[RX_MACRO_COMP_MAX]; 591 /* Main path clock users count */ 592 int main_clk_users[INTERP_MAX]; 593 int rx_port_value[RX_MACRO_PORTS_MAX]; 594 u16 prim_int_users[INTERP_MAX]; 595 int rx_mclk_users; 596 bool reset_swr; 597 int clsh_users; 598 int rx_mclk_cnt; 599 bool is_ear_mode_on; 600 bool hph_pwr_mode; 601 bool hph_hd2_mode; 602 struct snd_soc_component *component; 603 unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; 604 unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; 605 u16 bit_width[RX_MACRO_MAX_DAIS]; 606 int is_softclip_on; 607 int is_aux_hpf_on; 608 int softclip_clk_users; 609 610 struct regmap *regmap; 611 struct clk_bulk_data clks[RX_NUM_CLKS_MAX]; 612 struct clk_hw hw; 613 }; 614 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw) 615 616 struct wcd_iir_filter_ctl { 617 unsigned int iir_idx; 618 unsigned int band_idx; 619 struct soc_bytes_ext bytes_ext; 620 }; 621 622 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 623 624 static const char * const rx_int_mix_mux_text[] = { 625 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 626 }; 627 628 static const char * const rx_prim_mix_text[] = { 629 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 630 "RX3", "RX4", "RX5" 631 }; 632 633 static const char * const rx_sidetone_mix_text[] = { 634 "ZERO", "SRC0", "SRC1", "SRC_SUM" 635 }; 636 637 static const char * const iir_inp_mux_text[] = { 638 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", 639 "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 640 }; 641 642 static const char * const rx_int_dem_inp_mux_text[] = { 643 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 644 }; 645 646 static const char * const rx_int0_1_interp_mux_text[] = { 647 "ZERO", "RX INT0_1 MIX1", 648 }; 649 650 static const char * const rx_int1_1_interp_mux_text[] = { 651 "ZERO", "RX INT1_1 MIX1", 652 }; 653 654 static const char * const rx_int2_1_interp_mux_text[] = { 655 "ZERO", "RX INT2_1 MIX1", 656 }; 657 658 static const char * const rx_int0_2_interp_mux_text[] = { 659 "ZERO", "RX INT0_2 MUX", 660 }; 661 662 static const char * const rx_int1_2_interp_mux_text[] = { 663 "ZERO", "RX INT1_2 MUX", 664 }; 665 666 static const char * const rx_int2_2_interp_mux_text[] = { 667 "ZERO", "RX INT2_2 MUX", 668 }; 669 670 static const char *const rx_macro_mux_text[] = { 671 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB" 672 }; 673 674 static const char *const rx_macro_hph_pwr_mode_text[] = { 675 "ULP", "LOHIFI" 676 }; 677 678 static const char * const rx_echo_mux_text[] = { 679 "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2" 680 }; 681 682 static const struct soc_enum rx_macro_hph_pwr_mode_enum = 683 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text); 684 static const struct soc_enum rx_mix_tx2_mux_enum = 685 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text); 686 static const struct soc_enum rx_mix_tx1_mux_enum = 687 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text); 688 static const struct soc_enum rx_mix_tx0_mux_enum = 689 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text); 690 691 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 692 rx_int_mix_mux_text); 693 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 694 rx_int_mix_mux_text); 695 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 696 rx_int_mix_mux_text); 697 698 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 699 rx_prim_mix_text); 700 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 701 rx_prim_mix_text); 702 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 703 rx_prim_mix_text); 704 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 705 rx_prim_mix_text); 706 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 707 rx_prim_mix_text); 708 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 709 rx_prim_mix_text); 710 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 711 rx_prim_mix_text); 712 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 713 rx_prim_mix_text); 714 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 715 rx_prim_mix_text); 716 717 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 718 rx_sidetone_mix_text); 719 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 720 rx_sidetone_mix_text); 721 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 722 rx_sidetone_mix_text); 723 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, 724 iir_inp_mux_text); 725 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, 726 iir_inp_mux_text); 727 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, 728 iir_inp_mux_text); 729 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, 730 iir_inp_mux_text); 731 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, 732 iir_inp_mux_text); 733 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, 734 iir_inp_mux_text); 735 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, 736 iir_inp_mux_text); 737 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, 738 iir_inp_mux_text); 739 740 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0, 741 rx_int0_1_interp_mux_text); 742 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0, 743 rx_int1_1_interp_mux_text); 744 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0, 745 rx_int2_1_interp_mux_text); 746 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0, 747 rx_int0_2_interp_mux_text); 748 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0, 749 rx_int1_2_interp_mux_text); 750 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0, 751 rx_int2_2_interp_mux_text); 752 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0, 753 rx_int_dem_inp_mux_text); 754 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0, 755 rx_int_dem_inp_mux_text); 756 757 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 758 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 759 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 760 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 761 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 762 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 763 764 static const struct snd_kcontrol_new rx_mix_tx1_mux = 765 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum); 766 static const struct snd_kcontrol_new rx_mix_tx2_mux = 767 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum); 768 static const struct snd_kcontrol_new rx_int0_2_mux = 769 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum); 770 static const struct snd_kcontrol_new rx_int1_2_mux = 771 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum); 772 static const struct snd_kcontrol_new rx_int2_2_mux = 773 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum); 774 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 775 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum); 776 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 777 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum); 778 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 779 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum); 780 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 781 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum); 782 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 783 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum); 784 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 785 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum); 786 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 787 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum); 788 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 789 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum); 790 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 791 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum); 792 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 793 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum); 794 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 795 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum); 796 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 797 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum); 798 static const struct snd_kcontrol_new iir0_inp0_mux = 799 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum); 800 static const struct snd_kcontrol_new iir0_inp1_mux = 801 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum); 802 static const struct snd_kcontrol_new iir0_inp2_mux = 803 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum); 804 static const struct snd_kcontrol_new iir0_inp3_mux = 805 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum); 806 static const struct snd_kcontrol_new iir1_inp0_mux = 807 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum); 808 static const struct snd_kcontrol_new iir1_inp1_mux = 809 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum); 810 static const struct snd_kcontrol_new iir1_inp2_mux = 811 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum); 812 static const struct snd_kcontrol_new iir1_inp3_mux = 813 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum); 814 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 815 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum); 816 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 817 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum); 818 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 819 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum); 820 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 821 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum); 822 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 823 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum); 824 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 825 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum); 826 static const struct snd_kcontrol_new rx_mix_tx0_mux = 827 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum); 828 829 static const struct reg_default rx_defaults[] = { 830 /* RX Macro */ 831 { CDC_RX_TOP_TOP_CFG0, 0x00 }, 832 { CDC_RX_TOP_SWR_CTRL, 0x00 }, 833 { CDC_RX_TOP_DEBUG, 0x00 }, 834 { CDC_RX_TOP_DEBUG_BUS, 0x00 }, 835 { CDC_RX_TOP_DEBUG_EN0, 0x00 }, 836 { CDC_RX_TOP_DEBUG_EN1, 0x00 }, 837 { CDC_RX_TOP_DEBUG_EN2, 0x00 }, 838 { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 }, 839 { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 }, 840 { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 }, 841 { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 }, 842 { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 }, 843 { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 }, 844 { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 }, 845 { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 }, 846 { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 }, 847 { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 }, 848 { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 }, 849 { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 }, 850 { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 }, 851 { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 }, 852 { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 }, 853 { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 }, 854 { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 }, 855 { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 }, 856 { CDC_RX_TOP_RX_I2S_CTL, 0x0C }, 857 { CDC_RX_TOP_TX_I2S2_CTL, 0x0C }, 858 { CDC_RX_TOP_I2S_CLK, 0x0C }, 859 { CDC_RX_TOP_I2S_RESET, 0x00 }, 860 { CDC_RX_TOP_I2S_MUX, 0x00 }, 861 { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 862 { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 863 { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 }, 864 { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 }, 865 { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 }, 866 { CDC_RX_SOFTCLIP_CRC, 0x00 }, 867 { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 }, 868 { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 }, 869 { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 }, 870 { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 }, 871 { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 }, 872 { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 }, 873 { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 }, 874 { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 }, 875 { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 }, 876 { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 }, 877 { CDC_RX_CLSH_CRC, 0x00 }, 878 { CDC_RX_CLSH_DLY_CTRL, 0x03 }, 879 { CDC_RX_CLSH_DECAY_CTRL, 0x02 }, 880 { CDC_RX_CLSH_HPH_V_PA, 0x1C }, 881 { CDC_RX_CLSH_EAR_V_PA, 0x39 }, 882 { CDC_RX_CLSH_HPH_V_HD, 0x0C }, 883 { CDC_RX_CLSH_EAR_V_HD, 0x0C }, 884 { CDC_RX_CLSH_K1_MSB, 0x01 }, 885 { CDC_RX_CLSH_K1_LSB, 0x00 }, 886 { CDC_RX_CLSH_K2_MSB, 0x00 }, 887 { CDC_RX_CLSH_K2_LSB, 0x80 }, 888 { CDC_RX_CLSH_IDLE_CTRL, 0x00 }, 889 { CDC_RX_CLSH_IDLE_HPH, 0x00 }, 890 { CDC_RX_CLSH_IDLE_EAR, 0x00 }, 891 { CDC_RX_CLSH_TEST0, 0x07 }, 892 { CDC_RX_CLSH_TEST1, 0x00 }, 893 { CDC_RX_CLSH_OVR_VREF, 0x00 }, 894 { CDC_RX_CLSH_CLSG_CTL, 0x02 }, 895 { CDC_RX_CLSH_CLSG_CFG1, 0x9A }, 896 { CDC_RX_CLSH_CLSG_CFG2, 0x10 }, 897 { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 }, 898 { CDC_RX_BCL_VBAT_CFG, 0x10 }, 899 { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 }, 900 { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 }, 901 { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 }, 902 { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 }, 903 { CDC_RX_BCL_VBAT_PK_EST2, 0x01 }, 904 { CDC_RX_BCL_VBAT_PK_EST3, 0x40 }, 905 { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A }, 906 { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 }, 907 { CDC_RX_BCL_VBAT_TAC1, 0x00 }, 908 { CDC_RX_BCL_VBAT_TAC2, 0x18 }, 909 { CDC_RX_BCL_VBAT_TAC3, 0x18 }, 910 { CDC_RX_BCL_VBAT_TAC4, 0x03 }, 911 { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 }, 912 { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 }, 913 { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 }, 914 { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 }, 915 { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 }, 916 { CDC_RX_BCL_VBAT_DEBUG1, 0x00 }, 917 { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 }, 918 { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 }, 919 { CDC_RX_BCL_VBAT_BAN, 0x0C }, 920 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 }, 921 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 }, 922 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 }, 923 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 }, 924 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B }, 925 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 }, 926 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 }, 927 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 }, 928 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 }, 929 { CDC_RX_BCL_VBAT_ATTN1, 0x04 }, 930 { CDC_RX_BCL_VBAT_ATTN2, 0x08 }, 931 { CDC_RX_BCL_VBAT_ATTN3, 0x0C }, 932 { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 }, 933 { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 }, 934 { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 }, 935 { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 }, 936 { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 }, 937 { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 }, 938 { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 }, 939 { CDC_RX_INTR_CTRL_CFG, 0x00 }, 940 { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 }, 941 { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF }, 942 { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 }, 943 { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 }, 944 { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF }, 945 { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 }, 946 { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 }, 947 { CDC_RX_INTR_CTRL_LEVEL0, 0x00 }, 948 { CDC_RX_INTR_CTRL_BYPASS0, 0x00 }, 949 { CDC_RX_INTR_CTRL_SET0, 0x00 }, 950 { CDC_RX_RX0_RX_PATH_CTL, 0x04 }, 951 { CDC_RX_RX0_RX_PATH_CFG0, 0x00 }, 952 { CDC_RX_RX0_RX_PATH_CFG1, 0x64 }, 953 { CDC_RX_RX0_RX_PATH_CFG2, 0x8F }, 954 { CDC_RX_RX0_RX_PATH_CFG3, 0x00 }, 955 { CDC_RX_RX0_RX_VOL_CTL, 0x00 }, 956 { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 }, 957 { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E }, 958 { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 }, 959 { CDC_RX_RX0_RX_PATH_SEC1, 0x08 }, 960 { CDC_RX_RX0_RX_PATH_SEC2, 0x00 }, 961 { CDC_RX_RX0_RX_PATH_SEC3, 0x00 }, 962 { CDC_RX_RX0_RX_PATH_SEC4, 0x00 }, 963 { CDC_RX_RX0_RX_PATH_SEC7, 0x00 }, 964 { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 }, 965 { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 }, 966 { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 }, 967 { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 }, 968 { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 }, 969 { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 }, 970 { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 }, 971 { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 }, 972 { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 }, 973 { CDC_RX_RX1_RX_PATH_CTL, 0x04 }, 974 { CDC_RX_RX1_RX_PATH_CFG0, 0x00 }, 975 { CDC_RX_RX1_RX_PATH_CFG1, 0x64 }, 976 { CDC_RX_RX1_RX_PATH_CFG2, 0x8F }, 977 { CDC_RX_RX1_RX_PATH_CFG3, 0x00 }, 978 { CDC_RX_RX1_RX_VOL_CTL, 0x00 }, 979 { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 }, 980 { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E }, 981 { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 }, 982 { CDC_RX_RX1_RX_PATH_SEC1, 0x08 }, 983 { CDC_RX_RX1_RX_PATH_SEC2, 0x00 }, 984 { CDC_RX_RX1_RX_PATH_SEC3, 0x00 }, 985 { CDC_RX_RX1_RX_PATH_SEC4, 0x00 }, 986 { CDC_RX_RX1_RX_PATH_SEC7, 0x00 }, 987 { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 }, 988 { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 }, 989 { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 }, 990 { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 }, 991 { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 }, 992 { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 }, 993 { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 }, 994 { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 }, 995 { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 }, 996 { CDC_RX_RX2_RX_PATH_CTL, 0x04 }, 997 { CDC_RX_RX2_RX_PATH_CFG0, 0x00 }, 998 { CDC_RX_RX2_RX_PATH_CFG1, 0x64 }, 999 { CDC_RX_RX2_RX_PATH_CFG2, 0x8F }, 1000 { CDC_RX_RX2_RX_PATH_CFG3, 0x00 }, 1001 { CDC_RX_RX2_RX_VOL_CTL, 0x00 }, 1002 { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 }, 1003 { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E }, 1004 { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 }, 1005 { CDC_RX_RX2_RX_PATH_SEC0, 0x04 }, 1006 { CDC_RX_RX2_RX_PATH_SEC1, 0x08 }, 1007 { CDC_RX_RX2_RX_PATH_SEC2, 0x00 }, 1008 { CDC_RX_RX2_RX_PATH_SEC3, 0x00 }, 1009 { CDC_RX_RX2_RX_PATH_SEC4, 0x00 }, 1010 { CDC_RX_RX2_RX_PATH_SEC5, 0x00 }, 1011 { CDC_RX_RX2_RX_PATH_SEC6, 0x00 }, 1012 { CDC_RX_RX2_RX_PATH_SEC7, 0x00 }, 1013 { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 }, 1014 { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 }, 1015 { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 }, 1016 { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 }, 1017 { CDC_RX_IDLE_DETECT_CFG0, 0x07 }, 1018 { CDC_RX_IDLE_DETECT_CFG1, 0x3C }, 1019 { CDC_RX_IDLE_DETECT_CFG2, 0x00 }, 1020 { CDC_RX_IDLE_DETECT_CFG3, 0x00 }, 1021 { CDC_RX_COMPANDER0_CTL0, 0x60 }, 1022 { CDC_RX_COMPANDER0_CTL1, 0xDB }, 1023 { CDC_RX_COMPANDER0_CTL2, 0xFF }, 1024 { CDC_RX_COMPANDER0_CTL3, 0x35 }, 1025 { CDC_RX_COMPANDER0_CTL4, 0xFF }, 1026 { CDC_RX_COMPANDER0_CTL5, 0x00 }, 1027 { CDC_RX_COMPANDER0_CTL6, 0x01 }, 1028 { CDC_RX_COMPANDER0_CTL7, 0x28 }, 1029 { CDC_RX_COMPANDER1_CTL0, 0x60 }, 1030 { CDC_RX_COMPANDER1_CTL1, 0xDB }, 1031 { CDC_RX_COMPANDER1_CTL2, 0xFF }, 1032 { CDC_RX_COMPANDER1_CTL3, 0x35 }, 1033 { CDC_RX_COMPANDER1_CTL4, 0xFF }, 1034 { CDC_RX_COMPANDER1_CTL5, 0x00 }, 1035 { CDC_RX_COMPANDER1_CTL6, 0x01 }, 1036 { CDC_RX_COMPANDER1_CTL7, 0x28 }, 1037 { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 }, 1038 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 }, 1039 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 }, 1040 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 }, 1041 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 }, 1042 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 }, 1043 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 }, 1044 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 }, 1045 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 }, 1046 { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 }, 1047 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 }, 1048 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 }, 1049 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 }, 1050 { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 }, 1051 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 }, 1052 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 }, 1053 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 }, 1054 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 }, 1055 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 }, 1056 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 }, 1057 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 }, 1058 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 }, 1059 { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 }, 1060 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 }, 1061 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 }, 1062 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 }, 1063 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 }, 1064 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 }, 1065 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 }, 1066 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 }, 1067 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 }, 1068 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 }, 1069 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 }, 1070 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 }, 1071 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 }, 1072 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 }, 1073 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 }, 1074 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 }, 1075 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 }, 1076 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 }, 1077 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 }, 1078 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 }, 1079 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 }, 1080 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 }, 1081 { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 }, 1082 { CDC_RX_EC_ASRC0_CTL0, 0x00 }, 1083 { CDC_RX_EC_ASRC0_CTL1, 0x00 }, 1084 { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 }, 1085 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 }, 1086 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 }, 1087 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 }, 1088 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 }, 1089 { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 }, 1090 { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 }, 1091 { CDC_RX_EC_ASRC1_CTL0, 0x00 }, 1092 { CDC_RX_EC_ASRC1_CTL1, 0x00 }, 1093 { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 }, 1094 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 }, 1095 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 }, 1096 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 }, 1097 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 }, 1098 { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 }, 1099 { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 }, 1100 { CDC_RX_EC_ASRC2_CTL0, 0x00 }, 1101 { CDC_RX_EC_ASRC2_CTL1, 0x00 }, 1102 { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 }, 1103 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 }, 1104 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 }, 1105 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 }, 1106 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 }, 1107 { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 }, 1108 { CDC_RX_DSD0_PATH_CTL, 0x00 }, 1109 { CDC_RX_DSD0_CFG0, 0x00 }, 1110 { CDC_RX_DSD0_CFG1, 0x62 }, 1111 { CDC_RX_DSD0_CFG2, 0x96 }, 1112 { CDC_RX_DSD1_PATH_CTL, 0x00 }, 1113 { CDC_RX_DSD1_CFG0, 0x00 }, 1114 { CDC_RX_DSD1_CFG1, 0x62 }, 1115 { CDC_RX_DSD1_CFG2, 0x96 }, 1116 }; 1117 1118 static bool rx_is_wronly_register(struct device *dev, 1119 unsigned int reg) 1120 { 1121 switch (reg) { 1122 case CDC_RX_BCL_VBAT_GAIN_UPD_MON: 1123 case CDC_RX_INTR_CTRL_CLR_COMMIT: 1124 case CDC_RX_INTR_CTRL_PIN1_CLEAR0: 1125 case CDC_RX_INTR_CTRL_PIN2_CLEAR0: 1126 return true; 1127 } 1128 1129 return false; 1130 } 1131 1132 static bool rx_is_volatile_register(struct device *dev, unsigned int reg) 1133 { 1134 /* Update volatile list for rx/tx macros */ 1135 switch (reg) { 1136 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1137 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1138 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1139 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1140 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1141 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1142 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1143 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1144 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1145 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1146 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1147 case CDC_RX_BCL_VBAT_DECODE_ST: 1148 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1149 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1150 case CDC_RX_COMPANDER0_CTL6: 1151 case CDC_RX_COMPANDER1_CTL6: 1152 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1153 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1154 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1155 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1156 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1157 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1158 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1159 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1160 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1161 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1162 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1163 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1164 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1165 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1166 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1167 return true; 1168 } 1169 return false; 1170 } 1171 1172 static bool rx_is_rw_register(struct device *dev, unsigned int reg) 1173 { 1174 switch (reg) { 1175 case CDC_RX_TOP_TOP_CFG0: 1176 case CDC_RX_TOP_SWR_CTRL: 1177 case CDC_RX_TOP_DEBUG: 1178 case CDC_RX_TOP_DEBUG_BUS: 1179 case CDC_RX_TOP_DEBUG_EN0: 1180 case CDC_RX_TOP_DEBUG_EN1: 1181 case CDC_RX_TOP_DEBUG_EN2: 1182 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1183 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1184 case CDC_RX_TOP_HPHL_COMP_LUT: 1185 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1186 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1187 case CDC_RX_TOP_HPHR_COMP_LUT: 1188 case CDC_RX_TOP_DSD0_DEBUG_CFG0: 1189 case CDC_RX_TOP_DSD0_DEBUG_CFG1: 1190 case CDC_RX_TOP_DSD0_DEBUG_CFG3: 1191 case CDC_RX_TOP_DSD1_DEBUG_CFG0: 1192 case CDC_RX_TOP_DSD1_DEBUG_CFG1: 1193 case CDC_RX_TOP_DSD1_DEBUG_CFG3: 1194 case CDC_RX_TOP_RX_I2S_CTL: 1195 case CDC_RX_TOP_TX_I2S2_CTL: 1196 case CDC_RX_TOP_I2S_CLK: 1197 case CDC_RX_TOP_I2S_RESET: 1198 case CDC_RX_TOP_I2S_MUX: 1199 case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL: 1200 case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL: 1201 case CDC_RX_CLK_RST_CTRL_SWR_CONTROL: 1202 case CDC_RX_CLK_RST_CTRL_DSD_CONTROL: 1203 case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL: 1204 case CDC_RX_SOFTCLIP_CRC: 1205 case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL: 1206 case CDC_RX_INP_MUX_RX_INT0_CFG0: 1207 case CDC_RX_INP_MUX_RX_INT0_CFG1: 1208 case CDC_RX_INP_MUX_RX_INT1_CFG0: 1209 case CDC_RX_INP_MUX_RX_INT1_CFG1: 1210 case CDC_RX_INP_MUX_RX_INT2_CFG0: 1211 case CDC_RX_INP_MUX_RX_INT2_CFG1: 1212 case CDC_RX_INP_MUX_RX_MIX_CFG4: 1213 case CDC_RX_INP_MUX_RX_MIX_CFG5: 1214 case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0: 1215 case CDC_RX_CLSH_CRC: 1216 case CDC_RX_CLSH_DLY_CTRL: 1217 case CDC_RX_CLSH_DECAY_CTRL: 1218 case CDC_RX_CLSH_HPH_V_PA: 1219 case CDC_RX_CLSH_EAR_V_PA: 1220 case CDC_RX_CLSH_HPH_V_HD: 1221 case CDC_RX_CLSH_EAR_V_HD: 1222 case CDC_RX_CLSH_K1_MSB: 1223 case CDC_RX_CLSH_K1_LSB: 1224 case CDC_RX_CLSH_K2_MSB: 1225 case CDC_RX_CLSH_K2_LSB: 1226 case CDC_RX_CLSH_IDLE_CTRL: 1227 case CDC_RX_CLSH_IDLE_HPH: 1228 case CDC_RX_CLSH_IDLE_EAR: 1229 case CDC_RX_CLSH_TEST0: 1230 case CDC_RX_CLSH_TEST1: 1231 case CDC_RX_CLSH_OVR_VREF: 1232 case CDC_RX_CLSH_CLSG_CTL: 1233 case CDC_RX_CLSH_CLSG_CFG1: 1234 case CDC_RX_CLSH_CLSG_CFG2: 1235 case CDC_RX_BCL_VBAT_PATH_CTL: 1236 case CDC_RX_BCL_VBAT_CFG: 1237 case CDC_RX_BCL_VBAT_ADC_CAL1: 1238 case CDC_RX_BCL_VBAT_ADC_CAL2: 1239 case CDC_RX_BCL_VBAT_ADC_CAL3: 1240 case CDC_RX_BCL_VBAT_PK_EST1: 1241 case CDC_RX_BCL_VBAT_PK_EST2: 1242 case CDC_RX_BCL_VBAT_PK_EST3: 1243 case CDC_RX_BCL_VBAT_RF_PROC1: 1244 case CDC_RX_BCL_VBAT_RF_PROC2: 1245 case CDC_RX_BCL_VBAT_TAC1: 1246 case CDC_RX_BCL_VBAT_TAC2: 1247 case CDC_RX_BCL_VBAT_TAC3: 1248 case CDC_RX_BCL_VBAT_TAC4: 1249 case CDC_RX_BCL_VBAT_GAIN_UPD1: 1250 case CDC_RX_BCL_VBAT_GAIN_UPD2: 1251 case CDC_RX_BCL_VBAT_GAIN_UPD3: 1252 case CDC_RX_BCL_VBAT_GAIN_UPD4: 1253 case CDC_RX_BCL_VBAT_GAIN_UPD5: 1254 case CDC_RX_BCL_VBAT_DEBUG1: 1255 case CDC_RX_BCL_VBAT_BAN: 1256 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1: 1257 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2: 1258 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3: 1259 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4: 1260 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5: 1261 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6: 1262 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7: 1263 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8: 1264 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9: 1265 case CDC_RX_BCL_VBAT_ATTN1: 1266 case CDC_RX_BCL_VBAT_ATTN2: 1267 case CDC_RX_BCL_VBAT_ATTN3: 1268 case CDC_RX_BCL_VBAT_DECODE_CTL1: 1269 case CDC_RX_BCL_VBAT_DECODE_CTL2: 1270 case CDC_RX_BCL_VBAT_DECODE_CFG1: 1271 case CDC_RX_BCL_VBAT_DECODE_CFG2: 1272 case CDC_RX_BCL_VBAT_DECODE_CFG3: 1273 case CDC_RX_BCL_VBAT_DECODE_CFG4: 1274 case CDC_RX_INTR_CTRL_CFG: 1275 case CDC_RX_INTR_CTRL_PIN1_MASK0: 1276 case CDC_RX_INTR_CTRL_PIN2_MASK0: 1277 case CDC_RX_INTR_CTRL_LEVEL0: 1278 case CDC_RX_INTR_CTRL_BYPASS0: 1279 case CDC_RX_INTR_CTRL_SET0: 1280 case CDC_RX_RX0_RX_PATH_CTL: 1281 case CDC_RX_RX0_RX_PATH_CFG0: 1282 case CDC_RX_RX0_RX_PATH_CFG1: 1283 case CDC_RX_RX0_RX_PATH_CFG2: 1284 case CDC_RX_RX0_RX_PATH_CFG3: 1285 case CDC_RX_RX0_RX_VOL_CTL: 1286 case CDC_RX_RX0_RX_PATH_MIX_CTL: 1287 case CDC_RX_RX0_RX_PATH_MIX_CFG: 1288 case CDC_RX_RX0_RX_VOL_MIX_CTL: 1289 case CDC_RX_RX0_RX_PATH_SEC1: 1290 case CDC_RX_RX0_RX_PATH_SEC2: 1291 case CDC_RX_RX0_RX_PATH_SEC3: 1292 case CDC_RX_RX0_RX_PATH_SEC4: 1293 case CDC_RX_RX0_RX_PATH_SEC7: 1294 case CDC_RX_RX0_RX_PATH_MIX_SEC0: 1295 case CDC_RX_RX0_RX_PATH_MIX_SEC1: 1296 case CDC_RX_RX0_RX_PATH_DSM_CTL: 1297 case CDC_RX_RX0_RX_PATH_DSM_DATA1: 1298 case CDC_RX_RX0_RX_PATH_DSM_DATA2: 1299 case CDC_RX_RX0_RX_PATH_DSM_DATA3: 1300 case CDC_RX_RX0_RX_PATH_DSM_DATA4: 1301 case CDC_RX_RX0_RX_PATH_DSM_DATA5: 1302 case CDC_RX_RX0_RX_PATH_DSM_DATA6: 1303 case CDC_RX_RX1_RX_PATH_CTL: 1304 case CDC_RX_RX1_RX_PATH_CFG0: 1305 case CDC_RX_RX1_RX_PATH_CFG1: 1306 case CDC_RX_RX1_RX_PATH_CFG2: 1307 case CDC_RX_RX1_RX_PATH_CFG3: 1308 case CDC_RX_RX1_RX_VOL_CTL: 1309 case CDC_RX_RX1_RX_PATH_MIX_CTL: 1310 case CDC_RX_RX1_RX_PATH_MIX_CFG: 1311 case CDC_RX_RX1_RX_VOL_MIX_CTL: 1312 case CDC_RX_RX1_RX_PATH_SEC1: 1313 case CDC_RX_RX1_RX_PATH_SEC2: 1314 case CDC_RX_RX1_RX_PATH_SEC3: 1315 case CDC_RX_RX1_RX_PATH_SEC4: 1316 case CDC_RX_RX1_RX_PATH_SEC7: 1317 case CDC_RX_RX1_RX_PATH_MIX_SEC0: 1318 case CDC_RX_RX1_RX_PATH_MIX_SEC1: 1319 case CDC_RX_RX1_RX_PATH_DSM_CTL: 1320 case CDC_RX_RX1_RX_PATH_DSM_DATA1: 1321 case CDC_RX_RX1_RX_PATH_DSM_DATA2: 1322 case CDC_RX_RX1_RX_PATH_DSM_DATA3: 1323 case CDC_RX_RX1_RX_PATH_DSM_DATA4: 1324 case CDC_RX_RX1_RX_PATH_DSM_DATA5: 1325 case CDC_RX_RX1_RX_PATH_DSM_DATA6: 1326 case CDC_RX_RX2_RX_PATH_CTL: 1327 case CDC_RX_RX2_RX_PATH_CFG0: 1328 case CDC_RX_RX2_RX_PATH_CFG1: 1329 case CDC_RX_RX2_RX_PATH_CFG2: 1330 case CDC_RX_RX2_RX_PATH_CFG3: 1331 case CDC_RX_RX2_RX_VOL_CTL: 1332 case CDC_RX_RX2_RX_PATH_MIX_CTL: 1333 case CDC_RX_RX2_RX_PATH_MIX_CFG: 1334 case CDC_RX_RX2_RX_VOL_MIX_CTL: 1335 case CDC_RX_RX2_RX_PATH_SEC0: 1336 case CDC_RX_RX2_RX_PATH_SEC1: 1337 case CDC_RX_RX2_RX_PATH_SEC2: 1338 case CDC_RX_RX2_RX_PATH_SEC3: 1339 case CDC_RX_RX2_RX_PATH_SEC4: 1340 case CDC_RX_RX2_RX_PATH_SEC5: 1341 case CDC_RX_RX2_RX_PATH_SEC6: 1342 case CDC_RX_RX2_RX_PATH_SEC7: 1343 case CDC_RX_RX2_RX_PATH_MIX_SEC0: 1344 case CDC_RX_RX2_RX_PATH_MIX_SEC1: 1345 case CDC_RX_RX2_RX_PATH_DSM_CTL: 1346 case CDC_RX_IDLE_DETECT_PATH_CTL: 1347 case CDC_RX_IDLE_DETECT_CFG0: 1348 case CDC_RX_IDLE_DETECT_CFG1: 1349 case CDC_RX_IDLE_DETECT_CFG2: 1350 case CDC_RX_IDLE_DETECT_CFG3: 1351 case CDC_RX_COMPANDER0_CTL0: 1352 case CDC_RX_COMPANDER0_CTL1: 1353 case CDC_RX_COMPANDER0_CTL2: 1354 case CDC_RX_COMPANDER0_CTL3: 1355 case CDC_RX_COMPANDER0_CTL4: 1356 case CDC_RX_COMPANDER0_CTL5: 1357 case CDC_RX_COMPANDER0_CTL7: 1358 case CDC_RX_COMPANDER1_CTL0: 1359 case CDC_RX_COMPANDER1_CTL1: 1360 case CDC_RX_COMPANDER1_CTL2: 1361 case CDC_RX_COMPANDER1_CTL3: 1362 case CDC_RX_COMPANDER1_CTL4: 1363 case CDC_RX_COMPANDER1_CTL5: 1364 case CDC_RX_COMPANDER1_CTL7: 1365 case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL: 1366 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL: 1367 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL: 1368 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL: 1369 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL: 1370 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL: 1371 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL: 1372 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL: 1373 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL: 1374 case CDC_RX_SIDETONE_IIR0_IIR_CTL: 1375 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL: 1376 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL: 1377 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: 1378 case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL: 1379 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL: 1380 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL: 1381 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL: 1382 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL: 1383 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL: 1384 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL: 1385 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL: 1386 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL: 1387 case CDC_RX_SIDETONE_IIR1_IIR_CTL: 1388 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL: 1389 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: 1390 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: 1391 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0: 1392 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1: 1393 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2: 1394 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3: 1395 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0: 1396 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1: 1397 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2: 1398 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3: 1399 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL: 1400 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1: 1401 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL: 1402 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1: 1403 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL: 1404 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0: 1405 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL: 1406 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0: 1407 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL: 1408 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0: 1409 case CDC_RX_EC_ASRC0_CLK_RST_CTL: 1410 case CDC_RX_EC_ASRC0_CTL0: 1411 case CDC_RX_EC_ASRC0_CTL1: 1412 case CDC_RX_EC_ASRC0_FIFO_CTL: 1413 case CDC_RX_EC_ASRC1_CLK_RST_CTL: 1414 case CDC_RX_EC_ASRC1_CTL0: 1415 case CDC_RX_EC_ASRC1_CTL1: 1416 case CDC_RX_EC_ASRC1_FIFO_CTL: 1417 case CDC_RX_EC_ASRC2_CLK_RST_CTL: 1418 case CDC_RX_EC_ASRC2_CTL0: 1419 case CDC_RX_EC_ASRC2_CTL1: 1420 case CDC_RX_EC_ASRC2_FIFO_CTL: 1421 case CDC_RX_DSD0_PATH_CTL: 1422 case CDC_RX_DSD0_CFG0: 1423 case CDC_RX_DSD0_CFG1: 1424 case CDC_RX_DSD0_CFG2: 1425 case CDC_RX_DSD1_PATH_CTL: 1426 case CDC_RX_DSD1_CFG0: 1427 case CDC_RX_DSD1_CFG1: 1428 case CDC_RX_DSD1_CFG2: 1429 return true; 1430 } 1431 1432 return false; 1433 } 1434 1435 static bool rx_is_writeable_register(struct device *dev, unsigned int reg) 1436 { 1437 bool ret; 1438 1439 ret = rx_is_rw_register(dev, reg); 1440 if (!ret) 1441 return rx_is_wronly_register(dev, reg); 1442 1443 return ret; 1444 } 1445 1446 static bool rx_is_readable_register(struct device *dev, unsigned int reg) 1447 { 1448 switch (reg) { 1449 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1450 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1451 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1452 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1453 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1454 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1455 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1456 case CDC_RX_BCL_VBAT_DECODE_ST: 1457 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1458 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1459 case CDC_RX_COMPANDER0_CTL6: 1460 case CDC_RX_COMPANDER1_CTL6: 1461 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1462 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1463 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1464 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1465 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1466 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1467 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1468 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1469 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1470 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1471 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1472 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1473 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1474 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1475 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1476 return true; 1477 } 1478 1479 return rx_is_rw_register(dev, reg); 1480 } 1481 1482 static const struct regmap_config rx_regmap_config = { 1483 .name = "rx_macro", 1484 .reg_bits = 16, 1485 .val_bits = 32, /* 8 but with 32 bit read/write */ 1486 .reg_stride = 4, 1487 .cache_type = REGCACHE_FLAT, 1488 .reg_defaults = rx_defaults, 1489 .num_reg_defaults = ARRAY_SIZE(rx_defaults), 1490 .max_register = RX_MAX_OFFSET, 1491 .writeable_reg = rx_is_writeable_register, 1492 .volatile_reg = rx_is_volatile_register, 1493 .readable_reg = rx_is_readable_register, 1494 }; 1495 1496 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, 1497 struct snd_ctl_elem_value *ucontrol) 1498 { 1499 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1500 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1501 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1502 unsigned short look_ahead_dly_reg; 1503 unsigned int val; 1504 1505 val = ucontrol->value.enumerated.item[0]; 1506 1507 if (e->reg == CDC_RX_RX0_RX_PATH_CFG1) 1508 look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0; 1509 else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1) 1510 look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0; 1511 1512 /* Set Look Ahead Delay */ 1513 if (val) 1514 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1515 CDC_RX_DLY_ZN_EN_MASK, 1516 CDC_RX_DLY_ZN_ENABLE); 1517 else 1518 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1519 CDC_RX_DLY_ZN_EN_MASK, 0); 1520 /* Set DEM INP Select */ 1521 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1522 } 1523 1524 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1525 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum, 1526 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1527 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1528 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum, 1529 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1530 1531 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1532 int rate_reg_val, u32 sample_rate) 1533 { 1534 1535 u8 int_1_mix1_inp; 1536 u32 j, port; 1537 u16 int_mux_cfg0, int_mux_cfg1; 1538 u16 int_fs_reg; 1539 u8 inp0_sel, inp1_sel, inp2_sel; 1540 struct snd_soc_component *component = dai->component; 1541 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1542 1543 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1544 int_1_mix1_inp = port; 1545 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0; 1546 /* 1547 * Loop through all interpolator MUX inputs and find out 1548 * to which interpolator input, the rx port 1549 * is connected 1550 */ 1551 for (j = 0; j < INTERP_MAX; j++) { 1552 int_mux_cfg1 = int_mux_cfg0 + 4; 1553 1554 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1555 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 1556 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1557 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 1558 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 1559 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 1560 1561 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1562 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1563 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 1564 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j); 1565 /* sample_rate is in Hz */ 1566 snd_soc_component_update_bits(component, int_fs_reg, 1567 CDC_RX_PATH_PCM_RATE_MASK, 1568 rate_reg_val); 1569 } 1570 int_mux_cfg0 += 8; 1571 } 1572 } 1573 1574 return 0; 1575 } 1576 1577 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1578 int rate_reg_val, u32 sample_rate) 1579 { 1580 1581 u8 int_2_inp; 1582 u32 j, port; 1583 u16 int_mux_cfg1, int_fs_reg; 1584 u8 int_mux_cfg1_val; 1585 struct snd_soc_component *component = dai->component; 1586 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1587 1588 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1589 int_2_inp = port; 1590 1591 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1; 1592 for (j = 0; j < INTERP_MAX; j++) { 1593 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 1594 CDC_RX_INTX_2_SEL_MASK); 1595 1596 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 1597 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j); 1598 snd_soc_component_update_bits(component, int_fs_reg, 1599 CDC_RX_RXn_MIX_PCM_RATE_MASK, 1600 rate_reg_val); 1601 } 1602 int_mux_cfg1 += 8; 1603 } 1604 } 1605 return 0; 1606 } 1607 1608 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, 1609 u32 sample_rate) 1610 { 1611 int rate_val = 0; 1612 int i, ret; 1613 1614 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) 1615 if (sample_rate == sr_val_tbl[i].sample_rate) 1616 rate_val = sr_val_tbl[i].rate_val; 1617 1618 ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate); 1619 if (ret) 1620 return ret; 1621 1622 ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate); 1623 1624 return ret; 1625 } 1626 1627 static int rx_macro_hw_params(struct snd_pcm_substream *substream, 1628 struct snd_pcm_hw_params *params, 1629 struct snd_soc_dai *dai) 1630 { 1631 struct snd_soc_component *component = dai->component; 1632 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1633 int ret; 1634 1635 switch (substream->stream) { 1636 case SNDRV_PCM_STREAM_PLAYBACK: 1637 ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); 1638 if (ret) { 1639 dev_err(component->dev, "%s: cannot set sample rate: %u\n", 1640 __func__, params_rate(params)); 1641 return ret; 1642 } 1643 rx->bit_width[dai->id] = params_width(params); 1644 break; 1645 default: 1646 break; 1647 } 1648 return 0; 1649 } 1650 1651 static int rx_macro_get_channel_map(struct snd_soc_dai *dai, 1652 unsigned int *tx_num, unsigned int *tx_slot, 1653 unsigned int *rx_num, unsigned int *rx_slot) 1654 { 1655 struct snd_soc_component *component = dai->component; 1656 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1657 u16 val, mask = 0, cnt = 0, temp; 1658 1659 switch (dai->id) { 1660 case RX_MACRO_AIF1_PB: 1661 case RX_MACRO_AIF2_PB: 1662 case RX_MACRO_AIF3_PB: 1663 case RX_MACRO_AIF4_PB: 1664 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], 1665 RX_MACRO_PORTS_MAX) { 1666 mask |= (1 << temp); 1667 if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT) 1668 break; 1669 } 1670 /* 1671 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 1672 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 1673 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 1674 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 1675 * AIFn can pair to any CDC_DMA_RX_n port. 1676 * In general, below convention is used:: 1677 * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/ 1678 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4) 1679 */ 1680 if (mask & 0x0C) 1681 mask = mask >> 2; 1682 if ((mask & 0x10) || (mask & 0x20)) 1683 mask = 0x1; 1684 *rx_slot = mask; 1685 *rx_num = rx->active_ch_cnt[dai->id]; 1686 break; 1687 case RX_MACRO_AIF_ECHO: 1688 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4); 1689 if (val & RX_MACRO_EC_MIX_TX0_MASK) { 1690 mask |= 0x1; 1691 cnt++; 1692 } 1693 if (val & RX_MACRO_EC_MIX_TX1_MASK) { 1694 mask |= 0x2; 1695 cnt++; 1696 } 1697 val = snd_soc_component_read(component, 1698 CDC_RX_INP_MUX_RX_MIX_CFG5); 1699 if (val & RX_MACRO_EC_MIX_TX2_MASK) { 1700 mask |= 0x4; 1701 cnt++; 1702 } 1703 *tx_slot = mask; 1704 *tx_num = cnt; 1705 break; 1706 default: 1707 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1708 break; 1709 } 1710 return 0; 1711 } 1712 1713 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1714 { 1715 struct snd_soc_component *component = dai->component; 1716 uint16_t j, reg, mix_reg, dsm_reg; 1717 u16 int_mux_cfg0, int_mux_cfg1; 1718 u8 int_mux_cfg0_val, int_mux_cfg1_val; 1719 1720 switch (dai->id) { 1721 case RX_MACRO_AIF1_PB: 1722 case RX_MACRO_AIF2_PB: 1723 case RX_MACRO_AIF3_PB: 1724 case RX_MACRO_AIF4_PB: 1725 for (j = 0; j < INTERP_MAX; j++) { 1726 reg = CDC_RX_RXn_RX_PATH_CTL(j); 1727 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j); 1728 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j); 1729 1730 if (mute) { 1731 snd_soc_component_update_bits(component, reg, 1732 CDC_RX_PATH_PGA_MUTE_MASK, 1733 CDC_RX_PATH_PGA_MUTE_ENABLE); 1734 snd_soc_component_update_bits(component, mix_reg, 1735 CDC_RX_PATH_PGA_MUTE_MASK, 1736 CDC_RX_PATH_PGA_MUTE_ENABLE); 1737 } else { 1738 snd_soc_component_update_bits(component, reg, 1739 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1740 snd_soc_component_update_bits(component, mix_reg, 1741 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1742 } 1743 1744 if (j == INTERP_AUX) 1745 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL; 1746 1747 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8; 1748 int_mux_cfg1 = int_mux_cfg0 + 4; 1749 int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0); 1750 int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1); 1751 1752 if (snd_soc_component_read(component, dsm_reg) & 0x01) { 1753 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0)) 1754 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1755 if (int_mux_cfg1_val & 0x0F) { 1756 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1757 snd_soc_component_update_bits(component, mix_reg, 0x20, 1758 0x20); 1759 } 1760 } 1761 } 1762 break; 1763 default: 1764 break; 1765 } 1766 return 0; 1767 } 1768 1769 static const struct snd_soc_dai_ops rx_macro_dai_ops = { 1770 .hw_params = rx_macro_hw_params, 1771 .get_channel_map = rx_macro_get_channel_map, 1772 .mute_stream = rx_macro_digital_mute, 1773 }; 1774 1775 static struct snd_soc_dai_driver rx_macro_dai[] = { 1776 { 1777 .name = "rx_macro_rx1", 1778 .id = RX_MACRO_AIF1_PB, 1779 .playback = { 1780 .stream_name = "RX_MACRO_AIF1 Playback", 1781 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1782 .formats = RX_MACRO_FORMATS, 1783 .rate_max = 384000, 1784 .rate_min = 8000, 1785 .channels_min = 1, 1786 .channels_max = 2, 1787 }, 1788 .ops = &rx_macro_dai_ops, 1789 }, 1790 { 1791 .name = "rx_macro_rx2", 1792 .id = RX_MACRO_AIF2_PB, 1793 .playback = { 1794 .stream_name = "RX_MACRO_AIF2 Playback", 1795 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1796 .formats = RX_MACRO_FORMATS, 1797 .rate_max = 384000, 1798 .rate_min = 8000, 1799 .channels_min = 1, 1800 .channels_max = 2, 1801 }, 1802 .ops = &rx_macro_dai_ops, 1803 }, 1804 { 1805 .name = "rx_macro_rx3", 1806 .id = RX_MACRO_AIF3_PB, 1807 .playback = { 1808 .stream_name = "RX_MACRO_AIF3 Playback", 1809 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1810 .formats = RX_MACRO_FORMATS, 1811 .rate_max = 384000, 1812 .rate_min = 8000, 1813 .channels_min = 1, 1814 .channels_max = 2, 1815 }, 1816 .ops = &rx_macro_dai_ops, 1817 }, 1818 { 1819 .name = "rx_macro_rx4", 1820 .id = RX_MACRO_AIF4_PB, 1821 .playback = { 1822 .stream_name = "RX_MACRO_AIF4 Playback", 1823 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1824 .formats = RX_MACRO_FORMATS, 1825 .rate_max = 384000, 1826 .rate_min = 8000, 1827 .channels_min = 1, 1828 .channels_max = 2, 1829 }, 1830 .ops = &rx_macro_dai_ops, 1831 }, 1832 { 1833 .name = "rx_macro_echo", 1834 .id = RX_MACRO_AIF_ECHO, 1835 .capture = { 1836 .stream_name = "RX_AIF_ECHO Capture", 1837 .rates = RX_MACRO_ECHO_RATES, 1838 .formats = RX_MACRO_ECHO_FORMATS, 1839 .rate_max = 48000, 1840 .rate_min = 8000, 1841 .channels_min = 1, 1842 .channels_max = 3, 1843 }, 1844 .ops = &rx_macro_dai_ops, 1845 }, 1846 }; 1847 1848 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) 1849 { 1850 struct regmap *regmap = rx->regmap; 1851 1852 if (mclk_enable) { 1853 if (rx->rx_mclk_users == 0) { 1854 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 1855 CDC_RX_CLK_MCLK_EN_MASK | 1856 CDC_RX_CLK_MCLK2_EN_MASK, 1857 CDC_RX_CLK_MCLK_ENABLE | 1858 CDC_RX_CLK_MCLK2_ENABLE); 1859 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 1860 CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); 1861 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 1862 CDC_RX_FS_MCLK_CNT_EN_MASK, 1863 CDC_RX_FS_MCLK_CNT_ENABLE); 1864 regcache_mark_dirty(regmap); 1865 regcache_sync(regmap); 1866 } 1867 rx->rx_mclk_users++; 1868 } else { 1869 if (rx->rx_mclk_users <= 0) { 1870 dev_err(rx->dev, "%s: clock already disabled\n", __func__); 1871 rx->rx_mclk_users = 0; 1872 return; 1873 } 1874 rx->rx_mclk_users--; 1875 if (rx->rx_mclk_users == 0) { 1876 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 1877 CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0); 1878 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 1879 CDC_RX_FS_MCLK_CNT_CLR_MASK, 1880 CDC_RX_FS_MCLK_CNT_CLR); 1881 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 1882 CDC_RX_CLK_MCLK_EN_MASK | 1883 CDC_RX_CLK_MCLK2_EN_MASK, 0x0); 1884 } 1885 } 1886 } 1887 1888 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, 1889 struct snd_kcontrol *kcontrol, int event) 1890 { 1891 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1892 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1893 int ret = 0; 1894 1895 switch (event) { 1896 case SND_SOC_DAPM_PRE_PMU: 1897 rx_macro_mclk_enable(rx, true); 1898 break; 1899 case SND_SOC_DAPM_POST_PMD: 1900 rx_macro_mclk_enable(rx, false); 1901 break; 1902 default: 1903 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); 1904 ret = -EINVAL; 1905 } 1906 return ret; 1907 } 1908 1909 static bool rx_macro_adie_lb(struct snd_soc_component *component, 1910 int interp_idx) 1911 { 1912 u16 int_mux_cfg0, int_mux_cfg1; 1913 u8 int_n_inp0, int_n_inp1, int_n_inp2; 1914 1915 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 1916 int_mux_cfg1 = int_mux_cfg0 + 4; 1917 1918 int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 1919 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 1920 int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 1921 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 1922 int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 1923 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 1924 1925 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 1926 int_n_inp0 == INTn_1_INP_SEL_DEC1 || 1927 int_n_inp0 == INTn_1_INP_SEL_IIR0 || 1928 int_n_inp0 == INTn_1_INP_SEL_IIR1) 1929 return true; 1930 1931 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 1932 int_n_inp1 == INTn_1_INP_SEL_DEC1 || 1933 int_n_inp1 == INTn_1_INP_SEL_IIR0 || 1934 int_n_inp1 == INTn_1_INP_SEL_IIR1) 1935 return true; 1936 1937 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 1938 int_n_inp2 == INTn_1_INP_SEL_DEC1 || 1939 int_n_inp2 == INTn_1_INP_SEL_IIR0 || 1940 int_n_inp2 == INTn_1_INP_SEL_IIR1) 1941 return true; 1942 1943 return false; 1944 } 1945 1946 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 1947 int event, int interp_idx); 1948 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, 1949 struct snd_kcontrol *kcontrol, 1950 int event) 1951 { 1952 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1953 u16 gain_reg, reg; 1954 1955 reg = CDC_RX_RXn_RX_PATH_CTL(w->shift); 1956 gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift); 1957 1958 switch (event) { 1959 case SND_SOC_DAPM_PRE_PMU: 1960 rx_macro_enable_interp_clk(component, event, w->shift); 1961 if (rx_macro_adie_lb(component, w->shift)) 1962 snd_soc_component_update_bits(component, reg, 1963 CDC_RX_PATH_CLK_EN_MASK, 1964 CDC_RX_PATH_CLK_ENABLE); 1965 break; 1966 case SND_SOC_DAPM_POST_PMU: 1967 snd_soc_component_write(component, gain_reg, 1968 snd_soc_component_read(component, gain_reg)); 1969 break; 1970 case SND_SOC_DAPM_POST_PMD: 1971 rx_macro_enable_interp_clk(component, event, w->shift); 1972 break; 1973 } 1974 1975 return 0; 1976 } 1977 1978 static int rx_macro_config_compander(struct snd_soc_component *component, 1979 struct rx_macro *rx, 1980 int comp, int event) 1981 { 1982 u8 pcm_rate, val; 1983 1984 /* AUX does not have compander */ 1985 if (comp == INTERP_AUX) 1986 return 0; 1987 1988 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F; 1989 if (pcm_rate < 0x06) 1990 val = 0x03; 1991 else if (pcm_rate < 0x08) 1992 val = 0x01; 1993 else if (pcm_rate < 0x0B) 1994 val = 0x02; 1995 else 1996 val = 0x00; 1997 1998 if (SND_SOC_DAPM_EVENT_ON(event)) 1999 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp), 2000 CDC_RX_DC_COEFF_SEL_MASK, val); 2001 2002 if (SND_SOC_DAPM_EVENT_OFF(event)) 2003 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp), 2004 CDC_RX_DC_COEFF_SEL_MASK, 0x3); 2005 if (!rx->comp_enabled[comp]) 2006 return 0; 2007 2008 if (SND_SOC_DAPM_EVENT_ON(event)) { 2009 /* Enable Compander Clock */ 2010 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2011 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1); 2012 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2013 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1); 2014 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2015 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0); 2016 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp), 2017 CDC_RX_RXn_COMP_EN_MASK, 0x1); 2018 } 2019 2020 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2021 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2022 CDC_RX_COMPANDERn_HALT_MASK, 0x1); 2023 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp), 2024 CDC_RX_RXn_COMP_EN_MASK, 0x0); 2025 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2026 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0); 2027 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2028 CDC_RX_COMPANDERn_HALT_MASK, 0x0); 2029 } 2030 2031 return 0; 2032 } 2033 2034 static int rx_macro_load_compander_coeff(struct snd_soc_component *component, 2035 struct rx_macro *rx, 2036 int comp, int event) 2037 { 2038 u16 comp_coeff_lsb_reg, comp_coeff_msb_reg; 2039 int i; 2040 int hph_pwr_mode; 2041 2042 if (!rx->comp_enabled[comp]) 2043 return 0; 2044 2045 if (comp == INTERP_HPHL) { 2046 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB; 2047 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB; 2048 } else if (comp == INTERP_HPHR) { 2049 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB; 2050 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB; 2051 } else { 2052 /* compander coefficients are loaded only for hph path */ 2053 return 0; 2054 } 2055 2056 hph_pwr_mode = rx->hph_pwr_mode; 2057 2058 if (SND_SOC_DAPM_EVENT_ON(event)) { 2059 /* Load Compander Coeff */ 2060 for (i = 0; i < COMP_MAX_COEFF; i++) { 2061 snd_soc_component_write(component, comp_coeff_lsb_reg, 2062 comp_coeff_table[hph_pwr_mode][i].lsb); 2063 snd_soc_component_write(component, comp_coeff_msb_reg, 2064 comp_coeff_table[hph_pwr_mode][i].msb); 2065 } 2066 } 2067 2068 return 0; 2069 } 2070 2071 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, 2072 struct rx_macro *rx, bool enable) 2073 { 2074 if (enable) { 2075 if (rx->softclip_clk_users == 0) 2076 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2077 CDC_RX_SOFTCLIP_CLK_EN_MASK, 1); 2078 rx->softclip_clk_users++; 2079 } else { 2080 rx->softclip_clk_users--; 2081 if (rx->softclip_clk_users == 0) 2082 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2083 CDC_RX_SOFTCLIP_CLK_EN_MASK, 0); 2084 } 2085 } 2086 2087 static int rx_macro_config_softclip(struct snd_soc_component *component, 2088 struct rx_macro *rx, int event) 2089 { 2090 2091 if (!rx->is_softclip_on) 2092 return 0; 2093 2094 if (SND_SOC_DAPM_EVENT_ON(event)) { 2095 /* Enable Softclip clock */ 2096 rx_macro_enable_softclip_clk(component, rx, true); 2097 /* Enable Softclip control */ 2098 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2099 CDC_RX_SOFTCLIP_EN_MASK, 0x01); 2100 } 2101 2102 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2103 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2104 CDC_RX_SOFTCLIP_EN_MASK, 0x0); 2105 rx_macro_enable_softclip_clk(component, rx, false); 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int rx_macro_config_aux_hpf(struct snd_soc_component *component, 2112 struct rx_macro *rx, int event) 2113 { 2114 if (SND_SOC_DAPM_EVENT_ON(event)) { 2115 /* Update Aux HPF control */ 2116 if (!rx->is_aux_hpf_on) 2117 snd_soc_component_update_bits(component, 2118 CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00); 2119 } 2120 2121 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2122 /* Reset to default (HPF=ON) */ 2123 snd_soc_component_update_bits(component, 2124 CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04); 2125 } 2126 2127 return 0; 2128 } 2129 2130 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) 2131 { 2132 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) 2133 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, 2134 CDC_RX_CLSH_CLK_EN_MASK, enable); 2135 if (rx->clsh_users < 0) 2136 rx->clsh_users = 0; 2137 } 2138 2139 static int rx_macro_config_classh(struct snd_soc_component *component, 2140 struct rx_macro *rx, 2141 int interp_n, int event) 2142 { 2143 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2144 rx_macro_enable_clsh_block(rx, false); 2145 return 0; 2146 } 2147 2148 if (!SND_SOC_DAPM_EVENT_ON(event)) 2149 return 0; 2150 2151 rx_macro_enable_clsh_block(rx, true); 2152 if (interp_n == INTERP_HPHL || 2153 interp_n == INTERP_HPHR) { 2154 /* 2155 * These K1 values depend on the Headphone Impedance 2156 * For now it is assumed to be 16 ohm 2157 */ 2158 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0); 2159 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB, 2160 CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0); 2161 } 2162 switch (interp_n) { 2163 case INTERP_HPHL: 2164 if (rx->is_ear_mode_on) 2165 snd_soc_component_update_bits(component, 2166 CDC_RX_CLSH_HPH_V_PA, 2167 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2168 else 2169 snd_soc_component_update_bits(component, 2170 CDC_RX_CLSH_HPH_V_PA, 2171 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2172 snd_soc_component_update_bits(component, 2173 CDC_RX_CLSH_DECAY_CTRL, 2174 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2175 snd_soc_component_write_field(component, 2176 CDC_RX_RX0_RX_PATH_CFG0, 2177 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2178 break; 2179 case INTERP_HPHR: 2180 if (rx->is_ear_mode_on) 2181 snd_soc_component_update_bits(component, 2182 CDC_RX_CLSH_HPH_V_PA, 2183 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2184 else 2185 snd_soc_component_update_bits(component, 2186 CDC_RX_CLSH_HPH_V_PA, 2187 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2188 snd_soc_component_update_bits(component, 2189 CDC_RX_CLSH_DECAY_CTRL, 2190 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2191 snd_soc_component_write_field(component, 2192 CDC_RX_RX1_RX_PATH_CFG0, 2193 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2194 break; 2195 case INTERP_AUX: 2196 snd_soc_component_update_bits(component, 2197 CDC_RX_RX2_RX_PATH_CFG0, 2198 CDC_RX_RX2_DLY_Z_EN_MASK, 1); 2199 snd_soc_component_write_field(component, 2200 CDC_RX_RX2_RX_PATH_CFG0, 2201 CDC_RX_RX2_CLSH_EN_MASK, 1); 2202 break; 2203 } 2204 2205 return 0; 2206 } 2207 2208 static void rx_macro_hd2_control(struct snd_soc_component *component, 2209 u16 interp_idx, int event) 2210 { 2211 u16 hd2_scale_reg, hd2_enable_reg; 2212 2213 switch (interp_idx) { 2214 case INTERP_HPHL: 2215 hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3; 2216 hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0; 2217 break; 2218 case INTERP_HPHR: 2219 hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3; 2220 hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0; 2221 break; 2222 } 2223 2224 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2225 snd_soc_component_update_bits(component, hd2_scale_reg, 2226 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14); 2227 snd_soc_component_write_field(component, hd2_enable_reg, 2228 CDC_RX_RXn_HD2_EN_MASK, 1); 2229 } 2230 2231 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2232 snd_soc_component_write_field(component, hd2_enable_reg, 2233 CDC_RX_RXn_HD2_EN_MASK, 0); 2234 snd_soc_component_update_bits(component, hd2_scale_reg, 2235 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0); 2236 } 2237 } 2238 2239 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, 2240 struct snd_ctl_elem_value *ucontrol) 2241 { 2242 struct snd_soc_component *component = 2243 snd_soc_kcontrol_component(kcontrol); 2244 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2245 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2246 2247 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; 2248 return 0; 2249 } 2250 2251 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, 2252 struct snd_ctl_elem_value *ucontrol) 2253 { 2254 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2255 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2256 int value = ucontrol->value.integer.value[0]; 2257 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2258 2259 rx->comp_enabled[comp] = value; 2260 2261 return 0; 2262 } 2263 2264 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, 2265 struct snd_ctl_elem_value *ucontrol) 2266 { 2267 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2268 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2269 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2270 2271 ucontrol->value.integer.value[0] = 2272 rx->rx_port_value[widget->shift]; 2273 return 0; 2274 } 2275 2276 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, 2277 struct snd_ctl_elem_value *ucontrol) 2278 { 2279 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2280 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2281 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2282 struct snd_soc_dapm_update *update = NULL; 2283 u32 rx_port_value = ucontrol->value.integer.value[0]; 2284 u32 aif_rst; 2285 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2286 2287 aif_rst = rx->rx_port_value[widget->shift]; 2288 if (!rx_port_value) { 2289 if (aif_rst == 0) { 2290 dev_err(component->dev, "%s:AIF reset already\n", __func__); 2291 return 0; 2292 } 2293 if (aif_rst > RX_MACRO_AIF4_PB) { 2294 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 2295 return 0; 2296 } 2297 } 2298 rx->rx_port_value[widget->shift] = rx_port_value; 2299 2300 switch (rx_port_value) { 2301 case 0: 2302 if (rx->active_ch_cnt[aif_rst]) { 2303 clear_bit(widget->shift, 2304 &rx->active_ch_mask[aif_rst]); 2305 rx->active_ch_cnt[aif_rst]--; 2306 } 2307 break; 2308 case 1: 2309 case 2: 2310 case 3: 2311 case 4: 2312 set_bit(widget->shift, 2313 &rx->active_ch_mask[rx_port_value]); 2314 rx->active_ch_cnt[rx_port_value]++; 2315 break; 2316 default: 2317 dev_err(component->dev, 2318 "%s:Invalid AIF_ID for RX_MACRO MUX %d\n", 2319 __func__, rx_port_value); 2320 goto err; 2321 } 2322 2323 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 2324 rx_port_value, e, update); 2325 return 0; 2326 err: 2327 return -EINVAL; 2328 } 2329 2330 static const struct snd_kcontrol_new rx_macro_rx0_mux = 2331 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum, 2332 rx_macro_mux_get, rx_macro_mux_put); 2333 static const struct snd_kcontrol_new rx_macro_rx1_mux = 2334 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum, 2335 rx_macro_mux_get, rx_macro_mux_put); 2336 static const struct snd_kcontrol_new rx_macro_rx2_mux = 2337 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum, 2338 rx_macro_mux_get, rx_macro_mux_put); 2339 static const struct snd_kcontrol_new rx_macro_rx3_mux = 2340 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum, 2341 rx_macro_mux_get, rx_macro_mux_put); 2342 static const struct snd_kcontrol_new rx_macro_rx4_mux = 2343 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum, 2344 rx_macro_mux_get, rx_macro_mux_put); 2345 static const struct snd_kcontrol_new rx_macro_rx5_mux = 2346 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum, 2347 rx_macro_mux_get, rx_macro_mux_put); 2348 2349 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, 2350 struct snd_ctl_elem_value *ucontrol) 2351 { 2352 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2353 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2354 2355 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; 2356 return 0; 2357 } 2358 2359 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, 2360 struct snd_ctl_elem_value *ucontrol) 2361 { 2362 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2363 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2364 2365 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); 2366 return 0; 2367 } 2368 2369 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2370 struct snd_ctl_elem_value *ucontrol) 2371 { 2372 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2373 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2374 2375 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; 2376 return 0; 2377 } 2378 2379 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2380 struct snd_ctl_elem_value *ucontrol) 2381 { 2382 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2383 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2384 2385 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; 2386 return 0; 2387 } 2388 2389 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2390 struct snd_ctl_elem_value *ucontrol) 2391 { 2392 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2393 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2394 2395 ucontrol->value.integer.value[0] = rx->hph_pwr_mode; 2396 return 0; 2397 } 2398 2399 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2400 struct snd_ctl_elem_value *ucontrol) 2401 { 2402 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2403 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2404 2405 rx->hph_pwr_mode = ucontrol->value.integer.value[0]; 2406 return 0; 2407 } 2408 2409 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 2410 struct snd_ctl_elem_value *ucontrol) 2411 { 2412 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2413 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2414 2415 ucontrol->value.integer.value[0] = rx->is_softclip_on; 2416 2417 return 0; 2418 } 2419 2420 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 2421 struct snd_ctl_elem_value *ucontrol) 2422 { 2423 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2424 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2425 2426 rx->is_softclip_on = ucontrol->value.integer.value[0]; 2427 2428 return 0; 2429 } 2430 2431 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol, 2432 struct snd_ctl_elem_value *ucontrol) 2433 { 2434 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2435 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2436 2437 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; 2438 2439 return 0; 2440 } 2441 2442 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol, 2443 struct snd_ctl_elem_value *ucontrol) 2444 { 2445 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2446 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2447 2448 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; 2449 2450 return 0; 2451 } 2452 2453 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, 2454 struct rx_macro *rx, 2455 u16 interp_idx, int event) 2456 { 2457 u16 hph_lut_bypass_reg; 2458 u16 hph_comp_ctrl7; 2459 2460 switch (interp_idx) { 2461 case INTERP_HPHL: 2462 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT; 2463 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7; 2464 break; 2465 case INTERP_HPHR: 2466 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT; 2467 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7; 2468 break; 2469 default: 2470 return -EINVAL; 2471 } 2472 2473 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2474 if (interp_idx == INTERP_HPHL) { 2475 if (rx->is_ear_mode_on) 2476 snd_soc_component_write_field(component, 2477 CDC_RX_RX0_RX_PATH_CFG1, 2478 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1); 2479 else 2480 snd_soc_component_write_field(component, 2481 hph_lut_bypass_reg, 2482 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2483 } else { 2484 snd_soc_component_write_field(component, hph_lut_bypass_reg, 2485 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2486 } 2487 if (rx->hph_pwr_mode) 2488 snd_soc_component_write_field(component, hph_comp_ctrl7, 2489 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0); 2490 } 2491 2492 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2493 snd_soc_component_write_field(component, 2494 CDC_RX_RX0_RX_PATH_CFG1, 2495 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0); 2496 snd_soc_component_update_bits(component, hph_lut_bypass_reg, 2497 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0); 2498 snd_soc_component_write_field(component, hph_comp_ctrl7, 2499 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1); 2500 } 2501 2502 return 0; 2503 } 2504 2505 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 2506 int event, int interp_idx) 2507 { 2508 u16 main_reg, dsm_reg, rx_cfg2_reg; 2509 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2510 2511 main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx); 2512 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx); 2513 if (interp_idx == INTERP_AUX) 2514 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL; 2515 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx); 2516 2517 if (SND_SOC_DAPM_EVENT_ON(event)) { 2518 if (rx->main_clk_users[interp_idx] == 0) { 2519 /* Main path PGA mute enable */ 2520 snd_soc_component_write_field(component, main_reg, 2521 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2522 snd_soc_component_write_field(component, dsm_reg, 2523 CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1); 2524 snd_soc_component_update_bits(component, rx_cfg2_reg, 2525 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03); 2526 rx_macro_load_compander_coeff(component, rx, interp_idx, event); 2527 if (rx->hph_hd2_mode) 2528 rx_macro_hd2_control(component, interp_idx, event); 2529 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2530 rx_macro_config_compander(component, rx, interp_idx, event); 2531 if (interp_idx == INTERP_AUX) { 2532 rx_macro_config_softclip(component, rx, event); 2533 rx_macro_config_aux_hpf(component, rx, event); 2534 } 2535 rx_macro_config_classh(component, rx, interp_idx, event); 2536 } 2537 rx->main_clk_users[interp_idx]++; 2538 } 2539 2540 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2541 rx->main_clk_users[interp_idx]--; 2542 if (rx->main_clk_users[interp_idx] <= 0) { 2543 rx->main_clk_users[interp_idx] = 0; 2544 /* Main path PGA mute enable */ 2545 snd_soc_component_write_field(component, main_reg, 2546 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2547 /* Clk Disable */ 2548 snd_soc_component_write_field(component, dsm_reg, 2549 CDC_RX_RXn_DSM_CLK_EN_MASK, 0); 2550 snd_soc_component_write_field(component, main_reg, 2551 CDC_RX_PATH_CLK_EN_MASK, 0); 2552 /* Reset enable and disable */ 2553 snd_soc_component_write_field(component, main_reg, 2554 CDC_RX_PATH_RESET_EN_MASK, 1); 2555 snd_soc_component_write_field(component, main_reg, 2556 CDC_RX_PATH_RESET_EN_MASK, 0); 2557 /* Reset rate to 48K*/ 2558 snd_soc_component_update_bits(component, main_reg, 2559 CDC_RX_PATH_PCM_RATE_MASK, 2560 0x04); 2561 snd_soc_component_update_bits(component, rx_cfg2_reg, 2562 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00); 2563 rx_macro_config_classh(component, rx, interp_idx, event); 2564 rx_macro_config_compander(component, rx, interp_idx, event); 2565 if (interp_idx == INTERP_AUX) { 2566 rx_macro_config_softclip(component, rx, event); 2567 rx_macro_config_aux_hpf(component, rx, event); 2568 } 2569 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2570 if (rx->hph_hd2_mode) 2571 rx_macro_hd2_control(component, interp_idx, event); 2572 } 2573 } 2574 2575 return rx->main_clk_users[interp_idx]; 2576 } 2577 2578 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 2579 struct snd_kcontrol *kcontrol, int event) 2580 { 2581 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2582 u16 gain_reg, mix_reg; 2583 2584 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift); 2585 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift); 2586 2587 switch (event) { 2588 case SND_SOC_DAPM_PRE_PMU: 2589 rx_macro_enable_interp_clk(component, event, w->shift); 2590 break; 2591 case SND_SOC_DAPM_POST_PMU: 2592 snd_soc_component_write(component, gain_reg, 2593 snd_soc_component_read(component, gain_reg)); 2594 break; 2595 case SND_SOC_DAPM_POST_PMD: 2596 /* Clk Disable */ 2597 snd_soc_component_update_bits(component, mix_reg, 2598 CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00); 2599 rx_macro_enable_interp_clk(component, event, w->shift); 2600 /* Reset enable and disable */ 2601 snd_soc_component_update_bits(component, mix_reg, 2602 CDC_RX_RXn_MIX_RESET_MASK, 2603 CDC_RX_RXn_MIX_RESET); 2604 snd_soc_component_update_bits(component, mix_reg, 2605 CDC_RX_RXn_MIX_RESET_MASK, 0x00); 2606 break; 2607 } 2608 2609 return 0; 2610 } 2611 2612 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, 2613 struct snd_kcontrol *kcontrol, int event) 2614 { 2615 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2616 2617 switch (event) { 2618 case SND_SOC_DAPM_PRE_PMU: 2619 rx_macro_enable_interp_clk(component, event, w->shift); 2620 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift), 2621 CDC_RX_RXn_SIDETONE_EN_MASK, 1); 2622 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift), 2623 CDC_RX_PATH_CLK_EN_MASK, 1); 2624 break; 2625 case SND_SOC_DAPM_POST_PMD: 2626 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift), 2627 CDC_RX_RXn_SIDETONE_EN_MASK, 0); 2628 rx_macro_enable_interp_clk(component, event, w->shift); 2629 break; 2630 default: 2631 break; 2632 } 2633 return 0; 2634 } 2635 2636 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, 2637 struct snd_kcontrol *kcontrol, int event) 2638 { 2639 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2640 2641 switch (event) { 2642 case SND_SOC_DAPM_POST_PMU: /* fall through */ 2643 case SND_SOC_DAPM_PRE_PMD: 2644 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { 2645 snd_soc_component_write(component, 2646 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 2647 snd_soc_component_read(component, 2648 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)); 2649 snd_soc_component_write(component, 2650 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 2651 snd_soc_component_read(component, 2652 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)); 2653 snd_soc_component_write(component, 2654 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 2655 snd_soc_component_read(component, 2656 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)); 2657 snd_soc_component_write(component, 2658 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 2659 snd_soc_component_read(component, 2660 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)); 2661 } else { 2662 snd_soc_component_write(component, 2663 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 2664 snd_soc_component_read(component, 2665 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)); 2666 snd_soc_component_write(component, 2667 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 2668 snd_soc_component_read(component, 2669 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)); 2670 snd_soc_component_write(component, 2671 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 2672 snd_soc_component_read(component, 2673 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)); 2674 snd_soc_component_write(component, 2675 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 2676 snd_soc_component_read(component, 2677 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)); 2678 } 2679 break; 2680 } 2681 return 0; 2682 } 2683 2684 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 2685 int iir_idx, int band_idx, int coeff_idx) 2686 { 2687 u32 value; 2688 int reg, b2_reg; 2689 2690 /* Address does not automatically update if reading */ 2691 reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2692 b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2693 2694 snd_soc_component_write(component, reg, 2695 ((band_idx * BAND_MAX + coeff_idx) * 2696 sizeof(uint32_t)) & 0x7F); 2697 2698 value = snd_soc_component_read(component, b2_reg); 2699 snd_soc_component_write(component, reg, 2700 ((band_idx * BAND_MAX + coeff_idx) 2701 * sizeof(uint32_t) + 1) & 0x7F); 2702 2703 value |= (snd_soc_component_read(component, b2_reg) << 8); 2704 snd_soc_component_write(component, reg, 2705 ((band_idx * BAND_MAX + coeff_idx) 2706 * sizeof(uint32_t) + 2) & 0x7F); 2707 2708 value |= (snd_soc_component_read(component, b2_reg) << 16); 2709 snd_soc_component_write(component, reg, 2710 ((band_idx * BAND_MAX + coeff_idx) 2711 * sizeof(uint32_t) + 3) & 0x7F); 2712 2713 /* Mask bits top 2 bits since they are reserved */ 2714 value |= (snd_soc_component_read(component, b2_reg) << 24); 2715 return value; 2716 } 2717 2718 static void set_iir_band_coeff(struct snd_soc_component *component, 2719 int iir_idx, int band_idx, uint32_t value) 2720 { 2721 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2722 2723 snd_soc_component_write(component, reg, (value & 0xFF)); 2724 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 2725 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 2726 /* Mask top 2 bits, 7-8 are reserved */ 2727 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 2728 } 2729 2730 static int rx_macro_put_iir_band_audio_mixer( 2731 struct snd_kcontrol *kcontrol, 2732 struct snd_ctl_elem_value *ucontrol) 2733 { 2734 struct snd_soc_component *component = 2735 snd_soc_kcontrol_component(kcontrol); 2736 struct wcd_iir_filter_ctl *ctl = 2737 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2738 struct soc_bytes_ext *params = &ctl->bytes_ext; 2739 int iir_idx = ctl->iir_idx; 2740 int band_idx = ctl->band_idx; 2741 u32 coeff[BAND_MAX]; 2742 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2743 2744 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 2745 2746 /* Mask top bit it is reserved */ 2747 /* Updates addr automatically for each B2 write */ 2748 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 2749 sizeof(uint32_t)) & 0x7F); 2750 2751 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 2752 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 2753 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 2754 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 2755 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 2756 2757 return 0; 2758 } 2759 2760 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 2761 struct snd_ctl_elem_value *ucontrol) 2762 { 2763 struct snd_soc_component *component = 2764 snd_soc_kcontrol_component(kcontrol); 2765 struct wcd_iir_filter_ctl *ctl = 2766 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2767 struct soc_bytes_ext *params = &ctl->bytes_ext; 2768 int iir_idx = ctl->iir_idx; 2769 int band_idx = ctl->band_idx; 2770 u32 coeff[BAND_MAX]; 2771 2772 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 2773 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 2774 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 2775 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 2776 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 2777 2778 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 2779 2780 return 0; 2781 } 2782 2783 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol, 2784 struct snd_ctl_elem_info *ucontrol) 2785 { 2786 struct wcd_iir_filter_ctl *ctl = 2787 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2788 struct soc_bytes_ext *params = &ctl->bytes_ext; 2789 2790 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 2791 ucontrol->count = params->max; 2792 2793 return 0; 2794 } 2795 2796 static const struct snd_kcontrol_new rx_macro_snd_controls[] = { 2797 SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL, 2798 -84, 40, digital_gain), 2799 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL, 2800 -84, 40, digital_gain), 2801 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL, 2802 -84, 40, digital_gain), 2803 SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL, 2804 -84, 40, digital_gain), 2805 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL, 2806 -84, 40, digital_gain), 2807 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL, 2808 -84, 40, digital_gain), 2809 2810 SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, 2811 rx_macro_get_compander, rx_macro_set_compander), 2812 SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0, 2813 rx_macro_get_compander, rx_macro_set_compander), 2814 2815 SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0, 2816 rx_macro_get_ear_mode, rx_macro_put_ear_mode), 2817 2818 SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0, 2819 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode), 2820 2821 SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum, 2822 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode), 2823 2824 SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0, 2825 rx_macro_soft_clip_enable_get, 2826 rx_macro_soft_clip_enable_put), 2827 SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0, 2828 rx_macro_aux_hpf_mode_get, 2829 rx_macro_aux_hpf_mode_put), 2830 2831 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 2832 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 2833 digital_gain), 2834 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 2835 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 2836 digital_gain), 2837 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 2838 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 2839 digital_gain), 2840 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 2841 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 2842 digital_gain), 2843 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 2844 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 2845 digital_gain), 2846 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 2847 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 2848 digital_gain), 2849 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 2850 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 2851 digital_gain), 2852 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 2853 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 2854 digital_gain), 2855 2856 SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 2857 0, 1, 0), 2858 SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 2859 1, 1, 0), 2860 SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 2861 2, 1, 0), 2862 SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 2863 3, 1, 0), 2864 SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 2865 4, 1, 0), 2866 SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 2867 0, 1, 0), 2868 SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 2869 1, 1, 0), 2870 SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 2871 2, 1, 0), 2872 SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 2873 3, 1, 0), 2874 SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 2875 4, 1, 0), 2876 2877 RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 2878 RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 2879 RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 2880 RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 2881 RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 2882 2883 RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 2884 RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 2885 RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 2886 RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 2887 RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 2888 2889 }; 2890 2891 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, 2892 struct snd_kcontrol *kcontrol, 2893 int event) 2894 { 2895 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2896 u16 val, ec_hq_reg; 2897 int ec_tx = -1; 2898 2899 val = snd_soc_component_read(component, 2900 CDC_RX_INP_MUX_RX_MIX_CFG4); 2901 if (!(strcmp(w->name, "RX MIX TX0 MUX"))) 2902 ec_tx = ((val & 0xf0) >> 0x4) - 1; 2903 else if (!(strcmp(w->name, "RX MIX TX1 MUX"))) 2904 ec_tx = (val & 0x0f) - 1; 2905 2906 val = snd_soc_component_read(component, 2907 CDC_RX_INP_MUX_RX_MIX_CFG5); 2908 if (!(strcmp(w->name, "RX MIX TX2 MUX"))) 2909 ec_tx = (val & 0x0f) - 1; 2910 2911 if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) { 2912 dev_err(component->dev, "%s: EC mix control not set correctly\n", 2913 __func__); 2914 return -EINVAL; 2915 } 2916 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL + 2917 0x40 * ec_tx; 2918 snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); 2919 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 + 2920 0x40 * ec_tx; 2921 /* default set to 48k */ 2922 snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); 2923 2924 return 0; 2925 } 2926 2927 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { 2928 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0, 2929 SND_SOC_NOPM, 0, 0), 2930 2931 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0, 2932 SND_SOC_NOPM, 0, 0), 2933 2934 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0, 2935 SND_SOC_NOPM, 0, 0), 2936 2937 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0, 2938 SND_SOC_NOPM, 0, 0), 2939 2940 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0, 2941 SND_SOC_NOPM, 0, 0), 2942 2943 SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0, 2944 &rx_macro_rx0_mux), 2945 SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0, 2946 &rx_macro_rx1_mux), 2947 SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0, 2948 &rx_macro_rx2_mux), 2949 SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0, 2950 &rx_macro_rx3_mux), 2951 SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0, 2952 &rx_macro_rx4_mux), 2953 SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0, 2954 &rx_macro_rx5_mux), 2955 2956 SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 2957 SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 2958 SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 2959 SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 2960 SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 2961 SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 2962 2963 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 2964 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 2965 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 2966 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 2967 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 2968 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 2969 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 2970 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 2971 2972 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM, 2973 RX_MACRO_EC0_MUX, 0, 2974 &rx_mix_tx0_mux, rx_macro_enable_echo, 2975 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2976 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM, 2977 RX_MACRO_EC1_MUX, 0, 2978 &rx_mix_tx1_mux, rx_macro_enable_echo, 2979 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2980 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM, 2981 RX_MACRO_EC2_MUX, 0, 2982 &rx_mix_tx2_mux, rx_macro_enable_echo, 2983 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2984 2985 SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 2986 4, 0, NULL, 0, rx_macro_set_iir_gain, 2987 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2988 SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 2989 4, 0, NULL, 0, rx_macro_set_iir_gain, 2990 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2991 SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 2992 4, 0, NULL, 0), 2993 SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 2994 4, 0, NULL, 0), 2995 2996 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 2997 &rx_int0_dem_inp_mux), 2998 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 2999 &rx_int1_dem_inp_mux), 3000 3001 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 3002 &rx_int0_2_mux, rx_macro_enable_mix_path, 3003 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3004 SND_SOC_DAPM_POST_PMD), 3005 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 3006 &rx_int1_2_mux, rx_macro_enable_mix_path, 3007 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3008 SND_SOC_DAPM_POST_PMD), 3009 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0, 3010 &rx_int2_2_mux, rx_macro_enable_mix_path, 3011 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3012 SND_SOC_DAPM_POST_PMD), 3013 3014 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux), 3015 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux), 3016 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux), 3017 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux), 3018 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux), 3019 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux), 3020 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux), 3021 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux), 3022 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux), 3023 3024 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 3025 &rx_int0_1_interp_mux, rx_macro_enable_main_path, 3026 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3027 SND_SOC_DAPM_POST_PMD), 3028 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 3029 &rx_int1_1_interp_mux, rx_macro_enable_main_path, 3030 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3031 SND_SOC_DAPM_POST_PMD), 3032 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0, 3033 &rx_int2_1_interp_mux, rx_macro_enable_main_path, 3034 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3035 SND_SOC_DAPM_POST_PMD), 3036 3037 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 3038 &rx_int0_2_interp_mux), 3039 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 3040 &rx_int1_2_interp_mux), 3041 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 3042 &rx_int2_2_interp_mux), 3043 3044 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3045 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3046 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3047 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3048 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3049 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3050 3051 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL, 3052 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3053 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3054 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR, 3055 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3056 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3057 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX, 3058 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3059 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3060 3061 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3062 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3063 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3064 3065 SND_SOC_DAPM_OUTPUT("HPHL_OUT"), 3066 SND_SOC_DAPM_OUTPUT("HPHR_OUT"), 3067 SND_SOC_DAPM_OUTPUT("AUX_OUT"), 3068 3069 SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"), 3070 SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"), 3071 SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"), 3072 SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"), 3073 3074 SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0, 3075 rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3076 }; 3077 3078 static const struct snd_soc_dapm_route rx_audio_map[] = { 3079 {"RX AIF1 PB", NULL, "RX_MCLK"}, 3080 {"RX AIF2 PB", NULL, "RX_MCLK"}, 3081 {"RX AIF3 PB", NULL, "RX_MCLK"}, 3082 {"RX AIF4 PB", NULL, "RX_MCLK"}, 3083 3084 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"}, 3085 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"}, 3086 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"}, 3087 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"}, 3088 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"}, 3089 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"}, 3090 3091 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"}, 3092 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"}, 3093 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"}, 3094 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"}, 3095 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"}, 3096 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"}, 3097 3098 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"}, 3099 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"}, 3100 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"}, 3101 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"}, 3102 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"}, 3103 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"}, 3104 3105 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"}, 3106 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"}, 3107 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"}, 3108 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"}, 3109 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"}, 3110 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"}, 3111 3112 {"RX_RX0", NULL, "RX_MACRO RX0 MUX"}, 3113 {"RX_RX1", NULL, "RX_MACRO RX1 MUX"}, 3114 {"RX_RX2", NULL, "RX_MACRO RX2 MUX"}, 3115 {"RX_RX3", NULL, "RX_MACRO RX3 MUX"}, 3116 {"RX_RX4", NULL, "RX_MACRO RX4 MUX"}, 3117 {"RX_RX5", NULL, "RX_MACRO RX5 MUX"}, 3118 3119 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"}, 3120 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"}, 3121 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"}, 3122 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"}, 3123 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"}, 3124 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"}, 3125 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"}, 3126 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"}, 3127 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3128 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3129 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"}, 3130 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"}, 3131 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"}, 3132 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"}, 3133 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"}, 3134 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"}, 3135 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"}, 3136 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"}, 3137 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3138 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3139 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"}, 3140 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"}, 3141 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"}, 3142 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"}, 3143 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"}, 3144 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"}, 3145 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"}, 3146 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"}, 3147 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3148 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3149 3150 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"}, 3151 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"}, 3152 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"}, 3153 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"}, 3154 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"}, 3155 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"}, 3156 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"}, 3157 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"}, 3158 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3159 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3160 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"}, 3161 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"}, 3162 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"}, 3163 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"}, 3164 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"}, 3165 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"}, 3166 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"}, 3167 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"}, 3168 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3169 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3170 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"}, 3171 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"}, 3172 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"}, 3173 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"}, 3174 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"}, 3175 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"}, 3176 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"}, 3177 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"}, 3178 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3179 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3180 3181 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"}, 3182 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"}, 3183 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"}, 3184 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"}, 3185 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"}, 3186 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"}, 3187 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"}, 3188 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"}, 3189 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3190 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3191 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"}, 3192 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"}, 3193 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"}, 3194 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"}, 3195 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"}, 3196 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"}, 3197 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"}, 3198 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"}, 3199 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3200 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3201 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"}, 3202 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"}, 3203 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"}, 3204 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"}, 3205 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"}, 3206 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"}, 3207 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"}, 3208 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"}, 3209 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3210 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3211 3212 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"}, 3213 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"}, 3214 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"}, 3215 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"}, 3216 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"}, 3217 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"}, 3218 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"}, 3219 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"}, 3220 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"}, 3221 3222 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3223 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3224 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3225 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3226 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3227 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3228 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3229 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3230 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3231 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"}, 3232 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"}, 3233 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"}, 3234 {"RX AIF_ECHO", NULL, "RX_MCLK"}, 3235 3236 /* Mixing path INT0 */ 3237 {"RX INT0_2 MUX", "RX0", "RX_RX0"}, 3238 {"RX INT0_2 MUX", "RX1", "RX_RX1"}, 3239 {"RX INT0_2 MUX", "RX2", "RX_RX2"}, 3240 {"RX INT0_2 MUX", "RX3", "RX_RX3"}, 3241 {"RX INT0_2 MUX", "RX4", "RX_RX4"}, 3242 {"RX INT0_2 MUX", "RX5", "RX_RX5"}, 3243 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"}, 3244 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"}, 3245 3246 /* Mixing path INT1 */ 3247 {"RX INT1_2 MUX", "RX0", "RX_RX0"}, 3248 {"RX INT1_2 MUX", "RX1", "RX_RX1"}, 3249 {"RX INT1_2 MUX", "RX2", "RX_RX2"}, 3250 {"RX INT1_2 MUX", "RX3", "RX_RX3"}, 3251 {"RX INT1_2 MUX", "RX4", "RX_RX4"}, 3252 {"RX INT1_2 MUX", "RX5", "RX_RX5"}, 3253 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"}, 3254 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"}, 3255 3256 /* Mixing path INT2 */ 3257 {"RX INT2_2 MUX", "RX0", "RX_RX0"}, 3258 {"RX INT2_2 MUX", "RX1", "RX_RX1"}, 3259 {"RX INT2_2 MUX", "RX2", "RX_RX2"}, 3260 {"RX INT2_2 MUX", "RX3", "RX_RX3"}, 3261 {"RX INT2_2 MUX", "RX4", "RX_RX4"}, 3262 {"RX INT2_2 MUX", "RX5", "RX_RX5"}, 3263 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"}, 3264 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"}, 3265 3266 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"}, 3267 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"}, 3268 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"}, 3269 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"}, 3270 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 3271 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"}, 3272 {"HPHL_OUT", NULL, "RX_MCLK"}, 3273 3274 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"}, 3275 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"}, 3276 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"}, 3277 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"}, 3278 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"}, 3279 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"}, 3280 {"HPHR_OUT", NULL, "RX_MCLK"}, 3281 3282 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"}, 3283 3284 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"}, 3285 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"}, 3286 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"}, 3287 {"AUX_OUT", NULL, "RX INT2 MIX2"}, 3288 {"AUX_OUT", NULL, "RX_MCLK"}, 3289 3290 {"IIR0", NULL, "RX_MCLK"}, 3291 {"IIR0", NULL, "IIR0 INP0 MUX"}, 3292 {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3293 {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3294 {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3295 {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3296 {"IIR0 INP0 MUX", "RX0", "RX_RX0"}, 3297 {"IIR0 INP0 MUX", "RX1", "RX_RX1"}, 3298 {"IIR0 INP0 MUX", "RX2", "RX_RX2"}, 3299 {"IIR0 INP0 MUX", "RX3", "RX_RX3"}, 3300 {"IIR0 INP0 MUX", "RX4", "RX_RX4"}, 3301 {"IIR0 INP0 MUX", "RX5", "RX_RX5"}, 3302 {"IIR0", NULL, "IIR0 INP1 MUX"}, 3303 {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3304 {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3305 {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3306 {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3307 {"IIR0 INP1 MUX", "RX0", "RX_RX0"}, 3308 {"IIR0 INP1 MUX", "RX1", "RX_RX1"}, 3309 {"IIR0 INP1 MUX", "RX2", "RX_RX2"}, 3310 {"IIR0 INP1 MUX", "RX3", "RX_RX3"}, 3311 {"IIR0 INP1 MUX", "RX4", "RX_RX4"}, 3312 {"IIR0 INP1 MUX", "RX5", "RX_RX5"}, 3313 {"IIR0", NULL, "IIR0 INP2 MUX"}, 3314 {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3315 {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3316 {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3317 {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3318 {"IIR0 INP2 MUX", "RX0", "RX_RX0"}, 3319 {"IIR0 INP2 MUX", "RX1", "RX_RX1"}, 3320 {"IIR0 INP2 MUX", "RX2", "RX_RX2"}, 3321 {"IIR0 INP2 MUX", "RX3", "RX_RX3"}, 3322 {"IIR0 INP2 MUX", "RX4", "RX_RX4"}, 3323 {"IIR0 INP2 MUX", "RX5", "RX_RX5"}, 3324 {"IIR0", NULL, "IIR0 INP3 MUX"}, 3325 {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3326 {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3327 {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3328 {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3329 {"IIR0 INP3 MUX", "RX0", "RX_RX0"}, 3330 {"IIR0 INP3 MUX", "RX1", "RX_RX1"}, 3331 {"IIR0 INP3 MUX", "RX2", "RX_RX2"}, 3332 {"IIR0 INP3 MUX", "RX3", "RX_RX3"}, 3333 {"IIR0 INP3 MUX", "RX4", "RX_RX4"}, 3334 {"IIR0 INP3 MUX", "RX5", "RX_RX5"}, 3335 3336 {"IIR1", NULL, "RX_MCLK"}, 3337 {"IIR1", NULL, "IIR1 INP0 MUX"}, 3338 {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3339 {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3340 {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3341 {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3342 {"IIR1 INP0 MUX", "RX0", "RX_RX0"}, 3343 {"IIR1 INP0 MUX", "RX1", "RX_RX1"}, 3344 {"IIR1 INP0 MUX", "RX2", "RX_RX2"}, 3345 {"IIR1 INP0 MUX", "RX3", "RX_RX3"}, 3346 {"IIR1 INP0 MUX", "RX4", "RX_RX4"}, 3347 {"IIR1 INP0 MUX", "RX5", "RX_RX5"}, 3348 {"IIR1", NULL, "IIR1 INP1 MUX"}, 3349 {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3350 {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3351 {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3352 {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3353 {"IIR1 INP1 MUX", "RX0", "RX_RX0"}, 3354 {"IIR1 INP1 MUX", "RX1", "RX_RX1"}, 3355 {"IIR1 INP1 MUX", "RX2", "RX_RX2"}, 3356 {"IIR1 INP1 MUX", "RX3", "RX_RX3"}, 3357 {"IIR1 INP1 MUX", "RX4", "RX_RX4"}, 3358 {"IIR1 INP1 MUX", "RX5", "RX_RX5"}, 3359 {"IIR1", NULL, "IIR1 INP2 MUX"}, 3360 {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3361 {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3362 {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3363 {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3364 {"IIR1 INP2 MUX", "RX0", "RX_RX0"}, 3365 {"IIR1 INP2 MUX", "RX1", "RX_RX1"}, 3366 {"IIR1 INP2 MUX", "RX2", "RX_RX2"}, 3367 {"IIR1 INP2 MUX", "RX3", "RX_RX3"}, 3368 {"IIR1 INP2 MUX", "RX4", "RX_RX4"}, 3369 {"IIR1 INP2 MUX", "RX5", "RX_RX5"}, 3370 {"IIR1", NULL, "IIR1 INP3 MUX"}, 3371 {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3372 {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3373 {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3374 {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3375 {"IIR1 INP3 MUX", "RX0", "RX_RX0"}, 3376 {"IIR1 INP3 MUX", "RX1", "RX_RX1"}, 3377 {"IIR1 INP3 MUX", "RX2", "RX_RX2"}, 3378 {"IIR1 INP3 MUX", "RX3", "RX_RX3"}, 3379 {"IIR1 INP3 MUX", "RX4", "RX_RX4"}, 3380 {"IIR1 INP3 MUX", "RX5", "RX_RX5"}, 3381 3382 {"SRC0", NULL, "IIR0"}, 3383 {"SRC1", NULL, "IIR1"}, 3384 {"RX INT0 MIX2 INP", "SRC0", "SRC0"}, 3385 {"RX INT0 MIX2 INP", "SRC1", "SRC1"}, 3386 {"RX INT1 MIX2 INP", "SRC0", "SRC0"}, 3387 {"RX INT1 MIX2 INP", "SRC1", "SRC1"}, 3388 {"RX INT2 MIX2 INP", "SRC0", "SRC0"}, 3389 {"RX INT2 MIX2 INP", "SRC1", "SRC1"}, 3390 }; 3391 3392 static int rx_macro_component_probe(struct snd_soc_component *component) 3393 { 3394 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 3395 3396 snd_soc_component_init_regmap(component, rx->regmap); 3397 3398 snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7, 3399 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3400 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3401 snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7, 3402 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3403 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3404 snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7, 3405 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3406 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3407 snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3, 3408 CDC_RX_DC_COEFF_SEL_MASK, 3409 CDC_RX_DC_COEFF_SEL_TWO); 3410 snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3, 3411 CDC_RX_DC_COEFF_SEL_MASK, 3412 CDC_RX_DC_COEFF_SEL_TWO); 3413 snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3, 3414 CDC_RX_DC_COEFF_SEL_MASK, 3415 CDC_RX_DC_COEFF_SEL_TWO); 3416 3417 rx->component = component; 3418 3419 return 0; 3420 } 3421 3422 static int swclk_gate_enable(struct clk_hw *hw) 3423 { 3424 struct rx_macro *rx = to_rx_macro(hw); 3425 3426 rx_macro_mclk_enable(rx, true); 3427 if (rx->reset_swr) 3428 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3429 CDC_RX_SWR_RESET_MASK, 3430 CDC_RX_SWR_RESET); 3431 3432 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3433 CDC_RX_SWR_CLK_EN_MASK, 1); 3434 3435 if (rx->reset_swr) 3436 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3437 CDC_RX_SWR_RESET_MASK, 0); 3438 rx->reset_swr = false; 3439 3440 return 0; 3441 } 3442 3443 static void swclk_gate_disable(struct clk_hw *hw) 3444 { 3445 struct rx_macro *rx = to_rx_macro(hw); 3446 3447 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3448 CDC_RX_SWR_CLK_EN_MASK, 0); 3449 3450 rx_macro_mclk_enable(rx, false); 3451 } 3452 3453 static int swclk_gate_is_enabled(struct clk_hw *hw) 3454 { 3455 struct rx_macro *rx = to_rx_macro(hw); 3456 int ret, val; 3457 3458 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); 3459 ret = val & BIT(0); 3460 3461 return ret; 3462 } 3463 3464 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 3465 unsigned long parent_rate) 3466 { 3467 return parent_rate / 2; 3468 } 3469 3470 static const struct clk_ops swclk_gate_ops = { 3471 .prepare = swclk_gate_enable, 3472 .unprepare = swclk_gate_disable, 3473 .is_enabled = swclk_gate_is_enabled, 3474 .recalc_rate = swclk_recalc_rate, 3475 3476 }; 3477 3478 static struct clk *rx_macro_register_mclk_output(struct rx_macro *rx) 3479 { 3480 struct device *dev = rx->dev; 3481 struct device_node *np = dev->of_node; 3482 const char *parent_clk_name = NULL; 3483 const char *clk_name = "lpass-rx-mclk"; 3484 struct clk_hw *hw; 3485 struct clk_init_data init; 3486 int ret; 3487 3488 parent_clk_name = __clk_get_name(rx->clks[2].clk); 3489 3490 init.name = clk_name; 3491 init.ops = &swclk_gate_ops; 3492 init.flags = 0; 3493 init.parent_names = &parent_clk_name; 3494 init.num_parents = 1; 3495 rx->hw.init = &init; 3496 hw = &rx->hw; 3497 ret = clk_hw_register(rx->dev, hw); 3498 if (ret) 3499 return ERR_PTR(ret); 3500 3501 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); 3502 3503 return NULL; 3504 } 3505 3506 static const struct snd_soc_component_driver rx_macro_component_drv = { 3507 .name = "RX-MACRO", 3508 .probe = rx_macro_component_probe, 3509 .controls = rx_macro_snd_controls, 3510 .num_controls = ARRAY_SIZE(rx_macro_snd_controls), 3511 .dapm_widgets = rx_macro_dapm_widgets, 3512 .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets), 3513 .dapm_routes = rx_audio_map, 3514 .num_dapm_routes = ARRAY_SIZE(rx_audio_map), 3515 }; 3516 3517 static int rx_macro_probe(struct platform_device *pdev) 3518 { 3519 struct device *dev = &pdev->dev; 3520 struct rx_macro *rx; 3521 void __iomem *base; 3522 int ret; 3523 3524 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); 3525 if (!rx) 3526 return -ENOMEM; 3527 3528 rx->clks[0].id = "macro"; 3529 rx->clks[1].id = "dcodec"; 3530 rx->clks[2].id = "mclk"; 3531 rx->clks[3].id = "npl"; 3532 rx->clks[4].id = "fsgen"; 3533 3534 ret = devm_clk_bulk_get_optional(dev, RX_NUM_CLKS_MAX, rx->clks); 3535 if (ret) { 3536 dev_err(dev, "Error getting RX Clocks (%d)\n", ret); 3537 return ret; 3538 } 3539 3540 base = devm_platform_ioremap_resource(pdev, 0); 3541 if (IS_ERR(base)) 3542 return PTR_ERR(base); 3543 3544 rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config); 3545 3546 dev_set_drvdata(dev, rx); 3547 3548 rx->reset_swr = true; 3549 rx->dev = dev; 3550 3551 /* set MCLK and NPL rates */ 3552 clk_set_rate(rx->clks[2].clk, MCLK_FREQ); 3553 clk_set_rate(rx->clks[3].clk, 2 * MCLK_FREQ); 3554 3555 ret = clk_bulk_prepare_enable(RX_NUM_CLKS_MAX, rx->clks); 3556 if (ret) 3557 return ret; 3558 3559 rx_macro_register_mclk_output(rx); 3560 3561 ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv, 3562 rx_macro_dai, 3563 ARRAY_SIZE(rx_macro_dai)); 3564 if (ret) 3565 clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks); 3566 3567 return ret; 3568 } 3569 3570 static int rx_macro_remove(struct platform_device *pdev) 3571 { 3572 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); 3573 3574 of_clk_del_provider(pdev->dev.of_node); 3575 clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks); 3576 return 0; 3577 } 3578 3579 static const struct of_device_id rx_macro_dt_match[] = { 3580 { .compatible = "qcom,sc7280-lpass-rx-macro" }, 3581 { .compatible = "qcom,sm8250-lpass-rx-macro" }, 3582 { } 3583 }; 3584 MODULE_DEVICE_TABLE(of, rx_macro_dt_match); 3585 3586 static struct platform_driver rx_macro_driver = { 3587 .driver = { 3588 .name = "rx_macro", 3589 .of_match_table = rx_macro_dt_match, 3590 .suppress_bind_attrs = true, 3591 }, 3592 .probe = rx_macro_probe, 3593 .remove = rx_macro_remove, 3594 }; 3595 3596 module_platform_driver(rx_macro_driver); 3597 3598 MODULE_DESCRIPTION("RX macro driver"); 3599 MODULE_LICENSE("GPL"); 3600