1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/platform_device.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/clk.h> 10 #include <sound/soc.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc-dapm.h> 14 #include <sound/tlv.h> 15 #include <linux/of_clk.h> 16 #include <linux/clk-provider.h> 17 18 #include "lpass-macro-common.h" 19 20 #define CDC_RX_TOP_TOP_CFG0 (0x0000) 21 #define CDC_RX_TOP_SWR_CTRL (0x0008) 22 #define CDC_RX_TOP_DEBUG (0x000C) 23 #define CDC_RX_TOP_DEBUG_BUS (0x0010) 24 #define CDC_RX_TOP_DEBUG_EN0 (0x0014) 25 #define CDC_RX_TOP_DEBUG_EN1 (0x0018) 26 #define CDC_RX_TOP_DEBUG_EN2 (0x001C) 27 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020) 28 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024) 29 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028) 30 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7) 31 #define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C) 32 #define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030) 33 #define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034) 34 #define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038) 35 #define CDC_RX_TOP_HPHR_COMP_LUT (0x003C) 36 #define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040) 37 #define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044) 38 #define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070) 39 #define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074) 40 #define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078) 41 #define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C) 42 #define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080) 43 #define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084) 44 #define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088) 45 #define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C) 46 #define CDC_RX_TOP_RX_I2S_CTL (0x0090) 47 #define CDC_RX_TOP_TX_I2S2_CTL (0x0094) 48 #define CDC_RX_TOP_I2S_CLK (0x0098) 49 #define CDC_RX_TOP_I2S_RESET (0x009C) 50 #define CDC_RX_TOP_I2S_MUX (0x00A0) 51 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100) 52 #define CDC_RX_CLK_MCLK_EN_MASK BIT(0) 53 #define CDC_RX_CLK_MCLK_ENABLE BIT(0) 54 #define CDC_RX_CLK_MCLK2_EN_MASK BIT(1) 55 #define CDC_RX_CLK_MCLK2_ENABLE BIT(1) 56 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104) 57 #define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0) 58 #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0) 59 #define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1) 60 #define CDC_RX_FS_MCLK_CNT_CLR BIT(1) 61 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108) 62 #define CDC_RX_SWR_CLK_EN_MASK BIT(0) 63 #define CDC_RX_SWR_RESET_MASK BIT(1) 64 #define CDC_RX_SWR_RESET BIT(1) 65 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C) 66 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110) 67 #define CDC_RX_SOFTCLIP_CRC (0x0140) 68 #define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0) 69 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144) 70 #define CDC_RX_SOFTCLIP_EN_MASK BIT(0) 71 #define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180) 72 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0) 73 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4) 74 #define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184) 75 #define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0) 76 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4) 77 #define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188) 78 #define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C) 79 #define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190) 80 #define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194) 81 #define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198) 82 #define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C) 83 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0) 84 #define CDC_RX_CLSH_CRC (0x0200) 85 #define CDC_RX_CLSH_CLK_EN_MASK BIT(0) 86 #define CDC_RX_CLSH_DLY_CTRL (0x0204) 87 #define CDC_RX_CLSH_DECAY_CTRL (0x0208) 88 #define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0) 89 #define CDC_RX_CLSH_HPH_V_PA (0x020C) 90 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0) 91 #define CDC_RX_CLSH_EAR_V_PA (0x0210) 92 #define CDC_RX_CLSH_HPH_V_HD (0x0214) 93 #define CDC_RX_CLSH_EAR_V_HD (0x0218) 94 #define CDC_RX_CLSH_K1_MSB (0x021C) 95 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0) 96 #define CDC_RX_CLSH_K1_LSB (0x0220) 97 #define CDC_RX_CLSH_K2_MSB (0x0224) 98 #define CDC_RX_CLSH_K2_LSB (0x0228) 99 #define CDC_RX_CLSH_IDLE_CTRL (0x022C) 100 #define CDC_RX_CLSH_IDLE_HPH (0x0230) 101 #define CDC_RX_CLSH_IDLE_EAR (0x0234) 102 #define CDC_RX_CLSH_TEST0 (0x0238) 103 #define CDC_RX_CLSH_TEST1 (0x023C) 104 #define CDC_RX_CLSH_OVR_VREF (0x0240) 105 #define CDC_RX_CLSH_CLSG_CTL (0x0244) 106 #define CDC_RX_CLSH_CLSG_CFG1 (0x0248) 107 #define CDC_RX_CLSH_CLSG_CFG2 (0x024C) 108 #define CDC_RX_BCL_VBAT_PATH_CTL (0x0280) 109 #define CDC_RX_BCL_VBAT_CFG (0x0284) 110 #define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288) 111 #define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C) 112 #define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290) 113 #define CDC_RX_BCL_VBAT_PK_EST1 (0x0294) 114 #define CDC_RX_BCL_VBAT_PK_EST2 (0x0298) 115 #define CDC_RX_BCL_VBAT_PK_EST3 (0x029C) 116 #define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0) 117 #define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4) 118 #define CDC_RX_BCL_VBAT_TAC1 (0x02A8) 119 #define CDC_RX_BCL_VBAT_TAC2 (0x02AC) 120 #define CDC_RX_BCL_VBAT_TAC3 (0x02B0) 121 #define CDC_RX_BCL_VBAT_TAC4 (0x02B4) 122 #define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8) 123 #define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC) 124 #define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0) 125 #define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4) 126 #define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8) 127 #define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC) 128 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0) 129 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4) 130 #define CDC_RX_BCL_VBAT_BAN (0x02D8) 131 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC) 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0) 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4) 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8) 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC) 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0) 137 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4) 138 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8) 139 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC) 140 #define CDC_RX_BCL_VBAT_ATTN1 (0x0300) 141 #define CDC_RX_BCL_VBAT_ATTN2 (0x0304) 142 #define CDC_RX_BCL_VBAT_ATTN3 (0x0308) 143 #define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C) 144 #define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310) 145 #define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314) 146 #define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318) 147 #define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C) 148 #define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320) 149 #define CDC_RX_BCL_VBAT_DECODE_ST (0x0324) 150 #define CDC_RX_INTR_CTRL_CFG (0x0340) 151 #define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344) 152 #define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360) 153 #define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368) 154 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370) 155 #define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380) 156 #define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388) 157 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390) 158 #define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0) 159 #define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8) 160 #define CDC_RX_INTR_CTRL_SET0 (0x03D0) 161 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n) 162 #define CDC_RX_RX0_RX_PATH_CTL (0x0400) 163 #define CDC_RX_PATH_RESET_EN_MASK BIT(6) 164 #define CDC_RX_PATH_CLK_EN_MASK BIT(5) 165 #define CDC_RX_PATH_CLK_ENABLE BIT(5) 166 #define CDC_RX_PATH_PGA_MUTE_MASK BIT(4) 167 #define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4) 168 #define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0) 169 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n) 170 #define CDC_RX_RXn_COMP_EN_MASK BIT(1) 171 #define CDC_RX_RX0_RX_PATH_CFG0 (0x0404) 172 #define CDC_RX_RXn_CLSH_EN_MASK BIT(6) 173 #define CDC_RX_DLY_ZN_EN_MASK BIT(3) 174 #define CDC_RX_DLY_ZN_ENABLE BIT(3) 175 #define CDC_RX_RXn_HD2_EN_MASK BIT(2) 176 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n) 177 #define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4) 178 #define CDC_RX_RX0_RX_PATH_CFG1 (0x0408) 179 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1) 180 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n) 181 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0) 182 #define CDC_RX_RX0_RX_PATH_CFG2 (0x040C) 183 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n) 184 #define CDC_RX_RX0_RX_PATH_CFG3 (0x0410) 185 #define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0) 186 #define CDC_RX_DC_COEFF_SEL_TWO 0x2 187 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n) 188 #define CDC_RX_RX0_RX_VOL_CTL (0x0414) 189 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n) 190 #define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0) 191 #define CDC_RX_RXn_MIX_RESET_MASK BIT(6) 192 #define CDC_RX_RXn_MIX_RESET BIT(6) 193 #define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5) 194 #define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418) 195 #define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C) 196 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n) 197 #define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420) 198 #define CDC_RX_RX0_RX_PATH_SEC1 (0x0424) 199 #define CDC_RX_RX0_RX_PATH_SEC2 (0x0428) 200 #define CDC_RX_RX0_RX_PATH_SEC3 (0x042C) 201 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n) 202 #define CDC_RX_RX0_RX_PATH_SEC4 (0x0430) 203 #define CDC_RX_RX0_RX_PATH_SEC7 (0x0434) 204 #define CDC_RX_RXn_RX_PATH_SEC7(rx, n) (0x0434 + rx->rxn_reg_stride * n) 205 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0) 206 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2 207 #define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438) 208 #define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C) 209 #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) (0x0440 + rx->rxn_reg_stride * n) 210 #define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0) 211 #define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440) 212 #define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444) 213 #define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448) 214 #define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C) 215 #define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450) 216 #define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454) 217 #define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458) 218 /* RX offsets prior to 2.5 codec version */ 219 #define CDC_RX_RX1_RX_PATH_CTL (0x0480) 220 #define CDC_RX_RX1_RX_PATH_CFG0 (0x0484) 221 #define CDC_RX_RX1_RX_PATH_CFG1 (0x0488) 222 #define CDC_RX_RX1_RX_PATH_CFG2 (0x048C) 223 #define CDC_RX_RX1_RX_PATH_CFG3 (0x0490) 224 #define CDC_RX_RX1_RX_VOL_CTL (0x0494) 225 #define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498) 226 #define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C) 227 #define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0) 228 #define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4) 229 #define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8) 230 #define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC) 231 #define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2) 232 #define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0) 233 #define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4) 234 #define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8) 235 #define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC) 236 #define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0) 237 #define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4) 238 #define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8) 239 #define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC) 240 #define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0) 241 #define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4) 242 #define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8) 243 #define CDC_RX_RX2_RX_PATH_CTL (0x0500) 244 #define CDC_RX_RX2_RX_PATH_CFG0 (0x0504) 245 #define CDC_RX_RX2_CLSH_EN_MASK BIT(4) 246 #define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3) 247 #define CDC_RX_RX2_RX_PATH_CFG1 (0x0508) 248 #define CDC_RX_RX2_RX_PATH_CFG2 (0x050C) 249 #define CDC_RX_RX2_RX_PATH_CFG3 (0x0510) 250 #define CDC_RX_RX2_RX_VOL_CTL (0x0514) 251 #define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518) 252 #define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C) 253 #define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520) 254 #define CDC_RX_RX2_RX_PATH_SEC0 (0x0524) 255 #define CDC_RX_RX2_RX_PATH_SEC1 (0x0528) 256 #define CDC_RX_RX2_RX_PATH_SEC2 (0x052C) 257 #define CDC_RX_RX2_RX_PATH_SEC3 (0x0530) 258 #define CDC_RX_RX2_RX_PATH_SEC4 (0x0534) 259 #define CDC_RX_RX2_RX_PATH_SEC5 (0x0538) 260 #define CDC_RX_RX2_RX_PATH_SEC6 (0x053C) 261 #define CDC_RX_RX2_RX_PATH_SEC7 (0x0540) 262 #define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544) 263 #define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548) 264 #define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C) 265 266 /* LPASS CODEC version 2.5 rx reg offsets */ 267 #define CDC_2_5_RX_RX1_RX_PATH_CTL (0x04c0) 268 #define CDC_2_5_RX_RX1_RX_PATH_CFG0 (0x04c4) 269 #define CDC_2_5_RX_RX1_RX_PATH_CFG1 (0x04c8) 270 #define CDC_2_5_RX_RX1_RX_PATH_CFG2 (0x04cC) 271 #define CDC_2_5_RX_RX1_RX_PATH_CFG3 (0x04d0) 272 #define CDC_2_5_RX_RX1_RX_VOL_CTL (0x04d4) 273 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL (0x04d8) 274 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG (0x04dC) 275 #define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL (0x04e0) 276 #define CDC_2_5_RX_RX1_RX_PATH_SEC1 (0x04e4) 277 #define CDC_2_5_RX_RX1_RX_PATH_SEC2 (0x04e8) 278 #define CDC_2_5_RX_RX1_RX_PATH_SEC3 (0x04eC) 279 #define CDC_2_5_RX_RX1_RX_PATH_SEC4 (0x04f0) 280 #define CDC_2_5_RX_RX1_RX_PATH_SEC7 (0x04f4) 281 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0 (0x04f8) 282 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1 (0x04fC) 283 #define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL (0x0500) 284 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1 (0x0504) 285 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2 (0x0508) 286 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3 (0x050C) 287 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4 (0x0510) 288 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5 (0x0514) 289 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6 (0x0518) 290 291 #define CDC_2_5_RX_RX2_RX_PATH_CTL (0x0580) 292 #define CDC_2_5_RX_RX2_RX_PATH_CFG0 (0x0584) 293 #define CDC_2_5_RX_RX2_RX_PATH_CFG1 (0x0588) 294 #define CDC_2_5_RX_RX2_RX_PATH_CFG2 (0x058C) 295 #define CDC_2_5_RX_RX2_RX_PATH_CFG3 (0x0590) 296 #define CDC_2_5_RX_RX2_RX_VOL_CTL (0x0594) 297 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL (0x0598) 298 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG (0x059C) 299 #define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL (0x05a0) 300 #define CDC_2_5_RX_RX2_RX_PATH_SEC0 (0x05a4) 301 #define CDC_2_5_RX_RX2_RX_PATH_SEC1 (0x05a8) 302 #define CDC_2_5_RX_RX2_RX_PATH_SEC2 (0x05aC) 303 #define CDC_2_5_RX_RX2_RX_PATH_SEC3 (0x05b0) 304 #define CDC_2_5_RX_RX2_RX_PATH_SEC4 (0x05b4) 305 #define CDC_2_5_RX_RX2_RX_PATH_SEC5 (0x05b8) 306 #define CDC_2_5_RX_RX2_RX_PATH_SEC6 (0x05bC) 307 #define CDC_2_5_RX_RX2_RX_PATH_SEC7 (0x05c0) 308 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0 (0x05c4) 309 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1 (0x05c8) 310 #define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL (0x05cC) 311 312 #define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780) 313 #define CDC_RX_IDLE_DETECT_CFG0 (0x0784) 314 #define CDC_RX_IDLE_DETECT_CFG1 (0x0788) 315 #define CDC_RX_IDLE_DETECT_CFG2 (0x078C) 316 #define CDC_RX_IDLE_DETECT_CFG3 (0x0790) 317 #define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n) 318 #define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0) 319 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1) 320 #define CDC_RX_COMPANDERn_HALT_MASK BIT(2) 321 #define CDC_RX_COMPANDER0_CTL0 (0x0800) 322 #define CDC_RX_COMPANDER0_CTL1 (0x0804) 323 #define CDC_RX_COMPANDER0_CTL2 (0x0808) 324 #define CDC_RX_COMPANDER0_CTL3 (0x080C) 325 #define CDC_RX_COMPANDER0_CTL4 (0x0810) 326 #define CDC_RX_COMPANDER0_CTL5 (0x0814) 327 #define CDC_RX_COMPANDER0_CTL6 (0x0818) 328 #define CDC_RX_COMPANDER0_CTL7 (0x081C) 329 #define CDC_RX_COMPANDER1_CTL0 (0x0840) 330 #define CDC_RX_COMPANDER1_CTL1 (0x0844) 331 #define CDC_RX_COMPANDER1_CTL2 (0x0848) 332 #define CDC_RX_COMPANDER1_CTL3 (0x084C) 333 #define CDC_RX_COMPANDER1_CTL4 (0x0850) 334 #define CDC_RX_COMPANDER1_CTL5 (0x0854) 335 #define CDC_RX_COMPANDER1_CTL6 (0x0858) 336 #define CDC_RX_COMPANDER1_CTL7 (0x085C) 337 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5) 338 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00) 339 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04) 340 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08) 341 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C) 342 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10) 343 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14) 344 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18) 345 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C) 346 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20) 347 #define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24) 348 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28) 349 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C) 350 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30) 351 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80) 352 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84) 353 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88) 354 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C) 355 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90) 356 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94) 357 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98) 358 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C) 359 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0) 360 #define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4) 361 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8) 362 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC) 363 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0) 364 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00) 365 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04) 366 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08) 367 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C) 368 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10) 369 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14) 370 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18) 371 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C) 372 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40) 373 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44) 374 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50) 375 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54) 376 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00) 377 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04) 378 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40) 379 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44) 380 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80) 381 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84) 382 #define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00) 383 #define CDC_RX_EC_ASRC0_CTL0 (0x0D04) 384 #define CDC_RX_EC_ASRC0_CTL1 (0x0D08) 385 #define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C) 386 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10) 387 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14) 388 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18) 389 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C) 390 #define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20) 391 #define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40) 392 #define CDC_RX_EC_ASRC1_CTL0 (0x0D44) 393 #define CDC_RX_EC_ASRC1_CTL1 (0x0D48) 394 #define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C) 395 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50) 396 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54) 397 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58) 398 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C) 399 #define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60) 400 #define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80) 401 #define CDC_RX_EC_ASRC2_CTL0 (0x0D84) 402 #define CDC_RX_EC_ASRC2_CTL1 (0x0D88) 403 #define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C) 404 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90) 405 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94) 406 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98) 407 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C) 408 #define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0) 409 #define CDC_RX_DSD0_PATH_CTL (0x0F00) 410 #define CDC_RX_DSD0_CFG0 (0x0F04) 411 #define CDC_RX_DSD0_CFG1 (0x0F08) 412 #define CDC_RX_DSD0_CFG2 (0x0F0C) 413 #define CDC_RX_DSD1_PATH_CTL (0x0F80) 414 #define CDC_RX_DSD1_CFG0 (0x0F84) 415 #define CDC_RX_DSD1_CFG1 (0x0F88) 416 #define CDC_RX_DSD1_CFG2 (0x0F8C) 417 #define RX_MAX_OFFSET (0x0F8C) 418 419 #define MCLK_FREQ 19200000 420 421 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 422 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 423 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 424 SNDRV_PCM_RATE_384000) 425 /* Fractional Rates */ 426 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 427 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 428 429 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 430 SNDRV_PCM_FMTBIT_S24_LE |\ 431 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 432 433 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 434 SNDRV_PCM_RATE_48000) 435 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 436 SNDRV_PCM_FMTBIT_S24_LE |\ 437 SNDRV_PCM_FMTBIT_S24_3LE) 438 439 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2 440 441 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0 442 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f 443 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f 444 445 #define COMP_MAX_COEFF 25 446 #define RX_NUM_CLKS_MAX 5 447 448 struct comp_coeff_val { 449 u8 lsb; 450 u8 msb; 451 }; 452 453 enum { 454 HPH_ULP, 455 HPH_LOHIFI, 456 HPH_MODE_MAX, 457 }; 458 459 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = { 460 { 461 {0x40, 0x00}, 462 {0x4C, 0x00}, 463 {0x5A, 0x00}, 464 {0x6B, 0x00}, 465 {0x7F, 0x00}, 466 {0x97, 0x00}, 467 {0xB3, 0x00}, 468 {0xD5, 0x00}, 469 {0xFD, 0x00}, 470 {0x2D, 0x01}, 471 {0x66, 0x01}, 472 {0xA7, 0x01}, 473 {0xF8, 0x01}, 474 {0x57, 0x02}, 475 {0xC7, 0x02}, 476 {0x4B, 0x03}, 477 {0xE9, 0x03}, 478 {0xA3, 0x04}, 479 {0x7D, 0x05}, 480 {0x90, 0x06}, 481 {0xD1, 0x07}, 482 {0x49, 0x09}, 483 {0x00, 0x0B}, 484 {0x01, 0x0D}, 485 {0x59, 0x0F}, 486 }, 487 { 488 {0x40, 0x00}, 489 {0x4C, 0x00}, 490 {0x5A, 0x00}, 491 {0x6B, 0x00}, 492 {0x80, 0x00}, 493 {0x98, 0x00}, 494 {0xB4, 0x00}, 495 {0xD5, 0x00}, 496 {0xFE, 0x00}, 497 {0x2E, 0x01}, 498 {0x66, 0x01}, 499 {0xA9, 0x01}, 500 {0xF8, 0x01}, 501 {0x56, 0x02}, 502 {0xC4, 0x02}, 503 {0x4F, 0x03}, 504 {0xF0, 0x03}, 505 {0xAE, 0x04}, 506 {0x8B, 0x05}, 507 {0x8E, 0x06}, 508 {0xBC, 0x07}, 509 {0x56, 0x09}, 510 {0x0F, 0x0B}, 511 {0x13, 0x0D}, 512 {0x6F, 0x0F}, 513 }, 514 }; 515 516 enum { 517 INTERP_HPHL, 518 INTERP_HPHR, 519 INTERP_AUX, 520 INTERP_MAX 521 }; 522 523 enum { 524 RX_MACRO_RX0, 525 RX_MACRO_RX1, 526 RX_MACRO_RX2, 527 RX_MACRO_RX3, 528 RX_MACRO_RX4, 529 RX_MACRO_RX5, 530 RX_MACRO_PORTS_MAX 531 }; 532 533 enum { 534 RX_MACRO_COMP1, /* HPH_L */ 535 RX_MACRO_COMP2, /* HPH_R */ 536 RX_MACRO_COMP_MAX 537 }; 538 539 enum { 540 RX_MACRO_EC0_MUX = 0, 541 RX_MACRO_EC1_MUX, 542 RX_MACRO_EC2_MUX, 543 RX_MACRO_EC_MUX_MAX, 544 }; 545 546 enum { 547 INTn_1_INP_SEL_ZERO = 0, 548 INTn_1_INP_SEL_DEC0, 549 INTn_1_INP_SEL_DEC1, 550 INTn_1_INP_SEL_IIR0, 551 INTn_1_INP_SEL_IIR1, 552 INTn_1_INP_SEL_RX0, 553 INTn_1_INP_SEL_RX1, 554 INTn_1_INP_SEL_RX2, 555 INTn_1_INP_SEL_RX3, 556 INTn_1_INP_SEL_RX4, 557 INTn_1_INP_SEL_RX5, 558 }; 559 560 enum { 561 INTn_2_INP_SEL_ZERO = 0, 562 INTn_2_INP_SEL_RX0, 563 INTn_2_INP_SEL_RX1, 564 INTn_2_INP_SEL_RX2, 565 INTn_2_INP_SEL_RX3, 566 INTn_2_INP_SEL_RX4, 567 INTn_2_INP_SEL_RX5, 568 }; 569 570 enum { 571 INTERP_MAIN_PATH, 572 INTERP_MIX_PATH, 573 }; 574 575 /* Codec supports 2 IIR filters */ 576 enum { 577 IIR0 = 0, 578 IIR1, 579 IIR_MAX, 580 }; 581 582 /* Each IIR has 5 Filter Stages */ 583 enum { 584 BAND1 = 0, 585 BAND2, 586 BAND3, 587 BAND4, 588 BAND5, 589 BAND_MAX, 590 }; 591 592 #define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 593 594 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \ 595 { \ 596 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 597 .info = rx_macro_iir_filter_info, \ 598 .get = rx_macro_get_iir_band_audio_mixer, \ 599 .put = rx_macro_put_iir_band_audio_mixer, \ 600 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 601 .iir_idx = iidx, \ 602 .band_idx = bidx, \ 603 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \ 604 } \ 605 } 606 607 struct interp_sample_rate { 608 int sample_rate; 609 int rate_val; 610 }; 611 612 static struct interp_sample_rate sr_val_tbl[] = { 613 {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, 614 {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA}, 615 {176400, 0xB}, {352800, 0xC}, 616 }; 617 618 enum { 619 RX_MACRO_AIF_INVALID = 0, 620 RX_MACRO_AIF1_PB, 621 RX_MACRO_AIF2_PB, 622 RX_MACRO_AIF3_PB, 623 RX_MACRO_AIF4_PB, 624 RX_MACRO_AIF_ECHO, 625 RX_MACRO_MAX_DAIS, 626 }; 627 628 enum { 629 RX_MACRO_AIF1_CAP = 0, 630 RX_MACRO_AIF2_CAP, 631 RX_MACRO_AIF3_CAP, 632 RX_MACRO_MAX_AIF_CAP_DAIS 633 }; 634 635 struct rx_macro { 636 struct device *dev; 637 int comp_enabled[RX_MACRO_COMP_MAX]; 638 /* Main path clock users count */ 639 int main_clk_users[INTERP_MAX]; 640 int rx_port_value[RX_MACRO_PORTS_MAX]; 641 u16 prim_int_users[INTERP_MAX]; 642 int rx_mclk_users; 643 int clsh_users; 644 int rx_mclk_cnt; 645 int codec_version; 646 int rxn_reg_stride; 647 bool is_ear_mode_on; 648 bool hph_pwr_mode; 649 bool hph_hd2_mode; 650 struct snd_soc_component *component; 651 unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; 652 unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; 653 u16 bit_width[RX_MACRO_MAX_DAIS]; 654 int is_softclip_on; 655 int is_aux_hpf_on; 656 int softclip_clk_users; 657 struct lpass_macro *pds; 658 struct regmap *regmap; 659 struct clk *mclk; 660 struct clk *npl; 661 struct clk *macro; 662 struct clk *dcodec; 663 struct clk *fsgen; 664 struct clk_hw hw; 665 }; 666 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw) 667 668 struct wcd_iir_filter_ctl { 669 unsigned int iir_idx; 670 unsigned int band_idx; 671 struct soc_bytes_ext bytes_ext; 672 }; 673 674 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 675 676 static const char * const rx_int_mix_mux_text[] = { 677 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 678 }; 679 680 static const char * const rx_prim_mix_text[] = { 681 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 682 "RX3", "RX4", "RX5" 683 }; 684 685 static const char * const rx_sidetone_mix_text[] = { 686 "ZERO", "SRC0", "SRC1", "SRC_SUM" 687 }; 688 689 static const char * const iir_inp_mux_text[] = { 690 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", 691 "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 692 }; 693 694 static const char * const rx_int_dem_inp_mux_text[] = { 695 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 696 }; 697 698 static const char * const rx_int0_1_interp_mux_text[] = { 699 "ZERO", "RX INT0_1 MIX1", 700 }; 701 702 static const char * const rx_int1_1_interp_mux_text[] = { 703 "ZERO", "RX INT1_1 MIX1", 704 }; 705 706 static const char * const rx_int2_1_interp_mux_text[] = { 707 "ZERO", "RX INT2_1 MIX1", 708 }; 709 710 static const char * const rx_int0_2_interp_mux_text[] = { 711 "ZERO", "RX INT0_2 MUX", 712 }; 713 714 static const char * const rx_int1_2_interp_mux_text[] = { 715 "ZERO", "RX INT1_2 MUX", 716 }; 717 718 static const char * const rx_int2_2_interp_mux_text[] = { 719 "ZERO", "RX INT2_2 MUX", 720 }; 721 722 static const char *const rx_macro_mux_text[] = { 723 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB" 724 }; 725 726 static const char *const rx_macro_hph_pwr_mode_text[] = { 727 "ULP", "LOHIFI" 728 }; 729 730 static const char * const rx_echo_mux_text[] = { 731 "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2" 732 }; 733 734 static const struct soc_enum rx_macro_hph_pwr_mode_enum = 735 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text); 736 static const struct soc_enum rx_mix_tx2_mux_enum = 737 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text); 738 static const struct soc_enum rx_mix_tx1_mux_enum = 739 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text); 740 static const struct soc_enum rx_mix_tx0_mux_enum = 741 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text); 742 743 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 744 rx_int_mix_mux_text); 745 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 746 rx_int_mix_mux_text); 747 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 748 rx_int_mix_mux_text); 749 750 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 751 rx_prim_mix_text); 752 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 753 rx_prim_mix_text); 754 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 755 rx_prim_mix_text); 756 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 757 rx_prim_mix_text); 758 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 759 rx_prim_mix_text); 760 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 761 rx_prim_mix_text); 762 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 763 rx_prim_mix_text); 764 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 765 rx_prim_mix_text); 766 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 767 rx_prim_mix_text); 768 769 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 770 rx_sidetone_mix_text); 771 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 772 rx_sidetone_mix_text); 773 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 774 rx_sidetone_mix_text); 775 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, 776 iir_inp_mux_text); 777 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, 778 iir_inp_mux_text); 779 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, 780 iir_inp_mux_text); 781 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, 782 iir_inp_mux_text); 783 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, 784 iir_inp_mux_text); 785 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, 786 iir_inp_mux_text); 787 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, 788 iir_inp_mux_text); 789 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, 790 iir_inp_mux_text); 791 792 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0, 793 rx_int0_1_interp_mux_text); 794 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0, 795 rx_int1_1_interp_mux_text); 796 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0, 797 rx_int2_1_interp_mux_text); 798 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0, 799 rx_int0_2_interp_mux_text); 800 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0, 801 rx_int1_2_interp_mux_text); 802 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0, 803 rx_int2_2_interp_mux_text); 804 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0, 805 rx_int_dem_inp_mux_text); 806 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0, 807 rx_int_dem_inp_mux_text); 808 static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0, 809 rx_int_dem_inp_mux_text); 810 811 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 812 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 813 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 814 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 815 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 816 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 817 818 static const struct snd_kcontrol_new rx_mix_tx1_mux = 819 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum); 820 static const struct snd_kcontrol_new rx_mix_tx2_mux = 821 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum); 822 static const struct snd_kcontrol_new rx_int0_2_mux = 823 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum); 824 static const struct snd_kcontrol_new rx_int1_2_mux = 825 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum); 826 static const struct snd_kcontrol_new rx_int2_2_mux = 827 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum); 828 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 829 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum); 830 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 831 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum); 832 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 833 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum); 834 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 835 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum); 836 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 837 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum); 838 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 839 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum); 840 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 841 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum); 842 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 843 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum); 844 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 845 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum); 846 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 847 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum); 848 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 849 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum); 850 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 851 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum); 852 static const struct snd_kcontrol_new iir0_inp0_mux = 853 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum); 854 static const struct snd_kcontrol_new iir0_inp1_mux = 855 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum); 856 static const struct snd_kcontrol_new iir0_inp2_mux = 857 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum); 858 static const struct snd_kcontrol_new iir0_inp3_mux = 859 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum); 860 static const struct snd_kcontrol_new iir1_inp0_mux = 861 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum); 862 static const struct snd_kcontrol_new iir1_inp1_mux = 863 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum); 864 static const struct snd_kcontrol_new iir1_inp2_mux = 865 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum); 866 static const struct snd_kcontrol_new iir1_inp3_mux = 867 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum); 868 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 869 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum); 870 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 871 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum); 872 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 873 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum); 874 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 875 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum); 876 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 877 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum); 878 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 879 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum); 880 static const struct snd_kcontrol_new rx_mix_tx0_mux = 881 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum); 882 883 static const struct reg_default rx_defaults[] = { 884 /* RX Macro */ 885 { CDC_RX_TOP_TOP_CFG0, 0x00 }, 886 { CDC_RX_TOP_SWR_CTRL, 0x00 }, 887 { CDC_RX_TOP_DEBUG, 0x00 }, 888 { CDC_RX_TOP_DEBUG_BUS, 0x00 }, 889 { CDC_RX_TOP_DEBUG_EN0, 0x00 }, 890 { CDC_RX_TOP_DEBUG_EN1, 0x00 }, 891 { CDC_RX_TOP_DEBUG_EN2, 0x00 }, 892 { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 }, 893 { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 }, 894 { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 }, 895 { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 }, 896 { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 }, 897 { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 }, 898 { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 }, 899 { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 }, 900 { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 }, 901 { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 }, 902 { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 }, 903 { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 }, 904 { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 }, 905 { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 }, 906 { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 }, 907 { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 }, 908 { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 }, 909 { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 }, 910 { CDC_RX_TOP_RX_I2S_CTL, 0x0C }, 911 { CDC_RX_TOP_TX_I2S2_CTL, 0x0C }, 912 { CDC_RX_TOP_I2S_CLK, 0x0C }, 913 { CDC_RX_TOP_I2S_RESET, 0x00 }, 914 { CDC_RX_TOP_I2S_MUX, 0x00 }, 915 { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 916 { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 917 { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 }, 918 { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 }, 919 { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 }, 920 { CDC_RX_SOFTCLIP_CRC, 0x00 }, 921 { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 }, 922 { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 }, 923 { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 }, 924 { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 }, 925 { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 }, 926 { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 }, 927 { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 }, 928 { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 }, 929 { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 }, 930 { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 }, 931 { CDC_RX_CLSH_CRC, 0x00 }, 932 { CDC_RX_CLSH_DLY_CTRL, 0x03 }, 933 { CDC_RX_CLSH_DECAY_CTRL, 0x02 }, 934 { CDC_RX_CLSH_HPH_V_PA, 0x1C }, 935 { CDC_RX_CLSH_EAR_V_PA, 0x39 }, 936 { CDC_RX_CLSH_HPH_V_HD, 0x0C }, 937 { CDC_RX_CLSH_EAR_V_HD, 0x0C }, 938 { CDC_RX_CLSH_K1_MSB, 0x01 }, 939 { CDC_RX_CLSH_K1_LSB, 0x00 }, 940 { CDC_RX_CLSH_K2_MSB, 0x00 }, 941 { CDC_RX_CLSH_K2_LSB, 0x80 }, 942 { CDC_RX_CLSH_IDLE_CTRL, 0x00 }, 943 { CDC_RX_CLSH_IDLE_HPH, 0x00 }, 944 { CDC_RX_CLSH_IDLE_EAR, 0x00 }, 945 { CDC_RX_CLSH_TEST0, 0x07 }, 946 { CDC_RX_CLSH_TEST1, 0x00 }, 947 { CDC_RX_CLSH_OVR_VREF, 0x00 }, 948 { CDC_RX_CLSH_CLSG_CTL, 0x02 }, 949 { CDC_RX_CLSH_CLSG_CFG1, 0x9A }, 950 { CDC_RX_CLSH_CLSG_CFG2, 0x10 }, 951 { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 }, 952 { CDC_RX_BCL_VBAT_CFG, 0x10 }, 953 { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 }, 954 { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 }, 955 { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 }, 956 { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 }, 957 { CDC_RX_BCL_VBAT_PK_EST2, 0x01 }, 958 { CDC_RX_BCL_VBAT_PK_EST3, 0x40 }, 959 { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A }, 960 { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 }, 961 { CDC_RX_BCL_VBAT_TAC1, 0x00 }, 962 { CDC_RX_BCL_VBAT_TAC2, 0x18 }, 963 { CDC_RX_BCL_VBAT_TAC3, 0x18 }, 964 { CDC_RX_BCL_VBAT_TAC4, 0x03 }, 965 { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 }, 966 { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 }, 967 { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 }, 968 { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 }, 969 { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 }, 970 { CDC_RX_BCL_VBAT_DEBUG1, 0x00 }, 971 { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 }, 972 { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 }, 973 { CDC_RX_BCL_VBAT_BAN, 0x0C }, 974 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 }, 975 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 }, 976 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 }, 977 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 }, 978 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B }, 979 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 }, 980 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 }, 981 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 }, 982 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 }, 983 { CDC_RX_BCL_VBAT_ATTN1, 0x04 }, 984 { CDC_RX_BCL_VBAT_ATTN2, 0x08 }, 985 { CDC_RX_BCL_VBAT_ATTN3, 0x0C }, 986 { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 }, 987 { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 }, 988 { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 }, 989 { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 }, 990 { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 }, 991 { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 }, 992 { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 }, 993 { CDC_RX_INTR_CTRL_CFG, 0x00 }, 994 { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 }, 995 { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF }, 996 { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 }, 997 { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 }, 998 { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF }, 999 { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 }, 1000 { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 }, 1001 { CDC_RX_INTR_CTRL_LEVEL0, 0x00 }, 1002 { CDC_RX_INTR_CTRL_BYPASS0, 0x00 }, 1003 { CDC_RX_INTR_CTRL_SET0, 0x00 }, 1004 { CDC_RX_RX0_RX_PATH_CTL, 0x04 }, 1005 { CDC_RX_RX0_RX_PATH_CFG0, 0x00 }, 1006 { CDC_RX_RX0_RX_PATH_CFG1, 0x64 }, 1007 { CDC_RX_RX0_RX_PATH_CFG2, 0x8F }, 1008 { CDC_RX_RX0_RX_PATH_CFG3, 0x00 }, 1009 { CDC_RX_RX0_RX_VOL_CTL, 0x00 }, 1010 { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 }, 1011 { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E }, 1012 { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 }, 1013 { CDC_RX_RX0_RX_PATH_SEC1, 0x08 }, 1014 { CDC_RX_RX0_RX_PATH_SEC2, 0x00 }, 1015 { CDC_RX_RX0_RX_PATH_SEC3, 0x00 }, 1016 { CDC_RX_RX0_RX_PATH_SEC4, 0x00 }, 1017 { CDC_RX_RX0_RX_PATH_SEC7, 0x00 }, 1018 { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 }, 1019 { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 }, 1020 { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 }, 1021 { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 }, 1022 { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 }, 1023 { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 }, 1024 { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 }, 1025 { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 }, 1026 { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 }, 1027 { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 }, 1028 { CDC_RX_IDLE_DETECT_CFG0, 0x07 }, 1029 { CDC_RX_IDLE_DETECT_CFG1, 0x3C }, 1030 { CDC_RX_IDLE_DETECT_CFG2, 0x00 }, 1031 { CDC_RX_IDLE_DETECT_CFG3, 0x00 }, 1032 { CDC_RX_COMPANDER0_CTL0, 0x60 }, 1033 { CDC_RX_COMPANDER0_CTL1, 0xDB }, 1034 { CDC_RX_COMPANDER0_CTL2, 0xFF }, 1035 { CDC_RX_COMPANDER0_CTL3, 0x35 }, 1036 { CDC_RX_COMPANDER0_CTL4, 0xFF }, 1037 { CDC_RX_COMPANDER0_CTL5, 0x00 }, 1038 { CDC_RX_COMPANDER0_CTL6, 0x01 }, 1039 { CDC_RX_COMPANDER0_CTL7, 0x28 }, 1040 { CDC_RX_COMPANDER1_CTL0, 0x60 }, 1041 { CDC_RX_COMPANDER1_CTL1, 0xDB }, 1042 { CDC_RX_COMPANDER1_CTL2, 0xFF }, 1043 { CDC_RX_COMPANDER1_CTL3, 0x35 }, 1044 { CDC_RX_COMPANDER1_CTL4, 0xFF }, 1045 { CDC_RX_COMPANDER1_CTL5, 0x00 }, 1046 { CDC_RX_COMPANDER1_CTL6, 0x01 }, 1047 { CDC_RX_COMPANDER1_CTL7, 0x28 }, 1048 { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 }, 1049 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 }, 1050 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 }, 1051 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 }, 1052 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 }, 1053 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 }, 1054 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 }, 1055 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 }, 1056 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 }, 1057 { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 }, 1058 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 }, 1059 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 }, 1060 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 }, 1061 { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 }, 1062 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 }, 1063 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 }, 1064 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 }, 1065 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 }, 1066 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 }, 1067 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 }, 1068 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 }, 1069 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 }, 1070 { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 }, 1071 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 }, 1072 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 }, 1073 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 }, 1074 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 }, 1075 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 }, 1076 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 }, 1077 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 }, 1078 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 }, 1079 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 }, 1080 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 }, 1081 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 }, 1082 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 }, 1083 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 }, 1084 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 }, 1085 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 }, 1086 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 }, 1087 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 }, 1088 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 }, 1089 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 }, 1090 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 }, 1091 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 }, 1092 { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 }, 1093 { CDC_RX_EC_ASRC0_CTL0, 0x00 }, 1094 { CDC_RX_EC_ASRC0_CTL1, 0x00 }, 1095 { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 }, 1096 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 }, 1097 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 }, 1098 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 }, 1099 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 }, 1100 { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 }, 1101 { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 }, 1102 { CDC_RX_EC_ASRC1_CTL0, 0x00 }, 1103 { CDC_RX_EC_ASRC1_CTL1, 0x00 }, 1104 { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 }, 1105 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 }, 1106 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 }, 1107 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 }, 1108 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 }, 1109 { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 }, 1110 { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 }, 1111 { CDC_RX_EC_ASRC2_CTL0, 0x00 }, 1112 { CDC_RX_EC_ASRC2_CTL1, 0x00 }, 1113 { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 }, 1114 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 }, 1115 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 }, 1116 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 }, 1117 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 }, 1118 { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 }, 1119 { CDC_RX_DSD0_PATH_CTL, 0x00 }, 1120 { CDC_RX_DSD0_CFG0, 0x00 }, 1121 { CDC_RX_DSD0_CFG1, 0x62 }, 1122 { CDC_RX_DSD0_CFG2, 0x96 }, 1123 { CDC_RX_DSD1_PATH_CTL, 0x00 }, 1124 { CDC_RX_DSD1_CFG0, 0x00 }, 1125 { CDC_RX_DSD1_CFG1, 0x62 }, 1126 { CDC_RX_DSD1_CFG2, 0x96 }, 1127 }; 1128 1129 static const struct reg_default rx_2_5_defaults[] = { 1130 { CDC_2_5_RX_RX1_RX_PATH_CTL, 0x04 }, 1131 { CDC_2_5_RX_RX1_RX_PATH_CFG0, 0x00 }, 1132 { CDC_2_5_RX_RX1_RX_PATH_CFG1, 0x64 }, 1133 { CDC_2_5_RX_RX1_RX_PATH_CFG2, 0x8F }, 1134 { CDC_2_5_RX_RX1_RX_PATH_CFG3, 0x00 }, 1135 { CDC_2_5_RX_RX1_RX_VOL_CTL, 0x00 }, 1136 { CDC_2_5_RX_RX1_RX_PATH_MIX_CTL, 0x04 }, 1137 { CDC_2_5_RX_RX1_RX_PATH_MIX_CFG, 0x7E }, 1138 { CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 0x00 }, 1139 { CDC_2_5_RX_RX1_RX_PATH_SEC1, 0x08 }, 1140 { CDC_2_5_RX_RX1_RX_PATH_SEC2, 0x00 }, 1141 { CDC_2_5_RX_RX1_RX_PATH_SEC3, 0x00 }, 1142 { CDC_2_5_RX_RX1_RX_PATH_SEC4, 0x00 }, 1143 { CDC_2_5_RX_RX1_RX_PATH_SEC7, 0x00 }, 1144 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0, 0x08 }, 1145 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1, 0x00 }, 1146 { CDC_2_5_RX_RX1_RX_PATH_DSM_CTL, 0x08 }, 1147 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1, 0x00 }, 1148 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2, 0x00 }, 1149 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3, 0x00 }, 1150 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4, 0x55 }, 1151 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5, 0x55 }, 1152 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6, 0x55 }, 1153 { CDC_2_5_RX_RX2_RX_PATH_CTL, 0x04 }, 1154 { CDC_2_5_RX_RX2_RX_PATH_CFG0, 0x00 }, 1155 { CDC_2_5_RX_RX2_RX_PATH_CFG1, 0x64 }, 1156 { CDC_2_5_RX_RX2_RX_PATH_CFG2, 0x8F }, 1157 { CDC_2_5_RX_RX2_RX_PATH_CFG3, 0x00 }, 1158 { CDC_2_5_RX_RX2_RX_VOL_CTL, 0x00 }, 1159 { CDC_2_5_RX_RX2_RX_PATH_MIX_CTL, 0x04 }, 1160 { CDC_2_5_RX_RX2_RX_PATH_MIX_CFG, 0x7E }, 1161 { CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 0x00 }, 1162 { CDC_2_5_RX_RX2_RX_PATH_SEC0, 0x04 }, 1163 { CDC_2_5_RX_RX2_RX_PATH_SEC1, 0x08 }, 1164 { CDC_2_5_RX_RX2_RX_PATH_SEC2, 0x00 }, 1165 { CDC_2_5_RX_RX2_RX_PATH_SEC3, 0x00 }, 1166 { CDC_2_5_RX_RX2_RX_PATH_SEC4, 0x00 }, 1167 { CDC_2_5_RX_RX2_RX_PATH_SEC5, 0x00 }, 1168 { CDC_2_5_RX_RX2_RX_PATH_SEC6, 0x00 }, 1169 { CDC_2_5_RX_RX2_RX_PATH_SEC7, 0x00 }, 1170 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0, 0x08 }, 1171 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1, 0x00 }, 1172 { CDC_2_5_RX_RX2_RX_PATH_DSM_CTL, 0x00 }, 1173 }; 1174 1175 static const struct reg_default rx_pre_2_5_defaults[] = { 1176 { CDC_RX_RX1_RX_PATH_CTL, 0x04 }, 1177 { CDC_RX_RX1_RX_PATH_CFG0, 0x00 }, 1178 { CDC_RX_RX1_RX_PATH_CFG1, 0x64 }, 1179 { CDC_RX_RX1_RX_PATH_CFG2, 0x8F }, 1180 { CDC_RX_RX1_RX_PATH_CFG3, 0x00 }, 1181 { CDC_RX_RX1_RX_VOL_CTL, 0x00 }, 1182 { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 }, 1183 { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E }, 1184 { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 }, 1185 { CDC_RX_RX1_RX_PATH_SEC1, 0x08 }, 1186 { CDC_RX_RX1_RX_PATH_SEC2, 0x00 }, 1187 { CDC_RX_RX1_RX_PATH_SEC3, 0x00 }, 1188 { CDC_RX_RX1_RX_PATH_SEC4, 0x00 }, 1189 { CDC_RX_RX1_RX_PATH_SEC7, 0x00 }, 1190 { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 }, 1191 { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 }, 1192 { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 }, 1193 { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 }, 1194 { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 }, 1195 { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 }, 1196 { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 }, 1197 { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 }, 1198 { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 }, 1199 { CDC_RX_RX2_RX_PATH_CTL, 0x04 }, 1200 { CDC_RX_RX2_RX_PATH_CFG0, 0x00 }, 1201 { CDC_RX_RX2_RX_PATH_CFG1, 0x64 }, 1202 { CDC_RX_RX2_RX_PATH_CFG2, 0x8F }, 1203 { CDC_RX_RX2_RX_PATH_CFG3, 0x00 }, 1204 { CDC_RX_RX2_RX_VOL_CTL, 0x00 }, 1205 { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 }, 1206 { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E }, 1207 { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 }, 1208 { CDC_RX_RX2_RX_PATH_SEC0, 0x04 }, 1209 { CDC_RX_RX2_RX_PATH_SEC1, 0x08 }, 1210 { CDC_RX_RX2_RX_PATH_SEC2, 0x00 }, 1211 { CDC_RX_RX2_RX_PATH_SEC3, 0x00 }, 1212 { CDC_RX_RX2_RX_PATH_SEC4, 0x00 }, 1213 { CDC_RX_RX2_RX_PATH_SEC5, 0x00 }, 1214 { CDC_RX_RX2_RX_PATH_SEC6, 0x00 }, 1215 { CDC_RX_RX2_RX_PATH_SEC7, 0x00 }, 1216 { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 }, 1217 { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 }, 1218 { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 }, 1219 1220 }; 1221 1222 static bool rx_is_wronly_register(struct device *dev, 1223 unsigned int reg) 1224 { 1225 switch (reg) { 1226 case CDC_RX_BCL_VBAT_GAIN_UPD_MON: 1227 case CDC_RX_INTR_CTRL_CLR_COMMIT: 1228 case CDC_RX_INTR_CTRL_PIN1_CLEAR0: 1229 case CDC_RX_INTR_CTRL_PIN2_CLEAR0: 1230 return true; 1231 } 1232 1233 return false; 1234 } 1235 1236 static bool rx_is_volatile_register(struct device *dev, unsigned int reg) 1237 { 1238 /* Update volatile list for rx/tx macros */ 1239 switch (reg) { 1240 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1241 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1242 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1243 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1244 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1245 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1246 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1247 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1248 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1249 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1250 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1251 case CDC_RX_BCL_VBAT_DECODE_ST: 1252 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1253 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1254 case CDC_RX_COMPANDER0_CTL6: 1255 case CDC_RX_COMPANDER1_CTL6: 1256 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1257 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1258 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1259 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1260 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1261 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1262 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1263 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1264 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1265 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1266 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1267 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1268 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1269 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1270 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1271 return true; 1272 } 1273 return false; 1274 } 1275 1276 static bool rx_pre_2_5_is_rw_register(struct device *dev, unsigned int reg) 1277 { 1278 switch (reg) { 1279 case CDC_RX_RX1_RX_PATH_CTL: 1280 case CDC_RX_RX1_RX_PATH_CFG0: 1281 case CDC_RX_RX1_RX_PATH_CFG1: 1282 case CDC_RX_RX1_RX_PATH_CFG2: 1283 case CDC_RX_RX1_RX_PATH_CFG3: 1284 case CDC_RX_RX1_RX_VOL_CTL: 1285 case CDC_RX_RX1_RX_PATH_MIX_CTL: 1286 case CDC_RX_RX1_RX_PATH_MIX_CFG: 1287 case CDC_RX_RX1_RX_VOL_MIX_CTL: 1288 case CDC_RX_RX1_RX_PATH_SEC1: 1289 case CDC_RX_RX1_RX_PATH_SEC2: 1290 case CDC_RX_RX1_RX_PATH_SEC3: 1291 case CDC_RX_RX1_RX_PATH_SEC4: 1292 case CDC_RX_RX1_RX_PATH_SEC7: 1293 case CDC_RX_RX1_RX_PATH_MIX_SEC0: 1294 case CDC_RX_RX1_RX_PATH_MIX_SEC1: 1295 case CDC_RX_RX1_RX_PATH_DSM_CTL: 1296 case CDC_RX_RX1_RX_PATH_DSM_DATA1: 1297 case CDC_RX_RX1_RX_PATH_DSM_DATA2: 1298 case CDC_RX_RX1_RX_PATH_DSM_DATA3: 1299 case CDC_RX_RX1_RX_PATH_DSM_DATA4: 1300 case CDC_RX_RX1_RX_PATH_DSM_DATA5: 1301 case CDC_RX_RX1_RX_PATH_DSM_DATA6: 1302 case CDC_RX_RX2_RX_PATH_CTL: 1303 case CDC_RX_RX2_RX_PATH_CFG0: 1304 case CDC_RX_RX2_RX_PATH_CFG1: 1305 case CDC_RX_RX2_RX_PATH_CFG2: 1306 case CDC_RX_RX2_RX_PATH_CFG3: 1307 case CDC_RX_RX2_RX_VOL_CTL: 1308 case CDC_RX_RX2_RX_PATH_MIX_CTL: 1309 case CDC_RX_RX2_RX_PATH_MIX_CFG: 1310 case CDC_RX_RX2_RX_VOL_MIX_CTL: 1311 case CDC_RX_RX2_RX_PATH_SEC0: 1312 case CDC_RX_RX2_RX_PATH_SEC1: 1313 case CDC_RX_RX2_RX_PATH_SEC2: 1314 case CDC_RX_RX2_RX_PATH_SEC3: 1315 case CDC_RX_RX2_RX_PATH_SEC4: 1316 case CDC_RX_RX2_RX_PATH_SEC5: 1317 case CDC_RX_RX2_RX_PATH_SEC6: 1318 case CDC_RX_RX2_RX_PATH_SEC7: 1319 case CDC_RX_RX2_RX_PATH_MIX_SEC0: 1320 case CDC_RX_RX2_RX_PATH_MIX_SEC1: 1321 case CDC_RX_RX2_RX_PATH_DSM_CTL: 1322 return true; 1323 } 1324 1325 return false; 1326 } 1327 1328 static bool rx_2_5_is_rw_register(struct device *dev, unsigned int reg) 1329 { 1330 switch (reg) { 1331 case CDC_2_5_RX_RX1_RX_PATH_CTL: 1332 case CDC_2_5_RX_RX1_RX_PATH_CFG0: 1333 case CDC_2_5_RX_RX1_RX_PATH_CFG1: 1334 case CDC_2_5_RX_RX1_RX_PATH_CFG2: 1335 case CDC_2_5_RX_RX1_RX_PATH_CFG3: 1336 case CDC_2_5_RX_RX1_RX_VOL_CTL: 1337 case CDC_2_5_RX_RX1_RX_PATH_MIX_CTL: 1338 case CDC_2_5_RX_RX1_RX_PATH_MIX_CFG: 1339 case CDC_2_5_RX_RX1_RX_VOL_MIX_CTL: 1340 case CDC_2_5_RX_RX1_RX_PATH_SEC1: 1341 case CDC_2_5_RX_RX1_RX_PATH_SEC2: 1342 case CDC_2_5_RX_RX1_RX_PATH_SEC3: 1343 case CDC_2_5_RX_RX1_RX_PATH_SEC4: 1344 case CDC_2_5_RX_RX1_RX_PATH_SEC7: 1345 case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0: 1346 case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1: 1347 case CDC_2_5_RX_RX1_RX_PATH_DSM_CTL: 1348 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1: 1349 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2: 1350 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3: 1351 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4: 1352 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5: 1353 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6: 1354 case CDC_2_5_RX_RX2_RX_PATH_CTL: 1355 case CDC_2_5_RX_RX2_RX_PATH_CFG0: 1356 case CDC_2_5_RX_RX2_RX_PATH_CFG1: 1357 case CDC_2_5_RX_RX2_RX_PATH_CFG2: 1358 case CDC_2_5_RX_RX2_RX_PATH_CFG3: 1359 case CDC_2_5_RX_RX2_RX_VOL_CTL: 1360 case CDC_2_5_RX_RX2_RX_PATH_MIX_CTL: 1361 case CDC_2_5_RX_RX2_RX_PATH_MIX_CFG: 1362 case CDC_2_5_RX_RX2_RX_VOL_MIX_CTL: 1363 case CDC_2_5_RX_RX2_RX_PATH_SEC0: 1364 case CDC_2_5_RX_RX2_RX_PATH_SEC1: 1365 case CDC_2_5_RX_RX2_RX_PATH_SEC2: 1366 case CDC_2_5_RX_RX2_RX_PATH_SEC3: 1367 case CDC_2_5_RX_RX2_RX_PATH_SEC4: 1368 case CDC_2_5_RX_RX2_RX_PATH_SEC5: 1369 case CDC_2_5_RX_RX2_RX_PATH_SEC6: 1370 case CDC_2_5_RX_RX2_RX_PATH_SEC7: 1371 case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0: 1372 case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1: 1373 case CDC_2_5_RX_RX2_RX_PATH_DSM_CTL: 1374 return true; 1375 } 1376 1377 return false; 1378 } 1379 1380 static bool rx_is_rw_register(struct device *dev, unsigned int reg) 1381 { 1382 struct rx_macro *rx = dev_get_drvdata(dev); 1383 1384 switch (reg) { 1385 case CDC_RX_TOP_TOP_CFG0: 1386 case CDC_RX_TOP_SWR_CTRL: 1387 case CDC_RX_TOP_DEBUG: 1388 case CDC_RX_TOP_DEBUG_BUS: 1389 case CDC_RX_TOP_DEBUG_EN0: 1390 case CDC_RX_TOP_DEBUG_EN1: 1391 case CDC_RX_TOP_DEBUG_EN2: 1392 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1393 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1394 case CDC_RX_TOP_HPHL_COMP_LUT: 1395 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1396 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1397 case CDC_RX_TOP_HPHR_COMP_LUT: 1398 case CDC_RX_TOP_DSD0_DEBUG_CFG0: 1399 case CDC_RX_TOP_DSD0_DEBUG_CFG1: 1400 case CDC_RX_TOP_DSD0_DEBUG_CFG3: 1401 case CDC_RX_TOP_DSD1_DEBUG_CFG0: 1402 case CDC_RX_TOP_DSD1_DEBUG_CFG1: 1403 case CDC_RX_TOP_DSD1_DEBUG_CFG3: 1404 case CDC_RX_TOP_RX_I2S_CTL: 1405 case CDC_RX_TOP_TX_I2S2_CTL: 1406 case CDC_RX_TOP_I2S_CLK: 1407 case CDC_RX_TOP_I2S_RESET: 1408 case CDC_RX_TOP_I2S_MUX: 1409 case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL: 1410 case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL: 1411 case CDC_RX_CLK_RST_CTRL_SWR_CONTROL: 1412 case CDC_RX_CLK_RST_CTRL_DSD_CONTROL: 1413 case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL: 1414 case CDC_RX_SOFTCLIP_CRC: 1415 case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL: 1416 case CDC_RX_INP_MUX_RX_INT0_CFG0: 1417 case CDC_RX_INP_MUX_RX_INT0_CFG1: 1418 case CDC_RX_INP_MUX_RX_INT1_CFG0: 1419 case CDC_RX_INP_MUX_RX_INT1_CFG1: 1420 case CDC_RX_INP_MUX_RX_INT2_CFG0: 1421 case CDC_RX_INP_MUX_RX_INT2_CFG1: 1422 case CDC_RX_INP_MUX_RX_MIX_CFG4: 1423 case CDC_RX_INP_MUX_RX_MIX_CFG5: 1424 case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0: 1425 case CDC_RX_CLSH_CRC: 1426 case CDC_RX_CLSH_DLY_CTRL: 1427 case CDC_RX_CLSH_DECAY_CTRL: 1428 case CDC_RX_CLSH_HPH_V_PA: 1429 case CDC_RX_CLSH_EAR_V_PA: 1430 case CDC_RX_CLSH_HPH_V_HD: 1431 case CDC_RX_CLSH_EAR_V_HD: 1432 case CDC_RX_CLSH_K1_MSB: 1433 case CDC_RX_CLSH_K1_LSB: 1434 case CDC_RX_CLSH_K2_MSB: 1435 case CDC_RX_CLSH_K2_LSB: 1436 case CDC_RX_CLSH_IDLE_CTRL: 1437 case CDC_RX_CLSH_IDLE_HPH: 1438 case CDC_RX_CLSH_IDLE_EAR: 1439 case CDC_RX_CLSH_TEST0: 1440 case CDC_RX_CLSH_TEST1: 1441 case CDC_RX_CLSH_OVR_VREF: 1442 case CDC_RX_CLSH_CLSG_CTL: 1443 case CDC_RX_CLSH_CLSG_CFG1: 1444 case CDC_RX_CLSH_CLSG_CFG2: 1445 case CDC_RX_BCL_VBAT_PATH_CTL: 1446 case CDC_RX_BCL_VBAT_CFG: 1447 case CDC_RX_BCL_VBAT_ADC_CAL1: 1448 case CDC_RX_BCL_VBAT_ADC_CAL2: 1449 case CDC_RX_BCL_VBAT_ADC_CAL3: 1450 case CDC_RX_BCL_VBAT_PK_EST1: 1451 case CDC_RX_BCL_VBAT_PK_EST2: 1452 case CDC_RX_BCL_VBAT_PK_EST3: 1453 case CDC_RX_BCL_VBAT_RF_PROC1: 1454 case CDC_RX_BCL_VBAT_RF_PROC2: 1455 case CDC_RX_BCL_VBAT_TAC1: 1456 case CDC_RX_BCL_VBAT_TAC2: 1457 case CDC_RX_BCL_VBAT_TAC3: 1458 case CDC_RX_BCL_VBAT_TAC4: 1459 case CDC_RX_BCL_VBAT_GAIN_UPD1: 1460 case CDC_RX_BCL_VBAT_GAIN_UPD2: 1461 case CDC_RX_BCL_VBAT_GAIN_UPD3: 1462 case CDC_RX_BCL_VBAT_GAIN_UPD4: 1463 case CDC_RX_BCL_VBAT_GAIN_UPD5: 1464 case CDC_RX_BCL_VBAT_DEBUG1: 1465 case CDC_RX_BCL_VBAT_BAN: 1466 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1: 1467 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2: 1468 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3: 1469 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4: 1470 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5: 1471 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6: 1472 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7: 1473 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8: 1474 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9: 1475 case CDC_RX_BCL_VBAT_ATTN1: 1476 case CDC_RX_BCL_VBAT_ATTN2: 1477 case CDC_RX_BCL_VBAT_ATTN3: 1478 case CDC_RX_BCL_VBAT_DECODE_CTL1: 1479 case CDC_RX_BCL_VBAT_DECODE_CTL2: 1480 case CDC_RX_BCL_VBAT_DECODE_CFG1: 1481 case CDC_RX_BCL_VBAT_DECODE_CFG2: 1482 case CDC_RX_BCL_VBAT_DECODE_CFG3: 1483 case CDC_RX_BCL_VBAT_DECODE_CFG4: 1484 case CDC_RX_INTR_CTRL_CFG: 1485 case CDC_RX_INTR_CTRL_PIN1_MASK0: 1486 case CDC_RX_INTR_CTRL_PIN2_MASK0: 1487 case CDC_RX_INTR_CTRL_LEVEL0: 1488 case CDC_RX_INTR_CTRL_BYPASS0: 1489 case CDC_RX_INTR_CTRL_SET0: 1490 case CDC_RX_RX0_RX_PATH_CTL: 1491 case CDC_RX_RX0_RX_PATH_CFG0: 1492 case CDC_RX_RX0_RX_PATH_CFG1: 1493 case CDC_RX_RX0_RX_PATH_CFG2: 1494 case CDC_RX_RX0_RX_PATH_CFG3: 1495 case CDC_RX_RX0_RX_VOL_CTL: 1496 case CDC_RX_RX0_RX_PATH_MIX_CTL: 1497 case CDC_RX_RX0_RX_PATH_MIX_CFG: 1498 case CDC_RX_RX0_RX_VOL_MIX_CTL: 1499 case CDC_RX_RX0_RX_PATH_SEC1: 1500 case CDC_RX_RX0_RX_PATH_SEC2: 1501 case CDC_RX_RX0_RX_PATH_SEC3: 1502 case CDC_RX_RX0_RX_PATH_SEC4: 1503 case CDC_RX_RX0_RX_PATH_SEC7: 1504 case CDC_RX_RX0_RX_PATH_MIX_SEC0: 1505 case CDC_RX_RX0_RX_PATH_MIX_SEC1: 1506 case CDC_RX_RX0_RX_PATH_DSM_CTL: 1507 case CDC_RX_RX0_RX_PATH_DSM_DATA1: 1508 case CDC_RX_RX0_RX_PATH_DSM_DATA2: 1509 case CDC_RX_RX0_RX_PATH_DSM_DATA3: 1510 case CDC_RX_RX0_RX_PATH_DSM_DATA4: 1511 case CDC_RX_RX0_RX_PATH_DSM_DATA5: 1512 case CDC_RX_RX0_RX_PATH_DSM_DATA6: 1513 case CDC_RX_IDLE_DETECT_PATH_CTL: 1514 case CDC_RX_IDLE_DETECT_CFG0: 1515 case CDC_RX_IDLE_DETECT_CFG1: 1516 case CDC_RX_IDLE_DETECT_CFG2: 1517 case CDC_RX_IDLE_DETECT_CFG3: 1518 case CDC_RX_COMPANDER0_CTL0: 1519 case CDC_RX_COMPANDER0_CTL1: 1520 case CDC_RX_COMPANDER0_CTL2: 1521 case CDC_RX_COMPANDER0_CTL3: 1522 case CDC_RX_COMPANDER0_CTL4: 1523 case CDC_RX_COMPANDER0_CTL5: 1524 case CDC_RX_COMPANDER0_CTL7: 1525 case CDC_RX_COMPANDER1_CTL0: 1526 case CDC_RX_COMPANDER1_CTL1: 1527 case CDC_RX_COMPANDER1_CTL2: 1528 case CDC_RX_COMPANDER1_CTL3: 1529 case CDC_RX_COMPANDER1_CTL4: 1530 case CDC_RX_COMPANDER1_CTL5: 1531 case CDC_RX_COMPANDER1_CTL7: 1532 case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL: 1533 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL: 1534 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL: 1535 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL: 1536 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL: 1537 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL: 1538 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL: 1539 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL: 1540 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL: 1541 case CDC_RX_SIDETONE_IIR0_IIR_CTL: 1542 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL: 1543 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL: 1544 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: 1545 case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL: 1546 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL: 1547 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL: 1548 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL: 1549 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL: 1550 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL: 1551 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL: 1552 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL: 1553 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL: 1554 case CDC_RX_SIDETONE_IIR1_IIR_CTL: 1555 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL: 1556 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: 1557 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: 1558 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0: 1559 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1: 1560 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2: 1561 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3: 1562 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0: 1563 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1: 1564 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2: 1565 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3: 1566 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL: 1567 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1: 1568 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL: 1569 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1: 1570 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL: 1571 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0: 1572 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL: 1573 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0: 1574 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL: 1575 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0: 1576 case CDC_RX_EC_ASRC0_CLK_RST_CTL: 1577 case CDC_RX_EC_ASRC0_CTL0: 1578 case CDC_RX_EC_ASRC0_CTL1: 1579 case CDC_RX_EC_ASRC0_FIFO_CTL: 1580 case CDC_RX_EC_ASRC1_CLK_RST_CTL: 1581 case CDC_RX_EC_ASRC1_CTL0: 1582 case CDC_RX_EC_ASRC1_CTL1: 1583 case CDC_RX_EC_ASRC1_FIFO_CTL: 1584 case CDC_RX_EC_ASRC2_CLK_RST_CTL: 1585 case CDC_RX_EC_ASRC2_CTL0: 1586 case CDC_RX_EC_ASRC2_CTL1: 1587 case CDC_RX_EC_ASRC2_FIFO_CTL: 1588 case CDC_RX_DSD0_PATH_CTL: 1589 case CDC_RX_DSD0_CFG0: 1590 case CDC_RX_DSD0_CFG1: 1591 case CDC_RX_DSD0_CFG2: 1592 case CDC_RX_DSD1_PATH_CTL: 1593 case CDC_RX_DSD1_CFG0: 1594 case CDC_RX_DSD1_CFG1: 1595 case CDC_RX_DSD1_CFG2: 1596 return true; 1597 } 1598 1599 switch (rx->codec_version) { 1600 case LPASS_CODEC_VERSION_1_0: 1601 case LPASS_CODEC_VERSION_1_1: 1602 case LPASS_CODEC_VERSION_1_2: 1603 case LPASS_CODEC_VERSION_2_0: 1604 return rx_pre_2_5_is_rw_register(dev, reg); 1605 case LPASS_CODEC_VERSION_2_5: 1606 case LPASS_CODEC_VERSION_2_6: 1607 case LPASS_CODEC_VERSION_2_7: 1608 case LPASS_CODEC_VERSION_2_8: 1609 return rx_2_5_is_rw_register(dev, reg); 1610 default: 1611 break; 1612 } 1613 1614 return false; 1615 } 1616 1617 static bool rx_is_writeable_register(struct device *dev, unsigned int reg) 1618 { 1619 bool ret; 1620 1621 ret = rx_is_rw_register(dev, reg); 1622 if (!ret) 1623 return rx_is_wronly_register(dev, reg); 1624 1625 return ret; 1626 } 1627 1628 static bool rx_is_readable_register(struct device *dev, unsigned int reg) 1629 { 1630 switch (reg) { 1631 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1632 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1633 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1634 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1635 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1636 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1637 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1638 case CDC_RX_BCL_VBAT_DECODE_ST: 1639 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1640 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1641 case CDC_RX_COMPANDER0_CTL6: 1642 case CDC_RX_COMPANDER1_CTL6: 1643 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1644 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1645 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1646 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1647 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1648 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1649 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1650 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1651 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1652 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1653 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1654 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1655 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1656 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1657 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1658 return true; 1659 } 1660 1661 return rx_is_rw_register(dev, reg); 1662 } 1663 1664 static struct regmap_config rx_regmap_config = { 1665 .name = "rx_macro", 1666 .reg_bits = 16, 1667 .val_bits = 32, /* 8 but with 32 bit read/write */ 1668 .reg_stride = 4, 1669 .cache_type = REGCACHE_FLAT, 1670 .max_register = RX_MAX_OFFSET, 1671 .writeable_reg = rx_is_writeable_register, 1672 .volatile_reg = rx_is_volatile_register, 1673 .readable_reg = rx_is_readable_register, 1674 }; 1675 1676 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, 1677 struct snd_ctl_elem_value *ucontrol) 1678 { 1679 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1680 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1681 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1682 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1683 unsigned short look_ahead_dly_reg; 1684 unsigned int val; 1685 1686 val = ucontrol->value.enumerated.item[0]; 1687 1688 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) 1689 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); 1690 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) 1691 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); 1692 1693 /* Set Look Ahead Delay */ 1694 if (val) 1695 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1696 CDC_RX_DLY_ZN_EN_MASK, 1697 CDC_RX_DLY_ZN_ENABLE); 1698 else 1699 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1700 CDC_RX_DLY_ZN_EN_MASK, 0); 1701 /* Set DEM INP Select */ 1702 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1703 } 1704 1705 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1706 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum, 1707 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1708 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1709 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum, 1710 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1711 1712 static const struct snd_kcontrol_new rx_2_5_int1_dem_inp_mux = 1713 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_2_5_int1_dem_inp_enum, 1714 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1715 1716 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1717 int rate_reg_val, u32 sample_rate) 1718 { 1719 1720 u8 int_1_mix1_inp; 1721 u32 j, port; 1722 u16 int_mux_cfg0, int_mux_cfg1; 1723 u16 int_fs_reg; 1724 u8 inp0_sel, inp1_sel, inp2_sel; 1725 struct snd_soc_component *component = dai->component; 1726 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1727 1728 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1729 int_1_mix1_inp = port; 1730 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0; 1731 /* 1732 * Loop through all interpolator MUX inputs and find out 1733 * to which interpolator input, the rx port 1734 * is connected 1735 */ 1736 for (j = 0; j < INTERP_MAX; j++) { 1737 int_mux_cfg1 = int_mux_cfg0 + 4; 1738 1739 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1740 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 1741 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1742 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 1743 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 1744 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 1745 1746 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1747 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1748 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 1749 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); 1750 /* sample_rate is in Hz */ 1751 snd_soc_component_update_bits(component, int_fs_reg, 1752 CDC_RX_PATH_PCM_RATE_MASK, 1753 rate_reg_val); 1754 } 1755 int_mux_cfg0 += 8; 1756 } 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1763 int rate_reg_val, u32 sample_rate) 1764 { 1765 1766 u8 int_2_inp; 1767 u32 j, port; 1768 u16 int_mux_cfg1, int_fs_reg; 1769 u8 int_mux_cfg1_val; 1770 struct snd_soc_component *component = dai->component; 1771 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1772 1773 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1774 int_2_inp = port; 1775 1776 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1; 1777 for (j = 0; j < INTERP_MAX; j++) { 1778 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 1779 CDC_RX_INTX_2_SEL_MASK); 1780 1781 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 1782 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); 1783 snd_soc_component_update_bits(component, int_fs_reg, 1784 CDC_RX_RXn_MIX_PCM_RATE_MASK, 1785 rate_reg_val); 1786 } 1787 int_mux_cfg1 += 8; 1788 } 1789 } 1790 return 0; 1791 } 1792 1793 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, 1794 u32 sample_rate) 1795 { 1796 int rate_val = 0; 1797 int i, ret; 1798 1799 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) 1800 if (sample_rate == sr_val_tbl[i].sample_rate) 1801 rate_val = sr_val_tbl[i].rate_val; 1802 1803 ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate); 1804 if (ret) 1805 return ret; 1806 1807 ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate); 1808 1809 return ret; 1810 } 1811 1812 static int rx_macro_hw_params(struct snd_pcm_substream *substream, 1813 struct snd_pcm_hw_params *params, 1814 struct snd_soc_dai *dai) 1815 { 1816 struct snd_soc_component *component = dai->component; 1817 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1818 int ret; 1819 1820 switch (substream->stream) { 1821 case SNDRV_PCM_STREAM_PLAYBACK: 1822 ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); 1823 if (ret) { 1824 dev_err(component->dev, "%s: cannot set sample rate: %u\n", 1825 __func__, params_rate(params)); 1826 return ret; 1827 } 1828 rx->bit_width[dai->id] = params_width(params); 1829 break; 1830 default: 1831 break; 1832 } 1833 return 0; 1834 } 1835 1836 static int rx_macro_get_channel_map(struct snd_soc_dai *dai, 1837 unsigned int *tx_num, unsigned int *tx_slot, 1838 unsigned int *rx_num, unsigned int *rx_slot) 1839 { 1840 struct snd_soc_component *component = dai->component; 1841 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1842 u16 val, mask = 0, cnt = 0, temp; 1843 1844 switch (dai->id) { 1845 case RX_MACRO_AIF1_PB: 1846 case RX_MACRO_AIF2_PB: 1847 case RX_MACRO_AIF3_PB: 1848 case RX_MACRO_AIF4_PB: 1849 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], 1850 RX_MACRO_PORTS_MAX) { 1851 mask |= (1 << temp); 1852 if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT) 1853 break; 1854 } 1855 /* 1856 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 1857 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 1858 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 1859 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 1860 * AIFn can pair to any CDC_DMA_RX_n port. 1861 * In general, below convention is used:: 1862 * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/ 1863 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4) 1864 */ 1865 if (mask & 0x0C) 1866 mask = mask >> 2; 1867 if ((mask & 0x10) || (mask & 0x20)) 1868 mask = 0x1; 1869 *rx_slot = mask; 1870 *rx_num = rx->active_ch_cnt[dai->id]; 1871 break; 1872 case RX_MACRO_AIF_ECHO: 1873 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4); 1874 if (val & RX_MACRO_EC_MIX_TX0_MASK) { 1875 mask |= 0x1; 1876 cnt++; 1877 } 1878 if (val & RX_MACRO_EC_MIX_TX1_MASK) { 1879 mask |= 0x2; 1880 cnt++; 1881 } 1882 val = snd_soc_component_read(component, 1883 CDC_RX_INP_MUX_RX_MIX_CFG5); 1884 if (val & RX_MACRO_EC_MIX_TX2_MASK) { 1885 mask |= 0x4; 1886 cnt++; 1887 } 1888 *tx_slot = mask; 1889 *tx_num = cnt; 1890 break; 1891 default: 1892 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1893 break; 1894 } 1895 return 0; 1896 } 1897 1898 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1899 { 1900 struct snd_soc_component *component = dai->component; 1901 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1902 uint16_t j, reg, mix_reg, dsm_reg; 1903 u16 int_mux_cfg0, int_mux_cfg1; 1904 u8 int_mux_cfg0_val, int_mux_cfg1_val; 1905 1906 switch (dai->id) { 1907 case RX_MACRO_AIF1_PB: 1908 case RX_MACRO_AIF2_PB: 1909 case RX_MACRO_AIF3_PB: 1910 case RX_MACRO_AIF4_PB: 1911 for (j = 0; j < INTERP_MAX; j++) { 1912 reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); 1913 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); 1914 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j); 1915 1916 if (mute) { 1917 snd_soc_component_update_bits(component, reg, 1918 CDC_RX_PATH_PGA_MUTE_MASK, 1919 CDC_RX_PATH_PGA_MUTE_ENABLE); 1920 snd_soc_component_update_bits(component, mix_reg, 1921 CDC_RX_PATH_PGA_MUTE_MASK, 1922 CDC_RX_PATH_PGA_MUTE_ENABLE); 1923 } else { 1924 snd_soc_component_update_bits(component, reg, 1925 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1926 snd_soc_component_update_bits(component, mix_reg, 1927 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1928 } 1929 1930 if (j == INTERP_AUX) 1931 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2); 1932 1933 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8; 1934 int_mux_cfg1 = int_mux_cfg0 + 4; 1935 int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0); 1936 int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1); 1937 1938 if (snd_soc_component_read(component, dsm_reg) & 0x01) { 1939 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0)) 1940 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1941 if (int_mux_cfg1_val & 0x0F) { 1942 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1943 snd_soc_component_update_bits(component, mix_reg, 0x20, 1944 0x20); 1945 } 1946 } 1947 } 1948 break; 1949 default: 1950 break; 1951 } 1952 return 0; 1953 } 1954 1955 static const struct snd_soc_dai_ops rx_macro_dai_ops = { 1956 .hw_params = rx_macro_hw_params, 1957 .get_channel_map = rx_macro_get_channel_map, 1958 .mute_stream = rx_macro_digital_mute, 1959 }; 1960 1961 static struct snd_soc_dai_driver rx_macro_dai[] = { 1962 { 1963 .name = "rx_macro_rx1", 1964 .id = RX_MACRO_AIF1_PB, 1965 .playback = { 1966 .stream_name = "RX_MACRO_AIF1 Playback", 1967 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1968 .formats = RX_MACRO_FORMATS, 1969 .rate_max = 384000, 1970 .rate_min = 8000, 1971 .channels_min = 1, 1972 .channels_max = 2, 1973 }, 1974 .ops = &rx_macro_dai_ops, 1975 }, 1976 { 1977 .name = "rx_macro_rx2", 1978 .id = RX_MACRO_AIF2_PB, 1979 .playback = { 1980 .stream_name = "RX_MACRO_AIF2 Playback", 1981 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1982 .formats = RX_MACRO_FORMATS, 1983 .rate_max = 384000, 1984 .rate_min = 8000, 1985 .channels_min = 1, 1986 .channels_max = 2, 1987 }, 1988 .ops = &rx_macro_dai_ops, 1989 }, 1990 { 1991 .name = "rx_macro_rx3", 1992 .id = RX_MACRO_AIF3_PB, 1993 .playback = { 1994 .stream_name = "RX_MACRO_AIF3 Playback", 1995 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1996 .formats = RX_MACRO_FORMATS, 1997 .rate_max = 384000, 1998 .rate_min = 8000, 1999 .channels_min = 1, 2000 .channels_max = 2, 2001 }, 2002 .ops = &rx_macro_dai_ops, 2003 }, 2004 { 2005 .name = "rx_macro_rx4", 2006 .id = RX_MACRO_AIF4_PB, 2007 .playback = { 2008 .stream_name = "RX_MACRO_AIF4 Playback", 2009 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 2010 .formats = RX_MACRO_FORMATS, 2011 .rate_max = 384000, 2012 .rate_min = 8000, 2013 .channels_min = 1, 2014 .channels_max = 2, 2015 }, 2016 .ops = &rx_macro_dai_ops, 2017 }, 2018 { 2019 .name = "rx_macro_echo", 2020 .id = RX_MACRO_AIF_ECHO, 2021 .capture = { 2022 .stream_name = "RX_AIF_ECHO Capture", 2023 .rates = RX_MACRO_ECHO_RATES, 2024 .formats = RX_MACRO_ECHO_FORMATS, 2025 .rate_max = 48000, 2026 .rate_min = 8000, 2027 .channels_min = 1, 2028 .channels_max = 3, 2029 }, 2030 .ops = &rx_macro_dai_ops, 2031 }, 2032 }; 2033 2034 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) 2035 { 2036 struct regmap *regmap = rx->regmap; 2037 2038 if (mclk_enable) { 2039 if (rx->rx_mclk_users == 0) { 2040 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 2041 CDC_RX_CLK_MCLK_EN_MASK | 2042 CDC_RX_CLK_MCLK2_EN_MASK, 2043 CDC_RX_CLK_MCLK_ENABLE | 2044 CDC_RX_CLK_MCLK2_ENABLE); 2045 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2046 CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); 2047 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2048 CDC_RX_FS_MCLK_CNT_EN_MASK, 2049 CDC_RX_FS_MCLK_CNT_ENABLE); 2050 regcache_mark_dirty(regmap); 2051 regcache_sync(regmap); 2052 } 2053 rx->rx_mclk_users++; 2054 } else { 2055 if (rx->rx_mclk_users <= 0) { 2056 dev_err(rx->dev, "%s: clock already disabled\n", __func__); 2057 rx->rx_mclk_users = 0; 2058 return; 2059 } 2060 rx->rx_mclk_users--; 2061 if (rx->rx_mclk_users == 0) { 2062 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2063 CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0); 2064 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2065 CDC_RX_FS_MCLK_CNT_CLR_MASK, 2066 CDC_RX_FS_MCLK_CNT_CLR); 2067 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 2068 CDC_RX_CLK_MCLK_EN_MASK | 2069 CDC_RX_CLK_MCLK2_EN_MASK, 0x0); 2070 } 2071 } 2072 } 2073 2074 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, 2075 struct snd_kcontrol *kcontrol, int event) 2076 { 2077 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2078 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2079 int ret = 0; 2080 2081 switch (event) { 2082 case SND_SOC_DAPM_PRE_PMU: 2083 rx_macro_mclk_enable(rx, true); 2084 break; 2085 case SND_SOC_DAPM_POST_PMD: 2086 rx_macro_mclk_enable(rx, false); 2087 break; 2088 default: 2089 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); 2090 ret = -EINVAL; 2091 } 2092 return ret; 2093 } 2094 2095 static bool rx_macro_adie_lb(struct snd_soc_component *component, 2096 int interp_idx) 2097 { 2098 u16 int_mux_cfg0, int_mux_cfg1; 2099 u8 int_n_inp0, int_n_inp1, int_n_inp2; 2100 2101 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 2102 int_mux_cfg1 = int_mux_cfg0 + 4; 2103 2104 int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 2105 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 2106 int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 2107 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 2108 int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 2109 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 2110 2111 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 2112 int_n_inp0 == INTn_1_INP_SEL_DEC1 || 2113 int_n_inp0 == INTn_1_INP_SEL_IIR0 || 2114 int_n_inp0 == INTn_1_INP_SEL_IIR1) 2115 return true; 2116 2117 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 2118 int_n_inp1 == INTn_1_INP_SEL_DEC1 || 2119 int_n_inp1 == INTn_1_INP_SEL_IIR0 || 2120 int_n_inp1 == INTn_1_INP_SEL_IIR1) 2121 return true; 2122 2123 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 2124 int_n_inp2 == INTn_1_INP_SEL_DEC1 || 2125 int_n_inp2 == INTn_1_INP_SEL_IIR0 || 2126 int_n_inp2 == INTn_1_INP_SEL_IIR1) 2127 return true; 2128 2129 return false; 2130 } 2131 2132 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 2133 int event, int interp_idx); 2134 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, 2135 struct snd_kcontrol *kcontrol, 2136 int event) 2137 { 2138 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2139 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2140 u16 gain_reg, reg; 2141 2142 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); 2143 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); 2144 2145 switch (event) { 2146 case SND_SOC_DAPM_PRE_PMU: 2147 rx_macro_enable_interp_clk(component, event, w->shift); 2148 if (rx_macro_adie_lb(component, w->shift)) 2149 snd_soc_component_update_bits(component, reg, 2150 CDC_RX_PATH_CLK_EN_MASK, 2151 CDC_RX_PATH_CLK_ENABLE); 2152 break; 2153 case SND_SOC_DAPM_POST_PMU: 2154 snd_soc_component_write(component, gain_reg, 2155 snd_soc_component_read(component, gain_reg)); 2156 break; 2157 case SND_SOC_DAPM_POST_PMD: 2158 rx_macro_enable_interp_clk(component, event, w->shift); 2159 break; 2160 } 2161 2162 return 0; 2163 } 2164 2165 static int rx_macro_config_compander(struct snd_soc_component *component, 2166 struct rx_macro *rx, 2167 int comp, int event) 2168 { 2169 u8 pcm_rate, val; 2170 2171 /* AUX does not have compander */ 2172 if (comp == INTERP_AUX) 2173 return 0; 2174 2175 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F; 2176 if (pcm_rate < 0x06) 2177 val = 0x03; 2178 else if (pcm_rate < 0x08) 2179 val = 0x01; 2180 else if (pcm_rate < 0x0B) 2181 val = 0x02; 2182 else 2183 val = 0x00; 2184 2185 if (SND_SOC_DAPM_EVENT_ON(event)) 2186 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), 2187 CDC_RX_DC_COEFF_SEL_MASK, val); 2188 2189 if (SND_SOC_DAPM_EVENT_OFF(event)) 2190 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), 2191 CDC_RX_DC_COEFF_SEL_MASK, 0x3); 2192 if (!rx->comp_enabled[comp]) 2193 return 0; 2194 2195 if (SND_SOC_DAPM_EVENT_ON(event)) { 2196 /* Enable Compander Clock */ 2197 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2198 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1); 2199 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2200 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1); 2201 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2202 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0); 2203 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), 2204 CDC_RX_RXn_COMP_EN_MASK, 0x1); 2205 } 2206 2207 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2208 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2209 CDC_RX_COMPANDERn_HALT_MASK, 0x1); 2210 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), 2211 CDC_RX_RXn_COMP_EN_MASK, 0x0); 2212 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2213 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0); 2214 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2215 CDC_RX_COMPANDERn_HALT_MASK, 0x0); 2216 } 2217 2218 return 0; 2219 } 2220 2221 static int rx_macro_load_compander_coeff(struct snd_soc_component *component, 2222 struct rx_macro *rx, 2223 int comp, int event) 2224 { 2225 u16 comp_coeff_lsb_reg, comp_coeff_msb_reg; 2226 int i; 2227 int hph_pwr_mode; 2228 2229 /* AUX does not have compander */ 2230 if (comp == INTERP_AUX) 2231 return 0; 2232 2233 if (!rx->comp_enabled[comp]) 2234 return 0; 2235 2236 if (comp == INTERP_HPHL) { 2237 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB; 2238 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB; 2239 } else if (comp == INTERP_HPHR) { 2240 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB; 2241 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB; 2242 } else { 2243 /* compander coefficients are loaded only for hph path */ 2244 return 0; 2245 } 2246 2247 hph_pwr_mode = rx->hph_pwr_mode; 2248 2249 if (SND_SOC_DAPM_EVENT_ON(event)) { 2250 /* Load Compander Coeff */ 2251 for (i = 0; i < COMP_MAX_COEFF; i++) { 2252 snd_soc_component_write(component, comp_coeff_lsb_reg, 2253 comp_coeff_table[hph_pwr_mode][i].lsb); 2254 snd_soc_component_write(component, comp_coeff_msb_reg, 2255 comp_coeff_table[hph_pwr_mode][i].msb); 2256 } 2257 } 2258 2259 return 0; 2260 } 2261 2262 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, 2263 struct rx_macro *rx, bool enable) 2264 { 2265 if (enable) { 2266 if (rx->softclip_clk_users == 0) 2267 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2268 CDC_RX_SOFTCLIP_CLK_EN_MASK, 1); 2269 rx->softclip_clk_users++; 2270 } else { 2271 rx->softclip_clk_users--; 2272 if (rx->softclip_clk_users == 0) 2273 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2274 CDC_RX_SOFTCLIP_CLK_EN_MASK, 0); 2275 } 2276 } 2277 2278 static int rx_macro_config_softclip(struct snd_soc_component *component, 2279 struct rx_macro *rx, int event) 2280 { 2281 2282 if (!rx->is_softclip_on) 2283 return 0; 2284 2285 if (SND_SOC_DAPM_EVENT_ON(event)) { 2286 /* Enable Softclip clock */ 2287 rx_macro_enable_softclip_clk(component, rx, true); 2288 /* Enable Softclip control */ 2289 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2290 CDC_RX_SOFTCLIP_EN_MASK, 0x01); 2291 } 2292 2293 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2294 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2295 CDC_RX_SOFTCLIP_EN_MASK, 0x0); 2296 rx_macro_enable_softclip_clk(component, rx, false); 2297 } 2298 2299 return 0; 2300 } 2301 2302 static int rx_macro_config_aux_hpf(struct snd_soc_component *component, 2303 struct rx_macro *rx, int event) 2304 { 2305 if (SND_SOC_DAPM_EVENT_ON(event)) { 2306 /* Update Aux HPF control */ 2307 if (!rx->is_aux_hpf_on) 2308 snd_soc_component_update_bits(component, 2309 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00); 2310 } 2311 2312 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2313 /* Reset to default (HPF=ON) */ 2314 snd_soc_component_update_bits(component, 2315 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04); 2316 } 2317 2318 return 0; 2319 } 2320 2321 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) 2322 { 2323 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) 2324 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, 2325 CDC_RX_CLSH_CLK_EN_MASK, enable); 2326 if (rx->clsh_users < 0) 2327 rx->clsh_users = 0; 2328 } 2329 2330 static int rx_macro_config_classh(struct snd_soc_component *component, 2331 struct rx_macro *rx, 2332 int interp_n, int event) 2333 { 2334 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2335 rx_macro_enable_clsh_block(rx, false); 2336 return 0; 2337 } 2338 2339 if (!SND_SOC_DAPM_EVENT_ON(event)) 2340 return 0; 2341 2342 rx_macro_enable_clsh_block(rx, true); 2343 if (interp_n == INTERP_HPHL || 2344 interp_n == INTERP_HPHR) { 2345 /* 2346 * These K1 values depend on the Headphone Impedance 2347 * For now it is assumed to be 16 ohm 2348 */ 2349 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0); 2350 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB, 2351 CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0); 2352 } 2353 switch (interp_n) { 2354 case INTERP_HPHL: 2355 if (rx->is_ear_mode_on) 2356 snd_soc_component_update_bits(component, 2357 CDC_RX_CLSH_HPH_V_PA, 2358 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2359 else 2360 snd_soc_component_update_bits(component, 2361 CDC_RX_CLSH_HPH_V_PA, 2362 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2363 snd_soc_component_update_bits(component, 2364 CDC_RX_CLSH_DECAY_CTRL, 2365 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2366 snd_soc_component_write_field(component, 2367 CDC_RX_RXn_RX_PATH_CFG0(rx, 0), 2368 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2369 break; 2370 case INTERP_HPHR: 2371 if (rx->is_ear_mode_on) 2372 snd_soc_component_update_bits(component, 2373 CDC_RX_CLSH_HPH_V_PA, 2374 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2375 else 2376 snd_soc_component_update_bits(component, 2377 CDC_RX_CLSH_HPH_V_PA, 2378 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2379 snd_soc_component_update_bits(component, 2380 CDC_RX_CLSH_DECAY_CTRL, 2381 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2382 snd_soc_component_write_field(component, 2383 CDC_RX_RXn_RX_PATH_CFG0(rx, 1), 2384 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2385 break; 2386 case INTERP_AUX: 2387 snd_soc_component_update_bits(component, 2388 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), 2389 CDC_RX_RX2_DLY_Z_EN_MASK, 1); 2390 snd_soc_component_write_field(component, 2391 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), 2392 CDC_RX_RX2_CLSH_EN_MASK, 1); 2393 break; 2394 } 2395 2396 return 0; 2397 } 2398 2399 static void rx_macro_hd2_control(struct snd_soc_component *component, 2400 u16 interp_idx, int event) 2401 { 2402 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2403 u16 hd2_scale_reg, hd2_enable_reg; 2404 2405 switch (interp_idx) { 2406 case INTERP_HPHL: 2407 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0); 2408 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); 2409 break; 2410 case INTERP_HPHR: 2411 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1); 2412 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); 2413 break; 2414 } 2415 2416 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2417 snd_soc_component_update_bits(component, hd2_scale_reg, 2418 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14); 2419 snd_soc_component_write_field(component, hd2_enable_reg, 2420 CDC_RX_RXn_HD2_EN_MASK, 1); 2421 } 2422 2423 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2424 snd_soc_component_write_field(component, hd2_enable_reg, 2425 CDC_RX_RXn_HD2_EN_MASK, 0); 2426 snd_soc_component_update_bits(component, hd2_scale_reg, 2427 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0); 2428 } 2429 } 2430 2431 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, 2432 struct snd_ctl_elem_value *ucontrol) 2433 { 2434 struct snd_soc_component *component = 2435 snd_soc_kcontrol_component(kcontrol); 2436 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2437 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2438 2439 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; 2440 return 0; 2441 } 2442 2443 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, 2444 struct snd_ctl_elem_value *ucontrol) 2445 { 2446 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2447 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2448 int value = ucontrol->value.integer.value[0]; 2449 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2450 2451 rx->comp_enabled[comp] = value; 2452 2453 return 0; 2454 } 2455 2456 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, 2457 struct snd_ctl_elem_value *ucontrol) 2458 { 2459 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2460 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2461 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2462 2463 ucontrol->value.enumerated.item[0] = 2464 rx->rx_port_value[widget->shift]; 2465 return 0; 2466 } 2467 2468 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, 2469 struct snd_ctl_elem_value *ucontrol) 2470 { 2471 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2472 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2473 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2474 struct snd_soc_dapm_update *update = NULL; 2475 u32 rx_port_value = ucontrol->value.enumerated.item[0]; 2476 u32 aif_rst; 2477 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2478 2479 aif_rst = rx->rx_port_value[widget->shift]; 2480 if (!rx_port_value) { 2481 if (aif_rst == 0) 2482 return 0; 2483 if (aif_rst > RX_MACRO_AIF4_PB) { 2484 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 2485 return 0; 2486 } 2487 } 2488 rx->rx_port_value[widget->shift] = rx_port_value; 2489 2490 switch (rx_port_value) { 2491 case 0: 2492 if (rx->active_ch_cnt[aif_rst]) { 2493 clear_bit(widget->shift, 2494 &rx->active_ch_mask[aif_rst]); 2495 rx->active_ch_cnt[aif_rst]--; 2496 } 2497 break; 2498 case 1: 2499 case 2: 2500 case 3: 2501 case 4: 2502 set_bit(widget->shift, 2503 &rx->active_ch_mask[rx_port_value]); 2504 rx->active_ch_cnt[rx_port_value]++; 2505 break; 2506 default: 2507 dev_err(component->dev, 2508 "%s:Invalid AIF_ID for RX_MACRO MUX %d\n", 2509 __func__, rx_port_value); 2510 goto err; 2511 } 2512 2513 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 2514 rx_port_value, e, update); 2515 return 0; 2516 err: 2517 return -EINVAL; 2518 } 2519 2520 static const struct snd_kcontrol_new rx_macro_rx0_mux = 2521 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum, 2522 rx_macro_mux_get, rx_macro_mux_put); 2523 static const struct snd_kcontrol_new rx_macro_rx1_mux = 2524 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum, 2525 rx_macro_mux_get, rx_macro_mux_put); 2526 static const struct snd_kcontrol_new rx_macro_rx2_mux = 2527 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum, 2528 rx_macro_mux_get, rx_macro_mux_put); 2529 static const struct snd_kcontrol_new rx_macro_rx3_mux = 2530 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum, 2531 rx_macro_mux_get, rx_macro_mux_put); 2532 static const struct snd_kcontrol_new rx_macro_rx4_mux = 2533 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum, 2534 rx_macro_mux_get, rx_macro_mux_put); 2535 static const struct snd_kcontrol_new rx_macro_rx5_mux = 2536 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum, 2537 rx_macro_mux_get, rx_macro_mux_put); 2538 2539 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, 2540 struct snd_ctl_elem_value *ucontrol) 2541 { 2542 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2543 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2544 2545 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; 2546 return 0; 2547 } 2548 2549 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, 2550 struct snd_ctl_elem_value *ucontrol) 2551 { 2552 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2553 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2554 2555 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); 2556 return 0; 2557 } 2558 2559 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2560 struct snd_ctl_elem_value *ucontrol) 2561 { 2562 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2563 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2564 2565 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; 2566 return 0; 2567 } 2568 2569 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2570 struct snd_ctl_elem_value *ucontrol) 2571 { 2572 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2573 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2574 2575 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; 2576 return 0; 2577 } 2578 2579 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2580 struct snd_ctl_elem_value *ucontrol) 2581 { 2582 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2583 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2584 2585 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; 2586 return 0; 2587 } 2588 2589 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2590 struct snd_ctl_elem_value *ucontrol) 2591 { 2592 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2593 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2594 2595 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; 2596 return 0; 2597 } 2598 2599 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 2600 struct snd_ctl_elem_value *ucontrol) 2601 { 2602 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2603 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2604 2605 ucontrol->value.integer.value[0] = rx->is_softclip_on; 2606 2607 return 0; 2608 } 2609 2610 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 2611 struct snd_ctl_elem_value *ucontrol) 2612 { 2613 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2614 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2615 2616 rx->is_softclip_on = ucontrol->value.integer.value[0]; 2617 2618 return 0; 2619 } 2620 2621 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol, 2622 struct snd_ctl_elem_value *ucontrol) 2623 { 2624 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2625 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2626 2627 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; 2628 2629 return 0; 2630 } 2631 2632 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol, 2633 struct snd_ctl_elem_value *ucontrol) 2634 { 2635 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2636 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2637 2638 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; 2639 2640 return 0; 2641 } 2642 2643 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, 2644 struct rx_macro *rx, 2645 u16 interp_idx, int event) 2646 { 2647 u16 hph_lut_bypass_reg; 2648 u16 hph_comp_ctrl7; 2649 2650 switch (interp_idx) { 2651 case INTERP_HPHL: 2652 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT; 2653 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7; 2654 break; 2655 case INTERP_HPHR: 2656 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT; 2657 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7; 2658 break; 2659 default: 2660 return -EINVAL; 2661 } 2662 2663 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2664 if (interp_idx == INTERP_HPHL) { 2665 if (rx->is_ear_mode_on) 2666 snd_soc_component_write_field(component, 2667 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), 2668 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1); 2669 else 2670 snd_soc_component_write_field(component, 2671 hph_lut_bypass_reg, 2672 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2673 } else { 2674 snd_soc_component_write_field(component, hph_lut_bypass_reg, 2675 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2676 } 2677 if (rx->hph_pwr_mode) 2678 snd_soc_component_write_field(component, hph_comp_ctrl7, 2679 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0); 2680 } 2681 2682 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2683 snd_soc_component_write_field(component, 2684 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), 2685 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0); 2686 snd_soc_component_update_bits(component, hph_lut_bypass_reg, 2687 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0); 2688 snd_soc_component_write_field(component, hph_comp_ctrl7, 2689 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1); 2690 } 2691 2692 return 0; 2693 } 2694 2695 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 2696 int event, int interp_idx) 2697 { 2698 u16 main_reg, dsm_reg, rx_cfg2_reg; 2699 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2700 2701 main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx); 2702 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx); 2703 if (interp_idx == INTERP_AUX) 2704 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2); 2705 2706 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx); 2707 2708 if (SND_SOC_DAPM_EVENT_ON(event)) { 2709 if (rx->main_clk_users[interp_idx] == 0) { 2710 /* Main path PGA mute enable */ 2711 snd_soc_component_write_field(component, main_reg, 2712 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2713 snd_soc_component_write_field(component, dsm_reg, 2714 CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1); 2715 snd_soc_component_update_bits(component, rx_cfg2_reg, 2716 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03); 2717 rx_macro_load_compander_coeff(component, rx, interp_idx, event); 2718 if (rx->hph_hd2_mode) 2719 rx_macro_hd2_control(component, interp_idx, event); 2720 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2721 rx_macro_config_compander(component, rx, interp_idx, event); 2722 if (interp_idx == INTERP_AUX) { 2723 rx_macro_config_softclip(component, rx, event); 2724 rx_macro_config_aux_hpf(component, rx, event); 2725 } 2726 rx_macro_config_classh(component, rx, interp_idx, event); 2727 } 2728 rx->main_clk_users[interp_idx]++; 2729 } 2730 2731 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2732 rx->main_clk_users[interp_idx]--; 2733 if (rx->main_clk_users[interp_idx] <= 0) { 2734 rx->main_clk_users[interp_idx] = 0; 2735 /* Main path PGA mute enable */ 2736 snd_soc_component_write_field(component, main_reg, 2737 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2738 /* Clk Disable */ 2739 snd_soc_component_write_field(component, dsm_reg, 2740 CDC_RX_RXn_DSM_CLK_EN_MASK, 0); 2741 snd_soc_component_write_field(component, main_reg, 2742 CDC_RX_PATH_CLK_EN_MASK, 0); 2743 /* Reset enable and disable */ 2744 snd_soc_component_write_field(component, main_reg, 2745 CDC_RX_PATH_RESET_EN_MASK, 1); 2746 snd_soc_component_write_field(component, main_reg, 2747 CDC_RX_PATH_RESET_EN_MASK, 0); 2748 /* Reset rate to 48K*/ 2749 snd_soc_component_update_bits(component, main_reg, 2750 CDC_RX_PATH_PCM_RATE_MASK, 2751 0x04); 2752 snd_soc_component_update_bits(component, rx_cfg2_reg, 2753 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00); 2754 rx_macro_config_classh(component, rx, interp_idx, event); 2755 rx_macro_config_compander(component, rx, interp_idx, event); 2756 if (interp_idx == INTERP_AUX) { 2757 rx_macro_config_softclip(component, rx, event); 2758 rx_macro_config_aux_hpf(component, rx, event); 2759 } 2760 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2761 if (rx->hph_hd2_mode) 2762 rx_macro_hd2_control(component, interp_idx, event); 2763 } 2764 } 2765 2766 return rx->main_clk_users[interp_idx]; 2767 } 2768 2769 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 2770 struct snd_kcontrol *kcontrol, int event) 2771 { 2772 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2773 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2774 u16 gain_reg, mix_reg; 2775 2776 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); 2777 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); 2778 2779 switch (event) { 2780 case SND_SOC_DAPM_PRE_PMU: 2781 rx_macro_enable_interp_clk(component, event, w->shift); 2782 break; 2783 case SND_SOC_DAPM_POST_PMU: 2784 snd_soc_component_write(component, gain_reg, 2785 snd_soc_component_read(component, gain_reg)); 2786 break; 2787 case SND_SOC_DAPM_POST_PMD: 2788 /* Clk Disable */ 2789 snd_soc_component_update_bits(component, mix_reg, 2790 CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00); 2791 rx_macro_enable_interp_clk(component, event, w->shift); 2792 /* Reset enable and disable */ 2793 snd_soc_component_update_bits(component, mix_reg, 2794 CDC_RX_RXn_MIX_RESET_MASK, 2795 CDC_RX_RXn_MIX_RESET); 2796 snd_soc_component_update_bits(component, mix_reg, 2797 CDC_RX_RXn_MIX_RESET_MASK, 0x00); 2798 break; 2799 } 2800 2801 return 0; 2802 } 2803 2804 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, 2805 struct snd_kcontrol *kcontrol, int event) 2806 { 2807 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2808 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2809 2810 switch (event) { 2811 case SND_SOC_DAPM_PRE_PMU: 2812 rx_macro_enable_interp_clk(component, event, w->shift); 2813 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), 2814 CDC_RX_RXn_SIDETONE_EN_MASK, 1); 2815 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), 2816 CDC_RX_PATH_CLK_EN_MASK, 1); 2817 break; 2818 case SND_SOC_DAPM_POST_PMD: 2819 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), 2820 CDC_RX_RXn_SIDETONE_EN_MASK, 0); 2821 rx_macro_enable_interp_clk(component, event, w->shift); 2822 break; 2823 default: 2824 break; 2825 } 2826 return 0; 2827 } 2828 2829 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, 2830 struct snd_kcontrol *kcontrol, int event) 2831 { 2832 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2833 2834 switch (event) { 2835 case SND_SOC_DAPM_POST_PMU: /* fall through */ 2836 case SND_SOC_DAPM_PRE_PMD: 2837 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { 2838 snd_soc_component_write(component, 2839 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 2840 snd_soc_component_read(component, 2841 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)); 2842 snd_soc_component_write(component, 2843 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 2844 snd_soc_component_read(component, 2845 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)); 2846 snd_soc_component_write(component, 2847 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 2848 snd_soc_component_read(component, 2849 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)); 2850 snd_soc_component_write(component, 2851 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 2852 snd_soc_component_read(component, 2853 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)); 2854 } else { 2855 snd_soc_component_write(component, 2856 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 2857 snd_soc_component_read(component, 2858 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)); 2859 snd_soc_component_write(component, 2860 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 2861 snd_soc_component_read(component, 2862 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)); 2863 snd_soc_component_write(component, 2864 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 2865 snd_soc_component_read(component, 2866 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)); 2867 snd_soc_component_write(component, 2868 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 2869 snd_soc_component_read(component, 2870 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)); 2871 } 2872 break; 2873 } 2874 return 0; 2875 } 2876 2877 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 2878 int iir_idx, int band_idx, int coeff_idx) 2879 { 2880 u32 value; 2881 int reg, b2_reg; 2882 2883 /* Address does not automatically update if reading */ 2884 reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2885 b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2886 2887 snd_soc_component_write(component, reg, 2888 ((band_idx * BAND_MAX + coeff_idx) * 2889 sizeof(uint32_t)) & 0x7F); 2890 2891 value = snd_soc_component_read(component, b2_reg); 2892 snd_soc_component_write(component, reg, 2893 ((band_idx * BAND_MAX + coeff_idx) 2894 * sizeof(uint32_t) + 1) & 0x7F); 2895 2896 value |= (snd_soc_component_read(component, b2_reg) << 8); 2897 snd_soc_component_write(component, reg, 2898 ((band_idx * BAND_MAX + coeff_idx) 2899 * sizeof(uint32_t) + 2) & 0x7F); 2900 2901 value |= (snd_soc_component_read(component, b2_reg) << 16); 2902 snd_soc_component_write(component, reg, 2903 ((band_idx * BAND_MAX + coeff_idx) 2904 * sizeof(uint32_t) + 3) & 0x7F); 2905 2906 /* Mask bits top 2 bits since they are reserved */ 2907 value |= (snd_soc_component_read(component, b2_reg) << 24); 2908 return value; 2909 } 2910 2911 static void set_iir_band_coeff(struct snd_soc_component *component, 2912 int iir_idx, int band_idx, uint32_t value) 2913 { 2914 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2915 2916 snd_soc_component_write(component, reg, (value & 0xFF)); 2917 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 2918 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 2919 /* Mask top 2 bits, 7-8 are reserved */ 2920 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 2921 } 2922 2923 static int rx_macro_put_iir_band_audio_mixer( 2924 struct snd_kcontrol *kcontrol, 2925 struct snd_ctl_elem_value *ucontrol) 2926 { 2927 struct snd_soc_component *component = 2928 snd_soc_kcontrol_component(kcontrol); 2929 struct wcd_iir_filter_ctl *ctl = 2930 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2931 struct soc_bytes_ext *params = &ctl->bytes_ext; 2932 int iir_idx = ctl->iir_idx; 2933 int band_idx = ctl->band_idx; 2934 u32 coeff[BAND_MAX]; 2935 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2936 2937 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 2938 2939 /* Mask top bit it is reserved */ 2940 /* Updates addr automatically for each B2 write */ 2941 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 2942 sizeof(uint32_t)) & 0x7F); 2943 2944 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 2945 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 2946 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 2947 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 2948 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 2949 2950 return 0; 2951 } 2952 2953 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 2954 struct snd_ctl_elem_value *ucontrol) 2955 { 2956 struct snd_soc_component *component = 2957 snd_soc_kcontrol_component(kcontrol); 2958 struct wcd_iir_filter_ctl *ctl = 2959 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2960 struct soc_bytes_ext *params = &ctl->bytes_ext; 2961 int iir_idx = ctl->iir_idx; 2962 int band_idx = ctl->band_idx; 2963 u32 coeff[BAND_MAX]; 2964 2965 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 2966 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 2967 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 2968 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 2969 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 2970 2971 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 2972 2973 return 0; 2974 } 2975 2976 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol, 2977 struct snd_ctl_elem_info *ucontrol) 2978 { 2979 struct wcd_iir_filter_ctl *ctl = 2980 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2981 struct soc_bytes_ext *params = &ctl->bytes_ext; 2982 2983 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 2984 ucontrol->count = params->max; 2985 2986 return 0; 2987 } 2988 2989 static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = { 2990 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL, 2991 -84, 40, digital_gain), 2992 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL, 2993 -84, 40, digital_gain), 2994 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL, 2995 -84, 40, digital_gain), 2996 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL, 2997 -84, 40, digital_gain), 2998 }; 2999 3000 static const struct snd_kcontrol_new rx_macro_2_5_snd_controls[] = { 3001 3002 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_2_5_RX_RX1_RX_VOL_CTL, 3003 -84, 40, digital_gain), 3004 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_2_5_RX_RX2_RX_VOL_CTL, 3005 -84, 40, digital_gain), 3006 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 3007 -84, 40, digital_gain), 3008 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 3009 -84, 40, digital_gain), 3010 }; 3011 3012 static const struct snd_kcontrol_new rx_macro_snd_controls[] = { 3013 SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL, 3014 -84, 40, digital_gain), 3015 SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL, 3016 -84, 40, digital_gain), 3017 SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, 3018 rx_macro_get_compander, rx_macro_set_compander), 3019 SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0, 3020 rx_macro_get_compander, rx_macro_set_compander), 3021 3022 SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0, 3023 rx_macro_get_ear_mode, rx_macro_put_ear_mode), 3024 3025 SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0, 3026 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode), 3027 3028 SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum, 3029 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode), 3030 3031 SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0, 3032 rx_macro_soft_clip_enable_get, 3033 rx_macro_soft_clip_enable_put), 3034 SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0, 3035 rx_macro_aux_hpf_mode_get, 3036 rx_macro_aux_hpf_mode_put), 3037 3038 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3039 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3040 digital_gain), 3041 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 3042 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 3043 digital_gain), 3044 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 3045 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 3046 digital_gain), 3047 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 3048 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 3049 digital_gain), 3050 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 3051 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 3052 digital_gain), 3053 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 3054 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 3055 digital_gain), 3056 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 3057 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 3058 digital_gain), 3059 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 3060 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 3061 digital_gain), 3062 3063 SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3064 0, 1, 0), 3065 SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3066 1, 1, 0), 3067 SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3068 2, 1, 0), 3069 SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3070 3, 1, 0), 3071 SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3072 4, 1, 0), 3073 SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3074 0, 1, 0), 3075 SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3076 1, 1, 0), 3077 SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3078 2, 1, 0), 3079 SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3080 3, 1, 0), 3081 SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3082 4, 1, 0), 3083 3084 RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 3085 RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 3086 RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 3087 RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 3088 RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 3089 3090 RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 3091 RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 3092 RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 3093 RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 3094 RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 3095 3096 }; 3097 3098 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, 3099 struct snd_kcontrol *kcontrol, 3100 int event) 3101 { 3102 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 3103 u16 val, ec_hq_reg; 3104 int ec_tx = -1; 3105 3106 val = snd_soc_component_read(component, 3107 CDC_RX_INP_MUX_RX_MIX_CFG4); 3108 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX0 MUX"))) 3109 ec_tx = ((val & 0xf0) >> 0x4) - 1; 3110 else if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX1 MUX"))) 3111 ec_tx = (val & 0x0f) - 1; 3112 3113 val = snd_soc_component_read(component, 3114 CDC_RX_INP_MUX_RX_MIX_CFG5); 3115 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX2 MUX"))) 3116 ec_tx = (val & 0x0f) - 1; 3117 3118 if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) { 3119 dev_err(component->dev, "%s: EC mix control not set correctly\n", 3120 __func__); 3121 return -EINVAL; 3122 } 3123 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL + 3124 0x40 * ec_tx; 3125 snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); 3126 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 + 3127 0x40 * ec_tx; 3128 /* default set to 48k */ 3129 snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); 3130 3131 return 0; 3132 } 3133 3134 static const struct snd_soc_dapm_widget rx_macro_2_5_dapm_widgets[] = { 3135 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 3136 &rx_2_5_int1_dem_inp_mux), 3137 }; 3138 3139 static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = { 3140 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 3141 &rx_int1_dem_inp_mux), 3142 }; 3143 3144 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { 3145 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0, 3146 SND_SOC_NOPM, 0, 0), 3147 3148 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0, 3149 SND_SOC_NOPM, 0, 0), 3150 3151 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0, 3152 SND_SOC_NOPM, 0, 0), 3153 3154 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0, 3155 SND_SOC_NOPM, 0, 0), 3156 3157 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0, 3158 SND_SOC_NOPM, 0, 0), 3159 3160 SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0, 3161 &rx_macro_rx0_mux), 3162 SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0, 3163 &rx_macro_rx1_mux), 3164 SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0, 3165 &rx_macro_rx2_mux), 3166 SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0, 3167 &rx_macro_rx3_mux), 3168 SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0, 3169 &rx_macro_rx4_mux), 3170 SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0, 3171 &rx_macro_rx5_mux), 3172 3173 SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 3174 SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3175 SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3176 SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 3177 SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 3178 SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 3179 3180 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 3181 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 3182 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 3183 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 3184 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 3185 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 3186 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 3187 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 3188 3189 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM, 3190 RX_MACRO_EC0_MUX, 0, 3191 &rx_mix_tx0_mux, rx_macro_enable_echo, 3192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3193 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM, 3194 RX_MACRO_EC1_MUX, 0, 3195 &rx_mix_tx1_mux, rx_macro_enable_echo, 3196 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3197 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM, 3198 RX_MACRO_EC2_MUX, 0, 3199 &rx_mix_tx2_mux, rx_macro_enable_echo, 3200 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3201 3202 SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 3203 4, 0, NULL, 0, rx_macro_set_iir_gain, 3204 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3205 SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 3206 4, 0, NULL, 0, rx_macro_set_iir_gain, 3207 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3208 SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 3209 4, 0, NULL, 0), 3210 SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 3211 4, 0, NULL, 0), 3212 3213 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 3214 &rx_int0_dem_inp_mux), 3215 3216 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 3217 &rx_int0_2_mux, rx_macro_enable_mix_path, 3218 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3219 SND_SOC_DAPM_POST_PMD), 3220 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 3221 &rx_int1_2_mux, rx_macro_enable_mix_path, 3222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3223 SND_SOC_DAPM_POST_PMD), 3224 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0, 3225 &rx_int2_2_mux, rx_macro_enable_mix_path, 3226 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3227 SND_SOC_DAPM_POST_PMD), 3228 3229 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux), 3230 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux), 3231 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux), 3232 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux), 3233 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux), 3234 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux), 3235 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux), 3236 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux), 3237 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux), 3238 3239 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 3240 &rx_int0_1_interp_mux, rx_macro_enable_main_path, 3241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3242 SND_SOC_DAPM_POST_PMD), 3243 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 3244 &rx_int1_1_interp_mux, rx_macro_enable_main_path, 3245 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3246 SND_SOC_DAPM_POST_PMD), 3247 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0, 3248 &rx_int2_1_interp_mux, rx_macro_enable_main_path, 3249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3250 SND_SOC_DAPM_POST_PMD), 3251 3252 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 3253 &rx_int0_2_interp_mux), 3254 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 3255 &rx_int1_2_interp_mux), 3256 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 3257 &rx_int2_2_interp_mux), 3258 3259 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3260 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3261 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3262 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3263 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3264 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3265 3266 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL, 3267 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3268 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3269 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR, 3270 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3271 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3272 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX, 3273 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3274 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3275 3276 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3277 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3278 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3279 3280 SND_SOC_DAPM_OUTPUT("HPHL_OUT"), 3281 SND_SOC_DAPM_OUTPUT("HPHR_OUT"), 3282 SND_SOC_DAPM_OUTPUT("AUX_OUT"), 3283 3284 SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"), 3285 SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"), 3286 SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"), 3287 SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"), 3288 3289 SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0, 3290 rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3291 }; 3292 3293 static const struct snd_soc_dapm_route rx_audio_map[] = { 3294 {"RX AIF1 PB", NULL, "RX_MCLK"}, 3295 {"RX AIF2 PB", NULL, "RX_MCLK"}, 3296 {"RX AIF3 PB", NULL, "RX_MCLK"}, 3297 {"RX AIF4 PB", NULL, "RX_MCLK"}, 3298 3299 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"}, 3300 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"}, 3301 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"}, 3302 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"}, 3303 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"}, 3304 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"}, 3305 3306 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"}, 3307 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"}, 3308 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"}, 3309 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"}, 3310 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"}, 3311 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"}, 3312 3313 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"}, 3314 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"}, 3315 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"}, 3316 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"}, 3317 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"}, 3318 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"}, 3319 3320 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"}, 3321 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"}, 3322 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"}, 3323 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"}, 3324 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"}, 3325 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"}, 3326 3327 {"RX_RX0", NULL, "RX_MACRO RX0 MUX"}, 3328 {"RX_RX1", NULL, "RX_MACRO RX1 MUX"}, 3329 {"RX_RX2", NULL, "RX_MACRO RX2 MUX"}, 3330 {"RX_RX3", NULL, "RX_MACRO RX3 MUX"}, 3331 {"RX_RX4", NULL, "RX_MACRO RX4 MUX"}, 3332 {"RX_RX5", NULL, "RX_MACRO RX5 MUX"}, 3333 3334 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"}, 3335 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"}, 3336 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"}, 3337 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"}, 3338 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"}, 3339 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"}, 3340 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"}, 3341 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"}, 3342 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3343 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3344 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"}, 3345 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"}, 3346 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"}, 3347 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"}, 3348 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"}, 3349 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"}, 3350 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"}, 3351 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"}, 3352 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3353 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3354 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"}, 3355 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"}, 3356 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"}, 3357 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"}, 3358 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"}, 3359 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"}, 3360 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"}, 3361 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"}, 3362 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3363 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3364 3365 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"}, 3366 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"}, 3367 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"}, 3368 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"}, 3369 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"}, 3370 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"}, 3371 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"}, 3372 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"}, 3373 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3374 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3375 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"}, 3376 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"}, 3377 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"}, 3378 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"}, 3379 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"}, 3380 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"}, 3381 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"}, 3382 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"}, 3383 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3384 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3385 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"}, 3386 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"}, 3387 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"}, 3388 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"}, 3389 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"}, 3390 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"}, 3391 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"}, 3392 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"}, 3393 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3394 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3395 3396 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"}, 3397 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"}, 3398 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"}, 3399 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"}, 3400 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"}, 3401 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"}, 3402 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"}, 3403 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"}, 3404 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3405 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3406 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"}, 3407 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"}, 3408 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"}, 3409 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"}, 3410 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"}, 3411 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"}, 3412 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"}, 3413 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"}, 3414 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3415 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3416 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"}, 3417 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"}, 3418 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"}, 3419 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"}, 3420 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"}, 3421 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"}, 3422 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"}, 3423 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"}, 3424 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3425 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3426 3427 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"}, 3428 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"}, 3429 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"}, 3430 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"}, 3431 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"}, 3432 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"}, 3433 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"}, 3434 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"}, 3435 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"}, 3436 3437 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3438 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3439 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3440 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3441 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3442 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3443 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3444 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3445 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3446 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"}, 3447 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"}, 3448 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"}, 3449 {"RX AIF_ECHO", NULL, "RX_MCLK"}, 3450 3451 /* Mixing path INT0 */ 3452 {"RX INT0_2 MUX", "RX0", "RX_RX0"}, 3453 {"RX INT0_2 MUX", "RX1", "RX_RX1"}, 3454 {"RX INT0_2 MUX", "RX2", "RX_RX2"}, 3455 {"RX INT0_2 MUX", "RX3", "RX_RX3"}, 3456 {"RX INT0_2 MUX", "RX4", "RX_RX4"}, 3457 {"RX INT0_2 MUX", "RX5", "RX_RX5"}, 3458 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"}, 3459 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"}, 3460 3461 /* Mixing path INT1 */ 3462 {"RX INT1_2 MUX", "RX0", "RX_RX0"}, 3463 {"RX INT1_2 MUX", "RX1", "RX_RX1"}, 3464 {"RX INT1_2 MUX", "RX2", "RX_RX2"}, 3465 {"RX INT1_2 MUX", "RX3", "RX_RX3"}, 3466 {"RX INT1_2 MUX", "RX4", "RX_RX4"}, 3467 {"RX INT1_2 MUX", "RX5", "RX_RX5"}, 3468 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"}, 3469 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"}, 3470 3471 /* Mixing path INT2 */ 3472 {"RX INT2_2 MUX", "RX0", "RX_RX0"}, 3473 {"RX INT2_2 MUX", "RX1", "RX_RX1"}, 3474 {"RX INT2_2 MUX", "RX2", "RX_RX2"}, 3475 {"RX INT2_2 MUX", "RX3", "RX_RX3"}, 3476 {"RX INT2_2 MUX", "RX4", "RX_RX4"}, 3477 {"RX INT2_2 MUX", "RX5", "RX_RX5"}, 3478 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"}, 3479 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"}, 3480 3481 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"}, 3482 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"}, 3483 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"}, 3484 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"}, 3485 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 3486 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"}, 3487 {"HPHL_OUT", NULL, "RX_MCLK"}, 3488 3489 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"}, 3490 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"}, 3491 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"}, 3492 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"}, 3493 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"}, 3494 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"}, 3495 {"HPHR_OUT", NULL, "RX_MCLK"}, 3496 3497 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"}, 3498 3499 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"}, 3500 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"}, 3501 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"}, 3502 {"AUX_OUT", NULL, "RX INT2 MIX2"}, 3503 {"AUX_OUT", NULL, "RX_MCLK"}, 3504 3505 {"IIR0", NULL, "RX_MCLK"}, 3506 {"IIR0", NULL, "IIR0 INP0 MUX"}, 3507 {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3508 {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3509 {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3510 {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3511 {"IIR0 INP0 MUX", "RX0", "RX_RX0"}, 3512 {"IIR0 INP0 MUX", "RX1", "RX_RX1"}, 3513 {"IIR0 INP0 MUX", "RX2", "RX_RX2"}, 3514 {"IIR0 INP0 MUX", "RX3", "RX_RX3"}, 3515 {"IIR0 INP0 MUX", "RX4", "RX_RX4"}, 3516 {"IIR0 INP0 MUX", "RX5", "RX_RX5"}, 3517 {"IIR0", NULL, "IIR0 INP1 MUX"}, 3518 {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3519 {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3520 {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3521 {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3522 {"IIR0 INP1 MUX", "RX0", "RX_RX0"}, 3523 {"IIR0 INP1 MUX", "RX1", "RX_RX1"}, 3524 {"IIR0 INP1 MUX", "RX2", "RX_RX2"}, 3525 {"IIR0 INP1 MUX", "RX3", "RX_RX3"}, 3526 {"IIR0 INP1 MUX", "RX4", "RX_RX4"}, 3527 {"IIR0 INP1 MUX", "RX5", "RX_RX5"}, 3528 {"IIR0", NULL, "IIR0 INP2 MUX"}, 3529 {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3530 {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3531 {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3532 {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3533 {"IIR0 INP2 MUX", "RX0", "RX_RX0"}, 3534 {"IIR0 INP2 MUX", "RX1", "RX_RX1"}, 3535 {"IIR0 INP2 MUX", "RX2", "RX_RX2"}, 3536 {"IIR0 INP2 MUX", "RX3", "RX_RX3"}, 3537 {"IIR0 INP2 MUX", "RX4", "RX_RX4"}, 3538 {"IIR0 INP2 MUX", "RX5", "RX_RX5"}, 3539 {"IIR0", NULL, "IIR0 INP3 MUX"}, 3540 {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3541 {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3542 {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3543 {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3544 {"IIR0 INP3 MUX", "RX0", "RX_RX0"}, 3545 {"IIR0 INP3 MUX", "RX1", "RX_RX1"}, 3546 {"IIR0 INP3 MUX", "RX2", "RX_RX2"}, 3547 {"IIR0 INP3 MUX", "RX3", "RX_RX3"}, 3548 {"IIR0 INP3 MUX", "RX4", "RX_RX4"}, 3549 {"IIR0 INP3 MUX", "RX5", "RX_RX5"}, 3550 3551 {"IIR1", NULL, "RX_MCLK"}, 3552 {"IIR1", NULL, "IIR1 INP0 MUX"}, 3553 {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3554 {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3555 {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3556 {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3557 {"IIR1 INP0 MUX", "RX0", "RX_RX0"}, 3558 {"IIR1 INP0 MUX", "RX1", "RX_RX1"}, 3559 {"IIR1 INP0 MUX", "RX2", "RX_RX2"}, 3560 {"IIR1 INP0 MUX", "RX3", "RX_RX3"}, 3561 {"IIR1 INP0 MUX", "RX4", "RX_RX4"}, 3562 {"IIR1 INP0 MUX", "RX5", "RX_RX5"}, 3563 {"IIR1", NULL, "IIR1 INP1 MUX"}, 3564 {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3565 {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3566 {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3567 {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3568 {"IIR1 INP1 MUX", "RX0", "RX_RX0"}, 3569 {"IIR1 INP1 MUX", "RX1", "RX_RX1"}, 3570 {"IIR1 INP1 MUX", "RX2", "RX_RX2"}, 3571 {"IIR1 INP1 MUX", "RX3", "RX_RX3"}, 3572 {"IIR1 INP1 MUX", "RX4", "RX_RX4"}, 3573 {"IIR1 INP1 MUX", "RX5", "RX_RX5"}, 3574 {"IIR1", NULL, "IIR1 INP2 MUX"}, 3575 {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3576 {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3577 {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3578 {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3579 {"IIR1 INP2 MUX", "RX0", "RX_RX0"}, 3580 {"IIR1 INP2 MUX", "RX1", "RX_RX1"}, 3581 {"IIR1 INP2 MUX", "RX2", "RX_RX2"}, 3582 {"IIR1 INP2 MUX", "RX3", "RX_RX3"}, 3583 {"IIR1 INP2 MUX", "RX4", "RX_RX4"}, 3584 {"IIR1 INP2 MUX", "RX5", "RX_RX5"}, 3585 {"IIR1", NULL, "IIR1 INP3 MUX"}, 3586 {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3587 {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3588 {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3589 {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3590 {"IIR1 INP3 MUX", "RX0", "RX_RX0"}, 3591 {"IIR1 INP3 MUX", "RX1", "RX_RX1"}, 3592 {"IIR1 INP3 MUX", "RX2", "RX_RX2"}, 3593 {"IIR1 INP3 MUX", "RX3", "RX_RX3"}, 3594 {"IIR1 INP3 MUX", "RX4", "RX_RX4"}, 3595 {"IIR1 INP3 MUX", "RX5", "RX_RX5"}, 3596 3597 {"SRC0", NULL, "IIR0"}, 3598 {"SRC1", NULL, "IIR1"}, 3599 {"RX INT0 MIX2 INP", "SRC0", "SRC0"}, 3600 {"RX INT0 MIX2 INP", "SRC1", "SRC1"}, 3601 {"RX INT1 MIX2 INP", "SRC0", "SRC0"}, 3602 {"RX INT1 MIX2 INP", "SRC1", "SRC1"}, 3603 {"RX INT2 MIX2 INP", "SRC0", "SRC0"}, 3604 {"RX INT2 MIX2 INP", "SRC1", "SRC1"}, 3605 }; 3606 3607 static int rx_macro_component_probe(struct snd_soc_component *component) 3608 { 3609 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3610 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 3611 const struct snd_soc_dapm_widget *widgets; 3612 const struct snd_kcontrol_new *controls; 3613 unsigned int num_controls; 3614 int ret, num_widgets; 3615 3616 snd_soc_component_init_regmap(component, rx->regmap); 3617 3618 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0), 3619 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3620 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3621 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1), 3622 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3623 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3624 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2), 3625 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3626 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3627 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0), 3628 CDC_RX_DC_COEFF_SEL_MASK, 3629 CDC_RX_DC_COEFF_SEL_TWO); 3630 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1), 3631 CDC_RX_DC_COEFF_SEL_MASK, 3632 CDC_RX_DC_COEFF_SEL_TWO); 3633 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2), 3634 CDC_RX_DC_COEFF_SEL_MASK, 3635 CDC_RX_DC_COEFF_SEL_TWO); 3636 3637 switch (rx->codec_version) { 3638 case LPASS_CODEC_VERSION_1_0: 3639 case LPASS_CODEC_VERSION_1_1: 3640 case LPASS_CODEC_VERSION_1_2: 3641 case LPASS_CODEC_VERSION_2_0: 3642 controls = rx_macro_def_snd_controls; 3643 num_controls = ARRAY_SIZE(rx_macro_def_snd_controls); 3644 widgets = rx_macro_def_dapm_widgets; 3645 num_widgets = ARRAY_SIZE(rx_macro_def_dapm_widgets); 3646 break; 3647 case LPASS_CODEC_VERSION_2_5: 3648 case LPASS_CODEC_VERSION_2_6: 3649 case LPASS_CODEC_VERSION_2_7: 3650 case LPASS_CODEC_VERSION_2_8: 3651 controls = rx_macro_2_5_snd_controls; 3652 num_controls = ARRAY_SIZE(rx_macro_2_5_snd_controls); 3653 widgets = rx_macro_2_5_dapm_widgets; 3654 num_widgets = ARRAY_SIZE(rx_macro_2_5_dapm_widgets); 3655 break; 3656 default: 3657 return -EINVAL; 3658 } 3659 3660 rx->component = component; 3661 3662 ret = snd_soc_add_component_controls(component, controls, num_controls); 3663 if (ret) 3664 return ret; 3665 3666 return snd_soc_dapm_new_controls(dapm, widgets, num_widgets); 3667 } 3668 3669 static int swclk_gate_enable(struct clk_hw *hw) 3670 { 3671 struct rx_macro *rx = to_rx_macro(hw); 3672 int ret; 3673 3674 ret = clk_prepare_enable(rx->mclk); 3675 if (ret) { 3676 dev_err(rx->dev, "unable to prepare mclk\n"); 3677 return ret; 3678 } 3679 3680 rx_macro_mclk_enable(rx, true); 3681 3682 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3683 CDC_RX_SWR_CLK_EN_MASK, 1); 3684 3685 return 0; 3686 } 3687 3688 static void swclk_gate_disable(struct clk_hw *hw) 3689 { 3690 struct rx_macro *rx = to_rx_macro(hw); 3691 3692 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3693 CDC_RX_SWR_CLK_EN_MASK, 0); 3694 3695 rx_macro_mclk_enable(rx, false); 3696 clk_disable_unprepare(rx->mclk); 3697 } 3698 3699 static int swclk_gate_is_enabled(struct clk_hw *hw) 3700 { 3701 struct rx_macro *rx = to_rx_macro(hw); 3702 int ret, val; 3703 3704 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); 3705 ret = val & BIT(0); 3706 3707 return ret; 3708 } 3709 3710 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 3711 unsigned long parent_rate) 3712 { 3713 return parent_rate / 2; 3714 } 3715 3716 static const struct clk_ops swclk_gate_ops = { 3717 .prepare = swclk_gate_enable, 3718 .unprepare = swclk_gate_disable, 3719 .is_enabled = swclk_gate_is_enabled, 3720 .recalc_rate = swclk_recalc_rate, 3721 3722 }; 3723 3724 static int rx_macro_register_mclk_output(struct rx_macro *rx) 3725 { 3726 struct device *dev = rx->dev; 3727 const char *parent_clk_name = NULL; 3728 const char *clk_name = "lpass-rx-mclk"; 3729 struct clk_hw *hw; 3730 struct clk_init_data init; 3731 int ret; 3732 3733 if (rx->npl) 3734 parent_clk_name = __clk_get_name(rx->npl); 3735 else 3736 parent_clk_name = __clk_get_name(rx->mclk); 3737 3738 init.name = clk_name; 3739 init.ops = &swclk_gate_ops; 3740 init.flags = 0; 3741 init.parent_names = &parent_clk_name; 3742 init.num_parents = 1; 3743 rx->hw.init = &init; 3744 hw = &rx->hw; 3745 ret = devm_clk_hw_register(rx->dev, hw); 3746 if (ret) 3747 return ret; 3748 3749 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 3750 } 3751 3752 static const struct snd_soc_component_driver rx_macro_component_drv = { 3753 .name = "RX-MACRO", 3754 .probe = rx_macro_component_probe, 3755 .controls = rx_macro_snd_controls, 3756 .num_controls = ARRAY_SIZE(rx_macro_snd_controls), 3757 .dapm_widgets = rx_macro_dapm_widgets, 3758 .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets), 3759 .dapm_routes = rx_audio_map, 3760 .num_dapm_routes = ARRAY_SIZE(rx_audio_map), 3761 }; 3762 3763 static int rx_macro_probe(struct platform_device *pdev) 3764 { 3765 struct reg_default *reg_defaults; 3766 struct device *dev = &pdev->dev; 3767 kernel_ulong_t flags; 3768 struct rx_macro *rx; 3769 void __iomem *base; 3770 int ret, def_count; 3771 3772 flags = (kernel_ulong_t)device_get_match_data(dev); 3773 3774 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); 3775 if (!rx) 3776 return -ENOMEM; 3777 3778 rx->macro = devm_clk_get_optional(dev, "macro"); 3779 if (IS_ERR(rx->macro)) 3780 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); 3781 3782 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); 3783 if (IS_ERR(rx->dcodec)) 3784 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); 3785 3786 rx->mclk = devm_clk_get(dev, "mclk"); 3787 if (IS_ERR(rx->mclk)) 3788 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); 3789 3790 if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { 3791 rx->npl = devm_clk_get(dev, "npl"); 3792 if (IS_ERR(rx->npl)) 3793 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); 3794 } 3795 3796 rx->fsgen = devm_clk_get(dev, "fsgen"); 3797 if (IS_ERR(rx->fsgen)) 3798 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); 3799 3800 rx->pds = lpass_macro_pds_init(dev); 3801 if (IS_ERR(rx->pds)) 3802 return PTR_ERR(rx->pds); 3803 3804 base = devm_platform_ioremap_resource(pdev, 0); 3805 if (IS_ERR(base)) { 3806 ret = PTR_ERR(base); 3807 goto err; 3808 } 3809 rx->codec_version = lpass_macro_get_codec_version(); 3810 switch (rx->codec_version) { 3811 case LPASS_CODEC_VERSION_1_0: 3812 case LPASS_CODEC_VERSION_1_1: 3813 case LPASS_CODEC_VERSION_1_2: 3814 case LPASS_CODEC_VERSION_2_0: 3815 rx->rxn_reg_stride = 0x80; 3816 def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_5_defaults); 3817 reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL); 3818 if (!reg_defaults) { 3819 ret = -ENOMEM; 3820 goto err; 3821 } 3822 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); 3823 memcpy(®_defaults[ARRAY_SIZE(rx_defaults)], 3824 rx_pre_2_5_defaults, sizeof(rx_pre_2_5_defaults)); 3825 break; 3826 case LPASS_CODEC_VERSION_2_5: 3827 case LPASS_CODEC_VERSION_2_6: 3828 case LPASS_CODEC_VERSION_2_7: 3829 case LPASS_CODEC_VERSION_2_8: 3830 rx->rxn_reg_stride = 0xc0; 3831 def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_5_defaults); 3832 reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL); 3833 if (!reg_defaults) { 3834 ret = -ENOMEM; 3835 goto err; 3836 } 3837 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); 3838 memcpy(®_defaults[ARRAY_SIZE(rx_defaults)], 3839 rx_2_5_defaults, sizeof(rx_2_5_defaults)); 3840 break; 3841 default: 3842 dev_err(rx->dev, "Unsupported Codec version (%d)\n", rx->codec_version); 3843 ret = -EINVAL; 3844 goto err; 3845 } 3846 3847 rx_regmap_config.reg_defaults = reg_defaults; 3848 rx_regmap_config.num_reg_defaults = def_count; 3849 3850 rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config); 3851 if (IS_ERR(rx->regmap)) { 3852 ret = PTR_ERR(rx->regmap); 3853 goto err_ver; 3854 } 3855 3856 dev_set_drvdata(dev, rx); 3857 3858 rx->dev = dev; 3859 3860 /* set MCLK and NPL rates */ 3861 clk_set_rate(rx->mclk, MCLK_FREQ); 3862 clk_set_rate(rx->npl, MCLK_FREQ); 3863 3864 ret = clk_prepare_enable(rx->macro); 3865 if (ret) 3866 goto err_ver; 3867 3868 ret = clk_prepare_enable(rx->dcodec); 3869 if (ret) 3870 goto err_dcodec; 3871 3872 ret = clk_prepare_enable(rx->mclk); 3873 if (ret) 3874 goto err_mclk; 3875 3876 ret = clk_prepare_enable(rx->npl); 3877 if (ret) 3878 goto err_npl; 3879 3880 ret = clk_prepare_enable(rx->fsgen); 3881 if (ret) 3882 goto err_fsgen; 3883 3884 /* reset swr block */ 3885 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3886 CDC_RX_SWR_RESET_MASK, 3887 CDC_RX_SWR_RESET); 3888 3889 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3890 CDC_RX_SWR_CLK_EN_MASK, 1); 3891 3892 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3893 CDC_RX_SWR_RESET_MASK, 0); 3894 3895 ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv, 3896 rx_macro_dai, 3897 ARRAY_SIZE(rx_macro_dai)); 3898 if (ret) 3899 goto err_clkout; 3900 3901 3902 pm_runtime_set_autosuspend_delay(dev, 3000); 3903 pm_runtime_use_autosuspend(dev); 3904 pm_runtime_mark_last_busy(dev); 3905 pm_runtime_set_active(dev); 3906 pm_runtime_enable(dev); 3907 3908 ret = rx_macro_register_mclk_output(rx); 3909 if (ret) 3910 goto err_clkout; 3911 3912 kfree(reg_defaults); 3913 return 0; 3914 3915 err_clkout: 3916 clk_disable_unprepare(rx->fsgen); 3917 err_fsgen: 3918 clk_disable_unprepare(rx->npl); 3919 err_npl: 3920 clk_disable_unprepare(rx->mclk); 3921 err_mclk: 3922 clk_disable_unprepare(rx->dcodec); 3923 err_dcodec: 3924 clk_disable_unprepare(rx->macro); 3925 err_ver: 3926 kfree(reg_defaults); 3927 err: 3928 lpass_macro_pds_exit(rx->pds); 3929 3930 return ret; 3931 } 3932 3933 static void rx_macro_remove(struct platform_device *pdev) 3934 { 3935 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); 3936 3937 clk_disable_unprepare(rx->mclk); 3938 clk_disable_unprepare(rx->npl); 3939 clk_disable_unprepare(rx->fsgen); 3940 clk_disable_unprepare(rx->macro); 3941 clk_disable_unprepare(rx->dcodec); 3942 3943 lpass_macro_pds_exit(rx->pds); 3944 } 3945 3946 static const struct of_device_id rx_macro_dt_match[] = { 3947 { 3948 .compatible = "qcom,sc7280-lpass-rx-macro", 3949 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3950 3951 }, { 3952 .compatible = "qcom,sm8250-lpass-rx-macro", 3953 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3954 }, { 3955 .compatible = "qcom,sm8450-lpass-rx-macro", 3956 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3957 }, { 3958 .compatible = "qcom,sm8550-lpass-rx-macro", 3959 }, { 3960 .compatible = "qcom,sc8280xp-lpass-rx-macro", 3961 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3962 }, 3963 { } 3964 }; 3965 MODULE_DEVICE_TABLE(of, rx_macro_dt_match); 3966 3967 static int __maybe_unused rx_macro_runtime_suspend(struct device *dev) 3968 { 3969 struct rx_macro *rx = dev_get_drvdata(dev); 3970 3971 regcache_cache_only(rx->regmap, true); 3972 regcache_mark_dirty(rx->regmap); 3973 3974 clk_disable_unprepare(rx->fsgen); 3975 clk_disable_unprepare(rx->npl); 3976 clk_disable_unprepare(rx->mclk); 3977 3978 return 0; 3979 } 3980 3981 static int __maybe_unused rx_macro_runtime_resume(struct device *dev) 3982 { 3983 struct rx_macro *rx = dev_get_drvdata(dev); 3984 int ret; 3985 3986 ret = clk_prepare_enable(rx->mclk); 3987 if (ret) { 3988 dev_err(dev, "unable to prepare mclk\n"); 3989 return ret; 3990 } 3991 3992 ret = clk_prepare_enable(rx->npl); 3993 if (ret) { 3994 dev_err(dev, "unable to prepare mclkx2\n"); 3995 goto err_npl; 3996 } 3997 3998 ret = clk_prepare_enable(rx->fsgen); 3999 if (ret) { 4000 dev_err(dev, "unable to prepare fsgen\n"); 4001 goto err_fsgen; 4002 } 4003 regcache_cache_only(rx->regmap, false); 4004 regcache_sync(rx->regmap); 4005 4006 return 0; 4007 err_fsgen: 4008 clk_disable_unprepare(rx->npl); 4009 err_npl: 4010 clk_disable_unprepare(rx->mclk); 4011 4012 return ret; 4013 } 4014 4015 static const struct dev_pm_ops rx_macro_pm_ops = { 4016 SET_RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL) 4017 }; 4018 4019 static struct platform_driver rx_macro_driver = { 4020 .driver = { 4021 .name = "rx_macro", 4022 .of_match_table = rx_macro_dt_match, 4023 .suppress_bind_attrs = true, 4024 .pm = &rx_macro_pm_ops, 4025 }, 4026 .probe = rx_macro_probe, 4027 .remove_new = rx_macro_remove, 4028 }; 4029 4030 module_platform_driver(rx_macro_driver); 4031 4032 MODULE_DESCRIPTION("RX macro driver"); 4033 MODULE_LICENSE("GPL"); 4034