xref: /linux/sound/soc/codecs/jz4740.c (revision 4413e16d9d21673bb5048a2e542f1aaa00015c2e)
1 /*
2  * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  *  You should have received a copy of the  GNU General Public License along
9  *  with this program; if not, write  to the Free Software Foundation, Inc.,
10  *  675 Mass Ave, Cambridge, MA 02139, USA.
11  *
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 #include <linux/io.h>
19 
20 #include <linux/delay.h>
21 
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/initval.h>
26 #include <sound/soc.h>
27 
28 #define JZ4740_REG_CODEC_1 0x0
29 #define JZ4740_REG_CODEC_2 0x1
30 
31 #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
32 #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
33 #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
34 #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
35 #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
36 #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
37 #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
38 #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
39 #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
40 #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
41 #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
42 #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
43 #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
44 #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
45 #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
46 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
47 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
48 #define JZ4740_CODEC_1_SUSPEND BIT(1)
49 #define JZ4740_CODEC_1_RESET BIT(0)
50 
51 #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
52 #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
53 #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
54 #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
55 #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
56 #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
57 #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
58 #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
59 
60 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK		0x1f0000
61 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK			0x000f00
62 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK		0x000030
63 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK	0x000003
64 
65 #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET		16
66 #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET		 8
67 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET	 4
68 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET	 0
69 
70 static const uint32_t jz4740_codec_regs[] = {
71 	0x021b2302, 0x00170803,
72 };
73 
74 struct jz4740_codec {
75 	void __iomem *base;
76 	struct resource *mem;
77 };
78 
79 static unsigned int jz4740_codec_read(struct snd_soc_codec *codec,
80 	unsigned int reg)
81 {
82 	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
83 	return readl(jz4740_codec->base + (reg << 2));
84 }
85 
86 static int jz4740_codec_write(struct snd_soc_codec *codec, unsigned int reg,
87 	unsigned int val)
88 {
89 	struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
90 	u32 *cache = codec->reg_cache;
91 
92 	cache[reg] = val;
93 	writel(val, jz4740_codec->base + (reg << 2));
94 
95 	return 0;
96 }
97 
98 static const struct snd_kcontrol_new jz4740_codec_controls[] = {
99 	SOC_SINGLE("Master Playback Volume", JZ4740_REG_CODEC_2,
100 			JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0),
101 	SOC_SINGLE("Master Capture Volume", JZ4740_REG_CODEC_2,
102 			JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0),
103 	SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
104 			JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
105 	SOC_SINGLE("Mic Capture Volume", JZ4740_REG_CODEC_2,
106 			JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0),
107 };
108 
109 static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
110 	SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
111 			JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
112 	SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
113 			JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
114 };
115 
116 static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
117 	SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
118 			JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
119 	SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
120 			JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
121 };
122 
123 static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
124 	SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
125 			JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
126 	SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
127 			JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
128 
129 	SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
130 			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
131 			jz4740_codec_output_controls,
132 			ARRAY_SIZE(jz4740_codec_output_controls)),
133 
134 	SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
135 			jz4740_codec_input_controls,
136 			ARRAY_SIZE(jz4740_codec_input_controls)),
137 	SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
138 
139 	SND_SOC_DAPM_OUTPUT("LOUT"),
140 	SND_SOC_DAPM_OUTPUT("ROUT"),
141 
142 	SND_SOC_DAPM_INPUT("MIC"),
143 	SND_SOC_DAPM_INPUT("LIN"),
144 	SND_SOC_DAPM_INPUT("RIN"),
145 };
146 
147 static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
148 	{"Line Input", NULL, "LIN"},
149 	{"Line Input", NULL, "RIN"},
150 
151 	{"Input Mixer", "Line Capture Switch", "Line Input"},
152 	{"Input Mixer", "Mic Capture Switch", "MIC"},
153 
154 	{"ADC", NULL, "Input Mixer"},
155 
156 	{"Output Mixer", "Bypass Switch", "Input Mixer"},
157 	{"Output Mixer", "DAC Switch", "DAC"},
158 
159 	{"LOUT", NULL, "Output Mixer"},
160 	{"ROUT", NULL, "Output Mixer"},
161 };
162 
163 static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
164 	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
165 {
166 	uint32_t val;
167 	struct snd_soc_codec *codec = dai->codec;
168 
169 	switch (params_rate(params)) {
170 	case 8000:
171 		val = 0;
172 		break;
173 	case 11025:
174 		val = 1;
175 		break;
176 	case 12000:
177 		val = 2;
178 		break;
179 	case 16000:
180 		val = 3;
181 		break;
182 	case 22050:
183 		val = 4;
184 		break;
185 	case 24000:
186 		val = 5;
187 		break;
188 	case 32000:
189 		val = 6;
190 		break;
191 	case 44100:
192 		val = 7;
193 		break;
194 	case 48000:
195 		val = 8;
196 		break;
197 	default:
198 		return -EINVAL;
199 	}
200 
201 	val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
202 
203 	snd_soc_update_bits(codec, JZ4740_REG_CODEC_2,
204 				JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
205 
206 	return 0;
207 }
208 
209 static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
210 	.hw_params = jz4740_codec_hw_params,
211 };
212 
213 static struct snd_soc_dai_driver jz4740_codec_dai = {
214 	.name = "jz4740-hifi",
215 	.playback = {
216 		.stream_name = "Playback",
217 		.channels_min = 2,
218 		.channels_max = 2,
219 		.rates = SNDRV_PCM_RATE_8000_48000,
220 		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
221 	},
222 	.capture = {
223 		.stream_name = "Capture",
224 		.channels_min = 2,
225 		.channels_max = 2,
226 		.rates = SNDRV_PCM_RATE_8000_48000,
227 		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
228 	},
229 	.ops = &jz4740_codec_dai_ops,
230 	.symmetric_rates = 1,
231 };
232 
233 static void jz4740_codec_wakeup(struct snd_soc_codec *codec)
234 {
235 	int i;
236 	uint32_t *cache = codec->reg_cache;
237 
238 	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
239 		JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
240 	udelay(2);
241 
242 	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
243 		JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
244 
245 	for (i = 0; i < ARRAY_SIZE(jz4740_codec_regs); ++i)
246 		jz4740_codec_write(codec, i, cache[i]);
247 }
248 
249 static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
250 	enum snd_soc_bias_level level)
251 {
252 	unsigned int mask;
253 	unsigned int value;
254 
255 	switch (level) {
256 	case SND_SOC_BIAS_ON:
257 		break;
258 	case SND_SOC_BIAS_PREPARE:
259 		mask = JZ4740_CODEC_1_VREF_DISABLE |
260 				JZ4740_CODEC_1_VREF_AMP_DISABLE |
261 				JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
262 		value = 0;
263 
264 		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
265 		break;
266 	case SND_SOC_BIAS_STANDBY:
267 		/* The only way to clear the suspend flag is to reset the codec */
268 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
269 			jz4740_codec_wakeup(codec);
270 
271 		mask = JZ4740_CODEC_1_VREF_DISABLE |
272 			JZ4740_CODEC_1_VREF_AMP_DISABLE |
273 			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
274 		value = JZ4740_CODEC_1_VREF_DISABLE |
275 			JZ4740_CODEC_1_VREF_AMP_DISABLE |
276 			JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
277 
278 		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
279 		break;
280 	case SND_SOC_BIAS_OFF:
281 		mask = JZ4740_CODEC_1_SUSPEND;
282 		value = JZ4740_CODEC_1_SUSPEND;
283 
284 		snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, mask, value);
285 		break;
286 	default:
287 		break;
288 	}
289 
290 	codec->dapm.bias_level = level;
291 
292 	return 0;
293 }
294 
295 static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
296 {
297 	snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
298 			JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
299 
300 	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
301 
302 	return 0;
303 }
304 
305 static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
306 {
307 	jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
308 
309 	return 0;
310 }
311 
312 #ifdef CONFIG_PM_SLEEP
313 
314 static int jz4740_codec_suspend(struct snd_soc_codec *codec)
315 {
316 	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
317 }
318 
319 static int jz4740_codec_resume(struct snd_soc_codec *codec)
320 {
321 	return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
322 }
323 
324 #else
325 #define jz4740_codec_suspend NULL
326 #define jz4740_codec_resume NULL
327 #endif
328 
329 static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
330 	.probe = jz4740_codec_dev_probe,
331 	.remove = jz4740_codec_dev_remove,
332 	.suspend = jz4740_codec_suspend,
333 	.resume = jz4740_codec_resume,
334 	.read = jz4740_codec_read,
335 	.write = jz4740_codec_write,
336 	.set_bias_level = jz4740_codec_set_bias_level,
337 	.reg_cache_default	= jz4740_codec_regs,
338 	.reg_word_size = sizeof(u32),
339 	.reg_cache_size	= 2,
340 
341 	.controls = jz4740_codec_controls,
342 	.num_controls = ARRAY_SIZE(jz4740_codec_controls),
343 	.dapm_widgets = jz4740_codec_dapm_widgets,
344 	.num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
345 	.dapm_routes = jz4740_codec_dapm_routes,
346 	.num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
347 };
348 
349 static int __devinit jz4740_codec_probe(struct platform_device *pdev)
350 {
351 	int ret;
352 	struct jz4740_codec *jz4740_codec;
353 	struct resource *mem;
354 
355 	jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
356 				    GFP_KERNEL);
357 	if (!jz4740_codec)
358 		return -ENOMEM;
359 
360 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
361 	if (!mem) {
362 		dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
363 		ret = -ENOENT;
364 		goto err_out;
365 	}
366 
367 	mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
368 	if (!mem) {
369 		dev_err(&pdev->dev, "Failed to request mmio memory region\n");
370 		ret = -EBUSY;
371 		goto err_out;
372 	}
373 
374 	jz4740_codec->base = ioremap(mem->start, resource_size(mem));
375 	if (!jz4740_codec->base) {
376 		dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
377 		ret = -EBUSY;
378 		goto err_release_mem_region;
379 	}
380 	jz4740_codec->mem = mem;
381 
382 	platform_set_drvdata(pdev, jz4740_codec);
383 
384 	ret = snd_soc_register_codec(&pdev->dev,
385 			&soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
386 	if (ret) {
387 		dev_err(&pdev->dev, "Failed to register codec\n");
388 		goto err_iounmap;
389 	}
390 
391 	return 0;
392 
393 err_iounmap:
394 	iounmap(jz4740_codec->base);
395 err_release_mem_region:
396 	release_mem_region(mem->start, resource_size(mem));
397 err_out:
398 	return ret;
399 }
400 
401 static int __devexit jz4740_codec_remove(struct platform_device *pdev)
402 {
403 	struct jz4740_codec *jz4740_codec = platform_get_drvdata(pdev);
404 	struct resource *mem = jz4740_codec->mem;
405 
406 	snd_soc_unregister_codec(&pdev->dev);
407 
408 	iounmap(jz4740_codec->base);
409 	release_mem_region(mem->start, resource_size(mem));
410 
411 	platform_set_drvdata(pdev, NULL);
412 
413 	return 0;
414 }
415 
416 static struct platform_driver jz4740_codec_driver = {
417 	.probe = jz4740_codec_probe,
418 	.remove = __devexit_p(jz4740_codec_remove),
419 	.driver = {
420 		.name = "jz4740-codec",
421 		.owner = THIS_MODULE,
422 	},
423 };
424 
425 module_platform_driver(jz4740_codec_driver);
426 
427 MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
428 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
429 MODULE_LICENSE("GPL v2");
430 MODULE_ALIAS("platform:jz4740-codec");
431