1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // es8326.c -- es8326 ALSA SoC audio driver 4 // Copyright Everest Semiconductor Co., Ltd 5 // 6 // Authors: David Yang <yangxiaohua@everest-semi.com> 7 // 8 9 #include <linux/clk.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <sound/jack.h> 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <sound/soc-dapm.h> 18 #include <sound/tlv.h> 19 #include "es8326.h" 20 21 struct es8326_priv { 22 struct clk *mclk; 23 struct i2c_client *i2c; 24 struct regmap *regmap; 25 struct snd_soc_component *component; 26 struct delayed_work jack_detect_work; 27 struct delayed_work button_press_work; 28 struct snd_soc_jack *jack; 29 int irq; 30 /* The lock protects the situation that an irq is generated 31 * while enabling or disabling or during an irq. 32 */ 33 struct mutex lock; 34 u8 mic1_src; 35 u8 mic2_src; 36 u8 jack_pol; 37 u8 interrupt_src; 38 u8 interrupt_clk; 39 bool jd_inverted; 40 unsigned int sysclk; 41 42 bool calibrated; 43 int version; 44 int hp; 45 int jack_remove_retry; 46 }; 47 48 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9550, 50, 0); 49 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9550, 50, 0); 50 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_analog_pga_tlv, 0, 300, 0); 51 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_pga_tlv, 0, 600, 0); 52 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(softramp_rate, 0, 100, 0); 53 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_target_tlv, -3200, 200, 0); 54 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(drc_recovery_tlv, -125, 250, 0); 55 56 static const char *const winsize[] = { 57 "0.25db/2 LRCK", 58 "0.25db/4 LRCK", 59 "0.25db/8 LRCK", 60 "0.25db/16 LRCK", 61 "0.25db/32 LRCK", 62 "0.25db/64 LRCK", 63 "0.25db/128 LRCK", 64 "0.25db/256 LRCK", 65 "0.25db/512 LRCK", 66 "0.25db/1024 LRCK", 67 "0.25db/2048 LRCK", 68 "0.25db/4096 LRCK", 69 "0.25db/8192 LRCK", 70 "0.25db/16384 LRCK", 71 "0.25db/32768 LRCK", 72 "0.25db/65536 LRCK", 73 }; 74 75 static const char *const dacpol_txt[] = { 76 "Normal", "R Invert", "L Invert", "L + R Invert" }; 77 78 static const struct soc_enum dacpol = 79 SOC_ENUM_SINGLE(ES8326_DAC_DSM, 4, 4, dacpol_txt); 80 static const struct soc_enum alc_winsize = 81 SOC_ENUM_SINGLE(ES8326_ADC_RAMPRATE, 4, 16, winsize); 82 static const struct soc_enum drc_winsize = 83 SOC_ENUM_SINGLE(ES8326_DRC_WINSIZE, 4, 16, winsize); 84 85 static const struct snd_kcontrol_new es8326_snd_controls[] = { 86 SOC_SINGLE_TLV("DAC Playback Volume", ES8326_DAC_VOL, 0, 0xbf, 0, dac_vol_tlv), 87 SOC_ENUM("Playback Polarity", dacpol), 88 SOC_SINGLE_TLV("DAC Ramp Rate", ES8326_DAC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 89 SOC_SINGLE_TLV("DRC Recovery Level", ES8326_DRC_RECOVERY, 0, 4, 0, drc_recovery_tlv), 90 SOC_ENUM("DRC Winsize", drc_winsize), 91 SOC_SINGLE_TLV("DRC Target Level", ES8326_DRC_WINSIZE, 0, 0x0f, 0, drc_target_tlv), 92 93 SOC_DOUBLE_R_TLV("ADC Capture Volume", ES8326_ADC1_VOL, ES8326_ADC2_VOL, 0, 0xff, 0, 94 adc_vol_tlv), 95 SOC_DOUBLE_TLV("ADC PGA Volume", ES8326_ADC_SCALE, 4, 0, 5, 0, adc_pga_tlv), 96 SOC_SINGLE_TLV("ADC PGA Gain Volume", ES8326_PGAGAIN, 0, 10, 0, adc_analog_pga_tlv), 97 SOC_SINGLE_TLV("ADC Ramp Rate", ES8326_ADC_RAMPRATE, 0, 0x0f, 0, softramp_rate), 98 SOC_SINGLE("ALC Capture Switch", ES8326_ALC_RECOVERY, 3, 1, 0), 99 SOC_SINGLE_TLV("ALC Capture Recovery Level", ES8326_ALC_LEVEL, 100 0, 4, 0, drc_recovery_tlv), 101 SOC_ENUM("ALC Capture Winsize", alc_winsize), 102 SOC_SINGLE_TLV("ALC Capture Target Level", ES8326_ALC_LEVEL, 103 0, 0x0f, 0, drc_target_tlv), 104 105 }; 106 107 static const struct snd_soc_dapm_widget es8326_dapm_widgets[] = { 108 SND_SOC_DAPM_INPUT("MIC1"), 109 SND_SOC_DAPM_INPUT("MIC2"), 110 SND_SOC_DAPM_INPUT("MIC3"), 111 SND_SOC_DAPM_INPUT("MIC4"), 112 113 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 114 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 115 116 /* Digital Interface */ 117 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 0, SND_SOC_NOPM, 0, 0), 118 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0, SND_SOC_NOPM, 0, 0), 119 120 /* ADC Digital Mute */ 121 SND_SOC_DAPM_PGA("ADC L1", ES8326_ADC_MUTE, 0, 1, NULL, 0), 122 SND_SOC_DAPM_PGA("ADC R1", ES8326_ADC_MUTE, 1, 1, NULL, 0), 123 SND_SOC_DAPM_PGA("ADC L2", ES8326_ADC_MUTE, 2, 1, NULL, 0), 124 SND_SOC_DAPM_PGA("ADC R2", ES8326_ADC_MUTE, 3, 1, NULL, 0), 125 126 /* Analog Power Supply*/ 127 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8326_ANA_PDN, 0, 1), 128 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8326_ANA_PDN, 1, 1), 129 SND_SOC_DAPM_SUPPLY("MICBIAS1", ES8326_ANA_MICBIAS, 2, 0, NULL, 0), 130 SND_SOC_DAPM_SUPPLY("MICBIAS2", ES8326_ANA_MICBIAS, 3, 0, NULL, 0), 131 132 SND_SOC_DAPM_PGA("LHPMIX", ES8326_DAC2HPMIX, 7, 0, NULL, 0), 133 SND_SOC_DAPM_PGA("RHPMIX", ES8326_DAC2HPMIX, 3, 0, NULL, 0), 134 135 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOR Supply", ES8326_HP_CAL, 136 4, 7, 0, 0), 137 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPOL Supply", ES8326_HP_CAL, 138 0, 7, 0, 0), 139 140 SND_SOC_DAPM_OUTPUT("HPOL"), 141 SND_SOC_DAPM_OUTPUT("HPOR"), 142 }; 143 144 static const struct snd_soc_dapm_route es8326_dapm_routes[] = { 145 {"ADC L1", NULL, "MIC1"}, 146 {"ADC R1", NULL, "MIC2"}, 147 {"ADC L2", NULL, "MIC3"}, 148 {"ADC R2", NULL, "MIC4"}, 149 150 {"ADC L", NULL, "ADC L1"}, 151 {"ADC R", NULL, "ADC R1"}, 152 {"ADC L", NULL, "ADC L2"}, 153 {"ADC R", NULL, "ADC R2"}, 154 155 {"I2S OUT", NULL, "ADC L"}, 156 {"I2S OUT", NULL, "ADC R"}, 157 158 {"Right DAC", NULL, "I2S IN"}, 159 {"Left DAC", NULL, "I2S IN"}, 160 161 {"LHPMIX", NULL, "Left DAC"}, 162 {"RHPMIX", NULL, "Right DAC"}, 163 164 {"HPOR", NULL, "HPOR Supply"}, 165 {"HPOL", NULL, "HPOL Supply"}, 166 167 {"HPOL", NULL, "LHPMIX"}, 168 {"HPOR", NULL, "RHPMIX"}, 169 }; 170 171 static bool es8326_volatile_register(struct device *dev, unsigned int reg) 172 { 173 switch (reg) { 174 case ES8326_HPL_OFFSET_INI: 175 case ES8326_HPR_OFFSET_INI: 176 case ES8326_HPDET_STA: 177 case ES8326_CTIA_OMTP_STA: 178 case ES8326_CSM_MUTE_STA: 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 static const struct regmap_config es8326_regmap_config = { 186 .reg_bits = 8, 187 .val_bits = 8, 188 .max_register = 0xff, 189 .volatile_reg = es8326_volatile_register, 190 .cache_type = REGCACHE_RBTREE, 191 }; 192 193 struct _coeff_div { 194 u16 fs; 195 u32 rate; 196 u32 mclk; 197 u8 reg4; 198 u8 reg5; 199 u8 reg6; 200 u8 reg7; 201 u8 reg8; 202 u8 reg9; 203 u8 rega; 204 u8 regb; 205 }; 206 207 /* codec hifi mclk clock divider coefficients */ 208 /* {ratio, LRCK, MCLK, REG04, REG05, REG06, REG07, REG08, REG09, REG10, REG11} */ 209 static const struct _coeff_div coeff_div_v0[] = { 210 {64, 8000, 512000, 0x60, 0x01, 0x0F, 0x75, 0x0A, 0x1B, 0x1F, 0x7F}, 211 {64, 16000, 1024000, 0x20, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 212 {64, 44100, 2822400, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 213 {64, 48000, 3072000, 0xE0, 0x00, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 214 {128, 8000, 1024000, 0x60, 0x00, 0x33, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 215 {128, 16000, 2048000, 0x20, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 216 {128, 44100, 5644800, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 217 {128, 48000, 6144000, 0xE0, 0x01, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 218 219 {192, 32000, 6144000, 0xE0, 0x02, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 220 {256, 8000, 2048000, 0x60, 0x00, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 221 {256, 16000, 4096000, 0x20, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 222 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 223 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 224 {384, 32000, 12288000, 0xE0, 0x05, 0x03, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 225 {400, 48000, 19200000, 0xE9, 0x04, 0x0F, 0x6d, 0x4A, 0x0A, 0x1F, 0x1F}, 226 227 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0x4A, 0x0A, 0x1F, 0x1F}, 228 {512, 8000, 4096000, 0x60, 0x01, 0x03, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 229 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 230 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 231 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 232 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0x4A, 0x0A, 0x1F, 0x1F}, 233 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x0A, 0x1B, 0x1F, 0x7F}, 234 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x0A, 0x1B, 0x1F, 0x3F}, 235 }; 236 237 static const struct _coeff_div coeff_div_v3[] = { 238 {32, 8000, 256000, 0x60, 0x00, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 239 {32, 16000, 512000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 240 {32, 44100, 1411200, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 241 {32, 48000, 1536000, 0x00, 0x00, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 242 {36, 8000, 288000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 243 {36, 16000, 576000, 0x20, 0x00, 0x0D, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 244 {48, 8000, 384000, 0x60, 0x02, 0x1F, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 245 {48, 16000, 768000, 0x20, 0x02, 0x0F, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 246 {48, 48000, 2304000, 0x00, 0x02, 0x0D, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 247 248 {64, 8000, 512000, 0x60, 0x00, 0x35, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 249 {64, 16000, 1024000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 250 {64, 44100, 2822400, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 251 {64, 48000, 3072000, 0xE0, 0x00, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 252 {72, 8000, 576000, 0x20, 0x00, 0x13, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 253 {72, 16000, 1152000, 0x20, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x23, 0x47}, 254 {96, 8000, 768000, 0x60, 0x02, 0x1D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 255 {96, 16000, 1536000, 0x20, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x3F}, 256 {100, 48000, 4800000, 0x04, 0x04, 0x3F, 0x6D, 0xB8, 0x08, 0x4f, 0x1f}, 257 {125, 48000, 6000000, 0x04, 0x04, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 258 259 {128, 8000, 1024000, 0x60, 0x00, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 260 {128, 16000, 2048000, 0x20, 0x00, 0x31, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 261 {128, 44100, 5644800, 0xE0, 0x00, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 262 {128, 48000, 6144000, 0xE0, 0x00, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 263 {144, 8000, 1152000, 0x20, 0x00, 0x03, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 264 {144, 16000, 2304000, 0x20, 0x00, 0x11, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 265 {192, 8000, 1536000, 0x60, 0x02, 0x0D, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 266 {192, 32000, 6144000, 0xE0, 0x02, 0x31, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 267 {192, 16000, 3072000, 0x20, 0x02, 0x05, 0x75, 0xCA, 0x1B, 0x1F, 0x3F}, 268 269 {200, 48000, 9600000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 270 {250, 48000, 12000000, 0x04, 0x04, 0x0F, 0x2D, 0xCA, 0x0A, 0x27, 0x27}, 271 {256, 8000, 2048000, 0x60, 0x00, 0x31, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 272 {256, 16000, 4096000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 273 {256, 44100, 11289600, 0xE0, 0x00, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 274 {256, 48000, 12288000, 0xE0, 0x00, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 275 {288, 8000, 2304000, 0x20, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x23, 0x47}, 276 {384, 8000, 3072000, 0x60, 0x02, 0x05, 0x75, 0x8A, 0x1B, 0x1F, 0x7F}, 277 {384, 16000, 6144000, 0x20, 0x02, 0x03, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 278 {384, 32000, 12288000, 0xE0, 0x02, 0x01, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 279 {384, 48000, 18432000, 0x00, 0x02, 0x01, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 280 281 {400, 48000, 19200000, 0xE4, 0x04, 0x35, 0x6d, 0xCA, 0x0A, 0x1F, 0x1F}, 282 {500, 48000, 24000000, 0xF8, 0x04, 0x3F, 0x6D, 0xCA, 0x0A, 0x1F, 0x1F}, 283 {512, 8000, 4096000, 0x60, 0x00, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 284 {512, 16000, 8192000, 0x20, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 285 {512, 44100, 22579200, 0xE0, 0x00, 0x00, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 286 {512, 48000, 24576000, 0xE0, 0x00, 0x00, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 287 {768, 8000, 6144000, 0x60, 0x02, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 288 {768, 16000, 12288000, 0x20, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 289 {768, 32000, 24576000, 0xE0, 0x02, 0x30, 0x2D, 0xCA, 0x0A, 0x1F, 0x1F}, 290 {800, 48000, 38400000, 0x00, 0x18, 0x13, 0x2D, 0x8A, 0x0A, 0x1F, 0x1F}, 291 292 {1024, 8000, 8192000, 0x60, 0x00, 0x30, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 293 {1024, 16000, 16384000, 0x20, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 294 {1152, 16000, 18432000, 0x20, 0x08, 0x11, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 295 {1536, 8000, 12288000, 0x60, 0x02, 0x01, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 296 {1536, 16000, 24576000, 0x20, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x3F}, 297 {1625, 8000, 13000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 298 {1625, 16000, 26000000, 0x0C, 0x18, 0x1F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 299 {2048, 8000, 16384000, 0x60, 0x00, 0x00, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 300 {2304, 8000, 18432000, 0x40, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x5F}, 301 {3072, 8000, 24576000, 0x60, 0x02, 0x10, 0x35, 0x8A, 0x1B, 0x1F, 0x7F}, 302 {3250, 8000, 26000000, 0x0C, 0x18, 0x0F, 0x2D, 0x8A, 0x0A, 0x27, 0x27}, 303 }; 304 305 static inline int get_coeff(int mclk, int rate, int array, 306 const struct _coeff_div *coeff_div) 307 { 308 int i; 309 310 for (i = 0; i < array; i++) { 311 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk) 312 return i; 313 } 314 315 return -EINVAL; 316 } 317 318 static int es8326_set_dai_sysclk(struct snd_soc_dai *codec_dai, 319 int clk_id, unsigned int freq, int dir) 320 { 321 struct snd_soc_component *codec = codec_dai->component; 322 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 323 324 es8326->sysclk = freq; 325 326 return 0; 327 } 328 329 static int es8326_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 330 { 331 struct snd_soc_component *component = codec_dai->component; 332 u8 iface = 0; 333 334 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 335 case SND_SOC_DAIFMT_CBC_CFP: 336 snd_soc_component_update_bits(component, ES8326_RESET, 337 ES8326_MASTER_MODE_EN, ES8326_MASTER_MODE_EN); 338 break; 339 case SND_SOC_DAIFMT_CBC_CFC: 340 break; 341 default: 342 return -EINVAL; 343 } 344 345 /* interface format */ 346 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 347 case SND_SOC_DAIFMT_I2S: 348 break; 349 case SND_SOC_DAIFMT_RIGHT_J: 350 dev_err(component->dev, "Codec driver does not support right justified\n"); 351 return -EINVAL; 352 case SND_SOC_DAIFMT_LEFT_J: 353 iface |= ES8326_DAIFMT_LEFT_J; 354 break; 355 case SND_SOC_DAIFMT_DSP_A: 356 iface |= ES8326_DAIFMT_DSP_A; 357 break; 358 case SND_SOC_DAIFMT_DSP_B: 359 iface |= ES8326_DAIFMT_DSP_B; 360 break; 361 default: 362 return -EINVAL; 363 } 364 365 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DAIFMT_MASK, iface); 366 367 return 0; 368 } 369 370 static int es8326_pcm_hw_params(struct snd_pcm_substream *substream, 371 struct snd_pcm_hw_params *params, 372 struct snd_soc_dai *dai) 373 { 374 struct snd_soc_component *component = dai->component; 375 const struct _coeff_div *coeff_div; 376 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 377 u8 srate = 0; 378 int coeff, array; 379 380 if (es8326->version == 0) { 381 coeff_div = coeff_div_v0; 382 array = ARRAY_SIZE(coeff_div_v0); 383 } else { 384 coeff_div = coeff_div_v3; 385 array = ARRAY_SIZE(coeff_div_v3); 386 } 387 coeff = get_coeff(es8326->sysclk, params_rate(params), array, coeff_div); 388 /* bit size */ 389 switch (params_format(params)) { 390 case SNDRV_PCM_FORMAT_S16_LE: 391 srate |= ES8326_S16_LE; 392 break; 393 case SNDRV_PCM_FORMAT_S20_3LE: 394 srate |= ES8326_S20_3_LE; 395 break; 396 case SNDRV_PCM_FORMAT_S18_3LE: 397 srate |= ES8326_S18_LE; 398 break; 399 case SNDRV_PCM_FORMAT_S24_LE: 400 srate |= ES8326_S24_LE; 401 break; 402 case SNDRV_PCM_FORMAT_S32_LE: 403 srate |= ES8326_S32_LE; 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 /* set iface & srate */ 410 snd_soc_component_update_bits(component, ES8326_FMT, ES8326_DATA_LEN_MASK, srate); 411 412 if (coeff >= 0) { 413 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 414 coeff_div[coeff].reg4); 415 regmap_write(es8326->regmap, ES8326_CLK_DIV2, 416 coeff_div[coeff].reg5); 417 regmap_write(es8326->regmap, ES8326_CLK_DLL, 418 coeff_div[coeff].reg6); 419 regmap_write(es8326->regmap, ES8326_CLK_MUX, 420 coeff_div[coeff].reg7); 421 regmap_write(es8326->regmap, ES8326_CLK_ADC_SEL, 422 coeff_div[coeff].reg8); 423 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 424 coeff_div[coeff].reg9); 425 regmap_write(es8326->regmap, ES8326_CLK_ADC_OSR, 426 coeff_div[coeff].rega); 427 regmap_write(es8326->regmap, ES8326_CLK_DAC_OSR, 428 coeff_div[coeff].regb); 429 } else { 430 dev_warn(component->dev, "Clock coefficients do not match"); 431 } 432 433 return 0; 434 } 435 436 static int es8326_mute(struct snd_soc_dai *dai, int mute, int direction) 437 { 438 struct snd_soc_component *component = dai->component; 439 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 440 unsigned int offset_l, offset_r; 441 442 if (mute) { 443 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 444 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 445 ES8326_MUTE_MASK, ES8326_MUTE); 446 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xf0); 447 } else { 448 if (!es8326->calibrated) { 449 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL); 450 msleep(30); 451 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 452 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 453 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 454 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 455 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 456 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 457 es8326->calibrated = true; 458 } 459 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 460 regmap_write(es8326->regmap, ES8326_HP_VOL, 0x91); 461 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON); 462 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, 463 ES8326_MUTE_MASK, ~(ES8326_MUTE)); 464 } 465 return 0; 466 } 467 468 static int es8326_set_bias_level(struct snd_soc_component *codec, 469 enum snd_soc_bias_level level) 470 { 471 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec); 472 int ret; 473 474 switch (level) { 475 case SND_SOC_BIAS_ON: 476 ret = clk_prepare_enable(es8326->mclk); 477 if (ret) 478 return ret; 479 480 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00); 481 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk); 482 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, 483 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT)); 484 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E); 485 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40); 486 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00); 487 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20); 488 489 regmap_update_bits(es8326->regmap, ES8326_RESET, 490 ES8326_CSM_ON, ES8326_CSM_ON); 491 break; 492 case SND_SOC_BIAS_PREPARE: 493 break; 494 case SND_SOC_BIAS_STANDBY: 495 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 496 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x00); 497 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00); 498 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT); 499 break; 500 case SND_SOC_BIAS_OFF: 501 clk_disable_unprepare(es8326->mclk); 502 break; 503 } 504 505 return 0; 506 } 507 508 #define es8326_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 509 SNDRV_PCM_FMTBIT_S24_LE) 510 511 static const struct snd_soc_dai_ops es8326_ops = { 512 .hw_params = es8326_pcm_hw_params, 513 .set_fmt = es8326_set_dai_fmt, 514 .set_sysclk = es8326_set_dai_sysclk, 515 .mute_stream = es8326_mute, 516 .no_capture_mute = 1, 517 }; 518 519 static struct snd_soc_dai_driver es8326_dai = { 520 .name = "ES8326 HiFi", 521 .playback = { 522 .stream_name = "Playback", 523 .channels_min = 1, 524 .channels_max = 2, 525 .rates = SNDRV_PCM_RATE_8000_48000, 526 .formats = es8326_FORMATS, 527 }, 528 .capture = { 529 .stream_name = "Capture", 530 .channels_min = 1, 531 .channels_max = 2, 532 .rates = SNDRV_PCM_RATE_8000_48000, 533 .formats = es8326_FORMATS, 534 }, 535 .ops = &es8326_ops, 536 .symmetric_rate = 1, 537 }; 538 539 static void es8326_enable_micbias(struct snd_soc_component *component) 540 { 541 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 542 543 snd_soc_dapm_mutex_lock(dapm); 544 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1"); 545 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS2"); 546 snd_soc_dapm_sync_unlocked(dapm); 547 snd_soc_dapm_mutex_unlock(dapm); 548 } 549 550 static void es8326_disable_micbias(struct snd_soc_component *component) 551 { 552 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 553 554 snd_soc_dapm_mutex_lock(dapm); 555 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1"); 556 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS2"); 557 snd_soc_dapm_sync_unlocked(dapm); 558 snd_soc_dapm_mutex_unlock(dapm); 559 } 560 561 /* 562 * For button detection, set the following in soundcard 563 * snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE); 564 * snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP); 565 * snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN); 566 */ 567 static void es8326_jack_button_handler(struct work_struct *work) 568 { 569 struct es8326_priv *es8326 = 570 container_of(work, struct es8326_priv, button_press_work.work); 571 struct snd_soc_component *comp = es8326->component; 572 unsigned int iface; 573 static int button_to_report, press_count; 574 static int prev_button, cur_button; 575 576 if (!(es8326->jack->status & SND_JACK_HEADSET)) /* Jack unplugged */ 577 return; 578 579 mutex_lock(&es8326->lock); 580 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 581 switch (iface) { 582 case 0x93: 583 /* pause button detected */ 584 cur_button = SND_JACK_BTN_0; 585 break; 586 case 0x6f: 587 case 0x4b: 588 /* button volume up */ 589 cur_button = SND_JACK_BTN_1; 590 break; 591 case 0x27: 592 /* button volume down */ 593 cur_button = SND_JACK_BTN_2; 594 break; 595 case 0x1e: 596 case 0xe2: 597 /* button released or not pressed */ 598 cur_button = 0; 599 break; 600 default: 601 break; 602 } 603 604 if ((prev_button == cur_button) && (cur_button != 0)) { 605 press_count++; 606 if (press_count > 3) { 607 /* report a press every 120ms */ 608 snd_soc_jack_report(es8326->jack, cur_button, 609 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 610 press_count = 0; 611 } 612 button_to_report = cur_button; 613 queue_delayed_work(system_wq, &es8326->button_press_work, 614 msecs_to_jiffies(35)); 615 } else if (prev_button != cur_button) { 616 /* mismatch, detect again */ 617 prev_button = cur_button; 618 queue_delayed_work(system_wq, &es8326->button_press_work, 619 msecs_to_jiffies(35)); 620 } else { 621 /* released or no pressed */ 622 if (button_to_report != 0) { 623 snd_soc_jack_report(es8326->jack, button_to_report, 624 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 625 snd_soc_jack_report(es8326->jack, 0, 626 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2); 627 button_to_report = 0; 628 } 629 } 630 mutex_unlock(&es8326->lock); 631 } 632 633 static void es8326_jack_detect_handler(struct work_struct *work) 634 { 635 struct es8326_priv *es8326 = 636 container_of(work, struct es8326_priv, jack_detect_work.work); 637 struct snd_soc_component *comp = es8326->component; 638 unsigned int iface; 639 640 mutex_lock(&es8326->lock); 641 iface = snd_soc_component_read(comp, ES8326_HPDET_STA); 642 dev_dbg(comp->dev, "gpio flag %#04x", iface); 643 644 if ((es8326->jack_remove_retry == 1) && (es8326->version != ES8326_VERSION_B)) { 645 if (iface & ES8326_HPINSERT_FLAG) 646 es8326->jack_remove_retry = 2; 647 else 648 es8326->jack_remove_retry = 0; 649 650 dev_dbg(comp->dev, "remove event check, set HPJACK_POL normal, cnt = %d\n", 651 es8326->jack_remove_retry); 652 /* 653 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 654 */ 655 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 656 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 657 ~es8326->jack_pol : es8326->jack_pol)); 658 goto exit; 659 } 660 661 if ((iface & ES8326_HPINSERT_FLAG) == 0) { 662 /* Jack unplugged or spurious IRQ */ 663 dev_dbg(comp->dev, "No headset detected\n"); 664 es8326_disable_micbias(es8326->component); 665 if (es8326->jack->status & SND_JACK_HEADPHONE) { 666 dev_dbg(comp->dev, "Report hp remove event\n"); 667 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 668 /* mute adc when mic path switch */ 669 regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33); 670 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x44); 671 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x66); 672 es8326->hp = 0; 673 } 674 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 675 /* 676 * Inverted HPJACK_POL bit to trigger one IRQ to double check HP Removal event 677 */ 678 if ((es8326->jack_remove_retry == 0) && (es8326->version != ES8326_VERSION_B)) { 679 es8326->jack_remove_retry = 1; 680 dev_dbg(comp->dev, "remove event check, invert HPJACK_POL, cnt = %d\n", 681 es8326->jack_remove_retry); 682 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 683 ES8326_HP_DET_JACK_POL, (es8326->jd_inverted ? 684 es8326->jack_pol : ~es8326->jack_pol)); 685 686 } else { 687 es8326->jack_remove_retry = 0; 688 } 689 } else if ((iface & ES8326_HPINSERT_FLAG) == ES8326_HPINSERT_FLAG) { 690 es8326->jack_remove_retry = 0; 691 if (es8326->hp == 0) { 692 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n"); 693 /* 694 * set auto-check mode, then restart jack_detect_work after 400ms. 695 * Don't report jack status. 696 */ 697 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01); 698 usleep_range(50000, 70000); 699 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00); 700 queue_delayed_work(system_wq, &es8326->jack_detect_work, 701 msecs_to_jiffies(400)); 702 es8326->hp = 1; 703 goto exit; 704 } 705 if (es8326->jack->status & SND_JACK_HEADSET) { 706 /* detect button */ 707 dev_dbg(comp->dev, "button pressed\n"); 708 queue_delayed_work(system_wq, &es8326->button_press_work, 10); 709 goto exit; 710 } 711 if ((iface & ES8326_HPBUTTON_FLAG) == 0x01) { 712 dev_dbg(comp->dev, "Headphone detected\n"); 713 snd_soc_jack_report(es8326->jack, 714 SND_JACK_HEADPHONE, SND_JACK_HEADSET); 715 } else { 716 dev_dbg(comp->dev, "Headset detected\n"); 717 snd_soc_jack_report(es8326->jack, 718 SND_JACK_HEADSET, SND_JACK_HEADSET); 719 720 regmap_write(es8326->regmap, ES8326_ADC_SCALE, 0x33); 721 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 722 0x08, 0x08); 723 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, 724 0x80, 0x80); 725 regmap_write(es8326->regmap, ES8326_ADC1_SRC, 0x00); 726 regmap_write(es8326->regmap, ES8326_ADC2_SRC, 0x00); 727 regmap_update_bits(es8326->regmap, ES8326_PGA_PDN, 728 0x08, 0x00); 729 usleep_range(10000, 15000); 730 } 731 } 732 exit: 733 mutex_unlock(&es8326->lock); 734 } 735 736 static irqreturn_t es8326_irq(int irq, void *dev_id) 737 { 738 struct es8326_priv *es8326 = dev_id; 739 struct snd_soc_component *comp = es8326->component; 740 741 if (!es8326->jack) 742 goto out; 743 744 es8326_enable_micbias(comp); 745 746 if (es8326->jack->status & SND_JACK_HEADSET) 747 queue_delayed_work(system_wq, &es8326->jack_detect_work, 748 msecs_to_jiffies(10)); 749 else 750 queue_delayed_work(system_wq, &es8326->jack_detect_work, 751 msecs_to_jiffies(300)); 752 753 out: 754 return IRQ_HANDLED; 755 } 756 757 static int es8326_calibrate(struct snd_soc_component *component) 758 { 759 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 760 unsigned int reg; 761 unsigned int offset_l, offset_r; 762 763 regmap_read(es8326->regmap, ES8326_CHIP_VERSION, ®); 764 es8326->version = reg; 765 766 if ((es8326->version == ES8326_VERSION_B) && (es8326->calibrated == false)) { 767 dev_dbg(component->dev, "ES8326_VERSION_B, calibrating\n"); 768 regmap_write(es8326->regmap, ES8326_CLK_INV, 0xc0); 769 regmap_write(es8326->regmap, ES8326_CLK_DIV1, 0x01); 770 regmap_write(es8326->regmap, ES8326_CLK_DLL, 0x30); 771 regmap_write(es8326->regmap, ES8326_CLK_MUX, 0xed); 772 regmap_write(es8326->regmap, ES8326_CLK_DAC_SEL, 0x08); 773 regmap_write(es8326->regmap, ES8326_CLK_TRI, 0xc1); 774 regmap_write(es8326->regmap, ES8326_DAC_MUTE, 0x03); 775 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7f); 776 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x03); 777 regmap_write(es8326->regmap, ES8326_DAC2HPMIX, 0x88); 778 usleep_range(15000, 20000); 779 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 780 usleep_range(15000, 20000); 781 regmap_write(es8326->regmap, ES8326_RESET, 0xc0); 782 usleep_range(15000, 20000); 783 784 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, ES8326_HP_OFF); 785 regmap_read(es8326->regmap, ES8326_CSM_MUTE_STA, ®); 786 if ((reg & 0xf0) != 0x40) 787 msleep(50); 788 789 regmap_write(es8326->regmap, ES8326_HP_CAL, 0xd4); 790 msleep(200); 791 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x4d); 792 msleep(200); 793 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF); 794 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l); 795 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r); 796 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c); 797 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l); 798 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r); 799 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 800 801 es8326->calibrated = true; 802 } 803 804 return 0; 805 } 806 807 static int es8326_resume(struct snd_soc_component *component) 808 { 809 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 810 811 regcache_cache_only(es8326->regmap, false); 812 regcache_sync(es8326->regmap); 813 814 /* reset internal clock state */ 815 regmap_write(es8326->regmap, ES8326_RESET, 0x1f); 816 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E); 817 usleep_range(10000, 15000); 818 regmap_write(es8326->regmap, ES8326_HPJACK_TIMER, 0xe9); 819 regmap_write(es8326->regmap, ES8326_ANA_MICBIAS, 0x4b); 820 /* set headphone default type and detect pin */ 821 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x83); 822 regmap_write(es8326->regmap, ES8326_CLK_RESAMPLE, 0x05); 823 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x30); 824 825 /* set internal oscillator as clock source of headpone cp */ 826 regmap_write(es8326->regmap, ES8326_CLK_DIV_CPC, 0x89); 827 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_ON); 828 /* clock manager reset release */ 829 regmap_write(es8326->regmap, ES8326_RESET, 0x17); 830 /* set headphone detection as half scan mode */ 831 regmap_write(es8326->regmap, ES8326_HP_MISC, 0x30); 832 regmap_write(es8326->regmap, ES8326_PULLUP_CTL, 0x00); 833 834 /* enable headphone driver */ 835 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa7); 836 usleep_range(2000, 5000); 837 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0xa3); 838 regmap_write(es8326->regmap, ES8326_HP_DRIVER_REF, 0xb3); 839 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1); 840 841 regmap_write(es8326->regmap, ES8326_CLK_INV, 0x00); 842 regmap_write(es8326->regmap, ES8326_CLK_VMIDS1, 0xc4); 843 regmap_write(es8326->regmap, ES8326_CLK_VMIDS2, 0x81); 844 regmap_write(es8326->regmap, ES8326_CLK_CAL_TIME, 0x00); 845 /* calibrate for B version */ 846 es8326_calibrate(component); 847 /* turn off headphone out */ 848 regmap_write(es8326->regmap, ES8326_HP_CAL, 0x00); 849 /* set ADC and DAC in low power mode */ 850 regmap_write(es8326->regmap, ES8326_ANA_LP, 0xf0); 851 852 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F); 853 /* select vdda as micbias source */ 854 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23); 855 /* set dac dsmclip = 1 */ 856 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08); 857 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15); 858 859 regmap_write(es8326->regmap, ES8326_INT_SOURCE, 860 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON)); 861 regmap_write(es8326->regmap, ES8326_INTOUT_IO, 862 es8326->interrupt_clk); 863 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, 864 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT)); 865 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT); 866 867 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b); 868 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON); 869 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK, 870 ES8326_MIC1_SEL); 871 872 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK, 873 ES8326_MUTE); 874 875 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 | 876 ((es8326->version == ES8326_VERSION_B) ? 877 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) : 878 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04))); 879 regmap_write(es8326->regmap, ES8326_HP_VOL, 0x11); 880 881 es8326->jack_remove_retry = 0; 882 es8326->hp = 0; 883 return 0; 884 } 885 886 static int es8326_suspend(struct snd_soc_component *component) 887 { 888 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 889 890 cancel_delayed_work_sync(&es8326->jack_detect_work); 891 es8326_disable_micbias(component); 892 es8326->calibrated = false; 893 regmap_write(es8326->regmap, ES8326_CLK_CTL, ES8326_CLK_OFF); 894 regcache_cache_only(es8326->regmap, true); 895 regcache_mark_dirty(es8326->regmap); 896 897 /* reset register value to default */ 898 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x01); 899 usleep_range(1000, 3000); 900 regmap_write(es8326->regmap, ES8326_CSM_I2C_STA, 0x00); 901 return 0; 902 } 903 904 static int es8326_probe(struct snd_soc_component *component) 905 { 906 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 907 int ret; 908 909 es8326->component = component; 910 es8326->jd_inverted = device_property_read_bool(component->dev, 911 "everest,jack-detect-inverted"); 912 913 ret = device_property_read_u8(component->dev, "everest,mic1-src", &es8326->mic1_src); 914 if (ret != 0) { 915 dev_dbg(component->dev, "mic1-src return %d", ret); 916 es8326->mic1_src = ES8326_ADC_AMIC; 917 } 918 dev_dbg(component->dev, "mic1-src %x", es8326->mic1_src); 919 920 ret = device_property_read_u8(component->dev, "everest,mic2-src", &es8326->mic2_src); 921 if (ret != 0) { 922 dev_dbg(component->dev, "mic2-src return %d", ret); 923 es8326->mic2_src = ES8326_ADC_DMIC; 924 } 925 dev_dbg(component->dev, "mic2-src %x", es8326->mic2_src); 926 927 ret = device_property_read_u8(component->dev, "everest,jack-pol", &es8326->jack_pol); 928 if (ret != 0) { 929 dev_dbg(component->dev, "jack-pol return %d", ret); 930 es8326->jack_pol = ES8326_HP_TYPE_AUTO; 931 } 932 dev_dbg(component->dev, "jack-pol %x", es8326->jack_pol); 933 934 ret = device_property_read_u8(component->dev, "everest,interrupt-src", 935 &es8326->interrupt_src); 936 if (ret != 0) { 937 dev_dbg(component->dev, "interrupt-src return %d", ret); 938 es8326->interrupt_src = ES8326_HP_DET_SRC_PIN9; 939 } 940 dev_dbg(component->dev, "interrupt-src %x", es8326->interrupt_src); 941 942 ret = device_property_read_u8(component->dev, "everest,interrupt-clk", 943 &es8326->interrupt_clk); 944 if (ret != 0) { 945 dev_dbg(component->dev, "interrupt-clk return %d", ret); 946 es8326->interrupt_clk = 0x45; 947 } 948 dev_dbg(component->dev, "interrupt-clk %x", es8326->interrupt_clk); 949 950 es8326_resume(component); 951 return 0; 952 } 953 954 static void es8326_enable_jack_detect(struct snd_soc_component *component, 955 struct snd_soc_jack *jack) 956 { 957 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 958 959 mutex_lock(&es8326->lock); 960 if (es8326->jd_inverted) 961 snd_soc_component_update_bits(component, ES8326_HPDET_TYPE, 962 ES8326_HP_DET_JACK_POL, ~es8326->jack_pol); 963 es8326->jack = jack; 964 965 mutex_unlock(&es8326->lock); 966 es8326_irq(es8326->irq, es8326); 967 } 968 969 static void es8326_disable_jack_detect(struct snd_soc_component *component) 970 { 971 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component); 972 973 dev_dbg(component->dev, "Enter into %s\n", __func__); 974 if (!es8326->jack) 975 return; /* Already disabled (or never enabled) */ 976 cancel_delayed_work_sync(&es8326->jack_detect_work); 977 978 mutex_lock(&es8326->lock); 979 if (es8326->jack->status & SND_JACK_MICROPHONE) { 980 es8326_disable_micbias(component); 981 snd_soc_jack_report(es8326->jack, 0, SND_JACK_HEADSET); 982 } 983 es8326->jack = NULL; 984 mutex_unlock(&es8326->lock); 985 } 986 987 static int es8326_set_jack(struct snd_soc_component *component, 988 struct snd_soc_jack *jack, void *data) 989 { 990 if (jack) 991 es8326_enable_jack_detect(component, jack); 992 else 993 es8326_disable_jack_detect(component); 994 995 return 0; 996 } 997 998 static void es8326_remove(struct snd_soc_component *component) 999 { 1000 es8326_disable_jack_detect(component); 1001 es8326_set_bias_level(component, SND_SOC_BIAS_OFF); 1002 } 1003 1004 static const struct snd_soc_component_driver soc_component_dev_es8326 = { 1005 .probe = es8326_probe, 1006 .remove = es8326_remove, 1007 .resume = es8326_resume, 1008 .suspend = es8326_suspend, 1009 .set_bias_level = es8326_set_bias_level, 1010 .set_jack = es8326_set_jack, 1011 .dapm_widgets = es8326_dapm_widgets, 1012 .num_dapm_widgets = ARRAY_SIZE(es8326_dapm_widgets), 1013 .dapm_routes = es8326_dapm_routes, 1014 .num_dapm_routes = ARRAY_SIZE(es8326_dapm_routes), 1015 .controls = es8326_snd_controls, 1016 .num_controls = ARRAY_SIZE(es8326_snd_controls), 1017 .use_pmdown_time = 1, 1018 .endianness = 1, 1019 }; 1020 1021 static int es8326_i2c_probe(struct i2c_client *i2c) 1022 { 1023 struct es8326_priv *es8326; 1024 int ret; 1025 1026 es8326 = devm_kzalloc(&i2c->dev, sizeof(struct es8326_priv), GFP_KERNEL); 1027 if (!es8326) 1028 return -ENOMEM; 1029 1030 i2c_set_clientdata(i2c, es8326); 1031 es8326->i2c = i2c; 1032 mutex_init(&es8326->lock); 1033 es8326->regmap = devm_regmap_init_i2c(i2c, &es8326_regmap_config); 1034 if (IS_ERR(es8326->regmap)) { 1035 ret = PTR_ERR(es8326->regmap); 1036 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); 1037 return ret; 1038 } 1039 1040 es8326->irq = i2c->irq; 1041 INIT_DELAYED_WORK(&es8326->jack_detect_work, 1042 es8326_jack_detect_handler); 1043 INIT_DELAYED_WORK(&es8326->button_press_work, 1044 es8326_jack_button_handler); 1045 /* ES8316 is level-based while ES8326 is edge-based */ 1046 ret = devm_request_threaded_irq(&i2c->dev, es8326->irq, NULL, es8326_irq, 1047 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1048 "es8326", es8326); 1049 if (ret) { 1050 dev_warn(&i2c->dev, "Failed to request IRQ: %d: %d\n", 1051 es8326->irq, ret); 1052 es8326->irq = -ENXIO; 1053 } 1054 1055 es8326->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 1056 if (IS_ERR(es8326->mclk)) { 1057 dev_err(&i2c->dev, "unable to get mclk\n"); 1058 return PTR_ERR(es8326->mclk); 1059 } 1060 if (!es8326->mclk) 1061 dev_warn(&i2c->dev, "assuming static mclk\n"); 1062 1063 ret = clk_prepare_enable(es8326->mclk); 1064 if (ret) { 1065 dev_err(&i2c->dev, "unable to enable mclk\n"); 1066 return ret; 1067 } 1068 return devm_snd_soc_register_component(&i2c->dev, 1069 &soc_component_dev_es8326, 1070 &es8326_dai, 1); 1071 } 1072 1073 static const struct i2c_device_id es8326_i2c_id[] = { 1074 {"es8326", 0 }, 1075 {} 1076 }; 1077 MODULE_DEVICE_TABLE(i2c, es8326_i2c_id); 1078 1079 #ifdef CONFIG_OF 1080 static const struct of_device_id es8326_of_match[] = { 1081 { .compatible = "everest,es8326", }, 1082 {} 1083 }; 1084 MODULE_DEVICE_TABLE(of, es8326_of_match); 1085 #endif 1086 1087 #ifdef CONFIG_ACPI 1088 static const struct acpi_device_id es8326_acpi_match[] = { 1089 {"ESSX8326", 0}, 1090 {}, 1091 }; 1092 MODULE_DEVICE_TABLE(acpi, es8326_acpi_match); 1093 #endif 1094 1095 static struct i2c_driver es8326_i2c_driver = { 1096 .driver = { 1097 .name = "es8326", 1098 .acpi_match_table = ACPI_PTR(es8326_acpi_match), 1099 .of_match_table = of_match_ptr(es8326_of_match), 1100 }, 1101 .probe = es8326_i2c_probe, 1102 .id_table = es8326_i2c_id, 1103 }; 1104 module_i2c_driver(es8326_i2c_driver); 1105 1106 MODULE_DESCRIPTION("ASoC es8326 driver"); 1107 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>"); 1108 MODULE_LICENSE("GPL"); 1109