1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // es8323.c -- es8323 ALSA SoC audio driver 4 // 5 // Copyright 2024 Rockchip Electronics Co. Ltd. 6 // Copyright 2024 Everest Semiconductor Co.,Ltd. 7 // Copyright 2024 Loongson Technology Co.,Ltd. 8 // 9 // Author: Mark Brown <broonie@kernel.org> 10 // Jianqun Xu <jay.xu@rock-chips.com> 11 // Nickey Yang <nickey.yang@rock-chips.com> 12 // Further cleanup and restructuring by: 13 // Binbin Zhou <zhoubinbin@loongson.cn> 14 15 #include <linux/bitfield.h> 16 #include <linux/module.h> 17 #include <linux/acpi.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/i2c.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/regmap.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/soc-dapm.h> 27 #include <sound/tlv.h> 28 29 #include "es8323.h" 30 31 struct es8323_priv { 32 unsigned int sysclk; 33 struct clk *mclk; 34 struct regmap *regmap; 35 struct snd_pcm_hw_constraint_list *sysclk_constraints; 36 }; 37 38 /* es8323 register cache */ 39 static const struct reg_default es8323_reg_defaults[] = { 40 { ES8323_CONTROL1, 0x06 }, 41 { ES8323_CONTROL2, 0x1c }, 42 { ES8323_CHIPPOWER, 0xc3 }, 43 { ES8323_ADCPOWER, 0xfc }, 44 { ES8323_DACPOWER, 0xc0 }, 45 { ES8323_CHIPLOPOW1, 0x00 }, 46 { ES8323_CHIPLOPOW2, 0x00 }, 47 { ES8323_ANAVOLMANAG, 0x7c }, 48 { ES8323_MASTERMODE, 0x80 }, 49 { ES8323_ADCCONTROL1, 0x00 }, 50 { ES8323_ADCCONTROL2, 0x00 }, 51 { ES8323_ADCCONTROL3, 0x06 }, 52 { ES8323_ADCCONTROL4, 0x00 }, 53 { ES8323_ADCCONTROL5, 0x06 }, 54 { ES8323_ADCCONTROL6, 0x30 }, 55 { ES8323_ADCCONTROL7, 0x30 }, 56 { ES8323_LADC_VOL, 0xc0 }, 57 { ES8323_RADC_VOL, 0xc0 }, 58 { ES8323_ADCCONTROL10, 0x38 }, 59 { ES8323_ADCCONTROL11, 0xb0 }, 60 { ES8323_ADCCONTROL12, 0x32 }, 61 { ES8323_ADCCONTROL13, 0x06 }, 62 { ES8323_ADCCONTROL14, 0x00 }, 63 { ES8323_DACCONTROL1, 0x00 }, 64 { ES8323_DACCONTROL2, 0x06 }, 65 { ES8323_DACCONTROL3, 0x30 }, 66 { ES8323_LDAC_VOL, 0xc0 }, 67 { ES8323_RDAC_VOL, 0xc0 }, 68 { ES8323_DACCONTROL6, 0x08 }, 69 { ES8323_DACCONTROL7, 0x06 }, 70 { ES8323_DACCONTROL8, 0x1f }, 71 { ES8323_DACCONTROL9, 0xf7 }, 72 { ES8323_DACCONTROL10, 0xfd }, 73 { ES8323_DACCONTROL11, 0xff }, 74 { ES8323_DACCONTROL12, 0x1f }, 75 { ES8323_DACCONTROL13, 0xf7 }, 76 { ES8323_DACCONTROL14, 0xfd }, 77 { ES8323_DACCONTROL15, 0xff }, 78 { ES8323_DACCONTROL16, 0x00 }, 79 { ES8323_DACCONTROL17, 0x38 }, 80 { ES8323_DACCONTROL18, 0x38 }, 81 { ES8323_DACCONTROL19, 0x38 }, 82 { ES8323_DACCONTROL20, 0x38 }, 83 { ES8323_DACCONTROL21, 0x38 }, 84 { ES8323_DACCONTROL22, 0x38 }, 85 { ES8323_DACCONTROL23, 0x00 }, 86 { ES8323_LOUT1_VOL, 0x00 }, 87 { ES8323_ROUT1_VOL, 0x00 }, 88 }; 89 90 static const char *const es8323_stereo_3d_texts[] = { "No 3D ", "Level 1", "Level 2", "Level 3", 91 "Level 4", "Level 5", "Level 6", "Level 7" }; 92 static SOC_ENUM_SINGLE_DECL(es8323_stereo_3d_enum, ES8323_DACCONTROL7, 2, es8323_stereo_3d_texts); 93 94 static const char *const es8323_alc_func_texts[] = { "Off", "Right", "Left", "Stereo" }; 95 static SOC_ENUM_SINGLE_DECL(es8323_alc_function_enum, 96 ES8323_ADCCONTROL10, 6, es8323_alc_func_texts); 97 98 static const char *const es8323_ng_type_texts[] = { "Constant PGA Gain", "Mute ADC Output" }; 99 static SOC_ENUM_SINGLE_DECL(es8323_alc_ng_type_enum, ES8323_ADCCONTROL14, 1, es8323_ng_type_texts); 100 101 static const char *const es8323_deemph_texts[] = { "None", "32Khz", "44.1Khz", "48Khz" }; 102 static SOC_ENUM_SINGLE_DECL(es8323_playback_deemphasis_enum, 103 ES8323_DACCONTROL6, 6, es8323_deemph_texts); 104 105 static const char *const es8323_adcpol_texts[] = { "Normal", "L Invert", 106 "R Invert", "L + R Invert" }; 107 static SOC_ENUM_SINGLE_DECL(es8323_capture_polarity_enum, 108 ES8323_ADCCONTROL6, 6, es8323_adcpol_texts); 109 110 static const DECLARE_TLV_DB_SCALE(es8323_adc_tlv, -9600, 50, 1); 111 static const DECLARE_TLV_DB_SCALE(es8323_dac_tlv, -9600, 50, 1); 112 static const DECLARE_TLV_DB_SCALE(es8323_out_tlv, -4500, 150, 0); 113 static const DECLARE_TLV_DB_SCALE(es8323_bypass_tlv, 0, 300, 0); 114 static const DECLARE_TLV_DB_SCALE(es8323_bypass_tlv2, -15, 300, 0); 115 116 static const struct snd_kcontrol_new es8323_snd_controls[] = { 117 SOC_ENUM("3D Mode", es8323_stereo_3d_enum), 118 SOC_ENUM("ALC Capture Function", es8323_alc_function_enum), 119 SOC_ENUM("ALC Capture NG Type", es8323_alc_ng_type_enum), 120 SOC_ENUM("Playback De-emphasis", es8323_playback_deemphasis_enum), 121 SOC_ENUM("Capture Polarity", es8323_capture_polarity_enum), 122 123 SOC_SINGLE("ALC Capture ZC Switch", ES8323_ADCCONTROL13, 124 ES8323_ADCCONTROL13_ALCZC_OFF, 1, 0), 125 SOC_SINGLE("ALC Capture Decay Time", ES8323_ADCCONTROL12, 126 ES8323_ADCCONTROL12_ALCDCY_OFF, 15, 0), 127 SOC_SINGLE("ALC Capture Attack Time", ES8323_ADCCONTROL12, 128 ES8323_ADCCONTROL12_ALCATK_OFF, 15, 0), 129 SOC_SINGLE("ALC Capture NG Threshold", ES8323_ADCCONTROL14, 130 ES8323_ADCCONTROL14_NGTH_OFF, 31, 0), 131 SOC_SINGLE("ALC Capture NG Switch", ES8323_ADCCONTROL14, 132 ES8323_ADCCONTROL14_NGAT_OFF, 1, 0), 133 SOC_SINGLE("ZC Timeout Switch", ES8323_ADCCONTROL13, 134 ES8323_ADCCONTROL13_TIMEOUT_OFF, 1, 0), 135 SOC_SINGLE("Capture Mute Switch", ES8323_ADCCONTROL7, 136 ES8323_ADCCONTROL7_ADCMUTE_OFF, 1, 0), 137 138 SOC_SINGLE_TLV("Left Channel Capture Volume", ES8323_ADCCONTROL1, 139 ES8323_ADCCONTROL1_MICAMPL_OFF, 8, 0, es8323_bypass_tlv), 140 SOC_SINGLE_TLV("Right Channel Capture Volume", ES8323_ADCCONTROL1, 141 ES8323_ADCCONTROL1_MICAMPR_OFF, 8, 0, es8323_bypass_tlv), 142 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", ES8323_DACCONTROL17, 143 ES8323_DACCONTROL17_LI2LOVOL_OFF, 7, 1, es8323_bypass_tlv2), 144 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", ES8323_DACCONTROL20, 145 ES8323_DACCONTROL20_RI2ROVOL_OFF, 7, 1, es8323_bypass_tlv2), 146 147 SOC_DOUBLE_R_TLV("PCM Volume", 148 ES8323_LDAC_VOL, ES8323_RDAC_VOL, 149 0, 192, 1, es8323_dac_tlv), 150 SOC_DOUBLE_R_TLV("Capture Digital Volume", 151 ES8323_LADC_VOL, ES8323_RADC_VOL, 152 0, 192, 1, es8323_adc_tlv), 153 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", 154 ES8323_LOUT1_VOL, ES8323_ROUT1_VOL, 155 0, 33, 0, es8323_out_tlv), 156 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", 157 ES8323_LOUT2_VOL, ES8323_ROUT2_VOL, 158 0, 33, 0, es8323_out_tlv), 159 }; 160 161 /* Left DAC Route */ 162 static const char *const es8323_pga_sell[] = { "Line 1L", "Line 2L", "NC", "DifferentialL" }; 163 static SOC_ENUM_SINGLE_DECL(es8323_left_dac_enum, ES8323_ADCCONTROL2, 6, es8323_pga_sell); 164 static const struct snd_kcontrol_new es8323_left_dac_mux_controls = 165 SOC_DAPM_ENUM("Left DAC Route", es8323_left_dac_enum); 166 167 /* Right DAC Route */ 168 static const char *const es8323_pga_selr[] = { "Line 1R", "Line 2R", "NC", "DifferentialR" }; 169 static SOC_ENUM_SINGLE_DECL(es8323_right_dac_enum, ES8323_ADCCONTROL2, 4, es8323_pga_selr); 170 static const struct snd_kcontrol_new es8323_right_dac_mux_controls = 171 SOC_DAPM_ENUM("Right DAC Route", es8323_right_dac_enum); 172 173 /* Left Line Mux */ 174 static const char *const es8323_lin_sell[] = { "Line 1L", "Line 2L", "NC", "MicL" }; 175 static SOC_ENUM_SINGLE_DECL(es8323_llin_enum, ES8323_DACCONTROL16, 3, es8323_lin_sell); 176 static const struct snd_kcontrol_new es8323_left_line_controls = 177 SOC_DAPM_ENUM("LLIN Mux", es8323_llin_enum); 178 179 /* Right Line Mux */ 180 static const char *const es8323_lin_selr[] = { "Line 1R", "Line 2R", "NC", "MicR" }; 181 static SOC_ENUM_SINGLE_DECL(es8323_rlin_enum, ES8323_DACCONTROL16, 0, es8323_lin_selr); 182 static const struct snd_kcontrol_new es8323_right_line_controls = 183 SOC_DAPM_ENUM("RLIN Mux", es8323_rlin_enum); 184 185 /* Differential Mux */ 186 static const char *const es8323_diffmux_sel[] = { "Line 1", "Line 2" }; 187 static SOC_ENUM_SINGLE_DECL(es8323_diffmux_enum, ES8323_ADCCONTROL3, 7, es8323_diffmux_sel); 188 static const struct snd_kcontrol_new es8323_diffmux_controls = 189 SOC_DAPM_ENUM("Route2", es8323_diffmux_enum); 190 191 /* Mono ADC Mux */ 192 static const char *const es8323_mono_adc_mux[] = { "Stereo", "Mono (Left)", "Mono (Right)" }; 193 static SOC_ENUM_SINGLE_DECL(es8323_mono_adc_mux_enum, ES8323_ADCCONTROL3, 3, es8323_mono_adc_mux); 194 static const struct snd_kcontrol_new es8323_mono_adc_mux_controls = 195 SOC_DAPM_ENUM("Mono Mux", es8323_mono_adc_mux_enum); 196 197 /* Left Mixer */ 198 static const struct snd_kcontrol_new es8323_left_mixer_controls[] = { 199 SOC_DAPM_SINGLE("Left Playback Switch", ES8323_DACCONTROL17, 7, 1, 0), 200 SOC_DAPM_SINGLE("Left Bypass Switch", ES8323_DACCONTROL17, 6, 1, 0), 201 }; 202 203 /* Right Mixer */ 204 static const struct snd_kcontrol_new es8323_right_mixer_controls[] = { 205 SOC_DAPM_SINGLE("Right Playback Switch", ES8323_DACCONTROL20, 7, 1, 0), 206 SOC_DAPM_SINGLE("Right Bypass Switch", ES8323_DACCONTROL20, 6, 1, 0), 207 }; 208 209 static const struct snd_soc_dapm_widget es8323_dapm_widgets[] = { 210 SND_SOC_DAPM_INPUT("LINPUT1"), 211 SND_SOC_DAPM_INPUT("LINPUT2"), 212 SND_SOC_DAPM_INPUT("RINPUT1"), 213 SND_SOC_DAPM_INPUT("RINPUT2"), 214 215 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8323_ADCPOWER, 216 ES8323_ADCPOWER_PDNMICB_OFF, 1, NULL, 0), 217 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8323_ADCPOWER, 218 ES8323_ADCPOWER_PDNADCBIS_OFF, 1, NULL, 0), 219 220 SND_SOC_DAPM_SUPPLY("DAC STM", ES8323_CHIPPOWER, 221 ES8323_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), 222 SND_SOC_DAPM_SUPPLY("ADC STM", ES8323_CHIPPOWER, 223 ES8323_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), 224 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8323_CHIPPOWER, 225 ES8323_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), 226 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8323_CHIPPOWER, 227 ES8323_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), 228 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8323_CHIPPOWER, 229 ES8323_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), 230 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8323_CHIPPOWER, 231 ES8323_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), 232 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8323_CHIPPOWER, 233 ES8323_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), 234 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8323_CHIPPOWER, 235 ES8323_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), 236 237 /* Muxes */ 238 SND_SOC_DAPM_MUX("Left PGA Mux", ES8323_ADCPOWER, 239 ES8323_ADCPOWER_PDNAINL_OFF, 1, &es8323_left_dac_mux_controls), 240 SND_SOC_DAPM_MUX("Right PGA Mux", ES8323_ADCPOWER, 241 ES8323_ADCPOWER_PDNAINR_OFF, 1, &es8323_right_dac_mux_controls), 242 243 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, &es8323_diffmux_controls), 244 245 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, &es8323_mono_adc_mux_controls), 246 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, &es8323_mono_adc_mux_controls), 247 248 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, &es8323_left_line_controls), 249 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, &es8323_right_line_controls), 250 251 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 252 ES8323_ADCPOWER, ES8323_ADCPOWER_PDNADCR_OFF, 1), 253 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", 254 ES8323_ADCPOWER, ES8323_ADCPOWER_PDNADCL_OFF, 1), 255 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", 256 ES8323_DACPOWER, ES8323_DACPOWER_PDNDACR_OFF, 1), 257 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 258 ES8323_DACPOWER, ES8323_DACPOWER_PDNDACL_OFF, 1), 259 260 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, 261 &es8323_left_mixer_controls[0], 262 ARRAY_SIZE(es8323_left_mixer_controls)), 263 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, 264 &es8323_right_mixer_controls[0], 265 ARRAY_SIZE(es8323_right_mixer_controls)), 266 267 SND_SOC_DAPM_PGA("Right Out 2", ES8323_DACPOWER, ES8323_DACPOWER_ROUT2_OFF, 0, NULL, 0), 268 SND_SOC_DAPM_PGA("Left Out 2", ES8323_DACPOWER, ES8323_DACPOWER_LOUT2_OFF, 0, NULL, 0), 269 SND_SOC_DAPM_PGA("Right Out 1", ES8323_DACPOWER, ES8323_DACPOWER_ROUT1_OFF, 0, NULL, 0), 270 SND_SOC_DAPM_PGA("Left Out 1", ES8323_DACPOWER, ES8323_DACPOWER_LOUT1_OFF, 0, NULL, 0), 271 SND_SOC_DAPM_PGA("LAMP", ES8323_ADCCONTROL1, ES8323_ADCCONTROL1_MICAMPL_OFF, 0, NULL, 0), 272 SND_SOC_DAPM_PGA("RAMP", ES8323_ADCCONTROL1, ES8323_ADCCONTROL1_MICAMPR_OFF, 0, NULL, 0), 273 274 SND_SOC_DAPM_OUTPUT("LOUT1"), 275 SND_SOC_DAPM_OUTPUT("ROUT1"), 276 SND_SOC_DAPM_OUTPUT("LOUT2"), 277 SND_SOC_DAPM_OUTPUT("ROUT2"), 278 SND_SOC_DAPM_OUTPUT("VREF"), 279 }; 280 281 static const struct snd_soc_dapm_route es8323_dapm_routes[] = { 282 /*12.22*/ 283 {"Left PGA Mux", "Line 1L", "LINPUT1"}, 284 {"Left PGA Mux", "Line 2L", "LINPUT2"}, 285 {"Left PGA Mux", "DifferentialL", "Differential Mux"}, 286 287 {"Right PGA Mux", "Line 1R", "RINPUT1"}, 288 {"Right PGA Mux", "Line 2R", "RINPUT2"}, 289 {"Right PGA Mux", "DifferentialR", "Differential Mux"}, 290 291 {"Differential Mux", "Line 1", "LINPUT1"}, 292 {"Differential Mux", "Line 1", "RINPUT1"}, 293 {"Differential Mux", "Line 2", "LINPUT2"}, 294 {"Differential Mux", "Line 2", "RINPUT2"}, 295 296 {"Left ADC Mux", "Stereo", "Left PGA Mux"}, 297 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"}, 298 299 {"Right ADC Mux", "Stereo", "Right PGA Mux"}, 300 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"}, 301 302 {"Left ADC", NULL, "Left ADC Mux"}, 303 {"Right ADC", NULL, "Right ADC Mux"}, 304 305 { "Mic Bias", NULL, "Mic Bias Gen" }, 306 307 { "ADC DIG", NULL, "ADC STM" }, 308 { "ADC DIG", NULL, "ADC Vref" }, 309 { "ADC DIG", NULL, "ADC DLL" }, 310 311 { "Left ADC", NULL, "ADC DIG" }, 312 { "Right ADC", NULL, "ADC DIG" }, 313 314 { "DAC DIG", NULL, "DAC STM" }, 315 { "DAC DIG", NULL, "DAC Vref" }, 316 { "DAC DIG", NULL, "DAC DLL" }, 317 318 { "Left DAC", NULL, "DAC DIG" }, 319 { "Right DAC", NULL, "DAC DIG" }, 320 321 {"Left Line Mux", "Line 1L", "LINPUT1"}, 322 {"Left Line Mux", "Line 2L", "LINPUT2"}, 323 {"Left Line Mux", "MicL", "Left PGA Mux"}, 324 325 {"Right Line Mux", "Line 1R", "RINPUT1"}, 326 {"Right Line Mux", "Line 2R", "RINPUT2"}, 327 {"Right Line Mux", "MicR", "Right PGA Mux"}, 328 329 {"Left Mixer", "Left Playback Switch", "Left DAC"}, 330 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"}, 331 332 {"Right Mixer", "Right Playback Switch", "Right DAC"}, 333 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"}, 334 335 {"Left Out 1", NULL, "Left Mixer"}, 336 {"LOUT1", NULL, "Left Out 1"}, 337 {"Right Out 1", NULL, "Right Mixer"}, 338 {"ROUT1", NULL, "Right Out 1"}, 339 340 {"Left Out 2", NULL, "Left Mixer"}, 341 {"LOUT2", NULL, "Left Out 2"}, 342 {"Right Out 2", NULL, "Right Mixer"}, 343 {"ROUT2", NULL, "Right Out 2"}, 344 }; 345 346 struct coeff_div { 347 u32 mclk; 348 u32 rate; 349 u16 fs; 350 u8 sr:4; 351 u8 usb:1; 352 }; 353 354 /* codec hifi mclk clock divider coefficients */ 355 static const struct coeff_div es8323_coeff_div[] = { 356 /* 8k */ 357 {12288000, 8000, 1536, 0xa, 0x0}, 358 {11289600, 8000, 1408, 0x9, 0x0}, 359 {18432000, 8000, 2304, 0xc, 0x0}, 360 {16934400, 8000, 2112, 0xb, 0x0}, 361 {12000000, 8000, 1500, 0xb, 0x1}, 362 363 /* 11.025k */ 364 {11289600, 11025, 1024, 0x7, 0x0}, 365 {16934400, 11025, 1536, 0xa, 0x0}, 366 {12000000, 11025, 1088, 0x9, 0x1}, 367 368 /* 16k */ 369 {12288000, 16000, 768, 0x6, 0x0}, 370 {18432000, 16000, 1152, 0x8, 0x0}, 371 {12000000, 16000, 750, 0x7, 0x1}, 372 373 /* 22.05k */ 374 {11289600, 22050, 512, 0x4, 0x0}, 375 {16934400, 22050, 768, 0x6, 0x0}, 376 {12000000, 22050, 544, 0x6, 0x1}, 377 378 /* 32k */ 379 {12288000, 32000, 384, 0x3, 0x0}, 380 {18432000, 32000, 576, 0x5, 0x0}, 381 {12000000, 32000, 375, 0x4, 0x1}, 382 383 /* 44.1k */ 384 {11289600, 44100, 256, 0x2, 0x0}, 385 {16934400, 44100, 384, 0x3, 0x0}, 386 {12000000, 44100, 272, 0x3, 0x1}, 387 388 /* 48k */ 389 {12288000, 48000, 256, 0x2, 0x0}, 390 {18432000, 48000, 384, 0x3, 0x0}, 391 {12000000, 48000, 250, 0x2, 0x1}, 392 393 /* 88.2k */ 394 {11289600, 88200, 128, 0x0, 0x0}, 395 {16934400, 88200, 192, 0x1, 0x0}, 396 {12000000, 88200, 136, 0x1, 0x1}, 397 398 /* 96k */ 399 {12288000, 96000, 128, 0x0, 0x0}, 400 {18432000, 96000, 192, 0x1, 0x0}, 401 {12000000, 96000, 125, 0x0, 0x1}, 402 }; 403 404 static unsigned int rates_12288[] = { 405 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000, 406 }; 407 408 static struct snd_pcm_hw_constraint_list constraints_12288 = { 409 .count = ARRAY_SIZE(rates_12288), 410 .list = rates_12288, 411 }; 412 413 static unsigned int rates_112896[] = { 414 8000, 11025, 22050, 44100, 415 }; 416 417 static struct snd_pcm_hw_constraint_list constraints_112896 = { 418 .count = ARRAY_SIZE(rates_112896), 419 .list = rates_112896, 420 }; 421 422 static unsigned int rates_12[] = { 423 8000, 11025, 12000, 16000, 22050, 24000, 424 32000, 44100, 48000, 48000, 88235, 96000, 425 }; 426 427 static struct snd_pcm_hw_constraint_list constraints_12 = { 428 .count = ARRAY_SIZE(rates_12), 429 .list = rates_12, 430 }; 431 432 static inline int get_coeff(int mclk, int rate) 433 { 434 int i; 435 436 for (i = 0; i < ARRAY_SIZE(es8323_coeff_div); i++) { 437 if (es8323_coeff_div[i].rate == rate && 438 es8323_coeff_div[i].mclk == mclk) 439 return i; 440 } 441 442 return -EINVAL; 443 } 444 445 static int es8323_set_dai_sysclk(struct snd_soc_dai *codec_dai, 446 int clk_id, unsigned int freq, int dir) 447 { 448 struct snd_soc_component *component = codec_dai->component; 449 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 450 451 switch (freq) { 452 case 11289600: 453 case 18432000: 454 case 22579200: 455 case 36864000: 456 es8323->sysclk_constraints = &constraints_112896; 457 break; 458 case 12288000: 459 case 16934400: 460 case 24576000: 461 case 33868800: 462 es8323->sysclk_constraints = &constraints_12288; 463 break; 464 case 12000000: 465 case 24000000: 466 es8323->sysclk_constraints = &constraints_12; 467 break; 468 default: 469 return -EINVAL; 470 } 471 472 es8323->sysclk = freq; 473 return 0; 474 } 475 476 static int es8323_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 477 { 478 struct snd_soc_component *component = codec_dai->component; 479 u8 format_mode, inv_mode; 480 481 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 482 case SND_SOC_DAIFMT_BC_FP: 483 /* Master serial port mode */ 484 snd_soc_component_update_bits(component, ES8323_MASTERMODE, 485 ES8323_MASTERMODE_MSC, ES8323_MASTERMODE_MSC); 486 break; 487 case SND_SOC_DAIFMT_BC_FC: 488 /* Slave serial port mode */ 489 snd_soc_component_update_bits(component, ES8323_MASTERMODE, 490 ES8323_MASTERMODE_MSC, 0); 491 break; 492 default: 493 return -EINVAL; 494 } 495 496 /* interface format */ 497 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 498 case SND_SOC_DAIFMT_I2S: 499 format_mode = ES8323_FMT_I2S; 500 break; 501 case SND_SOC_DAIFMT_LEFT_J: 502 format_mode = ES8323_FMT_LEFT_J; 503 break; 504 case SND_SOC_DAIFMT_RIGHT_J: 505 format_mode = ES8323_FMT_RIGHT_J; 506 break; 507 case SND_SOC_DAIFMT_DSP_A: 508 case SND_SOC_DAIFMT_DSP_B: 509 format_mode = ES8323_FMT_DSP; 510 break; 511 default: 512 return -EINVAL; 513 } 514 515 snd_soc_component_write_field(component, ES8323_ADCCONTROL4, 516 ES8323_ADCCONTROL4_ADCFORMAT, format_mode); 517 snd_soc_component_write_field(component, ES8323_DACCONTROL1, 518 ES8323_DACCONTROL1_DACFORMAT, format_mode); 519 520 /* clock inversion */ 521 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 522 case SND_SOC_DAIFMT_NB_NF: 523 case SND_SOC_DAIFMT_IB_NF: 524 inv_mode = 0; 525 break; 526 case SND_SOC_DAIFMT_IB_IF: 527 case SND_SOC_DAIFMT_NB_IF: 528 inv_mode = 1; 529 break; 530 default: 531 return -EINVAL; 532 } 533 534 snd_soc_component_update_bits(component, ES8323_MASTERMODE, 535 ES8323_MASTERMODE_BCLKINV, inv_mode); 536 snd_soc_component_update_bits(component, ES8323_ADCCONTROL4, 537 ES8323_ADCCONTROL4_ADCLRP, inv_mode); 538 snd_soc_component_update_bits(component, ES8323_DACCONTROL1, 539 ES8323_DACCONTROL1_DACLRP, inv_mode); 540 541 return 0; 542 } 543 544 static int es8323_pcm_startup(struct snd_pcm_substream *substream, 545 struct snd_soc_dai *dai) 546 { 547 struct snd_soc_component *component = dai->component; 548 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 549 550 if (es8323->sysclk) { 551 snd_pcm_hw_constraint_list(substream->runtime, 0, 552 SNDRV_PCM_HW_PARAM_RATE, 553 es8323->sysclk_constraints); 554 } 555 556 return 0; 557 } 558 559 static int es8323_pcm_hw_params(struct snd_pcm_substream *substream, 560 struct snd_pcm_hw_params *params, 561 struct snd_soc_dai *dai) 562 { 563 struct snd_soc_component *component = dai->component; 564 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 565 u8 wl_mode, fs; 566 int coeff; 567 568 coeff = get_coeff(es8323->sysclk, params_rate(params)); 569 if (coeff < 0) { 570 coeff = get_coeff(es8323->sysclk / 2, params_rate(params)); 571 if (coeff < 0) { 572 dev_err(component->dev, 573 "Unable to configure sample rate %dHz with %dHz MCLK\n", 574 params_rate(params), es8323->sysclk); 575 return coeff; 576 } 577 578 snd_soc_component_update_bits(component, ES8323_MASTERMODE, 579 ES8323_MASTERMODE_MCLKDIV2, 580 ES8323_MASTERMODE_MCLKDIV2); 581 } 582 583 fs = FIELD_PREP(ES8323_DACCONTROL2_DACFSMODE, es8323_coeff_div[coeff].usb) 584 | FIELD_PREP(ES8323_DACCONTROL2_DACFSRATIO, es8323_coeff_div[coeff].sr); 585 586 snd_soc_component_write_field(component, ES8323_ADCCONTROL5, 587 ES8323_ADCCONTROL5_ADCFS_MASK, fs); 588 589 snd_soc_component_write_field(component, ES8323_DACCONTROL2, 590 ES8323_DACCONTROL2_DACFS_MASK, fs); 591 592 /* serial audio data word length */ 593 switch (params_format(params)) { 594 case SNDRV_PCM_FORMAT_S16_LE: 595 wl_mode = ES8323_S16_LE; 596 break; 597 case SNDRV_PCM_FORMAT_S20_3LE: 598 wl_mode = ES8323_S20_LE; 599 break; 600 case SNDRV_PCM_FORMAT_S24_LE: 601 wl_mode = ES8323_S24_LE; 602 break; 603 case SNDRV_PCM_FORMAT_S32_LE: 604 wl_mode = ES8323_S32_LE; 605 break; 606 default: 607 return -EINVAL; 608 } 609 610 snd_soc_component_write_field(component, ES8323_ADCCONTROL4, 611 ES8323_ADCCONTROL4_ADCWL, wl_mode); 612 613 snd_soc_component_write_field(component, ES8323_DACCONTROL1, 614 ES8323_DACCONTROL1_DACWL, wl_mode); 615 616 return 0; 617 } 618 619 static int es8323_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 620 { 621 return snd_soc_component_update_bits(dai->component, ES8323_DACCONTROL3, 622 ES8323_DACCONTROL3_DACMUTE, 623 mute ? ES8323_DACCONTROL3_DACMUTE : 0); 624 } 625 626 static const struct snd_soc_dai_ops es8323_ops = { 627 .startup = es8323_pcm_startup, 628 .hw_params = es8323_pcm_hw_params, 629 .set_fmt = es8323_set_dai_fmt, 630 .set_sysclk = es8323_set_dai_sysclk, 631 .mute_stream = es8323_mute_stream, 632 }; 633 634 #define ES8323_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 635 SNDRV_PCM_FMTBIT_S24_LE) 636 637 static struct snd_soc_dai_driver es8323_dai = { 638 .name = "ES8323 HiFi", 639 .playback = { 640 .stream_name = "Playback", 641 .channels_min = 1, 642 .channels_max = 2, 643 .rates = SNDRV_PCM_RATE_8000_96000, 644 .formats = ES8323_FORMATS, 645 }, 646 .capture = { 647 .stream_name = "Capture", 648 .channels_min = 1, 649 .channels_max = 2, 650 .rates = SNDRV_PCM_RATE_8000_96000, 651 .formats = ES8323_FORMATS, 652 }, 653 .ops = &es8323_ops, 654 .symmetric_rate = 1, 655 }; 656 657 static int es8323_probe(struct snd_soc_component *component) 658 { 659 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 660 int ret; 661 662 es8323->mclk = devm_clk_get_optional(component->dev, "mclk"); 663 if (IS_ERR(es8323->mclk)) { 664 dev_err(component->dev, "unable to get mclk\n"); 665 return PTR_ERR(es8323->mclk); 666 } 667 668 if (!es8323->mclk) 669 dev_warn(component->dev, "assuming static mclk\n"); 670 671 ret = clk_prepare_enable(es8323->mclk); 672 if (ret) { 673 dev_err(component->dev, "unable to enable mclk\n"); 674 return ret; 675 } 676 677 snd_soc_component_write(component, ES8323_CONTROL2, 0x60); 678 snd_soc_component_write(component, ES8323_DACCONTROL21, 0x80); 679 680 return 0; 681 } 682 683 static int es8323_set_bias_level(struct snd_soc_component *component, 684 enum snd_soc_bias_level level) 685 { 686 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 687 int ret; 688 689 switch (level) { 690 case SND_SOC_BIAS_ON: 691 break; 692 case SND_SOC_BIAS_PREPARE: 693 ret = clk_prepare_enable(es8323->mclk); 694 if (ret) 695 return ret; 696 697 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0x00); 698 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0x00); 699 snd_soc_component_update_bits(component, ES8323_ADCPOWER, 700 ES8323_ADCPOWER_PDNADCBIS, 0); 701 break; 702 case SND_SOC_BIAS_STANDBY: 703 break; 704 case SND_SOC_BIAS_OFF: 705 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0xff); 706 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0xff); 707 clk_disable_unprepare(es8323->mclk); 708 break; 709 } 710 711 return 0; 712 } 713 714 static void es8323_remove(struct snd_soc_component *component) 715 { 716 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 717 718 clk_disable_unprepare(es8323->mclk); 719 es8323_set_bias_level(component, SND_SOC_BIAS_OFF); 720 } 721 722 static int es8323_suspend(struct snd_soc_component *component) 723 { 724 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 725 726 regcache_cache_only(es8323->regmap, true); 727 regcache_mark_dirty(es8323->regmap); 728 729 return 0; 730 } 731 732 static int es8323_resume(struct snd_soc_component *component) 733 { 734 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component); 735 736 regcache_cache_only(es8323->regmap, false); 737 regcache_sync(es8323->regmap); 738 739 return 0; 740 } 741 742 static const struct snd_soc_component_driver soc_component_dev_es8323 = { 743 .probe = es8323_probe, 744 .remove = es8323_remove, 745 .suspend = es8323_suspend, 746 .resume = es8323_resume, 747 .set_bias_level = es8323_set_bias_level, 748 .controls = es8323_snd_controls, 749 .num_controls = ARRAY_SIZE(es8323_snd_controls), 750 .dapm_widgets = es8323_dapm_widgets, 751 .num_dapm_widgets = ARRAY_SIZE(es8323_dapm_widgets), 752 .dapm_routes = es8323_dapm_routes, 753 .num_dapm_routes = ARRAY_SIZE(es8323_dapm_routes), 754 .use_pmdown_time = 1, 755 .endianness = 1, 756 }; 757 758 static const struct regmap_config es8323_regmap = { 759 .reg_bits = 8, 760 .val_bits = 8, 761 .use_single_read = true, 762 .use_single_write = true, 763 .max_register = 0x53, 764 .reg_defaults = es8323_reg_defaults, 765 .num_reg_defaults = ARRAY_SIZE(es8323_reg_defaults), 766 .cache_type = REGCACHE_MAPLE, 767 }; 768 769 static int es8323_i2c_probe(struct i2c_client *i2c_client) 770 { 771 struct es8323_priv *es8323; 772 struct device *dev = &i2c_client->dev; 773 774 es8323 = devm_kzalloc(dev, sizeof(*es8323), GFP_KERNEL); 775 if (!es8323) 776 return -ENOMEM; 777 778 i2c_set_clientdata(i2c_client, es8323); 779 780 es8323->regmap = devm_regmap_init_i2c(i2c_client, &es8323_regmap); 781 if (IS_ERR(es8323->regmap)) 782 return PTR_ERR(es8323->regmap); 783 784 return devm_snd_soc_register_component(dev, 785 &soc_component_dev_es8323, 786 &es8323_dai, 1); 787 } 788 789 static const struct i2c_device_id es8323_i2c_id[] = { 790 { "es8323" }, 791 { } 792 }; 793 MODULE_DEVICE_TABLE(i2c, es8323_i2c_id); 794 795 static const struct acpi_device_id es8323_acpi_match[] = { 796 { "ESSX8323", 0 }, 797 { } 798 }; 799 MODULE_DEVICE_TABLE(acpi, es8323_acpi_match); 800 801 static const struct of_device_id es8323_of_match[] = { 802 { .compatible = "everest,es8323" }, 803 { } 804 }; 805 MODULE_DEVICE_TABLE(of, es8323_of_match); 806 807 static struct i2c_driver es8323_i2c_driver = { 808 .driver = { 809 .name = "ES8323", 810 .acpi_match_table = es8323_acpi_match, 811 .of_match_table = es8323_of_match, 812 }, 813 .probe = es8323_i2c_probe, 814 .id_table = es8323_i2c_id, 815 }; 816 module_i2c_driver(es8323_i2c_driver); 817 818 MODULE_DESCRIPTION("Everest Semi ES8323 ALSA SoC Codec Driver"); 819 MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); 820 MODULE_AUTHOR("Binbin Zhou <zhoubinbin@loongson.cn>"); 821 MODULE_LICENSE("GPL"); 822