1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * es8311.c -- es8311 ALSA SoC audio driver 4 * 5 * Copyright (C) 2024 Matteo Martelli <matteomartelli3@gmail.com> 6 * 7 * Author: Matteo Martelli <matteomartelli3@gmail.com> 8 */ 9 10 #ifndef _ES8311_H 11 #define _ES8311_H 12 13 #include <linux/bitops.h> 14 15 #define ES8311_RESET 0x00 16 #define ES8311_RESET_CSM_ON BIT(7) 17 #define ES8311_RESET_MSC BIT(6) 18 #define ES8311_RESET_RST_MASK GENMASK(4, 0) 19 20 /* Clock Manager Registers */ 21 #define ES8311_CLKMGR1 0x01 22 #define ES8311_CLKMGR1_MCLK_SEL BIT(7) 23 #define ES8311_CLKMGR1_MCLK_ON BIT(5) 24 #define ES8311_CLKMGR1_BCLK_ON BIT(4) 25 #define ES8311_CLKMGR1_CLKADC_ON_SHIFT 3 26 #define ES8311_CLKMGR1_CLKDAC_ON_SHIFT 2 27 #define ES8311_CLKMGR1_ANACLKADC_ON_SHIFT 1 28 #define ES8311_CLKMGR1_ANACLKDAC_ON_SHIFT 0 29 #define ES8311_CLKMGR2 0x02 30 #define ES8311_CLKMGR2_DIV_PRE_MASK GENMASK(7, 5) 31 #define ES8311_CLKMGR2_DIV_PRE_SHIFT 5 32 #define ES8311_CLKMGR2_DIV_PRE_MAX 0x07 33 #define ES8311_CLKMGR2_MULT_PRE_MASK GENMASK(4, 3) 34 #define ES8311_CLKMGR2_MULT_PRE_SHIFT 3 35 #define ES8311_CLKMGR3 0x03 36 #define ES8311_CLKMGR4 0x04 37 #define ES8311_CLKMGR5 0x05 38 #define ES8311_CLKMGR5_ADC_DIV_MASK GENMASK(7, 4) 39 #define ES8311_CLKMGR5_ADC_DIV_SHIFT 4 40 #define ES8311_CLKMGR5_DAC_DIV_MASK GENMASK(3, 0) 41 #define ES8311_CLKMGR5_DAC_DIV_SHIFT 0 42 #define ES8311_CLKMGR6 0x06 43 #define ES8311_CLKMGR6_BCLK_INV BIT(5) 44 #define ES8311_CLKMGR6_DIV_BCLK_MASK GENMASK(4, 0) 45 #define ES8311_CLKMGR7 0x07 46 #define ES8311_CLKMGR7_LRCLK_DIV_H_MASK GENMASK(3, 0) 47 #define ES8311_CLKMGR8 0x08 48 #define ES8311_CLKMGR_LRCLK_DIV_MAX 0x0FFF 49 50 /* SDP Mode Registers */ 51 #define ES8311_SDP_IN 0x09 52 #define ES8311_SDP_IN_SEL_SHIFT 7 53 #define ES8311_SDP_OUT 0x0A 54 /* Following values are the same for both SPD_IN and SDP_OUT */ 55 #define ES8311_SDP_MUTE_SHIFT 6 56 #define ES8311_SDP_LRP BIT(5) 57 #define ES8311_SDP_WL_MASK GENMASK(4, 2) 58 #define ES8311_SDP_WL_SHIFT 2 59 #define ES8311_SDP_WL_24 0x00 60 #define ES8311_SDP_WL_20 0x01 61 #define ES8311_SDP_WL_18 0x02 62 #define ES8311_SDP_WL_16 0x03 63 #define ES8311_SDP_WL_32 0x04 64 #define ES8311_SDP_FMT_MASK GENMASK(1, 0) 65 #define ES8311_SDP_FMT_I2S 0x00 66 #define ES8311_SDP_FMT_LEFT_J 0x01 67 #define ES8311_SDP_FMT_DSP 0x03 68 69 /* System registers */ 70 #define ES8311_SYS1 0x0B 71 #define ES8311_SYS2 0x0C 72 #define ES8311_SYS3 0x0D 73 #define ES8311_SYS3_PDN_ANA_SHIFT 7 74 #define ES8311_SYS3_PDN_IBIASGEN_SHIFT 6 75 #define ES8311_SYS3_PDN_ADCBIASGEN_SHIFT 5 76 #define ES8311_SYS3_PDN_ADCVREFGEN_SHIFT 4 77 #define ES8311_SYS3_PDN_DACVREFGEN_SHIFT 3 78 #define ES8311_SYS3_PDN_VREF_SHIFT 2 79 #define ES8311_SYS3_PDN_VMIDSEL_MASK GENMASK(1, 0) 80 #define ES8311_SYS3_PDN_VMIDSEL_POWER_DOWN 0 81 #define ES8311_SYS3_PDN_VMIDSEL_STARTUP_NORMAL_SPEED 1 82 #define ES8311_SYS3_PDN_VMIDSEL_NORMAL_OPERATION 2 83 #define ES8311_SYS3_PDN_VMIDSEL_STARTUP_FAST_SPEED 3 84 #define ES8311_SYS4 0x0E 85 #define ES8311_SYS4_PDN_PGA_SHIFT 6 86 #define ES8311_SYS4_PDN_MOD_SHIFT 5 87 #define ES8311_SYS5 0x0F 88 #define ES8311_SYS6 0x10 89 #define ES8311_SYS7 0x11 90 #define ES8311_SYS8 0x12 91 #define ES8311_SYS8_PDN_DAC_SHIFT 1 92 #define ES8311_SYS9 0x13 93 #define ES8311_SYS9_HPSW_SHIFT 4 94 #define ES8311_SYS10 0x14 95 #define ES8311_SYS10_DMIC_ON_SHIFT 6 96 #define ES8311_SYS10_LINESEL_SHIFT 4 97 #define ES8311_SYS10_PGAGAIN_SHIFT 0 98 #define ES8311_SYS10_PGAGAIN_MAX 0x0A 99 100 /* ADC Registers*/ 101 #define ES8311_ADC1 0x15 102 #define ES8311_ADC1_RAMPRATE_SHIFT 4 103 #define ES8311_ADC2 0x16 104 #define ES8311_ADC2_INV_SHIFT 4 105 #define ES8311_ADC2_SCALE_SHIFT 0 106 #define ES8311_ADC2_SCALE_MAX 0x07 107 #define ES8311_ADC3 0x17 108 #define ES8311_ADC3_VOLUME_SHIFT 0 109 #define ES8311_ADC3_VOLUME_MAX 0xFF 110 #define ES8311_ADC4 0x18 111 #define ES8311_ADC4_ALC_EN_SHIFT 7 112 #define ES8311_ADC4_AUTOMUTE_EN_SHIFT 6 113 #define ES8311_ADC4_ALC_WINSIZE_SHIFT 0 114 #define ES8311_ADC5 0x19 115 #define ES8311_ADC5_ALC_MAXLEVEL_SHIFT 4 116 #define ES8311_ADC5_ALC_MAXLEVEL_MAX 0x0F 117 #define ES8311_ADC5_ALC_MINLEVEL_SHIFT 0 118 #define ES8311_ADC5_ALC_MINLEVEL_MAX 0x0F 119 #define ES8311_ADC6 0x1A 120 #define ES8311_ADC6_AUTOMUTE_WS_SHIFT 4 121 #define ES8311_ADC6_AUTOMUTE_NG_SHIFT 0 122 #define ES8311_ADC6_AUTOMUTE_NG_MAX 0x0F 123 124 #define ES8311_ADC7 0x1B 125 #define ES8311_ADC7_AUTOMUTE_VOL_SHIFT 5 126 #define ES8311_ADC7_AUTOMUTE_VOL_MAX 0x07 127 #define ES8311_ADC8 0x1C 128 #define ES8311_ADC8_EQBYPASS_SHIFT 6 129 #define ES8311_ADC8_HPF_SHIFT 5 130 131 /* DAC Registers */ 132 #define ES8311_DAC1 0x31 133 #define ES8311_DAC1_DAC_DSMMUTE BIT(6) 134 #define ES8311_DAC1_DAC_DEMMUTE BIT(5) 135 #define ES8311_DAC2 0x32 136 #define ES8311_DAC2_VOLUME_MAX 0xFF 137 #define ES8311_DAC3 0x33 138 #define ES8311_DAC4 0x34 139 #define ES8311_DAC4_DRC_EN_SHIFT 7 140 #define ES8311_DAC4_DRC_WINSIZE_SHIFT 0 141 #define ES8311_DAC5 0x35 142 #define ES8311_DAC5_DRC_MAXLEVEL_SHIFT 4 143 #define ES8311_DAC5_DRC_MAXLEVEL_MAX 0x0F 144 #define ES8311_DAC5_DRC_MINLEVEL_SHIFT 0 145 #define ES8311_DAC5_DRC_MINLEVEL_MAX 0x0F 146 #define ES8311_DAC6 0x37 147 #define ES8311_DAC6_RAMPRATE_SHIFT 4 148 #define ES8311_DAC6_EQBYPASS_SHIFT 3 149 150 /* GPIO Registers */ 151 #define ES8311_GPIO 0x44 152 #define ES8311_GPIO_ADC2DAC_SEL_SHIFT 7 153 #define ES8311_GPIO_ADCDAT_SEL_SHIFT 4 154 155 /* Chip Info Registers */ 156 #define ES8311_CHIPID1 0xFD /* 0x83 */ 157 #define ES8311_CHIPID2 0xFE /* 0x11 */ 158 #define ES8311_CHIPVER 0xFF 159 160 #define ES8311_REG_MAX 0xFF 161 162 #endif 163