1 /* 2 * da732x.c --- Dialog DA732X ALSA SoC Audio Driver 3 * 4 * Copyright (C) 2012 Dialog Semiconductor GmbH 5 * 6 * Author: Michal Hajduk <Michal.Hajduk@diasemi.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/i2c.h> 19 #include <linux/regmap.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/sysfs.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/initval.h> 29 #include <sound/tlv.h> 30 #include <asm/div64.h> 31 32 #include "da732x.h" 33 #include "da732x_reg.h" 34 35 36 struct da732x_priv { 37 struct regmap *regmap; 38 struct snd_soc_codec *codec; 39 40 unsigned int sysclk; 41 bool pll_en; 42 }; 43 44 /* 45 * da732x register cache - default settings 46 */ 47 static struct reg_default da732x_reg_cache[] = { 48 { DA732X_REG_REF1 , 0x02 }, 49 { DA732X_REG_BIAS_EN , 0x80 }, 50 { DA732X_REG_BIAS1 , 0x00 }, 51 { DA732X_REG_BIAS2 , 0x00 }, 52 { DA732X_REG_BIAS3 , 0x00 }, 53 { DA732X_REG_BIAS4 , 0x00 }, 54 { DA732X_REG_MICBIAS2 , 0x00 }, 55 { DA732X_REG_MICBIAS1 , 0x00 }, 56 { DA732X_REG_MICDET , 0x00 }, 57 { DA732X_REG_MIC1_PRE , 0x01 }, 58 { DA732X_REG_MIC1 , 0x40 }, 59 { DA732X_REG_MIC2_PRE , 0x01 }, 60 { DA732X_REG_MIC2 , 0x40 }, 61 { DA732X_REG_AUX1L , 0x75 }, 62 { DA732X_REG_AUX1R , 0x75 }, 63 { DA732X_REG_MIC3_PRE , 0x01 }, 64 { DA732X_REG_MIC3 , 0x40 }, 65 { DA732X_REG_INP_PINBIAS , 0x00 }, 66 { DA732X_REG_INP_ZC_EN , 0x00 }, 67 { DA732X_REG_INP_MUX , 0x50 }, 68 { DA732X_REG_HP_DET , 0x00 }, 69 { DA732X_REG_HPL_DAC_OFFSET , 0x00 }, 70 { DA732X_REG_HPL_DAC_OFF_CNTL , 0x00 }, 71 { DA732X_REG_HPL_OUT_OFFSET , 0x00 }, 72 { DA732X_REG_HPL , 0x40 }, 73 { DA732X_REG_HPL_VOL , 0x0F }, 74 { DA732X_REG_HPR_DAC_OFFSET , 0x00 }, 75 { DA732X_REG_HPR_DAC_OFF_CNTL , 0x00 }, 76 { DA732X_REG_HPR_OUT_OFFSET , 0x00 }, 77 { DA732X_REG_HPR , 0x40 }, 78 { DA732X_REG_HPR_VOL , 0x0F }, 79 { DA732X_REG_LIN2 , 0x4F }, 80 { DA732X_REG_LIN3 , 0x4F }, 81 { DA732X_REG_LIN4 , 0x4F }, 82 { DA732X_REG_OUT_ZC_EN , 0x00 }, 83 { DA732X_REG_HP_LIN1_GNDSEL , 0x00 }, 84 { DA732X_REG_CP_HP1 , 0x0C }, 85 { DA732X_REG_CP_HP2 , 0x03 }, 86 { DA732X_REG_CP_CTRL1 , 0x00 }, 87 { DA732X_REG_CP_CTRL2 , 0x99 }, 88 { DA732X_REG_CP_CTRL3 , 0x25 }, 89 { DA732X_REG_CP_LEVEL_MASK , 0x3F }, 90 { DA732X_REG_CP_DET , 0x00 }, 91 { DA732X_REG_CP_STATUS , 0x00 }, 92 { DA732X_REG_CP_THRESH1 , 0x00 }, 93 { DA732X_REG_CP_THRESH2 , 0x00 }, 94 { DA732X_REG_CP_THRESH3 , 0x00 }, 95 { DA732X_REG_CP_THRESH4 , 0x00 }, 96 { DA732X_REG_CP_THRESH5 , 0x00 }, 97 { DA732X_REG_CP_THRESH6 , 0x00 }, 98 { DA732X_REG_CP_THRESH7 , 0x00 }, 99 { DA732X_REG_CP_THRESH8 , 0x00 }, 100 { DA732X_REG_PLL_DIV_LO , 0x00 }, 101 { DA732X_REG_PLL_DIV_MID , 0x00 }, 102 { DA732X_REG_PLL_DIV_HI , 0x00 }, 103 { DA732X_REG_PLL_CTRL , 0x02 }, 104 { DA732X_REG_CLK_CTRL , 0xaa }, 105 { DA732X_REG_CLK_DSP , 0x07 }, 106 { DA732X_REG_CLK_EN1 , 0x00 }, 107 { DA732X_REG_CLK_EN2 , 0x00 }, 108 { DA732X_REG_CLK_EN3 , 0x00 }, 109 { DA732X_REG_CLK_EN4 , 0x00 }, 110 { DA732X_REG_CLK_EN5 , 0x00 }, 111 { DA732X_REG_AIF_MCLK , 0x00 }, 112 { DA732X_REG_AIFA1 , 0x02 }, 113 { DA732X_REG_AIFA2 , 0x00 }, 114 { DA732X_REG_AIFA3 , 0x08 }, 115 { DA732X_REG_AIFB1 , 0x02 }, 116 { DA732X_REG_AIFB2 , 0x00 }, 117 { DA732X_REG_AIFB3 , 0x08 }, 118 { DA732X_REG_PC_CTRL , 0xC0 }, 119 { DA732X_REG_DATA_ROUTE , 0x00 }, 120 { DA732X_REG_DSP_CTRL , 0x00 }, 121 { DA732X_REG_CIF_CTRL2 , 0x00 }, 122 { DA732X_REG_HANDSHAKE , 0x00 }, 123 { DA732X_REG_SPARE1_OUT , 0x00 }, 124 { DA732X_REG_SPARE2_OUT , 0x00 }, 125 { DA732X_REG_SPARE1_IN , 0x00 }, 126 { DA732X_REG_ADC1_PD , 0x00 }, 127 { DA732X_REG_ADC1_HPF , 0x00 }, 128 { DA732X_REG_ADC1_SEL , 0x00 }, 129 { DA732X_REG_ADC1_EQ12 , 0x00 }, 130 { DA732X_REG_ADC1_EQ34 , 0x00 }, 131 { DA732X_REG_ADC1_EQ5 , 0x00 }, 132 { DA732X_REG_ADC2_PD , 0x00 }, 133 { DA732X_REG_ADC2_HPF , 0x00 }, 134 { DA732X_REG_ADC2_SEL , 0x00 }, 135 { DA732X_REG_ADC2_EQ12 , 0x00 }, 136 { DA732X_REG_ADC2_EQ34 , 0x00 }, 137 { DA732X_REG_ADC2_EQ5 , 0x00 }, 138 { DA732X_REG_DAC1_HPF , 0x00 }, 139 { DA732X_REG_DAC1_L_VOL , 0x00 }, 140 { DA732X_REG_DAC1_R_VOL , 0x00 }, 141 { DA732X_REG_DAC1_SEL , 0x00 }, 142 { DA732X_REG_DAC1_SOFTMUTE , 0x00 }, 143 { DA732X_REG_DAC1_EQ12 , 0x00 }, 144 { DA732X_REG_DAC1_EQ34 , 0x00 }, 145 { DA732X_REG_DAC1_EQ5 , 0x00 }, 146 { DA732X_REG_DAC2_HPF , 0x00 }, 147 { DA732X_REG_DAC2_L_VOL , 0x00 }, 148 { DA732X_REG_DAC2_R_VOL , 0x00 }, 149 { DA732X_REG_DAC2_SEL , 0x00 }, 150 { DA732X_REG_DAC2_SOFTMUTE , 0x00 }, 151 { DA732X_REG_DAC2_EQ12 , 0x00 }, 152 { DA732X_REG_DAC2_EQ34 , 0x00 }, 153 { DA732X_REG_DAC2_EQ5 , 0x00 }, 154 { DA732X_REG_DAC3_HPF , 0x00 }, 155 { DA732X_REG_DAC3_VOL , 0x00 }, 156 { DA732X_REG_DAC3_SEL , 0x00 }, 157 { DA732X_REG_DAC3_SOFTMUTE , 0x00 }, 158 { DA732X_REG_DAC3_EQ12 , 0x00 }, 159 { DA732X_REG_DAC3_EQ34 , 0x00 }, 160 { DA732X_REG_DAC3_EQ5 , 0x00 }, 161 { DA732X_REG_BIQ_BYP , 0x00 }, 162 { DA732X_REG_DMA_CMD , 0x00 }, 163 { DA732X_REG_DMA_ADDR0 , 0x00 }, 164 { DA732X_REG_DMA_ADDR1 , 0x00 }, 165 { DA732X_REG_DMA_DATA0 , 0x00 }, 166 { DA732X_REG_DMA_DATA1 , 0x00 }, 167 { DA732X_REG_DMA_DATA2 , 0x00 }, 168 { DA732X_REG_DMA_DATA3 , 0x00 }, 169 { DA732X_REG_UNLOCK , 0x00 }, 170 }; 171 172 static inline int da732x_get_input_div(struct snd_soc_codec *codec, int sysclk) 173 { 174 int val; 175 int ret; 176 177 if (sysclk < DA732X_MCLK_10MHZ) { 178 val = DA732X_MCLK_RET_0_10MHZ; 179 ret = DA732X_MCLK_VAL_0_10MHZ; 180 } else if ((sysclk >= DA732X_MCLK_10MHZ) && 181 (sysclk < DA732X_MCLK_20MHZ)) { 182 val = DA732X_MCLK_RET_10_20MHZ; 183 ret = DA732X_MCLK_VAL_10_20MHZ; 184 } else if ((sysclk >= DA732X_MCLK_20MHZ) && 185 (sysclk < DA732X_MCLK_40MHZ)) { 186 val = DA732X_MCLK_RET_20_40MHZ; 187 ret = DA732X_MCLK_VAL_20_40MHZ; 188 } else if ((sysclk >= DA732X_MCLK_40MHZ) && 189 (sysclk <= DA732X_MCLK_54MHZ)) { 190 val = DA732X_MCLK_RET_40_54MHZ; 191 ret = DA732X_MCLK_VAL_40_54MHZ; 192 } else { 193 return -EINVAL; 194 } 195 196 snd_soc_write(codec, DA732X_REG_PLL_CTRL, val); 197 198 return ret; 199 } 200 201 static void da732x_set_charge_pump(struct snd_soc_codec *codec, int state) 202 { 203 switch (state) { 204 case DA732X_ENABLE_CP: 205 snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_EN); 206 snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_EN | 207 DA732X_HP_CP_REG | DA732X_HP_CP_PULSESKIP); 208 snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA732X_CP_EN | 209 DA732X_CP_CTRL_CPVDD1); 210 snd_soc_write(codec, DA732X_REG_CP_CTRL2, 211 DA732X_CP_MANAGE_MAGNITUDE | DA732X_CP_BOOST); 212 snd_soc_write(codec, DA732X_REG_CP_CTRL3, DA732X_CP_1MHZ); 213 break; 214 case DA732X_DISABLE_CP: 215 snd_soc_write(codec, DA732X_REG_CLK_EN2, DA732X_CP_CLK_DIS); 216 snd_soc_write(codec, DA732X_REG_CP_HP2, DA732X_HP_CP_DIS); 217 snd_soc_write(codec, DA732X_REG_CP_CTRL1, DA723X_CP_DIS); 218 break; 219 default: 220 pr_err(KERN_ERR "Wrong charge pump state\n"); 221 break; 222 } 223 } 224 225 static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, DA732X_MIC_PRE_VOL_DB_MIN, 226 DA732X_MIC_PRE_VOL_DB_INC, 0); 227 228 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, DA732X_MIC_VOL_DB_MIN, 229 DA732X_MIC_VOL_DB_INC, 0); 230 231 static const DECLARE_TLV_DB_SCALE(aux_pga_tlv, DA732X_AUX_VOL_DB_MIN, 232 DA732X_AUX_VOL_DB_INC, 0); 233 234 static const DECLARE_TLV_DB_SCALE(hp_pga_tlv, DA732X_HP_VOL_DB_MIN, 235 DA732X_AUX_VOL_DB_INC, 0); 236 237 static const DECLARE_TLV_DB_SCALE(lin2_pga_tlv, DA732X_LIN2_VOL_DB_MIN, 238 DA732X_LIN2_VOL_DB_INC, 0); 239 240 static const DECLARE_TLV_DB_SCALE(lin3_pga_tlv, DA732X_LIN3_VOL_DB_MIN, 241 DA732X_LIN3_VOL_DB_INC, 0); 242 243 static const DECLARE_TLV_DB_SCALE(lin4_pga_tlv, DA732X_LIN4_VOL_DB_MIN, 244 DA732X_LIN4_VOL_DB_INC, 0); 245 246 static const DECLARE_TLV_DB_SCALE(adc_pga_tlv, DA732X_ADC_VOL_DB_MIN, 247 DA732X_ADC_VOL_DB_INC, 0); 248 249 static const DECLARE_TLV_DB_SCALE(dac_pga_tlv, DA732X_DAC_VOL_DB_MIN, 250 DA732X_DAC_VOL_DB_INC, 0); 251 252 static const DECLARE_TLV_DB_SCALE(eq_band_pga_tlv, DA732X_EQ_BAND_VOL_DB_MIN, 253 DA732X_EQ_BAND_VOL_DB_INC, 0); 254 255 static const DECLARE_TLV_DB_SCALE(eq_overall_tlv, DA732X_EQ_OVERALL_VOL_DB_MIN, 256 DA732X_EQ_OVERALL_VOL_DB_INC, 0); 257 258 /* High Pass Filter */ 259 static const char *da732x_hpf_mode[] = { 260 "Disable", "Music", "Voice", 261 }; 262 263 static const char *da732x_hpf_music[] = { 264 "1.8Hz", "3.75Hz", "7.5Hz", "15Hz", 265 }; 266 267 static const char *da732x_hpf_voice[] = { 268 "2.5Hz", "25Hz", "50Hz", "100Hz", 269 "150Hz", "200Hz", "300Hz", "400Hz" 270 }; 271 272 static const struct soc_enum da732x_dac1_hpf_mode_enum[] = { 273 SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_MODE_SHIFT, 274 DA732X_HPF_MODE_MAX, da732x_hpf_mode) 275 }; 276 277 static const struct soc_enum da732x_dac2_hpf_mode_enum[] = { 278 SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_MODE_SHIFT, 279 DA732X_HPF_MODE_MAX, da732x_hpf_mode) 280 }; 281 282 static const struct soc_enum da732x_dac3_hpf_mode_enum[] = { 283 SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_MODE_SHIFT, 284 DA732X_HPF_MODE_MAX, da732x_hpf_mode) 285 }; 286 287 static const struct soc_enum da732x_adc1_hpf_mode_enum[] = { 288 SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_MODE_SHIFT, 289 DA732X_HPF_MODE_MAX, da732x_hpf_mode) 290 }; 291 292 static const struct soc_enum da732x_adc2_hpf_mode_enum[] = { 293 SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_MODE_SHIFT, 294 DA732X_HPF_MODE_MAX, da732x_hpf_mode) 295 }; 296 297 static const struct soc_enum da732x_dac1_hp_filter_enum[] = { 298 SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_MUSIC_SHIFT, 299 DA732X_HPF_MUSIC_MAX, da732x_hpf_music) 300 }; 301 302 static const struct soc_enum da732x_dac2_hp_filter_enum[] = { 303 SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_MUSIC_SHIFT, 304 DA732X_HPF_MUSIC_MAX, da732x_hpf_music) 305 }; 306 307 static const struct soc_enum da732x_dac3_hp_filter_enum[] = { 308 SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_MUSIC_SHIFT, 309 DA732X_HPF_MUSIC_MAX, da732x_hpf_music) 310 }; 311 312 static const struct soc_enum da732x_adc1_hp_filter_enum[] = { 313 SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_MUSIC_SHIFT, 314 DA732X_HPF_MUSIC_MAX, da732x_hpf_music) 315 }; 316 317 static const struct soc_enum da732x_adc2_hp_filter_enum[] = { 318 SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_MUSIC_SHIFT, 319 DA732X_HPF_MUSIC_MAX, da732x_hpf_music) 320 }; 321 322 static const struct soc_enum da732x_dac1_voice_filter_enum[] = { 323 SOC_ENUM_SINGLE(DA732X_REG_DAC1_HPF, DA732X_HPF_VOICE_SHIFT, 324 DA732X_HPF_VOICE_MAX, da732x_hpf_voice) 325 }; 326 327 static const struct soc_enum da732x_dac2_voice_filter_enum[] = { 328 SOC_ENUM_SINGLE(DA732X_REG_DAC2_HPF, DA732X_HPF_VOICE_SHIFT, 329 DA732X_HPF_VOICE_MAX, da732x_hpf_voice) 330 }; 331 332 static const struct soc_enum da732x_dac3_voice_filter_enum[] = { 333 SOC_ENUM_SINGLE(DA732X_REG_DAC3_HPF, DA732X_HPF_VOICE_SHIFT, 334 DA732X_HPF_VOICE_MAX, da732x_hpf_voice) 335 }; 336 337 static const struct soc_enum da732x_adc1_voice_filter_enum[] = { 338 SOC_ENUM_SINGLE(DA732X_REG_ADC1_HPF, DA732X_HPF_VOICE_SHIFT, 339 DA732X_HPF_VOICE_MAX, da732x_hpf_voice) 340 }; 341 342 static const struct soc_enum da732x_adc2_voice_filter_enum[] = { 343 SOC_ENUM_SINGLE(DA732X_REG_ADC2_HPF, DA732X_HPF_VOICE_SHIFT, 344 DA732X_HPF_VOICE_MAX, da732x_hpf_voice) 345 }; 346 347 348 static int da732x_hpf_set(struct snd_kcontrol *kcontrol, 349 struct snd_ctl_elem_value *ucontrol) 350 { 351 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 352 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value; 353 unsigned int reg = enum_ctrl->reg; 354 unsigned int sel = ucontrol->value.integer.value[0]; 355 unsigned int bits; 356 357 switch (sel) { 358 case DA732X_HPF_DISABLED: 359 bits = DA732X_HPF_DIS; 360 break; 361 case DA732X_HPF_VOICE: 362 bits = DA732X_HPF_VOICE_EN; 363 break; 364 case DA732X_HPF_MUSIC: 365 bits = DA732X_HPF_MUSIC_EN; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 snd_soc_update_bits(codec, reg, DA732X_HPF_MASK, bits); 372 373 return 0; 374 } 375 376 static int da732x_hpf_get(struct snd_kcontrol *kcontrol, 377 struct snd_ctl_elem_value *ucontrol) 378 { 379 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 380 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value; 381 unsigned int reg = enum_ctrl->reg; 382 int val; 383 384 val = snd_soc_read(codec, reg) & DA732X_HPF_MASK; 385 386 switch (val) { 387 case DA732X_HPF_VOICE_EN: 388 ucontrol->value.integer.value[0] = DA732X_HPF_VOICE; 389 break; 390 case DA732X_HPF_MUSIC_EN: 391 ucontrol->value.integer.value[0] = DA732X_HPF_MUSIC; 392 break; 393 default: 394 ucontrol->value.integer.value[0] = DA732X_HPF_DISABLED; 395 break; 396 } 397 398 return 0; 399 } 400 401 static const struct snd_kcontrol_new da732x_snd_controls[] = { 402 /* Input PGAs */ 403 SOC_SINGLE_RANGE_TLV("MIC1 Boost Volume", DA732X_REG_MIC1_PRE, 404 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN, 405 DA732X_MICBOOST_MAX, 0, mic_boost_tlv), 406 SOC_SINGLE_RANGE_TLV("MIC2 Boost Volume", DA732X_REG_MIC2_PRE, 407 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN, 408 DA732X_MICBOOST_MAX, 0, mic_boost_tlv), 409 SOC_SINGLE_RANGE_TLV("MIC3 Boost Volume", DA732X_REG_MIC3_PRE, 410 DA732X_MICBOOST_SHIFT, DA732X_MICBOOST_MIN, 411 DA732X_MICBOOST_MAX, 0, mic_boost_tlv), 412 413 /* MICs */ 414 SOC_SINGLE("MIC1 Switch", DA732X_REG_MIC1, DA732X_MIC_MUTE_SHIFT, 415 DA732X_SWITCH_MAX, DA732X_INVERT), 416 SOC_SINGLE_RANGE_TLV("MIC1 Volume", DA732X_REG_MIC1, 417 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN, 418 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv), 419 SOC_SINGLE("MIC2 Switch", DA732X_REG_MIC2, DA732X_MIC_MUTE_SHIFT, 420 DA732X_SWITCH_MAX, DA732X_INVERT), 421 SOC_SINGLE_RANGE_TLV("MIC2 Volume", DA732X_REG_MIC2, 422 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN, 423 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv), 424 SOC_SINGLE("MIC3 Switch", DA732X_REG_MIC3, DA732X_MIC_MUTE_SHIFT, 425 DA732X_SWITCH_MAX, DA732X_INVERT), 426 SOC_SINGLE_RANGE_TLV("MIC3 Volume", DA732X_REG_MIC3, 427 DA732X_MIC_VOL_SHIFT, DA732X_MIC_VOL_VAL_MIN, 428 DA732X_MIC_VOL_VAL_MAX, 0, mic_pga_tlv), 429 430 /* AUXs */ 431 SOC_SINGLE("AUX1L Switch", DA732X_REG_AUX1L, DA732X_AUX_MUTE_SHIFT, 432 DA732X_SWITCH_MAX, DA732X_INVERT), 433 SOC_SINGLE_TLV("AUX1L Volume", DA732X_REG_AUX1L, 434 DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX, 435 DA732X_NO_INVERT, aux_pga_tlv), 436 SOC_SINGLE("AUX1R Switch", DA732X_REG_AUX1R, DA732X_AUX_MUTE_SHIFT, 437 DA732X_SWITCH_MAX, DA732X_INVERT), 438 SOC_SINGLE_TLV("AUX1R Volume", DA732X_REG_AUX1R, 439 DA732X_AUX_VOL_SHIFT, DA732X_AUX_VOL_VAL_MAX, 440 DA732X_NO_INVERT, aux_pga_tlv), 441 442 /* ADCs */ 443 SOC_DOUBLE_TLV("ADC1 Volume", DA732X_REG_ADC1_SEL, 444 DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT, 445 DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv), 446 447 SOC_DOUBLE_TLV("ADC2 Volume", DA732X_REG_ADC2_SEL, 448 DA732X_ADCL_VOL_SHIFT, DA732X_ADCR_VOL_SHIFT, 449 DA732X_ADC_VOL_VAL_MAX, DA732X_INVERT, adc_pga_tlv), 450 451 /* DACs */ 452 SOC_DOUBLE("Digital Playback DAC12 Switch", DA732X_REG_DAC1_SEL, 453 DA732X_DACL_MUTE_SHIFT, DA732X_DACR_MUTE_SHIFT, 454 DA732X_SWITCH_MAX, DA732X_INVERT), 455 SOC_DOUBLE_R_TLV("Digital Playback DAC12 Volume", DA732X_REG_DAC1_L_VOL, 456 DA732X_REG_DAC1_R_VOL, DA732X_DAC_VOL_SHIFT, 457 DA732X_DAC_VOL_VAL_MAX, DA732X_INVERT, dac_pga_tlv), 458 SOC_SINGLE("Digital Playback DAC3 Switch", DA732X_REG_DAC2_SEL, 459 DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT), 460 SOC_SINGLE_TLV("Digital Playback DAC3 Volume", DA732X_REG_DAC2_L_VOL, 461 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX, 462 DA732X_INVERT, dac_pga_tlv), 463 SOC_SINGLE("Digital Playback DAC4 Switch", DA732X_REG_DAC2_SEL, 464 DA732X_DACR_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT), 465 SOC_SINGLE_TLV("Digital Playback DAC4 Volume", DA732X_REG_DAC2_R_VOL, 466 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX, 467 DA732X_INVERT, dac_pga_tlv), 468 SOC_SINGLE("Digital Playback DAC5 Switch", DA732X_REG_DAC3_SEL, 469 DA732X_DACL_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT), 470 SOC_SINGLE_TLV("Digital Playback DAC5 Volume", DA732X_REG_DAC3_VOL, 471 DA732X_DAC_VOL_SHIFT, DA732X_DAC_VOL_VAL_MAX, 472 DA732X_INVERT, dac_pga_tlv), 473 474 /* High Pass Filters */ 475 SOC_ENUM_EXT("DAC1 High Pass Filter Mode", 476 da732x_dac1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set), 477 SOC_ENUM("DAC1 High Pass Filter", da732x_dac1_hp_filter_enum), 478 SOC_ENUM("DAC1 Voice Filter", da732x_dac1_voice_filter_enum), 479 480 SOC_ENUM_EXT("DAC2 High Pass Filter Mode", 481 da732x_dac2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set), 482 SOC_ENUM("DAC2 High Pass Filter", da732x_dac2_hp_filter_enum), 483 SOC_ENUM("DAC2 Voice Filter", da732x_dac2_voice_filter_enum), 484 485 SOC_ENUM_EXT("DAC3 High Pass Filter Mode", 486 da732x_dac3_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set), 487 SOC_ENUM("DAC3 High Pass Filter", da732x_dac3_hp_filter_enum), 488 SOC_ENUM("DAC3 Filter Mode", da732x_dac3_voice_filter_enum), 489 490 SOC_ENUM_EXT("ADC1 High Pass Filter Mode", 491 da732x_adc1_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set), 492 SOC_ENUM("ADC1 High Pass Filter", da732x_adc1_hp_filter_enum), 493 SOC_ENUM("ADC1 Voice Filter", da732x_adc1_voice_filter_enum), 494 495 SOC_ENUM_EXT("ADC2 High Pass Filter Mode", 496 da732x_adc2_hpf_mode_enum, da732x_hpf_get, da732x_hpf_set), 497 SOC_ENUM("ADC2 High Pass Filter", da732x_adc2_hp_filter_enum), 498 SOC_ENUM("ADC2 Voice Filter", da732x_adc2_voice_filter_enum), 499 500 /* Equalizers */ 501 SOC_SINGLE("ADC1 EQ Switch", DA732X_REG_ADC1_EQ5, 502 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT), 503 SOC_SINGLE_TLV("ADC1 EQ Band 1 Volume", DA732X_REG_ADC1_EQ12, 504 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX, 505 DA732X_INVERT, eq_band_pga_tlv), 506 SOC_SINGLE_TLV("ADC1 EQ Band 2 Volume", DA732X_REG_ADC1_EQ12, 507 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX, 508 DA732X_INVERT, eq_band_pga_tlv), 509 SOC_SINGLE_TLV("ADC1 EQ Band 3 Volume", DA732X_REG_ADC1_EQ34, 510 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX, 511 DA732X_INVERT, eq_band_pga_tlv), 512 SOC_SINGLE_TLV("ADC1 EQ Band 4 Volume", DA732X_REG_ADC1_EQ34, 513 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX, 514 DA732X_INVERT, eq_band_pga_tlv), 515 SOC_SINGLE_TLV("ADC1 EQ Band 5 Volume", DA732X_REG_ADC1_EQ5, 516 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX, 517 DA732X_INVERT, eq_band_pga_tlv), 518 SOC_SINGLE_TLV("ADC1 EQ Overall Volume", DA732X_REG_ADC1_EQ5, 519 DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX, 520 DA732X_INVERT, eq_overall_tlv), 521 522 SOC_SINGLE("ADC2 EQ Switch", DA732X_REG_ADC2_EQ5, 523 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT), 524 SOC_SINGLE_TLV("ADC2 EQ Band 1 Volume", DA732X_REG_ADC2_EQ12, 525 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX, 526 DA732X_INVERT, eq_band_pga_tlv), 527 SOC_SINGLE_TLV("ADC2 EQ Band 2 Volume", DA732X_REG_ADC2_EQ12, 528 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX, 529 DA732X_INVERT, eq_band_pga_tlv), 530 SOC_SINGLE_TLV("ADC2 EQ Band 3 Volume", DA732X_REG_ADC2_EQ34, 531 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX, 532 DA732X_INVERT, eq_band_pga_tlv), 533 SOC_SINGLE_TLV("ACD2 EQ Band 4 Volume", DA732X_REG_ADC2_EQ34, 534 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX, 535 DA732X_INVERT, eq_band_pga_tlv), 536 SOC_SINGLE_TLV("ACD2 EQ Band 5 Volume", DA732X_REG_ADC2_EQ5, 537 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX, 538 DA732X_INVERT, eq_band_pga_tlv), 539 SOC_SINGLE_TLV("ADC2 EQ Overall Volume", DA732X_REG_ADC1_EQ5, 540 DA732X_EQ_OVERALL_SHIFT, DA732X_EQ_OVERALL_VOL_VAL_MAX, 541 DA732X_INVERT, eq_overall_tlv), 542 543 SOC_SINGLE("DAC1 EQ Switch", DA732X_REG_DAC1_EQ5, 544 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT), 545 SOC_SINGLE_TLV("DAC1 EQ Band 1 Volume", DA732X_REG_DAC1_EQ12, 546 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX, 547 DA732X_INVERT, eq_band_pga_tlv), 548 SOC_SINGLE_TLV("DAC1 EQ Band 2 Volume", DA732X_REG_DAC1_EQ12, 549 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX, 550 DA732X_INVERT, eq_band_pga_tlv), 551 SOC_SINGLE_TLV("DAC1 EQ Band 3 Volume", DA732X_REG_DAC1_EQ34, 552 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX, 553 DA732X_INVERT, eq_band_pga_tlv), 554 SOC_SINGLE_TLV("DAC1 EQ Band 4 Volume", DA732X_REG_DAC1_EQ34, 555 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX, 556 DA732X_INVERT, eq_band_pga_tlv), 557 SOC_SINGLE_TLV("DAC1 EQ Band 5 Volume", DA732X_REG_DAC1_EQ5, 558 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX, 559 DA732X_INVERT, eq_band_pga_tlv), 560 561 SOC_SINGLE("DAC2 EQ Switch", DA732X_REG_DAC2_EQ5, 562 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT), 563 SOC_SINGLE_TLV("DAC2 EQ Band 1 Volume", DA732X_REG_DAC2_EQ12, 564 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX, 565 DA732X_INVERT, eq_band_pga_tlv), 566 SOC_SINGLE_TLV("DAC2 EQ Band 2 Volume", DA732X_REG_DAC2_EQ12, 567 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX, 568 DA732X_INVERT, eq_band_pga_tlv), 569 SOC_SINGLE_TLV("DAC2 EQ Band 3 Volume", DA732X_REG_DAC2_EQ34, 570 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX, 571 DA732X_INVERT, eq_band_pga_tlv), 572 SOC_SINGLE_TLV("DAC2 EQ Band 4 Volume", DA732X_REG_DAC2_EQ34, 573 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX, 574 DA732X_INVERT, eq_band_pga_tlv), 575 SOC_SINGLE_TLV("DAC2 EQ Band 5 Volume", DA732X_REG_DAC2_EQ5, 576 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX, 577 DA732X_INVERT, eq_band_pga_tlv), 578 579 SOC_SINGLE("DAC3 EQ Switch", DA732X_REG_DAC3_EQ5, 580 DA732X_EQ_EN_SHIFT, DA732X_EQ_EN_MAX, DA732X_NO_INVERT), 581 SOC_SINGLE_TLV("DAC3 EQ Band 1 Volume", DA732X_REG_DAC3_EQ12, 582 DA732X_EQ_BAND1_SHIFT, DA732X_EQ_VOL_VAL_MAX, 583 DA732X_INVERT, eq_band_pga_tlv), 584 SOC_SINGLE_TLV("DAC3 EQ Band 2 Volume", DA732X_REG_DAC3_EQ12, 585 DA732X_EQ_BAND2_SHIFT, DA732X_EQ_VOL_VAL_MAX, 586 DA732X_INVERT, eq_band_pga_tlv), 587 SOC_SINGLE_TLV("DAC3 EQ Band 3 Volume", DA732X_REG_DAC3_EQ34, 588 DA732X_EQ_BAND3_SHIFT, DA732X_EQ_VOL_VAL_MAX, 589 DA732X_INVERT, eq_band_pga_tlv), 590 SOC_SINGLE_TLV("DAC3 EQ Band 4 Volume", DA732X_REG_DAC3_EQ34, 591 DA732X_EQ_BAND4_SHIFT, DA732X_EQ_VOL_VAL_MAX, 592 DA732X_INVERT, eq_band_pga_tlv), 593 SOC_SINGLE_TLV("DAC3 EQ Band 5 Volume", DA732X_REG_DAC3_EQ5, 594 DA732X_EQ_BAND5_SHIFT, DA732X_EQ_VOL_VAL_MAX, 595 DA732X_INVERT, eq_band_pga_tlv), 596 597 /* Lineout 2 Reciever*/ 598 SOC_SINGLE("Lineout 2 Switch", DA732X_REG_LIN2, DA732X_LOUT_MUTE_SHIFT, 599 DA732X_SWITCH_MAX, DA732X_INVERT), 600 SOC_SINGLE_TLV("Lineout 2 Volume", DA732X_REG_LIN2, 601 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX, 602 DA732X_NO_INVERT, lin2_pga_tlv), 603 604 /* Lineout 3 SPEAKER*/ 605 SOC_SINGLE("Lineout 3 Switch", DA732X_REG_LIN3, DA732X_LOUT_MUTE_SHIFT, 606 DA732X_SWITCH_MAX, DA732X_INVERT), 607 SOC_SINGLE_TLV("Lineout 3 Volume", DA732X_REG_LIN3, 608 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX, 609 DA732X_NO_INVERT, lin3_pga_tlv), 610 611 /* Lineout 4 */ 612 SOC_SINGLE("Lineout 4 Switch", DA732X_REG_LIN4, DA732X_LOUT_MUTE_SHIFT, 613 DA732X_SWITCH_MAX, DA732X_INVERT), 614 SOC_SINGLE_TLV("Lineout 4 Volume", DA732X_REG_LIN4, 615 DA732X_LOUT_VOL_SHIFT, DA732X_LOUT_VOL_VAL_MAX, 616 DA732X_NO_INVERT, lin4_pga_tlv), 617 618 /* Headphones */ 619 SOC_DOUBLE_R("Headphone Switch", DA732X_REG_HPR, DA732X_REG_HPL, 620 DA732X_HP_MUTE_SHIFT, DA732X_SWITCH_MAX, DA732X_INVERT), 621 SOC_DOUBLE_R_TLV("Headphone Volume", DA732X_REG_HPL_VOL, 622 DA732X_REG_HPR_VOL, DA732X_HP_VOL_SHIFT, 623 DA732X_HP_VOL_VAL_MAX, DA732X_NO_INVERT, hp_pga_tlv), 624 }; 625 626 static int da732x_adc_event(struct snd_soc_dapm_widget *w, 627 struct snd_kcontrol *kcontrol, int event) 628 { 629 struct snd_soc_codec *codec = w->codec; 630 631 switch (event) { 632 case SND_SOC_DAPM_POST_PMU: 633 switch (w->reg) { 634 case DA732X_REG_ADC1_PD: 635 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3, 636 DA732X_ADCA_BB_CLK_EN, 637 DA732X_ADCA_BB_CLK_EN); 638 break; 639 case DA732X_REG_ADC2_PD: 640 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3, 641 DA732X_ADCC_BB_CLK_EN, 642 DA732X_ADCC_BB_CLK_EN); 643 break; 644 default: 645 return -EINVAL; 646 } 647 648 snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK, 649 DA732X_ADC_SET_ACT); 650 snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK, 651 DA732X_ADC_ON); 652 break; 653 case SND_SOC_DAPM_POST_PMD: 654 snd_soc_update_bits(codec, w->reg, DA732X_ADC_PD_MASK, 655 DA732X_ADC_OFF); 656 snd_soc_update_bits(codec, w->reg, DA732X_ADC_RST_MASK, 657 DA732X_ADC_SET_RST); 658 659 switch (w->reg) { 660 case DA732X_REG_ADC1_PD: 661 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3, 662 DA732X_ADCA_BB_CLK_EN, 0); 663 break; 664 case DA732X_REG_ADC2_PD: 665 snd_soc_update_bits(codec, DA732X_REG_CLK_EN3, 666 DA732X_ADCC_BB_CLK_EN, 0); 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 break; 673 default: 674 return -EINVAL; 675 } 676 677 return 0; 678 } 679 680 static int da732x_out_pga_event(struct snd_soc_dapm_widget *w, 681 struct snd_kcontrol *kcontrol, int event) 682 { 683 struct snd_soc_codec *codec = w->codec; 684 685 switch (event) { 686 case SND_SOC_DAPM_POST_PMU: 687 snd_soc_update_bits(codec, w->reg, 688 (1 << w->shift) | DA732X_OUT_HIZ_EN, 689 (1 << w->shift) | DA732X_OUT_HIZ_EN); 690 break; 691 case SND_SOC_DAPM_POST_PMD: 692 snd_soc_update_bits(codec, w->reg, 693 (1 << w->shift) | DA732X_OUT_HIZ_EN, 694 (1 << w->shift) | DA732X_OUT_HIZ_DIS); 695 break; 696 default: 697 return -EINVAL; 698 } 699 700 return 0; 701 } 702 703 static const char *adcl_text[] = { 704 "AUX1L", "MIC1" 705 }; 706 707 static const char *adcr_text[] = { 708 "AUX1R", "MIC2", "MIC3" 709 }; 710 711 static const char *enable_text[] = { 712 "Disabled", 713 "Enabled" 714 }; 715 716 /* ADC1LMUX */ 717 static const struct soc_enum adc1l_enum = 718 SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC1L_MUX_SEL_SHIFT, 719 DA732X_ADCL_MUX_MAX, adcl_text); 720 static const struct snd_kcontrol_new adc1l_mux = 721 SOC_DAPM_ENUM("ADC Route", adc1l_enum); 722 723 /* ADC1RMUX */ 724 static const struct soc_enum adc1r_enum = 725 SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC1R_MUX_SEL_SHIFT, 726 DA732X_ADCR_MUX_MAX, adcr_text); 727 static const struct snd_kcontrol_new adc1r_mux = 728 SOC_DAPM_ENUM("ADC Route", adc1r_enum); 729 730 /* ADC2LMUX */ 731 static const struct soc_enum adc2l_enum = 732 SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC2L_MUX_SEL_SHIFT, 733 DA732X_ADCL_MUX_MAX, adcl_text); 734 static const struct snd_kcontrol_new adc2l_mux = 735 SOC_DAPM_ENUM("ADC Route", adc2l_enum); 736 737 /* ADC2RMUX */ 738 static const struct soc_enum adc2r_enum = 739 SOC_ENUM_SINGLE(DA732X_REG_INP_MUX, DA732X_ADC2R_MUX_SEL_SHIFT, 740 DA732X_ADCR_MUX_MAX, adcr_text); 741 742 static const struct snd_kcontrol_new adc2r_mux = 743 SOC_DAPM_ENUM("ADC Route", adc2r_enum); 744 745 static const struct soc_enum da732x_hp_left_output = 746 SOC_ENUM_SINGLE(DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN_SHIFT, 747 DA732X_DAC_EN_MAX, enable_text); 748 749 static const struct snd_kcontrol_new hpl_mux = 750 SOC_DAPM_ENUM("HPL Switch", da732x_hp_left_output); 751 752 static const struct soc_enum da732x_hp_right_output = 753 SOC_ENUM_SINGLE(DA732X_REG_HPR, DA732X_HP_OUT_DAC_EN_SHIFT, 754 DA732X_DAC_EN_MAX, enable_text); 755 756 static const struct snd_kcontrol_new hpr_mux = 757 SOC_DAPM_ENUM("HPR Switch", da732x_hp_right_output); 758 759 static const struct soc_enum da732x_speaker_output = 760 SOC_ENUM_SINGLE(DA732X_REG_LIN3, DA732X_LOUT_DAC_EN_SHIFT, 761 DA732X_DAC_EN_MAX, enable_text); 762 763 static const struct snd_kcontrol_new spk_mux = 764 SOC_DAPM_ENUM("SPK Switch", da732x_speaker_output); 765 766 static const struct soc_enum da732x_lout4_output = 767 SOC_ENUM_SINGLE(DA732X_REG_LIN4, DA732X_LOUT_DAC_EN_SHIFT, 768 DA732X_DAC_EN_MAX, enable_text); 769 770 static const struct snd_kcontrol_new lout4_mux = 771 SOC_DAPM_ENUM("LOUT4 Switch", da732x_lout4_output); 772 773 static const struct soc_enum da732x_lout2_output = 774 SOC_ENUM_SINGLE(DA732X_REG_LIN2, DA732X_LOUT_DAC_EN_SHIFT, 775 DA732X_DAC_EN_MAX, enable_text); 776 777 static const struct snd_kcontrol_new lout2_mux = 778 SOC_DAPM_ENUM("LOUT2 Switch", da732x_lout2_output); 779 780 static const struct snd_soc_dapm_widget da732x_dapm_widgets[] = { 781 /* Supplies */ 782 SND_SOC_DAPM_SUPPLY("ADC1 Supply", DA732X_REG_ADC1_PD, 0, 783 DA732X_NO_INVERT, da732x_adc_event, 784 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 785 SND_SOC_DAPM_SUPPLY("ADC2 Supply", DA732X_REG_ADC2_PD, 0, 786 DA732X_NO_INVERT, da732x_adc_event, 787 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 788 SND_SOC_DAPM_SUPPLY("DAC1 CLK", DA732X_REG_CLK_EN4, 789 DA732X_DACA_BB_CLK_SHIFT, DA732X_NO_INVERT, 790 NULL, 0), 791 SND_SOC_DAPM_SUPPLY("DAC2 CLK", DA732X_REG_CLK_EN4, 792 DA732X_DACC_BB_CLK_SHIFT, DA732X_NO_INVERT, 793 NULL, 0), 794 SND_SOC_DAPM_SUPPLY("DAC3 CLK", DA732X_REG_CLK_EN5, 795 DA732X_DACE_BB_CLK_SHIFT, DA732X_NO_INVERT, 796 NULL, 0), 797 798 /* Micbias */ 799 SND_SOC_DAPM_SUPPLY("MICBIAS1", DA732X_REG_MICBIAS1, 800 DA732X_MICBIAS_EN_SHIFT, 801 DA732X_NO_INVERT, NULL, 0), 802 SND_SOC_DAPM_SUPPLY("MICBIAS2", DA732X_REG_MICBIAS2, 803 DA732X_MICBIAS_EN_SHIFT, 804 DA732X_NO_INVERT, NULL, 0), 805 806 /* Inputs */ 807 SND_SOC_DAPM_INPUT("MIC1"), 808 SND_SOC_DAPM_INPUT("MIC2"), 809 SND_SOC_DAPM_INPUT("MIC3"), 810 SND_SOC_DAPM_INPUT("AUX1L"), 811 SND_SOC_DAPM_INPUT("AUX1R"), 812 813 /* Outputs */ 814 SND_SOC_DAPM_OUTPUT("HPL"), 815 SND_SOC_DAPM_OUTPUT("HPR"), 816 SND_SOC_DAPM_OUTPUT("LOUTL"), 817 SND_SOC_DAPM_OUTPUT("LOUTR"), 818 SND_SOC_DAPM_OUTPUT("ClassD"), 819 820 /* ADCs */ 821 SND_SOC_DAPM_ADC("ADC1L", NULL, DA732X_REG_ADC1_SEL, 822 DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT), 823 SND_SOC_DAPM_ADC("ADC1R", NULL, DA732X_REG_ADC1_SEL, 824 DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT), 825 SND_SOC_DAPM_ADC("ADC2L", NULL, DA732X_REG_ADC2_SEL, 826 DA732X_ADCL_EN_SHIFT, DA732X_NO_INVERT), 827 SND_SOC_DAPM_ADC("ADC2R", NULL, DA732X_REG_ADC2_SEL, 828 DA732X_ADCR_EN_SHIFT, DA732X_NO_INVERT), 829 830 /* DACs */ 831 SND_SOC_DAPM_DAC("DAC1L", NULL, DA732X_REG_DAC1_SEL, 832 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT), 833 SND_SOC_DAPM_DAC("DAC1R", NULL, DA732X_REG_DAC1_SEL, 834 DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT), 835 SND_SOC_DAPM_DAC("DAC2L", NULL, DA732X_REG_DAC2_SEL, 836 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT), 837 SND_SOC_DAPM_DAC("DAC2R", NULL, DA732X_REG_DAC2_SEL, 838 DA732X_DACR_EN_SHIFT, DA732X_NO_INVERT), 839 SND_SOC_DAPM_DAC("DAC3", NULL, DA732X_REG_DAC3_SEL, 840 DA732X_DACL_EN_SHIFT, DA732X_NO_INVERT), 841 842 /* Input Pgas */ 843 SND_SOC_DAPM_PGA("MIC1 PGA", DA732X_REG_MIC1, DA732X_MIC_EN_SHIFT, 844 0, NULL, 0), 845 SND_SOC_DAPM_PGA("MIC2 PGA", DA732X_REG_MIC2, DA732X_MIC_EN_SHIFT, 846 0, NULL, 0), 847 SND_SOC_DAPM_PGA("MIC3 PGA", DA732X_REG_MIC3, DA732X_MIC_EN_SHIFT, 848 0, NULL, 0), 849 SND_SOC_DAPM_PGA("AUX1L PGA", DA732X_REG_AUX1L, DA732X_AUX_EN_SHIFT, 850 0, NULL, 0), 851 SND_SOC_DAPM_PGA("AUX1R PGA", DA732X_REG_AUX1R, DA732X_AUX_EN_SHIFT, 852 0, NULL, 0), 853 854 SND_SOC_DAPM_PGA_E("HP Left", DA732X_REG_HPL, DA732X_HP_OUT_EN_SHIFT, 855 0, NULL, 0, da732x_out_pga_event, 856 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 857 SND_SOC_DAPM_PGA_E("HP Right", DA732X_REG_HPR, DA732X_HP_OUT_EN_SHIFT, 858 0, NULL, 0, da732x_out_pga_event, 859 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 860 SND_SOC_DAPM_PGA_E("LIN2", DA732X_REG_LIN2, DA732X_LIN_OUT_EN_SHIFT, 861 0, NULL, 0, da732x_out_pga_event, 862 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 863 SND_SOC_DAPM_PGA_E("LIN3", DA732X_REG_LIN3, DA732X_LIN_OUT_EN_SHIFT, 864 0, NULL, 0, da732x_out_pga_event, 865 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 866 SND_SOC_DAPM_PGA_E("LIN4", DA732X_REG_LIN4, DA732X_LIN_OUT_EN_SHIFT, 867 0, NULL, 0, da732x_out_pga_event, 868 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 869 870 /* MUXs */ 871 SND_SOC_DAPM_MUX("ADC1 Left MUX", SND_SOC_NOPM, 0, 0, &adc1l_mux), 872 SND_SOC_DAPM_MUX("ADC1 Right MUX", SND_SOC_NOPM, 0, 0, &adc1r_mux), 873 SND_SOC_DAPM_MUX("ADC2 Left MUX", SND_SOC_NOPM, 0, 0, &adc2l_mux), 874 SND_SOC_DAPM_MUX("ADC2 Right MUX", SND_SOC_NOPM, 0, 0, &adc2r_mux), 875 876 SND_SOC_DAPM_MUX("HP Left MUX", SND_SOC_NOPM, 0, 0, &hpl_mux), 877 SND_SOC_DAPM_MUX("HP Right MUX", SND_SOC_NOPM, 0, 0, &hpr_mux), 878 SND_SOC_DAPM_MUX("Speaker MUX", SND_SOC_NOPM, 0, 0, &spk_mux), 879 SND_SOC_DAPM_MUX("LOUT2 MUX", SND_SOC_NOPM, 0, 0, &lout2_mux), 880 SND_SOC_DAPM_MUX("LOUT4 MUX", SND_SOC_NOPM, 0, 0, &lout4_mux), 881 882 /* AIF interfaces */ 883 SND_SOC_DAPM_AIF_OUT("AIFA Output", "AIFA Capture", 0, DA732X_REG_AIFA3, 884 DA732X_AIF_EN_SHIFT, 0), 885 SND_SOC_DAPM_AIF_IN("AIFA Input", "AIFA Playback", 0, DA732X_REG_AIFA3, 886 DA732X_AIF_EN_SHIFT, 0), 887 888 SND_SOC_DAPM_AIF_OUT("AIFB Output", "AIFB Capture", 0, DA732X_REG_AIFB3, 889 DA732X_AIF_EN_SHIFT, 0), 890 SND_SOC_DAPM_AIF_IN("AIFB Input", "AIFB Playback", 0, DA732X_REG_AIFB3, 891 DA732X_AIF_EN_SHIFT, 0), 892 }; 893 894 static const struct snd_soc_dapm_route da732x_dapm_routes[] = { 895 /* Inputs */ 896 {"AUX1L PGA", "NULL", "AUX1L"}, 897 {"AUX1R PGA", "NULL", "AUX1R"}, 898 {"MIC1 PGA", NULL, "MIC1"}, 899 {"MIC2 PGA", "NULL", "MIC2"}, 900 {"MIC3 PGA", "NULL", "MIC3"}, 901 902 /* Capture Path */ 903 {"ADC1 Left MUX", "MIC1", "MIC1 PGA"}, 904 {"ADC1 Left MUX", "AUX1L", "AUX1L PGA"}, 905 906 {"ADC1 Right MUX", "AUX1R", "AUX1R PGA"}, 907 {"ADC1 Right MUX", "MIC2", "MIC2 PGA"}, 908 {"ADC1 Right MUX", "MIC3", "MIC3 PGA"}, 909 910 {"ADC2 Left MUX", "AUX1L", "AUX1L PGA"}, 911 {"ADC2 Left MUX", "MIC1", "MIC1 PGA"}, 912 913 {"ADC2 Right MUX", "AUX1R", "AUX1R PGA"}, 914 {"ADC2 Right MUX", "MIC2", "MIC2 PGA"}, 915 {"ADC2 Right MUX", "MIC3", "MIC3 PGA"}, 916 917 {"ADC1L", NULL, "ADC1 Supply"}, 918 {"ADC1R", NULL, "ADC1 Supply"}, 919 {"ADC2L", NULL, "ADC2 Supply"}, 920 {"ADC2R", NULL, "ADC2 Supply"}, 921 922 {"ADC1L", NULL, "ADC1 Left MUX"}, 923 {"ADC1R", NULL, "ADC1 Right MUX"}, 924 {"ADC2L", NULL, "ADC2 Left MUX"}, 925 {"ADC2R", NULL, "ADC2 Right MUX"}, 926 927 {"AIFA Output", NULL, "ADC1L"}, 928 {"AIFA Output", NULL, "ADC1R"}, 929 {"AIFB Output", NULL, "ADC2L"}, 930 {"AIFB Output", NULL, "ADC2R"}, 931 932 {"HP Left MUX", "Enabled", "AIFA Input"}, 933 {"HP Right MUX", "Enabled", "AIFA Input"}, 934 {"Speaker MUX", "Enabled", "AIFB Input"}, 935 {"LOUT2 MUX", "Enabled", "AIFB Input"}, 936 {"LOUT4 MUX", "Enabled", "AIFB Input"}, 937 938 {"DAC1L", NULL, "DAC1 CLK"}, 939 {"DAC1R", NULL, "DAC1 CLK"}, 940 {"DAC2L", NULL, "DAC2 CLK"}, 941 {"DAC2R", NULL, "DAC2 CLK"}, 942 {"DAC3", NULL, "DAC3 CLK"}, 943 944 {"DAC1L", NULL, "HP Left MUX"}, 945 {"DAC1R", NULL, "HP Right MUX"}, 946 {"DAC2L", NULL, "Speaker MUX"}, 947 {"DAC2R", NULL, "LOUT4 MUX"}, 948 {"DAC3", NULL, "LOUT2 MUX"}, 949 950 /* Output Pgas */ 951 {"HP Left", NULL, "DAC1L"}, 952 {"HP Right", NULL, "DAC1R"}, 953 {"LIN3", NULL, "DAC2L"}, 954 {"LIN4", NULL, "DAC2R"}, 955 {"LIN2", NULL, "DAC3"}, 956 957 /* Outputs */ 958 {"ClassD", NULL, "LIN3"}, 959 {"LOUTL", NULL, "LIN2"}, 960 {"LOUTR", NULL, "LIN4"}, 961 {"HPL", NULL, "HP Left"}, 962 {"HPR", NULL, "HP Right"}, 963 }; 964 965 static int da732x_hw_params(struct snd_pcm_substream *substream, 966 struct snd_pcm_hw_params *params, 967 struct snd_soc_dai *dai) 968 { 969 struct snd_soc_codec *codec = dai->codec; 970 u32 aif = 0; 971 u32 reg_aif; 972 u32 fs; 973 974 reg_aif = dai->driver->base; 975 976 switch (params_width(params)) { 977 case 16: 978 aif |= DA732X_AIF_WORD_16; 979 break; 980 case 20: 981 aif |= DA732X_AIF_WORD_20; 982 break; 983 case 24: 984 aif |= DA732X_AIF_WORD_24; 985 break; 986 case 32: 987 aif |= DA732X_AIF_WORD_32; 988 break; 989 default: 990 return -EINVAL; 991 } 992 993 switch (params_rate(params)) { 994 case 8000: 995 fs = DA732X_SR_8KHZ; 996 break; 997 case 11025: 998 fs = DA732X_SR_11_025KHZ; 999 break; 1000 case 12000: 1001 fs = DA732X_SR_12KHZ; 1002 break; 1003 case 16000: 1004 fs = DA732X_SR_16KHZ; 1005 break; 1006 case 22050: 1007 fs = DA732X_SR_22_05KHZ; 1008 break; 1009 case 24000: 1010 fs = DA732X_SR_24KHZ; 1011 break; 1012 case 32000: 1013 fs = DA732X_SR_32KHZ; 1014 break; 1015 case 44100: 1016 fs = DA732X_SR_44_1KHZ; 1017 break; 1018 case 48000: 1019 fs = DA732X_SR_48KHZ; 1020 break; 1021 case 88100: 1022 fs = DA732X_SR_88_1KHZ; 1023 break; 1024 case 96000: 1025 fs = DA732X_SR_96KHZ; 1026 break; 1027 default: 1028 return -EINVAL; 1029 } 1030 1031 snd_soc_update_bits(codec, reg_aif, DA732X_AIF_WORD_MASK, aif); 1032 snd_soc_update_bits(codec, DA732X_REG_CLK_CTRL, DA732X_SR1_MASK, fs); 1033 1034 return 0; 1035 } 1036 1037 static int da732x_set_dai_fmt(struct snd_soc_dai *dai, u32 fmt) 1038 { 1039 struct snd_soc_codec *codec = dai->codec; 1040 u32 aif_mclk, pc_count; 1041 u32 reg_aif1, aif1; 1042 u32 reg_aif3, aif3; 1043 1044 switch (dai->id) { 1045 case DA732X_DAI_ID1: 1046 reg_aif1 = DA732X_REG_AIFA1; 1047 reg_aif3 = DA732X_REG_AIFA3; 1048 pc_count = DA732X_PC_PULSE_AIFA | DA732X_PC_RESYNC_NOT_AUT | 1049 DA732X_PC_SAME; 1050 break; 1051 case DA732X_DAI_ID2: 1052 reg_aif1 = DA732X_REG_AIFB1; 1053 reg_aif3 = DA732X_REG_AIFB3; 1054 pc_count = DA732X_PC_PULSE_AIFB | DA732X_PC_RESYNC_NOT_AUT | 1055 DA732X_PC_SAME; 1056 break; 1057 default: 1058 return -EINVAL; 1059 } 1060 1061 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1062 case SND_SOC_DAIFMT_CBS_CFS: 1063 aif1 = DA732X_AIF_SLAVE; 1064 aif_mclk = DA732X_AIFM_FRAME_64 | DA732X_AIFM_SRC_SEL_AIFA; 1065 break; 1066 case SND_SOC_DAIFMT_CBM_CFM: 1067 aif1 = DA732X_AIF_CLK_FROM_SRC; 1068 aif_mclk = DA732X_CLK_GENERATION_AIF_A; 1069 break; 1070 default: 1071 return -EINVAL; 1072 } 1073 1074 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1075 case SND_SOC_DAIFMT_I2S: 1076 aif3 = DA732X_AIF_I2S_MODE; 1077 break; 1078 case SND_SOC_DAIFMT_RIGHT_J: 1079 aif3 = DA732X_AIF_RIGHT_J_MODE; 1080 break; 1081 case SND_SOC_DAIFMT_LEFT_J: 1082 aif3 = DA732X_AIF_LEFT_J_MODE; 1083 break; 1084 case SND_SOC_DAIFMT_DSP_B: 1085 aif3 = DA732X_AIF_DSP_MODE; 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 1091 /* Clock inversion */ 1092 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1093 case SND_SOC_DAIFMT_DSP_B: 1094 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1095 case SND_SOC_DAIFMT_NB_NF: 1096 break; 1097 case SND_SOC_DAIFMT_IB_NF: 1098 aif3 |= DA732X_AIF_BCLK_INV; 1099 break; 1100 default: 1101 return -EINVAL; 1102 } 1103 break; 1104 case SND_SOC_DAIFMT_I2S: 1105 case SND_SOC_DAIFMT_RIGHT_J: 1106 case SND_SOC_DAIFMT_LEFT_J: 1107 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1108 case SND_SOC_DAIFMT_NB_NF: 1109 break; 1110 case SND_SOC_DAIFMT_IB_IF: 1111 aif3 |= DA732X_AIF_BCLK_INV | DA732X_AIF_WCLK_INV; 1112 break; 1113 case SND_SOC_DAIFMT_IB_NF: 1114 aif3 |= DA732X_AIF_BCLK_INV; 1115 break; 1116 case SND_SOC_DAIFMT_NB_IF: 1117 aif3 |= DA732X_AIF_WCLK_INV; 1118 break; 1119 default: 1120 return -EINVAL; 1121 } 1122 break; 1123 default: 1124 return -EINVAL; 1125 } 1126 1127 snd_soc_write(codec, DA732X_REG_AIF_MCLK, aif_mclk); 1128 snd_soc_update_bits(codec, reg_aif1, DA732X_AIF1_CLK_MASK, aif1); 1129 snd_soc_update_bits(codec, reg_aif3, DA732X_AIF_BCLK_INV | 1130 DA732X_AIF_WCLK_INV | DA732X_AIF_MODE_MASK, aif3); 1131 snd_soc_write(codec, DA732X_REG_PC_CTRL, pc_count); 1132 1133 return 0; 1134 } 1135 1136 1137 1138 static int da732x_set_dai_pll(struct snd_soc_codec *codec, int pll_id, 1139 int source, unsigned int freq_in, 1140 unsigned int freq_out) 1141 { 1142 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec); 1143 int fref, indiv; 1144 u8 div_lo, div_mid, div_hi; 1145 u64 frac_div; 1146 1147 /* Disable PLL */ 1148 if (freq_out == 0) { 1149 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL, 1150 DA732X_PLL_EN, 0); 1151 da732x->pll_en = false; 1152 return 0; 1153 } 1154 1155 if (da732x->pll_en) 1156 return -EBUSY; 1157 1158 if (source == DA732X_SRCCLK_MCLK) { 1159 /* Validate Sysclk rate */ 1160 switch (da732x->sysclk) { 1161 case 11290000: 1162 case 12288000: 1163 case 22580000: 1164 case 24576000: 1165 case 45160000: 1166 case 49152000: 1167 snd_soc_write(codec, DA732X_REG_PLL_CTRL, 1168 DA732X_PLL_BYPASS); 1169 return 0; 1170 default: 1171 dev_err(codec->dev, 1172 "Cannot use PLL Bypass, invalid SYSCLK rate\n"); 1173 return -EINVAL; 1174 } 1175 } 1176 1177 indiv = da732x_get_input_div(codec, da732x->sysclk); 1178 if (indiv < 0) 1179 return indiv; 1180 1181 fref = (da732x->sysclk / indiv); 1182 div_hi = freq_out / fref; 1183 frac_div = (u64)(freq_out % fref) * 8192ULL; 1184 do_div(frac_div, fref); 1185 div_mid = (frac_div >> DA732X_1BYTE_SHIFT) & DA732X_U8_MASK; 1186 div_lo = (frac_div) & DA732X_U8_MASK; 1187 1188 snd_soc_write(codec, DA732X_REG_PLL_DIV_LO, div_lo); 1189 snd_soc_write(codec, DA732X_REG_PLL_DIV_MID, div_mid); 1190 snd_soc_write(codec, DA732X_REG_PLL_DIV_HI, div_hi); 1191 1192 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL, DA732X_PLL_EN, 1193 DA732X_PLL_EN); 1194 1195 da732x->pll_en = true; 1196 1197 return 0; 1198 } 1199 1200 static int da732x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 1201 unsigned int freq, int dir) 1202 { 1203 struct snd_soc_codec *codec = dai->codec; 1204 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec); 1205 1206 da732x->sysclk = freq; 1207 1208 return 0; 1209 } 1210 1211 #define DA732X_RATES SNDRV_PCM_RATE_8000_96000 1212 1213 #define DA732X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1214 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1215 1216 static struct snd_soc_dai_ops da732x_dai1_ops = { 1217 .hw_params = da732x_hw_params, 1218 .set_fmt = da732x_set_dai_fmt, 1219 .set_sysclk = da732x_set_dai_sysclk, 1220 }; 1221 1222 static struct snd_soc_dai_ops da732x_dai2_ops = { 1223 .hw_params = da732x_hw_params, 1224 .set_fmt = da732x_set_dai_fmt, 1225 .set_sysclk = da732x_set_dai_sysclk, 1226 }; 1227 1228 static struct snd_soc_dai_driver da732x_dai[] = { 1229 { 1230 .name = "DA732X_AIFA", 1231 .id = DA732X_DAI_ID1, 1232 .base = DA732X_REG_AIFA1, 1233 .playback = { 1234 .stream_name = "AIFA Playback", 1235 .channels_min = 1, 1236 .channels_max = 2, 1237 .rates = DA732X_RATES, 1238 .formats = DA732X_FORMATS, 1239 }, 1240 .capture = { 1241 .stream_name = "AIFA Capture", 1242 .channels_min = 1, 1243 .channels_max = 2, 1244 .rates = DA732X_RATES, 1245 .formats = DA732X_FORMATS, 1246 }, 1247 .ops = &da732x_dai1_ops, 1248 }, 1249 { 1250 .name = "DA732X_AIFB", 1251 .id = DA732X_DAI_ID2, 1252 .base = DA732X_REG_AIFB1, 1253 .playback = { 1254 .stream_name = "AIFB Playback", 1255 .channels_min = 1, 1256 .channels_max = 2, 1257 .rates = DA732X_RATES, 1258 .formats = DA732X_FORMATS, 1259 }, 1260 .capture = { 1261 .stream_name = "AIFB Capture", 1262 .channels_min = 1, 1263 .channels_max = 2, 1264 .rates = DA732X_RATES, 1265 .formats = DA732X_FORMATS, 1266 }, 1267 .ops = &da732x_dai2_ops, 1268 }, 1269 }; 1270 1271 static bool da732x_volatile(struct device *dev, unsigned int reg) 1272 { 1273 switch (reg) { 1274 case DA732X_REG_HPL_DAC_OFF_CNTL: 1275 case DA732X_REG_HPR_DAC_OFF_CNTL: 1276 return true; 1277 default: 1278 return false; 1279 } 1280 } 1281 1282 static const struct regmap_config da732x_regmap = { 1283 .reg_bits = 8, 1284 .val_bits = 8, 1285 1286 .max_register = DA732X_MAX_REG, 1287 .volatile_reg = da732x_volatile, 1288 .reg_defaults = da732x_reg_cache, 1289 .num_reg_defaults = ARRAY_SIZE(da732x_reg_cache), 1290 .cache_type = REGCACHE_RBTREE, 1291 }; 1292 1293 1294 static void da732x_dac_offset_adjust(struct snd_soc_codec *codec) 1295 { 1296 u8 offset[DA732X_HP_DACS]; 1297 u8 sign[DA732X_HP_DACS]; 1298 u8 step = DA732X_DAC_OFFSET_STEP; 1299 1300 /* Initialize DAC offset calibration circuits and registers */ 1301 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET, 1302 DA732X_HP_DAC_OFFSET_TRIM_VAL); 1303 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET, 1304 DA732X_HP_DAC_OFFSET_TRIM_VAL); 1305 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL, 1306 DA732X_HP_DAC_OFF_CALIBRATION | 1307 DA732X_HP_DAC_OFF_SCALE_STEPS); 1308 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL, 1309 DA732X_HP_DAC_OFF_CALIBRATION | 1310 DA732X_HP_DAC_OFF_SCALE_STEPS); 1311 1312 /* Wait for voltage stabilization */ 1313 msleep(DA732X_WAIT_FOR_STABILIZATION); 1314 1315 /* Check DAC offset sign */ 1316 sign[DA732X_HPL_DAC] = (codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & 1317 DA732X_HP_DAC_OFF_CNTL_COMPO); 1318 sign[DA732X_HPR_DAC] = (codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & 1319 DA732X_HP_DAC_OFF_CNTL_COMPO); 1320 1321 /* Binary search DAC offset values (both channels at once) */ 1322 offset[DA732X_HPL_DAC] = sign[DA732X_HPL_DAC] << DA732X_HP_DAC_COMPO_SHIFT; 1323 offset[DA732X_HPR_DAC] = sign[DA732X_HPR_DAC] << DA732X_HP_DAC_COMPO_SHIFT; 1324 1325 do { 1326 offset[DA732X_HPL_DAC] |= step; 1327 offset[DA732X_HPR_DAC] |= step; 1328 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET, 1329 ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK); 1330 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET, 1331 ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK); 1332 1333 msleep(DA732X_WAIT_FOR_STABILIZATION); 1334 1335 if ((codec->hw_read(codec, DA732X_REG_HPL_DAC_OFF_CNTL) & 1336 DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPL_DAC]) 1337 offset[DA732X_HPL_DAC] &= ~step; 1338 if ((codec->hw_read(codec, DA732X_REG_HPR_DAC_OFF_CNTL) & 1339 DA732X_HP_DAC_OFF_CNTL_COMPO) ^ sign[DA732X_HPR_DAC]) 1340 offset[DA732X_HPR_DAC] &= ~step; 1341 1342 step >>= 1; 1343 } while (step); 1344 1345 /* Write final DAC offsets to registers */ 1346 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFFSET, 1347 ~offset[DA732X_HPL_DAC] & DA732X_HP_DAC_OFF_MASK); 1348 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFFSET, 1349 ~offset[DA732X_HPR_DAC] & DA732X_HP_DAC_OFF_MASK); 1350 1351 /* End DAC calibration mode */ 1352 snd_soc_write(codec, DA732X_REG_HPL_DAC_OFF_CNTL, 1353 DA732X_HP_DAC_OFF_SCALE_STEPS); 1354 snd_soc_write(codec, DA732X_REG_HPR_DAC_OFF_CNTL, 1355 DA732X_HP_DAC_OFF_SCALE_STEPS); 1356 } 1357 1358 static void da732x_output_offset_adjust(struct snd_soc_codec *codec) 1359 { 1360 u8 offset[DA732X_HP_AMPS]; 1361 u8 sign[DA732X_HP_AMPS]; 1362 u8 step = DA732X_OUTPUT_OFFSET_STEP; 1363 1364 offset[DA732X_HPL_AMP] = DA732X_HP_OUT_TRIM_VAL; 1365 offset[DA732X_HPR_AMP] = DA732X_HP_OUT_TRIM_VAL; 1366 1367 /* Initialize output offset calibration circuits and registers */ 1368 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL); 1369 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, DA732X_HP_OUT_TRIM_VAL); 1370 snd_soc_write(codec, DA732X_REG_HPL, 1371 DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN); 1372 snd_soc_write(codec, DA732X_REG_HPR, 1373 DA732X_HP_OUT_COMP | DA732X_HP_OUT_EN); 1374 1375 /* Wait for voltage stabilization */ 1376 msleep(DA732X_WAIT_FOR_STABILIZATION); 1377 1378 /* Check output offset sign */ 1379 sign[DA732X_HPL_AMP] = codec->hw_read(codec, DA732X_REG_HPL) & 1380 DA732X_HP_OUT_COMPO; 1381 sign[DA732X_HPR_AMP] = codec->hw_read(codec, DA732X_REG_HPR) & 1382 DA732X_HP_OUT_COMPO; 1383 1384 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_COMP | 1385 (sign[DA732X_HPL_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) | 1386 DA732X_HP_OUT_EN); 1387 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_COMP | 1388 (sign[DA732X_HPR_AMP] >> DA732X_HP_OUT_COMPO_SHIFT) | 1389 DA732X_HP_OUT_EN); 1390 1391 /* Binary search output offset values (both channels at once) */ 1392 do { 1393 offset[DA732X_HPL_AMP] |= step; 1394 offset[DA732X_HPR_AMP] |= step; 1395 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, 1396 offset[DA732X_HPL_AMP]); 1397 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, 1398 offset[DA732X_HPR_AMP]); 1399 1400 msleep(DA732X_WAIT_FOR_STABILIZATION); 1401 1402 if ((codec->hw_read(codec, DA732X_REG_HPL) & 1403 DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPL_AMP]) 1404 offset[DA732X_HPL_AMP] &= ~step; 1405 if ((codec->hw_read(codec, DA732X_REG_HPR) & 1406 DA732X_HP_OUT_COMPO) ^ sign[DA732X_HPR_AMP]) 1407 offset[DA732X_HPR_AMP] &= ~step; 1408 1409 step >>= 1; 1410 } while (step); 1411 1412 /* Write final DAC offsets to registers */ 1413 snd_soc_write(codec, DA732X_REG_HPL_OUT_OFFSET, offset[DA732X_HPL_AMP]); 1414 snd_soc_write(codec, DA732X_REG_HPR_OUT_OFFSET, offset[DA732X_HPR_AMP]); 1415 } 1416 1417 static void da732x_hp_dc_offset_cancellation(struct snd_soc_codec *codec) 1418 { 1419 /* Make sure that we have Soft Mute enabled */ 1420 snd_soc_write(codec, DA732X_REG_DAC1_SOFTMUTE, DA732X_SOFTMUTE_EN | 1421 DA732X_GAIN_RAMPED | DA732X_16_SAMPLES); 1422 snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACL_EN | 1423 DA732X_DACR_EN | DA732X_DACL_SDM | DA732X_DACR_SDM | 1424 DA732X_DACL_MUTE | DA732X_DACR_MUTE); 1425 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_OUT_DAC_EN | 1426 DA732X_HP_OUT_MUTE | DA732X_HP_OUT_EN); 1427 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_OUT_EN | 1428 DA732X_HP_OUT_MUTE | DA732X_HP_OUT_DAC_EN); 1429 1430 da732x_dac_offset_adjust(codec); 1431 da732x_output_offset_adjust(codec); 1432 1433 snd_soc_write(codec, DA732X_REG_DAC1_SEL, DA732X_DACS_DIS); 1434 snd_soc_write(codec, DA732X_REG_HPL, DA732X_HP_DIS); 1435 snd_soc_write(codec, DA732X_REG_HPR, DA732X_HP_DIS); 1436 } 1437 1438 static int da732x_set_bias_level(struct snd_soc_codec *codec, 1439 enum snd_soc_bias_level level) 1440 { 1441 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec); 1442 1443 switch (level) { 1444 case SND_SOC_BIAS_ON: 1445 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN, 1446 DA732X_BIAS_BOOST_MASK, 1447 DA732X_BIAS_BOOST_100PC); 1448 break; 1449 case SND_SOC_BIAS_PREPARE: 1450 break; 1451 case SND_SOC_BIAS_STANDBY: 1452 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1453 /* Init Codec */ 1454 snd_soc_write(codec, DA732X_REG_REF1, 1455 DA732X_VMID_FASTCHG); 1456 snd_soc_write(codec, DA732X_REG_BIAS_EN, 1457 DA732X_BIAS_EN); 1458 1459 mdelay(DA732X_STARTUP_DELAY); 1460 1461 /* Disable Fast Charge and enable DAC ref voltage */ 1462 snd_soc_write(codec, DA732X_REG_REF1, 1463 DA732X_REFBUFX2_EN); 1464 1465 /* Enable bypass DSP routing */ 1466 snd_soc_write(codec, DA732X_REG_DATA_ROUTE, 1467 DA732X_BYPASS_DSP); 1468 1469 /* Enable Digital subsystem */ 1470 snd_soc_write(codec, DA732X_REG_DSP_CTRL, 1471 DA732X_DIGITAL_EN); 1472 1473 snd_soc_write(codec, DA732X_REG_SPARE1_OUT, 1474 DA732X_HP_DRIVER_EN | 1475 DA732X_HP_GATE_LOW | 1476 DA732X_HP_LOOP_GAIN_CTRL); 1477 snd_soc_write(codec, DA732X_REG_HP_LIN1_GNDSEL, 1478 DA732X_HP_OUT_GNDSEL); 1479 1480 da732x_set_charge_pump(codec, DA732X_ENABLE_CP); 1481 1482 snd_soc_write(codec, DA732X_REG_CLK_EN1, 1483 DA732X_SYS3_CLK_EN | DA732X_PC_CLK_EN); 1484 1485 /* Enable Zero Crossing */ 1486 snd_soc_write(codec, DA732X_REG_INP_ZC_EN, 1487 DA732X_MIC1_PRE_ZC_EN | 1488 DA732X_MIC1_ZC_EN | 1489 DA732X_MIC2_PRE_ZC_EN | 1490 DA732X_MIC2_ZC_EN | 1491 DA732X_AUXL_ZC_EN | 1492 DA732X_AUXR_ZC_EN | 1493 DA732X_MIC3_PRE_ZC_EN | 1494 DA732X_MIC3_ZC_EN); 1495 snd_soc_write(codec, DA732X_REG_OUT_ZC_EN, 1496 DA732X_HPL_ZC_EN | DA732X_HPR_ZC_EN | 1497 DA732X_LIN2_ZC_EN | DA732X_LIN3_ZC_EN | 1498 DA732X_LIN4_ZC_EN); 1499 1500 da732x_hp_dc_offset_cancellation(codec); 1501 1502 regcache_cache_only(codec->control_data, false); 1503 regcache_sync(codec->control_data); 1504 } else { 1505 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN, 1506 DA732X_BIAS_BOOST_MASK, 1507 DA732X_BIAS_BOOST_50PC); 1508 snd_soc_update_bits(codec, DA732X_REG_PLL_CTRL, 1509 DA732X_PLL_EN, 0); 1510 da732x->pll_en = false; 1511 } 1512 break; 1513 case SND_SOC_BIAS_OFF: 1514 regcache_cache_only(codec->control_data, true); 1515 da732x_set_charge_pump(codec, DA732X_DISABLE_CP); 1516 snd_soc_update_bits(codec, DA732X_REG_BIAS_EN, DA732X_BIAS_EN, 1517 DA732X_BIAS_DIS); 1518 da732x->pll_en = false; 1519 break; 1520 } 1521 1522 codec->dapm.bias_level = level; 1523 1524 return 0; 1525 } 1526 1527 static int da732x_probe(struct snd_soc_codec *codec) 1528 { 1529 struct da732x_priv *da732x = snd_soc_codec_get_drvdata(codec); 1530 struct snd_soc_dapm_context *dapm = &codec->dapm; 1531 int ret = 0; 1532 1533 da732x->codec = codec; 1534 1535 dapm->idle_bias_off = false; 1536 1537 codec->control_data = da732x->regmap; 1538 1539 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 1540 if (ret != 0) { 1541 dev_err(codec->dev, "Failed to register codec.\n"); 1542 goto err; 1543 } 1544 1545 da732x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1546 err: 1547 return ret; 1548 } 1549 1550 static int da732x_remove(struct snd_soc_codec *codec) 1551 { 1552 1553 da732x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1554 1555 return 0; 1556 } 1557 1558 static struct snd_soc_codec_driver soc_codec_dev_da732x = { 1559 .probe = da732x_probe, 1560 .remove = da732x_remove, 1561 .set_bias_level = da732x_set_bias_level, 1562 .controls = da732x_snd_controls, 1563 .num_controls = ARRAY_SIZE(da732x_snd_controls), 1564 .dapm_widgets = da732x_dapm_widgets, 1565 .num_dapm_widgets = ARRAY_SIZE(da732x_dapm_widgets), 1566 .dapm_routes = da732x_dapm_routes, 1567 .num_dapm_routes = ARRAY_SIZE(da732x_dapm_routes), 1568 .set_pll = da732x_set_dai_pll, 1569 .reg_cache_size = ARRAY_SIZE(da732x_reg_cache), 1570 }; 1571 1572 static int da732x_i2c_probe(struct i2c_client *i2c, 1573 const struct i2c_device_id *id) 1574 { 1575 struct da732x_priv *da732x; 1576 unsigned int reg; 1577 int ret; 1578 1579 da732x = devm_kzalloc(&i2c->dev, sizeof(struct da732x_priv), 1580 GFP_KERNEL); 1581 if (!da732x) 1582 return -ENOMEM; 1583 1584 i2c_set_clientdata(i2c, da732x); 1585 1586 da732x->regmap = devm_regmap_init_i2c(i2c, &da732x_regmap); 1587 if (IS_ERR(da732x->regmap)) { 1588 ret = PTR_ERR(da732x->regmap); 1589 dev_err(&i2c->dev, "Failed to initialize regmap\n"); 1590 goto err; 1591 } 1592 1593 ret = regmap_read(da732x->regmap, DA732X_REG_ID, ®); 1594 if (ret < 0) { 1595 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 1596 goto err; 1597 } 1598 1599 dev_info(&i2c->dev, "Revision: %d.%d\n", 1600 (reg & DA732X_ID_MAJOR_MASK), (reg & DA732X_ID_MINOR_MASK)); 1601 1602 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_da732x, 1603 da732x_dai, ARRAY_SIZE(da732x_dai)); 1604 if (ret != 0) 1605 dev_err(&i2c->dev, "Failed to register codec.\n"); 1606 1607 err: 1608 return ret; 1609 } 1610 1611 static int da732x_i2c_remove(struct i2c_client *client) 1612 { 1613 snd_soc_unregister_codec(&client->dev); 1614 1615 return 0; 1616 } 1617 1618 static const struct i2c_device_id da732x_i2c_id[] = { 1619 { "da7320", 0}, 1620 { } 1621 }; 1622 MODULE_DEVICE_TABLE(i2c, da732x_i2c_id); 1623 1624 static struct i2c_driver da732x_i2c_driver = { 1625 .driver = { 1626 .name = "da7320", 1627 .owner = THIS_MODULE, 1628 }, 1629 .probe = da732x_i2c_probe, 1630 .remove = da732x_i2c_remove, 1631 .id_table = da732x_i2c_id, 1632 }; 1633 1634 module_i2c_driver(da732x_i2c_driver); 1635 1636 1637 MODULE_DESCRIPTION("ASoC DA732X driver"); 1638 MODULE_AUTHOR("Michal Hajduk <michal.hajduk@diasemi.com>"); 1639 MODULE_LICENSE("GPL"); 1640