1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Regmap tables and other data for Cirrus Logic CS48L32 audio DSP. 4 // 5 // Copyright (C) 2018, 2020, 2022, 2025 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/build_bug.h> 10 #include <linux/device.h> 11 #include <linux/linear_range.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <sound/cs48l32.h> 15 #include <sound/cs48l32_registers.h> 16 17 #include "cs48l32.h" 18 19 static const struct reg_sequence cs48l32_reva_patch[] = { 20 { 0x00001044, 0x0005000f }, 21 { 0x00001c34, 0x000037e8 }, 22 { 0x000046d8, 0x00000fe0 }, 23 }; 24 25 int cs48l32_apply_patch(struct cs48l32 *cs48l32) 26 { 27 int ret; 28 29 ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch, 30 ARRAY_SIZE(cs48l32_reva_patch)); 31 if (ret < 0) 32 return dev_err_probe(cs48l32->dev, ret, "Failed to apply patch\n"); 33 34 return 0; 35 } 36 37 static const struct reg_default cs48l32_reg_default[] = { 38 { 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */ 39 { 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */ 40 { 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */ 41 { 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */ 42 { 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */ 43 { 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */ 44 { 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */ 45 { 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */ 46 { 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */ 47 { 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */ 48 { 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */ 49 { 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */ 50 { 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */ 51 { 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */ 52 { 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */ 53 { 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */ 54 { 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */ 55 { 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */ 56 { 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */ 57 { 0x00001400, 0x00000002 }, /* CLOCK32K */ 58 { 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */ 59 { 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */ 60 { 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */ 61 { 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */ 62 { 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */ 63 { 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */ 64 { 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */ 65 { 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */ 66 { 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */ 67 { 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */ 68 { 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */ 69 { 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */ 70 { 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */ 71 { 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */ 72 { 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */ 73 { 0x00004000, 0x00000000 }, /* INPUT_CONTROL */ 74 { 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */ 75 { 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */ 76 { 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */ 77 { 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */ 78 { 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */ 79 { 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */ 80 { 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */ 81 { 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */ 82 { 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */ 83 { 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */ 84 { 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */ 85 { 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */ 86 { 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */ 87 { 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */ 88 { 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */ 89 { 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */ 90 { 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */ 91 { 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */ 92 { 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */ 93 { 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */ 94 { 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */ 95 { 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */ 96 { 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */ 97 { 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */ 98 { 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */ 99 { 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */ 100 { 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */ 101 { 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */ 102 { 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */ 103 { 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */ 104 { 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */ 105 { 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */ 106 { 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */ 107 { 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */ 108 { 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */ 109 { 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */ 110 { 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */ 111 { 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */ 112 { 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */ 113 { 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */ 114 { 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */ 115 { 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */ 116 { 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */ 117 { 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */ 118 { 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */ 119 { 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */ 120 { 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */ 121 { 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */ 122 { 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */ 123 { 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */ 124 { 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */ 125 { 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */ 126 { 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */ 127 { 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */ 128 { 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */ 129 { 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */ 130 { 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */ 131 { 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */ 132 { 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */ 133 { 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */ 134 { 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */ 135 { 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */ 136 { 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */ 137 { 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */ 138 { 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */ 139 { 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */ 140 { 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */ 141 { 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */ 142 { 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */ 143 { 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */ 144 { 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */ 145 { 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */ 146 { 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */ 147 { 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */ 148 { 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */ 149 { 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */ 150 { 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */ 151 { 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */ 152 { 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */ 153 { 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */ 154 { 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */ 155 { 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */ 156 { 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */ 157 { 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */ 158 { 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */ 159 { 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */ 160 { 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */ 161 { 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */ 162 { 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */ 163 { 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */ 164 { 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */ 165 { 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */ 166 { 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */ 167 { 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */ 168 { 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */ 169 { 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */ 170 { 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */ 171 { 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */ 172 { 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */ 173 { 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */ 174 { 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */ 175 { 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */ 176 { 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */ 177 { 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */ 178 { 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */ 179 { 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */ 180 { 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */ 181 { 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */ 182 { 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */ 183 { 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */ 184 { 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */ 185 { 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */ 186 { 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */ 187 { 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */ 188 { 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */ 189 { 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */ 190 { 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */ 191 { 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */ 192 { 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */ 193 { 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */ 194 { 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */ 195 { 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */ 196 { 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */ 197 { 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */ 198 { 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */ 199 { 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */ 200 { 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */ 201 { 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */ 202 { 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */ 203 { 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */ 204 { 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */ 205 { 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */ 206 { 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */ 207 { 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */ 208 { 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */ 209 { 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */ 210 { 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */ 211 { 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */ 212 { 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */ 213 { 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */ 214 { 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */ 215 { 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */ 216 { 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */ 217 { 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */ 218 { 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */ 219 { 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */ 220 { 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */ 221 { 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */ 222 { 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */ 223 { 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */ 224 { 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */ 225 { 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */ 226 { 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */ 227 { 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */ 228 { 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */ 229 { 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */ 230 { 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */ 231 { 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */ 232 { 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */ 233 { 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */ 234 { 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */ 235 { 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */ 236 { 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */ 237 { 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */ 238 { 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */ 239 { 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */ 240 { 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */ 241 { 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */ 242 { 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */ 243 { 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */ 244 { 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */ 245 { 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */ 246 { 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */ 247 { 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */ 248 { 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */ 249 { 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */ 250 { 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */ 251 { 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */ 252 { 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */ 253 { 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */ 254 { 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */ 255 { 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */ 256 { 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */ 257 { 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */ 258 { 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */ 259 { 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */ 260 { 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */ 261 { 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */ 262 { 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */ 263 { 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */ 264 { 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */ 265 { 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */ 266 { 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */ 267 { 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */ 268 { 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */ 269 { 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */ 270 { 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */ 271 { 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */ 272 { 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */ 273 { 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */ 274 { 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */ 275 { 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */ 276 { 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */ 277 { 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */ 278 { 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */ 279 { 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */ 280 { 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */ 281 { 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */ 282 { 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */ 283 { 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */ 284 { 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */ 285 { 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */ 286 { 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */ 287 { 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */ 288 { 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */ 289 { 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */ 290 { 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */ 291 { 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */ 292 { 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */ 293 { 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */ 294 { 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */ 295 { 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */ 296 { 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */ 297 { 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */ 298 { 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */ 299 { 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */ 300 { 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */ 301 { 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */ 302 { 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */ 303 { 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */ 304 { 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */ 305 { 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */ 306 { 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */ 307 { 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */ 308 { 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */ 309 { 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */ 310 { 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */ 311 { 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */ 312 { 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */ 313 { 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */ 314 { 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */ 315 { 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */ 316 { 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */ 317 { 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */ 318 { 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */ 319 { 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */ 320 { 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */ 321 { 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */ 322 { 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */ 323 { 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */ 324 { 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */ 325 { 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */ 326 { 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */ 327 { 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */ 328 { 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */ 329 { 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */ 330 { 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */ 331 { 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */ 332 { 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */ 333 { 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */ 334 { 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */ 335 { 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */ 336 { 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */ 337 { 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */ 338 { 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */ 339 { 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */ 340 { 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */ 341 { 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */ 342 { 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */ 343 { 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */ 344 { 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */ 345 { 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */ 346 { 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */ 347 { 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */ 348 { 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */ 349 { 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */ 350 { 0x0000b800, 0x00000000 }, /* US_CONTROL */ 351 { 0x0000b804, 0x00002020 }, /* US1_CONTROL */ 352 { 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */ 353 { 0x0000b814, 0x00002020 }, /* US2_CONTROL */ 354 { 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */ 355 { 0x00018110, 0x00000700 }, /* IRQ1_MASK_1 */ 356 { 0x00018114, 0x00000004 }, /* IRQ1_MASK_2 */ 357 { 0x00018120, 0x03ff0000 }, /* IRQ1_MASK_5 */ 358 { 0x00018124, 0x00000103 }, /* IRQ1_MASK_6 */ 359 { 0x00018128, 0x003f0000 }, /* IRQ1_MASK_7 */ 360 { 0x00018130, 0xff00000f }, /* IRQ1_MASK_9 */ 361 { 0x00018138, 0xffff0000 }, /* IRQ1_MASK_11 */ 362 }; 363 364 static bool cs48l32_readable_register(struct device *dev, unsigned int reg) 365 { 366 switch (reg) { 367 case CS48L32_DEVID: 368 case CS48L32_REVID: 369 case CS48L32_OTPID: 370 case CS48L32_SFT_RESET: 371 case CS48L32_CTRL_IF_DEBUG3: 372 case CS48L32_MCU_CTRL1: 373 case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1: 374 case CS48L32_OUTPUT_SYS_CLK: 375 case CS48L32_AUXPDM_CTRL: 376 case CS48L32_AUXPDM_CTRL2: 377 case CS48L32_CLOCK32K: 378 case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2: 379 case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4: 380 case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK: 381 case CS48L32_CHARGE_PUMP1: 382 case CS48L32_LDO2_CTRL1: 383 case CS48L32_MICBIAS_CTRL1: 384 case CS48L32_MICBIAS_CTRL5: 385 case CS48L32_IRQ1_CTRL_AOD: 386 case CS48L32_INPUT_CONTROL: 387 case CS48L32_INPUT_STATUS: 388 case CS48L32_INPUT_RATE_CONTROL: 389 case CS48L32_INPUT_CONTROL2: 390 case CS48L32_INPUT_CONTROL3: 391 case CS48L32_INPUT1_CONTROL1: 392 case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2: 393 case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2: 394 case CS48L32_INPUT2_CONTROL1: 395 case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2: 396 case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2: 397 case CS48L32_INPUT_HPF_CONTROL: 398 case CS48L32_INPUT_VOL_CONTROL: 399 case CS48L32_AUXPDM_CONTROL1: 400 case CS48L32_AUXPDM_CONTROL2: 401 case CS48L32_AUXPDM1_CONTROL1: 402 case CS48L32_AUXPDM2_CONTROL1: 403 case CS48L32_ADC1L_ANA_CONTROL1: 404 case CS48L32_ADC1R_ANA_CONTROL1: 405 case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5: 406 case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5: 407 case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4: 408 case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4: 409 case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1: 410 case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1: 411 case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1: 412 case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4: 413 case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4: 414 case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4: 415 case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4: 416 case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4: 417 case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4: 418 case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4: 419 case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4: 420 case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2: 421 case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2: 422 case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2: 423 case CS48L32_FX_SAMPLE_RATE: 424 case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2: 425 case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG: 426 case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG: 427 case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG: 428 case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG: 429 case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2: 430 case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF: 431 case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4: 432 case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4: 433 case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2: 434 case CS48L32_COMFORT_NOISE_GENERATOR: 435 case CS48L32_US_CONTROL: 436 case CS48L32_US1_CONTROL: 437 case CS48L32_US1_DET_CONTROL: 438 case CS48L32_US2_CONTROL: 439 case CS48L32_US2_DET_CONTROL: 440 case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: 441 case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: 442 case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: 443 case CS48L32_IRQ1_STATUS: 444 case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: 445 case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: 446 case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11: 447 case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST: 448 case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: 449 case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_LAST: 450 case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: 451 case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: 452 case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: 453 case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST: 454 case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_LAST: 455 case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST: 456 return true; 457 default: 458 return false; 459 } 460 } 461 462 static bool cs48l32_volatile_register(struct device *dev, unsigned int reg) 463 { 464 switch (reg) { 465 case CS48L32_DEVID: 466 case CS48L32_REVID: 467 case CS48L32_OTPID: 468 case CS48L32_SFT_RESET: 469 case CS48L32_CTRL_IF_DEBUG3: 470 case CS48L32_MCU_CTRL1: 471 case CS48L32_SYSTEM_CLOCK2: 472 case CS48L32_FLL1_CONTROL5: 473 case CS48L32_FLL1_CONTROL6: 474 case CS48L32_INPUT_STATUS: 475 case CS48L32_INPUT_CONTROL3: 476 case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24: 477 case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8: 478 case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7: 479 case CS48L32_IRQ1_STATUS: 480 case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11: 481 case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11: 482 case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST: 483 case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1: 484 case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_LAST: 485 case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8: 486 case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4: 487 case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1: 488 case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST: 489 case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_LAST: 490 case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST: 491 return true; 492 default: 493 return false; 494 } 495 } 496 497 /* 498 * The bus bridge requires DSP packed memory registers to be accessed in 499 * aligned block multiples. 500 * Mark precious to prevent regmap debugfs causing an illegal bus transaction. 501 */ 502 static bool cs48l32_precious_register(struct device *dev, unsigned int reg) 503 { 504 switch (reg) { 505 case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST: 506 case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST: 507 case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST: 508 return true; 509 default: 510 return false; 511 } 512 } 513 514 static const struct regmap_config cs48l32_regmap = { 515 .name = "cs48l32", 516 .reg_bits = 32, 517 .reg_stride = 4, 518 .pad_bits = 32, 519 .val_bits = 32, 520 .reg_format_endian = REGMAP_ENDIAN_BIG, 521 .val_format_endian = REGMAP_ENDIAN_BIG, 522 523 .max_register = CS48L32_DSP1_PMEM_LAST, 524 .readable_reg = &cs48l32_readable_register, 525 .volatile_reg = &cs48l32_volatile_register, 526 .precious_reg = &cs48l32_precious_register, 527 528 .cache_type = REGCACHE_MAPLE, 529 .reg_defaults = cs48l32_reg_default, 530 .num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default), 531 }; 532 533 int cs48l32_create_regmap(struct spi_device *spi, struct cs48l32 *cs48l32) 534 { 535 cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_regmap); 536 if (IS_ERR(cs48l32->regmap)) 537 return PTR_ERR(cs48l32->regmap); 538 539 return 0; 540 } 541