1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) The Asahi Linux Contributors 4 * 5 * Based on sound/soc/codecs/cs42l42.h 6 * 7 * Copyright 2016 Cirrus Logic, Inc. 8 */ 9 10 11 #ifndef __CS42L84_H__ 12 #define __CS42L84_H__ 13 14 #include <linux/bits.h> 15 16 #define CS42L84_CHIP_ID 0x42a84 17 18 #define CS42L84_DEVID 0x0000 19 #define CS42L84_REVID 0x73fe 20 #define CS42L84_FRZ_CTL 0x0006 21 #define CS42L84_FRZ_CTL_ENGAGE BIT(0) 22 23 #define CS42L84_TSRS_PLUG_INT_STATUS 0x0400 24 #define CS42L84_TSRS_PLUG_INT_MASK 0x0418 25 #define CS42L84_RS_PLUG_SHIFT 0 26 #define CS42L84_RS_PLUG BIT(0) 27 #define CS42L84_RS_UNPLUG BIT(1) 28 #define CS42L84_TS_PLUG_SHIFT 2 29 #define CS42L84_TS_PLUG BIT(2) 30 #define CS42L84_TS_UNPLUG BIT(3) 31 #define CS42L84_TSRS_PLUG_VAL_MASK GENMASK(3, 0) 32 #define CS42L84_PLL_LOCK_STATUS 0x040e // probably bit 0x10 33 #define CS42L84_PLL_LOCK_STATUS_LOCKED BIT(4) 34 #define CS42L84_PLL_LOCK_STATUS_ERROR BIT(5) 35 36 #define CS42L84_PLUG 3 37 #define CS42L84_UNPLUG 0 38 #define CS42L84_TRANS 1 39 40 #define CS42L84_CCM_CTL1 0x0600 41 #define CS42L84_CCM_CTL1_MCLK_SRC GENMASK(1, 0) 42 #define CS42L84_CCM_CTL1_MCLK_SRC_RCO 0 43 #define CS42L84_CCM_CTL1_MCLK_SRC_MCLK 1 44 #define CS42L84_CCM_CTL1_MCLK_SRC_BCLK 2 45 #define CS42L84_CCM_CTL1_MCLK_SRC_PLL 3 46 #define CS42L84_CCM_CTL1_MCLK_FREQ GENMASK(3, 2) 47 #define CS42L84_CCM_CTL1_MCLK_F_12MHZ 0b00 48 #define CS42L84_CCM_CTL1_MCLK_F_24MHZ 0b01 49 #define CS42L84_CCM_CTL1_MCLK_F_12_288KHZ 0b10 50 #define CS42L84_CCM_CTL1_MCLK_F_24_576KHZ 0b11 51 #define CS42L84_CCM_CTL1_RCO \ 52 (FIELD_PREP(CS42L84_CCM_CTL1_MCLK_SRC, CS42L84_CCM_CTL1_MCLK_SRC_RCO) \ 53 | FIELD_PREP(CS42L84_CCM_CTL1_MCLK_FREQ, CS42L84_CCM_CTL1_MCLK_F_12MHZ)) 54 55 #define CS42L84_CCM_SAMP_RATE 0x0601 56 #define CS42L84_CCM_SAMP_RATE_RATE_48KHZ 4 57 #define CS42L84_CCM_SAMP_RATE_RATE_96KHZ 5 58 #define CS42L84_CCM_SAMP_RATE_RATE_192KHZ 6 59 #define CS42L84_CCM_SAMP_RATE_RATE_44K1HZ 12 60 #define CS42L84_CCM_SAMP_RATE_RATE_88K2HZ 13 61 #define CS42L84_CCM_SAMP_RATE_RATE_176K4HZ 14 62 #define CS42L84_CCM_CTL3 0x0602 63 #define CS42L84_CCM_CTL3_REFCLK_DIV GENMASK(2, 1) 64 #define CS42L84_CCM_CTL4 0x0603 65 #define CS42L84_CCM_CTL4_REFCLK_EN BIT(0) 66 67 #define CS42L84_CCM_ASP_CLK_CTRL 0x0608 68 69 #define CS42L84_PLL_CTL1 0x0800 70 #define CS42L84_PLL_CTL1_EN BIT(0) 71 #define CS42L84_PLL_CTL1_MODE GENMASK(2, 1) 72 #define CS42L84_PLL_DIV_FRAC0 0x0804 73 #define CS42L84_PLL_DIV_FRAC1 0x0805 74 #define CS42L84_PLL_DIV_FRAC2 0x0806 75 #define CS42L84_PLL_DIV_INT 0x0807 76 #define CS42L84_PLL_DIVOUT 0x0808 77 78 #define CS42L84_RING_SENSE_CTL 0x1282 79 #define CS42L84_RING_SENSE_CTL_INV BIT(7) 80 #define CS42L84_RING_SENSE_CTL_UNK1 BIT(6) 81 #define CS42L84_RING_SENSE_CTL_FALLTIME GENMASK(5, 3) 82 #define CS42L84_RING_SENSE_CTL_RISETIME GENMASK(2, 0) 83 #define CS42L84_TIP_SENSE_CTL 0x1283 84 #define CS42L84_TIP_SENSE_CTL_INV BIT(7) 85 #define CS42L84_TIP_SENSE_CTL_FALLTIME GENMASK(5, 3) 86 #define CS42L84_TIP_SENSE_CTL_RISETIME GENMASK(2, 0) 87 88 #define CS42L84_TSRS_PLUG_STATUS 0x1288 89 90 #define CS42L84_TIP_SENSE_CTL2 0x1473 91 #define CS42L84_TIP_SENSE_CTL2_MODE GENMASK(7, 6) 92 #define CS42L84_TIP_SENSE_CTL2_MODE_DISABLED 0b00 93 #define CS42L84_TIP_SENSE_CTL2_MODE_DIG_INPUT 0b01 94 #define CS42L84_TIP_SENSE_CTL2_MODE_SHORT_DET 0b11 95 #define CS42L84_TIP_SENSE_CTL2_INV BIT(5) 96 97 #define CS42L84_MISC_DET_CTL 0x1474 98 #define CS42L84_MISC_DET_CTL_DETECT_MODE GENMASK(4, 3) 99 #define CS42L84_MISC_DET_CTL_HSBIAS_CTL GENMASK(2, 1) 100 #define CS42L84_MISC_DET_CTL_PDN_MIC_LVL_DET BIT(0) 101 102 #define CS42L84_MIC_DET_CTL1 0x1475 103 #define CS42L84_MIC_DET_CTL1_HS_DET_LEVEL GENMASK(5, 0) 104 105 #define CS42L84_MIC_DET_CTL4 0x1477 106 #define CS42L84_MIC_DET_CTL4_LATCH_TO_VP BIT(1) 107 108 #define CS42L84_HS_DET_STATUS2 0x147d 109 110 #define CS42L84_MSM_BLOCK_EN1 0x1800 111 #define CS42L84_MSM_BLOCK_EN2 0x1801 112 #define CS42L84_MSM_BLOCK_EN2_ASP_SHIFT 6 113 #define CS42L84_MSM_BLOCK_EN2_BUS_SHIFT 5 114 #define CS42L84_MSM_BLOCK_EN2_DAC_SHIFT 4 115 #define CS42L84_MSM_BLOCK_EN2_ADC_SHIFT 3 116 #define CS42L84_MSM_BLOCK_EN3 0x1802 117 #define CS42L84_MSM_BLOCK_EN3_TR_SENSE BIT(3) 118 119 #define CS42L84_HS_DET_CTL2 0x1811 120 #define CS42L84_HS_DET_CTL2_CTL GENMASK(7, 6) 121 #define CS42L84_HS_DET_CTL2_SET GENMASK(5, 4) 122 #define CS42L84_HS_DET_CTL2_REF BIT(3) 123 #define CS42L84_HS_DET_CTL2_AUTO_TIME GENMASK(1, 0) 124 125 #define CS42L84_HS_SWITCH_CTL 0x1812 126 #define CS42L84_HS_SWITCH_CTL_REF_HS3 BIT(7) 127 #define CS42L84_HS_SWITCH_CTL_REF_HS4 BIT(6) 128 #define CS42L84_HS_SWITCH_CTL_HSB_FILT_HS3 BIT(5) 129 #define CS42L84_HS_SWITCH_CTL_HSB_FILT_HS4 BIT(4) 130 #define CS42L84_HS_SWITCH_CTL_HSB_HS3 BIT(3) 131 #define CS42L84_HS_SWITCH_CTL_HSB_HS4 BIT(2) 132 #define CS42L84_HS_SWITCH_CTL_GNDHS_HS3 BIT(1) 133 #define CS42L84_HS_SWITCH_CTL_GNDHS_HS4 BIT(0) 134 135 #define CS42L84_HS_CLAMP_DISABLE 0x1813 136 137 #define CS42L84_ADC_CTL1 0x2000 138 #define CS42L84_ADC_CTL1_PREAMP_GAIN_SHIFT 6 139 #define CS42L84_ADC_CTL1_PGA_GAIN_SHIFT 0 140 #define CS42L84_ADC_CTL4 0x2003 141 #define CS42L84_ADC_CTL4_WNF_CF_SHIFT 4 142 #define CS42L84_ADC_CTL4_WNF_EN_SHIFT 3 143 #define CS42L84_ADC_CTL4_HPF_CF_SHIFT 1 144 #define CS42L84_ADC_CTL4_HPF_EN_SHIFT 0 145 146 #define CS42L84_DAC_CTL1 0x3000 147 #define CS42L84_DAC_CTL1_UNMUTE BIT(0) 148 //#define CS42L84_DAC_CTL1_DACB_INV_SHIFT 1 149 //#define CS42L84_DAC_CTL1_DACA_INV_SHIFT 0 150 #define CS42L84_DAC_CTL2 0x3001 151 152 #define CS42L84_DAC_CHA_VOL_LSB 0x3004 153 #define CS42L84_DAC_CHA_VOL_MSB 0x3005 154 #define CS42L84_DAC_CHB_VOL_LSB 0x3006 155 #define CS42L84_DAC_CHB_VOL_MSB 0x3007 156 #define CS42L84_HP_VOL_CTL 0x3020 157 #define CS42L84_HP_VOL_CTL_ZERO_CROSS BIT(1) 158 #define CS42L84_HP_VOL_CTL_SOFT BIT(0) 159 160 #define CS42L84_SRC_ASP_RX_CH1 0b1101 161 #define CS42L84_SRC_ASP_RX_CH2 0b1110 162 163 #define CS42L84_BUS_ASP_TX_SRC 0x4000 164 #define CS42L84_BUS_ASP_TX_SRC_CH1_SHIFT 0 165 #define CS42L84_BUS_DAC_SRC 0x4001 166 #define CS42L84_BUS_DAC_SRC_DACA_SHIFT 0 167 #define CS42L84_BUS_DAC_SRC_DACB_SHIFT 4 168 169 #define CS42L84_ASP_CTL 0x5000 170 #define CS42L84_ASP_CTL_BCLK_EN_SHIFT 1 171 #define CS42L84_ASP_CTL_TDM_MODE BIT(2) 172 #define CS42L84_ASP_FSYNC_CTL2 0x5010 173 #define CS42L84_ASP_FSYNC_CTL2_BCLK_PERIOD_LO GENMASK(7, 1) 174 #define CS42L84_ASP_FSYNC_CTL3 0x5011 175 #define CS42L84_ASP_FSYNC_CTL3_BCLK_PERIOD_HI GENMASK(4, 0) 176 #define CS42L84_ASP_DATA_CTL 0x5018 177 178 #define CS42L84_ASP_RX_EN 0x5020 179 #define CS42L84_ASP_RX_EN_CH1_SHIFT 0 180 #define CS42L84_ASP_RX_EN_CH2_SHIFT 1 181 #define CS42L84_ASP_TX_EN 0x5024 182 #define CS42L84_ASP_TX_EN_CH1_SHIFT 0 183 184 #define CS42L84_ASP_RX_CH1_CTL1 0x5028 185 #define CS42L84_ASP_RX_CH1_CTL2 0x5029 186 #define CS42L84_ASP_RX_CH1_WIDTH 0x502a 187 #define CS42L84_ASP_RX_CH2_CTL1 0x502c 188 #define CS42L84_ASP_RX_CH2_CTL2 0x502d 189 #define CS42L84_ASP_RX_CH2_WIDTH 0x502e 190 191 #define CS42L84_ASP_RX_CHx_CTL1_EDGE BIT(0) 192 #define CS42L84_ASP_RX_CHx_CTL1_SLOT_START_LSB GENMASK(7, 1) 193 #define CS42L84_ASP_RX_CHx_CTL2_SLOT_START_MSB GENMASK(2, 0) 194 195 #define CS42L84_ASP_TX_CH1_CTL1 0x5068 196 #define CS42L84_ASP_TX_CH1_CTL2 0x5069 197 #define CS42L84_ASP_TX_CH1_WIDTH 0x506a 198 #define CS42L84_ASP_TX_CH2_CTL1 0x506c 199 #define CS42L84_ASP_TX_CH2_CTL2 0x506d 200 #define CS42L84_ASP_TX_CH2_WIDTH 0x506e 201 202 #define CS42L84_DEBOUNCE_TIME_125MS 0b001 203 #define CS42L84_DEBOUNCE_TIME_500MS 0b011 204 205 #define CS42L84_BOOT_TIME_US 3000 206 #define CS42L84_CLOCK_SWITCH_DELAY_US 150 207 #define CS42L84_PLL_LOCK_POLL_US 250 208 #define CS42L84_PLL_LOCK_TIMEOUT_US 1250 209 210 #endif /* __CS42L84_H__ */ 211