1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // CS42L43 CODEC driver 4 // 5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/bitops.h> 9 #include <linux/bits.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/errno.h> 14 #include <linux/find.h> 15 #include <linux/gcd.h> 16 #include <linux/irq.h> 17 #include <linux/irqdomain.h> 18 #include <linux/jiffies.h> 19 #include <linux/mfd/cs42l43.h> 20 #include <linux/mfd/cs42l43-regs.h> 21 #include <linux/mod_devicetable.h> 22 #include <linux/module.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/string.h> 27 #include <linux/workqueue.h> 28 #include <sound/control.h> 29 #include <sound/cs42l43.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc-component.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/soc-dai.h> 35 #include <sound/soc.h> 36 #include <sound/tlv.h> 37 38 #include "cs42l43.h" 39 40 #define CS42L43_DECL_MUX(name, reg) \ 41 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ 42 0, CS42L43_MIXER_SRC_MASK, \ 43 cs42l43_mixer_texts, cs42l43_mixer_values); \ 44 static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 45 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 46 47 #define CS42L43_DECL_MIXER(name, reg) \ 48 CS42L43_DECL_MUX(name##_in1, reg); \ 49 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ 50 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ 51 CS42L43_DECL_MUX(name##_in4, reg + 0xC) 52 53 #define CS42L43_DAPM_MUX(name_str, name) \ 54 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) 55 56 #define CS42L43_DAPM_MIXER(name_str, name) \ 57 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \ 58 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \ 59 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \ 60 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \ 61 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) 62 63 #define CS42L43_BASE_ROUTES(name_str) \ 64 { name_str, "Tone Generator 1", "Tone 1" }, \ 65 { name_str, "Tone Generator 2", "Tone 2" }, \ 66 { name_str, "Decimator 1", "Decimator 1" }, \ 67 { name_str, "Decimator 2", "Decimator 2" }, \ 68 { name_str, "Decimator 3", "Decimator 3" }, \ 69 { name_str, "Decimator 4", "Decimator 4" }, \ 70 { name_str, "ASPRX1", "ASPRX1" }, \ 71 { name_str, "ASPRX2", "ASPRX2" }, \ 72 { name_str, "ASPRX3", "ASPRX3" }, \ 73 { name_str, "ASPRX4", "ASPRX4" }, \ 74 { name_str, "ASPRX5", "ASPRX5" }, \ 75 { name_str, "ASPRX6", "ASPRX6" }, \ 76 { name_str, "DP5RX1", "DP5RX1" }, \ 77 { name_str, "DP5RX2", "DP5RX2" }, \ 78 { name_str, "DP6RX1", "DP6RX1" }, \ 79 { name_str, "DP6RX2", "DP6RX2" }, \ 80 { name_str, "DP7RX1", "DP7RX1" }, \ 81 { name_str, "DP7RX2", "DP7RX2" }, \ 82 { name_str, "ASRC INT1", "ASRC_INT1" }, \ 83 { name_str, "ASRC INT2", "ASRC_INT2" }, \ 84 { name_str, "ASRC INT3", "ASRC_INT3" }, \ 85 { name_str, "ASRC INT4", "ASRC_INT4" }, \ 86 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \ 87 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \ 88 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \ 89 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \ 90 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \ 91 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \ 92 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \ 93 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \ 94 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \ 95 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \ 96 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \ 97 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \ 98 { name_str, "EQ1", "EQ" }, \ 99 { name_str, "EQ2", "EQ" } 100 101 #define CS42L43_MUX_ROUTES(name_str, widget) \ 102 { widget, NULL, name_str " Input" }, \ 103 { name_str " Input", NULL, "Mixer Core" }, \ 104 CS42L43_BASE_ROUTES(name_str " Input") 105 106 #define CS42L43_MIXER_ROUTES(name_str, widget) \ 107 { name_str " Mixer", NULL, name_str " Input 1" }, \ 108 { name_str " Mixer", NULL, name_str " Input 2" }, \ 109 { name_str " Mixer", NULL, name_str " Input 3" }, \ 110 { name_str " Mixer", NULL, name_str " Input 4" }, \ 111 { widget, NULL, name_str " Mixer" }, \ 112 { name_str " Mixer", NULL, "Mixer Core" }, \ 113 CS42L43_BASE_ROUTES(name_str " Input 1"), \ 114 CS42L43_BASE_ROUTES(name_str " Input 2"), \ 115 CS42L43_BASE_ROUTES(name_str " Input 3"), \ 116 CS42L43_BASE_ROUTES(name_str " Input 4") 117 118 #define CS42L43_MIXER_VOLUMES(name_str, base) \ 119 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ 120 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 121 cs42l43_mixer_tlv), \ 122 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \ 123 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 124 cs42l43_mixer_tlv), \ 125 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \ 126 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 127 cs42l43_mixer_tlv), \ 128 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \ 129 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 130 cs42l43_mixer_tlv) 131 132 #define CS42L43_IRQ_ERROR(name) \ 133 static irqreturn_t cs42l43_##name(int irq, void *data) \ 134 { \ 135 struct cs42l43_codec *priv = data; \ 136 dev_err(priv->dev, "Error " #name " IRQ\n"); \ 137 return IRQ_HANDLED; \ 138 } 139 140 CS42L43_IRQ_ERROR(pll_lost_lock) 141 CS42L43_IRQ_ERROR(spkr_clock_stop) 142 CS42L43_IRQ_ERROR(spkl_clock_stop) 143 CS42L43_IRQ_ERROR(spkr_brown_out) 144 CS42L43_IRQ_ERROR(spkl_brown_out) 145 CS42L43_IRQ_ERROR(spkr_therm_shutdown) 146 CS42L43_IRQ_ERROR(spkl_therm_shutdown) 147 CS42L43_IRQ_ERROR(spkr_therm_warm) 148 CS42L43_IRQ_ERROR(spkl_therm_warm) 149 CS42L43_IRQ_ERROR(spkr_sc_detect) 150 CS42L43_IRQ_ERROR(spkl_sc_detect) 151 152 static void cs42l43_hp_ilimit_clear_work(struct work_struct *work) 153 { 154 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec, 155 hp_ilimit_clear_work.work); 156 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component); 157 158 snd_soc_dapm_mutex_lock(dapm); 159 160 priv->hp_ilimit_count--; 161 162 if (priv->hp_ilimit_count) 163 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work, 164 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 165 166 snd_soc_dapm_mutex_unlock(dapm); 167 } 168 169 static void cs42l43_hp_ilimit_work(struct work_struct *work) 170 { 171 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec, 172 hp_ilimit_work); 173 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component); 174 struct cs42l43 *cs42l43 = priv->core; 175 176 snd_soc_dapm_mutex_lock(dapm); 177 178 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) { 179 if (!priv->hp_ilimit_count) 180 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work, 181 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 182 183 priv->hp_ilimit_count++; 184 snd_soc_dapm_mutex_unlock(dapm); 185 return; 186 } 187 188 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n", 189 CS42L43_HP_ILIMIT_BACKOFF_MS); 190 191 priv->hp_ilimited = true; 192 193 // No need to wait for disable, as just disabling for a period of time 194 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 195 CS42L43_HP_EN_MASK, 0); 196 197 snd_soc_dapm_mutex_unlock(dapm); 198 199 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS); 200 201 snd_soc_dapm_mutex_lock(dapm); 202 203 if (priv->hp_ena && !priv->load_detect_running) { 204 unsigned long time_left; 205 206 reinit_completion(&priv->hp_startup); 207 208 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 209 CS42L43_HP_EN_MASK, priv->hp_ena); 210 211 time_left = wait_for_completion_timeout(&priv->hp_startup, 212 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS)); 213 if (!time_left) 214 dev_err(priv->dev, "ilimit HP restore timed out\n"); 215 } 216 217 priv->hp_ilimited = false; 218 219 snd_soc_dapm_mutex_unlock(dapm); 220 } 221 222 static irqreturn_t cs42l43_hp_ilimit(int irq, void *data) 223 { 224 struct cs42l43_codec *priv = data; 225 226 dev_dbg(priv->dev, "headphone ilimit IRQ\n"); 227 228 queue_work(system_long_wq, &priv->hp_ilimit_work); 229 230 return IRQ_HANDLED; 231 } 232 233 #define CS42L43_IRQ_COMPLETE(name) \ 234 static irqreturn_t cs42l43_##name(int irq, void *data) \ 235 { \ 236 struct cs42l43_codec *priv = data; \ 237 dev_dbg(priv->dev, #name " completed\n"); \ 238 complete(&priv->name); \ 239 return IRQ_HANDLED; \ 240 } 241 242 CS42L43_IRQ_COMPLETE(pll_ready) 243 CS42L43_IRQ_COMPLETE(hp_startup) 244 CS42L43_IRQ_COMPLETE(hp_shutdown) 245 CS42L43_IRQ_COMPLETE(type_detect) 246 CS42L43_IRQ_COMPLETE(spkr_shutdown) 247 CS42L43_IRQ_COMPLETE(spkl_shutdown) 248 CS42L43_IRQ_COMPLETE(spkr_startup) 249 CS42L43_IRQ_COMPLETE(spkl_startup) 250 CS42L43_IRQ_COMPLETE(load_detect) 251 252 static irqreturn_t cs42l43_mic_shutter(int irq, void *data) 253 { 254 struct cs42l43_codec *priv = data; 255 static const char * const controls[] = { 256 "Decimator 1 Switch", 257 "Decimator 2 Switch", 258 "Decimator 3 Switch", 259 "Decimator 4 Switch", 260 }; 261 int i, ret; 262 263 dev_dbg(priv->dev, "Microphone shutter changed\n"); 264 265 if (!priv->component) 266 return IRQ_NONE; 267 268 for (i = 0; i < ARRAY_SIZE(controls); i++) { 269 ret = snd_soc_component_notify_control(priv->component, 270 controls[i]); 271 if (ret) 272 return IRQ_NONE; 273 } 274 275 return IRQ_HANDLED; 276 } 277 278 static irqreturn_t cs42l43_spk_shutter(int irq, void *data) 279 { 280 struct cs42l43_codec *priv = data; 281 int ret; 282 283 dev_dbg(priv->dev, "Speaker shutter changed\n"); 284 285 if (!priv->component) 286 return IRQ_NONE; 287 288 ret = snd_soc_component_notify_control(priv->component, 289 "Speaker Digital Switch"); 290 if (ret) 291 return IRQ_NONE; 292 293 return IRQ_HANDLED; 294 } 295 296 static const unsigned int cs42l43_sample_rates[] = { 297 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000, 298 }; 299 300 #define CS42L43_CONSUMER_RATE_MASK 0xFF 301 #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer 302 303 static const struct snd_pcm_hw_constraint_list cs42l43_constraint = { 304 .count = ARRAY_SIZE(cs42l43_sample_rates), 305 .list = cs42l43_sample_rates, 306 }; 307 308 static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 309 { 310 struct snd_soc_component *component = dai->component; 311 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 312 struct cs42l43 *cs42l43 = priv->core; 313 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap, 314 CS42L43_ASP_CLK_CONFIG2, 315 CS42L43_ASP_MASTER_MODE_MASK); 316 317 if (provider) 318 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK; 319 else 320 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; 321 322 return snd_pcm_hw_constraint_list(substream->runtime, 0, 323 SNDRV_PCM_HW_PARAM_RATE, 324 &priv->constraint); 325 } 326 327 static int cs42l43_convert_sample_rate(unsigned int rate) 328 { 329 switch (rate) { 330 case 8000: 331 return 0x11; 332 case 16000: 333 return 0x12; 334 case 24000: 335 return 0x02; 336 case 32000: 337 return 0x13; 338 case 44100: 339 return 0x0B; 340 case 48000: 341 return 0x03; 342 case 96000: 343 return 0x04; 344 case 192000: 345 return 0x05; 346 default: 347 return -EINVAL; 348 } 349 } 350 351 static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream, 352 struct snd_pcm_hw_params *params, 353 struct snd_soc_dai *dai) 354 { 355 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 356 struct cs42l43 *cs42l43 = priv->core; 357 int ret; 358 359 ret = cs42l43_convert_sample_rate(params_rate(params)); 360 if (ret < 0) { 361 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret); 362 return ret; 363 } 364 365 //FIXME: For now lets just set sample rate 1, this needs expanded in the future 366 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1, 367 CS42L43_SAMPLE_RATE_MASK, ret); 368 369 return 0; 370 } 371 372 static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream, 373 struct snd_pcm_hw_params *params, 374 struct snd_soc_dai *dai) 375 { 376 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 377 struct cs42l43 *cs42l43 = priv->core; 378 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 379 CS42L43_ASP_FSYNC_MODE_MASK); 380 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 381 CS42L43_ASP_MASTER_MODE_MASK); 382 int n_chans = params_channels(params); 383 int data_width = params_width(params); 384 int n_slots = n_chans; 385 int slot_width = data_width; 386 int frame, bclk_target, i; 387 unsigned int reg; 388 int *slots; 389 390 if (priv->n_slots) { 391 n_slots = priv->n_slots; 392 slot_width = priv->slot_width; 393 } 394 395 if (!dsp_mode && (n_slots & 0x1)) { 396 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n"); 397 n_slots++; 398 } 399 400 frame = n_slots * slot_width; 401 bclk_target = params_rate(params) * frame; 402 403 if (provider) { 404 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK); 405 int n = bclk_target / gcd_nm; 406 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm; 407 408 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) || 409 m > CS42L43_ASP_BCLK_M_MASK) { 410 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target); 411 return -EINVAL; 412 } 413 414 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n", 415 n, m, bclk_target, n_slots, slot_width); 416 417 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1, 418 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK, 419 n << CS42L43_ASP_BCLK_N_SHIFT | 420 m << CS42L43_ASP_BCLK_M_SHIFT); 421 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1, 422 CS42L43_ASP_FSYNC_M_MASK, frame); 423 } 424 425 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4, 426 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK, 427 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT); 428 429 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 430 reg = CS42L43_ASP_TX_CH1_CTRL; 431 slots = priv->tx_slots; 432 } else { 433 reg = CS42L43_ASP_RX_CH1_CTRL; 434 slots = priv->rx_slots; 435 } 436 437 for (i = 0; i < n_chans; i++, reg += 4) { 438 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK); 439 int slot_pos; 440 441 if (dsp_mode) 442 slot_pos = slots[i] * slot_width; 443 else 444 slot_pos = (slots[i] / 2) * slot_width; 445 446 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n", 447 i, slots[i], slot_pos, slot_phase); 448 449 regmap_update_bits(cs42l43->regmap, reg, 450 CS42L43_ASP_CH_WIDTH_MASK | 451 CS42L43_ASP_CH_SLOT_MASK | 452 CS42L43_ASP_CH_SLOT_PHASE_MASK, 453 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) | 454 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) | 455 slot_phase); 456 } 457 458 return cs42l43_set_sample_rate(substream, params, dai); 459 } 460 461 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 462 { 463 struct snd_soc_component *component = dai->component; 464 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 465 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 466 struct cs42l43 *cs42l43 = priv->core; 467 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 468 CS42L43_ASP_MASTER_MODE_MASK); 469 struct snd_soc_dapm_route routes[] = { 470 { "BCLK", NULL, "FSYNC" }, 471 }; 472 unsigned int asp_ctrl = 0; 473 unsigned int data_ctrl = 0; 474 unsigned int fsync_ctrl = 0; 475 unsigned int clk_config = 0; 476 477 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 478 case SND_SOC_DAIFMT_DSP_A: 479 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 480 fallthrough; 481 case SND_SOC_DAIFMT_DSP_B: 482 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK; 483 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 484 break; 485 case SND_SOC_DAIFMT_I2S: 486 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 487 break; 488 case SND_SOC_DAIFMT_LEFT_J: 489 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 490 break; 491 default: 492 dev_err(priv->dev, "Unsupported DAI format 0x%x\n", 493 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 494 return -EINVAL; 495 } 496 497 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 498 case SND_SOC_DAIFMT_CBC_CFC: 499 if (provider) 500 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes)); 501 break; 502 case SND_SOC_DAIFMT_CBP_CFP: 503 if (!provider) 504 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 505 clk_config |= CS42L43_ASP_MASTER_MODE_MASK; 506 break; 507 default: 508 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n", 509 fmt & SND_SOC_DAIFMT_MASTER_MASK); 510 return -EINVAL; 511 } 512 513 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 514 case SND_SOC_DAIFMT_NB_NF: 515 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */ 516 break; 517 case SND_SOC_DAIFMT_IB_NF: 518 break; 519 case SND_SOC_DAIFMT_NB_IF: 520 clk_config |= CS42L43_ASP_BCLK_INV_MASK; 521 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 522 CS42L43_ASP_FSYNC_OUT_INV_MASK; 523 break; 524 case SND_SOC_DAIFMT_IB_IF: 525 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 526 CS42L43_ASP_FSYNC_OUT_INV_MASK; 527 break; 528 default: 529 dev_err(priv->dev, "Unsupported invert mode 0x%x\n", 530 fmt & SND_SOC_DAIFMT_INV_MASK); 531 return -EINVAL; 532 } 533 534 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 535 CS42L43_ASP_FSYNC_MODE_MASK, 536 asp_ctrl); 537 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL, 538 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK | 539 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK, 540 data_ctrl); 541 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 542 CS42L43_ASP_MASTER_MODE_MASK | 543 CS42L43_ASP_BCLK_INV_MASK, 544 clk_config); 545 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3, 546 CS42L43_ASP_FSYNC_IN_INV_MASK | 547 CS42L43_ASP_FSYNC_OUT_INV_MASK, 548 fsync_ctrl); 549 550 return 0; 551 } 552 553 static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned long mask, 554 int *slots, unsigned int nslots) 555 { 556 int i = 0; 557 int slot; 558 559 for_each_set_bit(slot, &mask, BITS_PER_TYPE(mask)) { 560 if (i == nslots) { 561 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n", 562 mask); 563 return; 564 } 565 566 slots[i++] = slot; 567 } 568 569 } 570 571 static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 572 unsigned int rx_mask, int slots, int slot_width) 573 { 574 struct snd_soc_component *component = dai->component; 575 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 576 577 priv->n_slots = slots; 578 priv->slot_width = slot_width; 579 580 if (!slots) { 581 tx_mask = CS42L43_DEFAULT_SLOTS; 582 rx_mask = CS42L43_DEFAULT_SLOTS; 583 } 584 585 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots, 586 ARRAY_SIZE(priv->tx_slots)); 587 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots, 588 ARRAY_SIZE(priv->rx_slots)); 589 590 return 0; 591 } 592 593 static const struct snd_soc_dai_ops cs42l43_asp_ops = { 594 .startup = cs42l43_startup, 595 .hw_params = cs42l43_asp_hw_params, 596 .set_fmt = cs42l43_asp_set_fmt, 597 .set_tdm_slot = cs42l43_asp_set_tdm_slot, 598 }; 599 600 static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream, 601 struct snd_pcm_hw_params *params, 602 struct snd_soc_dai *dai) 603 { 604 int ret; 605 606 ret = cs42l43_sdw_add_peripheral(substream, params, dai); 607 if (ret) 608 return ret; 609 610 return cs42l43_set_sample_rate(substream, params, dai); 611 }; 612 613 static const struct snd_soc_dai_ops cs42l43_sdw_ops = { 614 .startup = cs42l43_startup, 615 .set_stream = cs42l43_sdw_set_stream, 616 .hw_params = cs42l43_sdw_hw_params, 617 .hw_free = cs42l43_sdw_remove_peripheral, 618 }; 619 620 #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 621 SNDRV_PCM_FMTBIT_S32_LE) 622 #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 623 624 static struct snd_soc_dai_driver cs42l43_dais[] = { 625 { 626 .name = "cs42l43-asp", 627 .ops = &cs42l43_asp_ops, 628 .symmetric_rate = 1, 629 .capture = { 630 .stream_name = "ASP Capture", 631 .channels_min = 1, 632 .channels_max = CS42L43_ASP_MAX_CHANNELS, 633 .rates = SNDRV_PCM_RATE_KNOT, 634 .formats = CS42L43_ASP_FORMATS, 635 }, 636 .playback = { 637 .stream_name = "ASP Playback", 638 .channels_min = 1, 639 .channels_max = CS42L43_ASP_MAX_CHANNELS, 640 .rates = SNDRV_PCM_RATE_KNOT, 641 .formats = CS42L43_ASP_FORMATS, 642 }, 643 }, 644 { 645 .name = "cs42l43-dp1", 646 .id = 1, 647 .ops = &cs42l43_sdw_ops, 648 .capture = { 649 .stream_name = "DP1 Capture", 650 .channels_min = 1, 651 .channels_max = 4, 652 .rates = SNDRV_PCM_RATE_KNOT, 653 .formats = CS42L43_SDW_FORMATS, 654 }, 655 }, 656 { 657 .name = "cs42l43-dp2", 658 .id = 2, 659 .ops = &cs42l43_sdw_ops, 660 .capture = { 661 .stream_name = "DP2 Capture", 662 .channels_min = 1, 663 .channels_max = 2, 664 .rates = SNDRV_PCM_RATE_KNOT, 665 .formats = CS42L43_SDW_FORMATS, 666 }, 667 }, 668 { 669 .name = "cs42l43-dp3", 670 .id = 3, 671 .ops = &cs42l43_sdw_ops, 672 .capture = { 673 .stream_name = "DP3 Capture", 674 .channels_min = 1, 675 .channels_max = 2, 676 .rates = SNDRV_PCM_RATE_KNOT, 677 .formats = CS42L43_SDW_FORMATS, 678 }, 679 }, 680 { 681 .name = "cs42l43-dp4", 682 .id = 4, 683 .ops = &cs42l43_sdw_ops, 684 .capture = { 685 .stream_name = "DP4 Capture", 686 .channels_min = 1, 687 .channels_max = 2, 688 .rates = SNDRV_PCM_RATE_KNOT, 689 .formats = CS42L43_SDW_FORMATS, 690 }, 691 }, 692 { 693 .name = "cs42l43-dp5", 694 .id = 5, 695 .ops = &cs42l43_sdw_ops, 696 .playback = { 697 .stream_name = "DP5 Playback", 698 .channels_min = 1, 699 .channels_max = 2, 700 .rates = SNDRV_PCM_RATE_KNOT, 701 .formats = CS42L43_SDW_FORMATS, 702 }, 703 }, 704 { 705 .name = "cs42l43-dp6", 706 .id = 6, 707 .ops = &cs42l43_sdw_ops, 708 .playback = { 709 .stream_name = "DP6 Playback", 710 .channels_min = 1, 711 .channels_max = 2, 712 .rates = SNDRV_PCM_RATE_KNOT, 713 .formats = CS42L43_SDW_FORMATS, 714 }, 715 }, 716 { 717 .name = "cs42l43-dp7", 718 .id = 7, 719 .ops = &cs42l43_sdw_ops, 720 .playback = { 721 .stream_name = "DP7 Playback", 722 .channels_min = 1, 723 .channels_max = 2, 724 .rates = SNDRV_PCM_RATE_KNOT, 725 .formats = CS42L43_SDW_FORMATS, 726 }, 727 }, 728 }; 729 730 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0); 731 732 static const char * const cs42l43_ramp_text[] = { 733 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", 734 "15ms/6dB", "30ms/6dB", 735 }; 736 737 static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" }; 738 739 static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1, 740 CS42L43_ADC_AIN_SEL_SHIFT, 741 cs42l43_adc1_input_text); 742 743 static const struct snd_kcontrol_new cs42l43_adc1_input_ctl = 744 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input); 745 746 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" }; 747 748 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text); 749 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text); 750 751 static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = { 752 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode), 753 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode), 754 }; 755 756 static const char * const cs42l43_pdm_clk_text[] = { 757 "3.072MHz", "1.536MHz", "768kHz", 758 }; 759 760 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL, 761 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 762 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL, 763 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 764 765 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0); 766 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0); 767 768 static const char * const cs42l43_wnf_corner_text[] = { 769 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", 770 }; 771 772 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 773 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 774 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 775 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 776 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 777 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 778 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 779 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 780 781 static const char * const cs42l43_hpf_corner_text[] = { 782 "3Hz", "12Hz", "48Hz", "96Hz", 783 }; 784 785 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 786 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 787 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 788 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 789 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 790 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 791 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 792 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 793 794 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 795 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); 796 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 797 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); 798 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 799 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); 800 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 801 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); 802 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 803 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); 804 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 805 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); 806 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 807 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 808 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 809 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 810 811 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); 812 813 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP, 814 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text); 815 816 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP, 817 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text); 818 819 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1); 820 821 static const char * const cs42l43_headphone_ramp_text[] = { 822 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44", 823 "48", "66", "72", 824 }; 825 826 static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL, 827 CS42L43_HP_PATH_VOL_RAMP_SHIFT, 828 cs42l43_headphone_ramp_text); 829 830 static const char * const cs42l43_tone_freq_text[] = { 831 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz", 832 }; 833 834 static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL, 835 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 836 837 static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL, 838 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 839 840 static const char * const cs42l43_mixer_texts[] = { 841 "None", 842 "Tone Generator 1", "Tone Generator 2", 843 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", 844 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", 845 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", 846 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", 847 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", 848 "ISRC1 INT1", "ISRC1 INT2", 849 "ISRC1 DEC1", "ISRC1 DEC2", 850 "ISRC2 INT1", "ISRC2 INT2", 851 "ISRC2 DEC1", "ISRC2 DEC2", 852 "EQ1", "EQ2", 853 }; 854 855 static const unsigned int cs42l43_mixer_values[] = { 856 0x00, // None 857 0x04, 0x05, // Tone Generator 1, 2 858 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4 859 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 860 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 861 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 862 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 863 0x50, 0x51, // ISRC1 INT1, 2 864 0x52, 0x53, // ISRC1 DEC1, 2 865 0x54, 0x55, // ISRC2 INT1, 2 866 0x56, 0x57, // ISRC2 DEC1, 2 867 0x58, 0x59, // EQ1, 2 868 }; 869 870 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); 871 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); 872 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); 873 CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT); 874 CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT); 875 CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT); 876 877 CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); 878 CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); 879 CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); 880 CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); 881 CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); 882 CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); 883 CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); 884 CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); 885 CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); 886 CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); 887 888 CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1); 889 CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1); 890 CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1); 891 CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1); 892 CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1); 893 CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1); 894 CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1); 895 CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1); 896 897 CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1); 898 CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1); 899 CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); 900 CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); 901 CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1); 902 CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1); 903 CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); 904 CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); 905 906 CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1); 907 CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1); 908 909 CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1); 910 CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1); 911 912 CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1); 913 CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1); 914 915 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); 916 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); 917 918 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, 919 struct snd_ctl_elem_value *ucontrol) 920 { 921 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 922 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 923 int ret; 924 925 snd_soc_dapm_mutex_lock(dapm); 926 ret = snd_soc_get_volsw(kcontrol, ucontrol); 927 snd_soc_dapm_mutex_unlock(dapm); 928 929 return ret; 930 } 931 932 static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol, 933 struct snd_ctl_elem_value *ucontrol) 934 { 935 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 936 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 937 int ret; 938 939 snd_soc_dapm_mutex_lock(dapm); 940 ret = snd_soc_put_volsw(kcontrol, ucontrol); 941 snd_soc_dapm_mutex_unlock(dapm); 942 943 return ret; 944 } 945 946 static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol, 947 struct snd_ctl_elem_value *ucontrol) 948 { 949 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 950 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 951 int ret; 952 953 snd_soc_dapm_mutex_lock(dapm); 954 ret = snd_soc_get_enum_double(kcontrol, ucontrol); 955 snd_soc_dapm_mutex_unlock(dapm); 956 957 return ret; 958 } 959 960 static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol, 961 struct snd_ctl_elem_value *ucontrol) 962 { 963 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 964 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 965 int ret; 966 967 snd_soc_dapm_mutex_lock(dapm); 968 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 969 snd_soc_dapm_mutex_unlock(dapm); 970 971 return ret; 972 } 973 974 static int cs42l43_eq_get(struct snd_kcontrol *kcontrol, 975 struct snd_ctl_elem_value *ucontrol) 976 { 977 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 978 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 979 980 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs)); 981 982 return 0; 983 } 984 985 static int cs42l43_eq_put(struct snd_kcontrol *kcontrol, 986 struct snd_ctl_elem_value *ucontrol) 987 { 988 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 989 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 990 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 991 992 snd_soc_dapm_mutex_lock(dapm); 993 994 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs)); 995 996 snd_soc_dapm_mutex_unlock(dapm); 997 998 return 0; 999 } 1000 1001 static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv) 1002 { 1003 struct cs42l43 *cs42l43 = priv->core; 1004 1005 mutex_lock(&priv->spk_vu_lock); 1006 1007 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 1008 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK); 1009 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 1010 CS42L43_AMP1_2_VU_MASK, 0); 1011 1012 mutex_unlock(&priv->spk_vu_lock); 1013 } 1014 1015 static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift) 1016 { 1017 struct cs42l43 *cs42l43 = priv->core; 1018 unsigned int val; 1019 int ret; 1020 1021 ret = pm_runtime_resume_and_get(priv->dev); 1022 if (ret) { 1023 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret); 1024 return ret; 1025 } 1026 1027 /* 1028 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must 1029 * be cached for the non-volatiles, so drop it from the cache here so 1030 * we force a read. 1031 */ 1032 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, 1033 CS42L43_SHUTTER_CONTROL); 1034 if (ret) { 1035 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret); 1036 goto error; 1037 } 1038 1039 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 1040 if (ret) { 1041 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret); 1042 goto error; 1043 } 1044 1045 ret = !(val & BIT(shift)); 1046 1047 dev_dbg(priv->dev, "%s shutter is %s\n", 1048 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker", 1049 ret ? "open" : "closed"); 1050 1051 error: 1052 pm_runtime_mark_last_busy(priv->dev); 1053 pm_runtime_put_autosuspend(priv->dev); 1054 1055 return ret; 1056 } 1057 1058 static int cs42l43_decim_get(struct snd_kcontrol *kcontrol, 1059 struct snd_ctl_elem_value *ucontrol) 1060 { 1061 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1062 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1063 int ret; 1064 1065 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT); 1066 if (ret > 0) 1067 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol); 1068 else if (!ret) 1069 ucontrol->value.integer.value[0] = ret; 1070 1071 return ret; 1072 } 1073 1074 static int cs42l43_spk_get(struct snd_kcontrol *kcontrol, 1075 struct snd_ctl_elem_value *ucontrol) 1076 { 1077 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1078 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1079 int ret; 1080 1081 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT); 1082 if (ret > 0) 1083 ret = snd_soc_get_volsw(kcontrol, ucontrol); 1084 else if (!ret) 1085 ucontrol->value.integer.value[0] = ret; 1086 1087 return ret; 1088 } 1089 1090 static int cs42l43_spk_put(struct snd_kcontrol *kcontrol, 1091 struct snd_ctl_elem_value *ucontrol) 1092 { 1093 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1094 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1095 int ret; 1096 1097 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1098 if (ret > 0) 1099 cs42l43_spk_vu_sync(priv); 1100 1101 return ret; 1102 } 1103 1104 static const struct snd_kcontrol_new cs42l43_controls[] = { 1105 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum, 1106 cs42l43_jack_get, cs42l43_jack_put), 1107 1108 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2, 1109 CS42L43_ADC_PGA_GAIN_SHIFT, 1110 0xF, 5, cs42l43_adc_tlv), 1111 1112 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1113 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0), 1114 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1115 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0), 1116 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk), 1117 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk), 1118 1119 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1120 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1121 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1122 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1123 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1124 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1125 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1126 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1127 1128 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner), 1129 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner), 1130 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner), 1131 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner), 1132 1133 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1134 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1135 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1136 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1137 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1138 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1139 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1140 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1141 1142 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner), 1143 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner), 1144 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), 1145 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), 1146 1147 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1148 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1149 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1150 CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 1151 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1152 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1153 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1154 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1155 CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 1156 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1157 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1158 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1159 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1160 CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 1161 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1162 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1163 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1164 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1165 CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 1166 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1167 1168 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, 1169 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1170 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, 1171 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1172 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, 1173 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1174 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, 1175 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1176 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, 1177 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1178 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, 1179 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1180 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, 1181 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1182 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, 1183 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1184 1185 SOC_DOUBLE_R_EXT("Speaker Digital Switch", 1186 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1187 CS42L43_AMP_MUTE_SHIFT, 1, 1, 1188 cs42l43_spk_get, cs42l43_spk_put), 1189 1190 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume", 1191 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1192 CS42L43_AMP_VOL_SHIFT, 1193 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put, 1194 cs42l43_speaker_tlv), 1195 1196 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up), 1197 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down), 1198 1199 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1), 1200 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1), 1201 1202 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL, 1203 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT, 1204 0x11B, 229, cs42l43_headphone_tlv), 1205 1206 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1, 1207 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0), 1208 1209 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL, 1210 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0), 1211 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL, 1212 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0), 1213 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp), 1214 1215 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1), 1216 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1), 1217 1218 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq), 1219 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq), 1220 1221 SOC_DOUBLE_EXT("EQ Switch", 1222 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT, 1223 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1, 1224 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw), 1225 1226 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS, 1227 cs42l43_eq_get, cs42l43_eq_put), 1228 1229 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1), 1230 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1), 1231 }; 1232 1233 static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w, 1234 struct snd_kcontrol *kcontrol, int event) 1235 { 1236 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1237 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1238 struct cs42l43 *cs42l43 = priv->core; 1239 unsigned int val; 1240 int i, ret; 1241 1242 switch (event) { 1243 case SND_SOC_DAPM_PRE_PMU: 1244 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1245 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 1246 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK); 1247 1248 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1249 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK); 1250 1251 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++) 1252 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0, 1253 priv->eq_coeffs[i]); 1254 1255 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1256 CS42L43_WRITE_MODE_MASK, 0); 1257 1258 return 0; 1259 case SND_SOC_DAPM_POST_PMU: 1260 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0, 1261 val, (val & CS42L43_INITIALIZE_DONE_MASK), 1262 2000, 10000); 1263 if (ret) 1264 dev_err(priv->dev, "Failed to start EQs: %d\n", ret); 1265 1266 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1267 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0); 1268 return ret; 1269 default: 1270 return 0; 1271 } 1272 } 1273 1274 struct cs42l43_pll_config { 1275 unsigned int freq; 1276 1277 unsigned int div; 1278 unsigned int mode; 1279 unsigned int cal; 1280 }; 1281 1282 static const struct cs42l43_pll_config cs42l43_pll_configs[] = { 1283 { 2400000, 0x50000000, 0x1, 0xA4 }, 1284 { 3000000, 0x40000000, 0x1, 0x83 }, 1285 { 3072000, 0x40000000, 0x3, 0x80 }, 1286 }; 1287 1288 static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src, 1289 unsigned int freq) 1290 { 1291 struct cs42l43 *cs42l43 = priv->core; 1292 1293 lockdep_assert_held(&cs42l43->pll_lock); 1294 1295 if (priv->refclk_src == src && priv->refclk_freq == freq) 1296 return 0; 1297 1298 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) { 1299 dev_err(priv->dev, "PLL active, can't change configuration\n"); 1300 return -EBUSY; 1301 } 1302 1303 switch (src) { 1304 case CS42L43_SYSCLK_MCLK: 1305 case CS42L43_SYSCLK_SDW: 1306 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n", 1307 src ? "SoundWire" : "MCLK", freq); 1308 1309 priv->refclk_src = src; 1310 priv->refclk_freq = freq; 1311 1312 return 0; 1313 default: 1314 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src); 1315 return -EINVAL; 1316 } 1317 } 1318 1319 static int cs42l43_enable_pll(struct cs42l43_codec *priv) 1320 { 1321 static const struct reg_sequence enable_seq[] = { 1322 { CS42L43_OSC_DIV_SEL, 0x0, }, 1323 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, }, 1324 }; 1325 struct cs42l43 *cs42l43 = priv->core; 1326 const struct cs42l43_pll_config *config = NULL; 1327 unsigned int div = 0; 1328 unsigned int freq = priv->refclk_freq; 1329 unsigned long time_left; 1330 1331 lockdep_assert_held(&cs42l43->pll_lock); 1332 1333 if (priv->refclk_src == CS42L43_SYSCLK_SDW) { 1334 if (!freq) 1335 freq = cs42l43->sdw_freq; 1336 else if (!cs42l43->sdw_freq) 1337 cs42l43->sdw_freq = freq; 1338 } 1339 1340 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq); 1341 1342 div = fls(freq) - 1343 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq); 1344 freq >>= div; 1345 1346 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) { 1347 int i; 1348 1349 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) { 1350 if (freq == cs42l43_pll_configs[i].freq) { 1351 config = &cs42l43_pll_configs[i]; 1352 break; 1353 } 1354 } 1355 } 1356 1357 if (!config) { 1358 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq); 1359 return -EINVAL; 1360 } 1361 1362 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1363 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK, 1364 div << CS42L43_PLL_REFCLK_DIV_SHIFT | 1365 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT); 1366 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div); 1367 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1368 CS42L43_PLL_MODE_BYPASS_500_MASK | 1369 CS42L43_PLL_MODE_BYPASS_1029_MASK, 1370 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT); 1371 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO, 1372 CS42L43_PLL_CAL_RATIO_MASK, config->cal); 1373 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1374 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK); 1375 1376 reinit_completion(&priv->pll_ready); 1377 1378 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1379 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK); 1380 1381 time_left = wait_for_completion_timeout(&priv->pll_ready, 1382 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS)); 1383 if (!time_left) { 1384 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1385 CS42L43_PLL_EN_MASK, 0); 1386 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1387 CS42L43_PLL_REFCLK_EN_MASK, 0); 1388 1389 dev_err(priv->dev, "Timeout out waiting for PLL\n"); 1390 return -ETIMEDOUT; 1391 } 1392 1393 if (priv->refclk_src == CS42L43_SYSCLK_SDW) 1394 cs42l43->sdw_pll_active = true; 1395 1396 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left)); 1397 1398 /* 1399 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL, 1400 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole 1401 * change over happens under the regmap lock to prevent any reads. 1402 */ 1403 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq)); 1404 1405 return 0; 1406 } 1407 1408 static int cs42l43_disable_pll(struct cs42l43_codec *priv) 1409 { 1410 static const struct reg_sequence disable_seq[] = { 1411 { CS42L43_MCLK_SRC_SEL, 0x0, 5, }, 1412 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, }, 1413 }; 1414 struct cs42l43 *cs42l43 = priv->core; 1415 1416 dev_dbg(priv->dev, "Disabling PLL\n"); 1417 1418 lockdep_assert_held(&cs42l43->pll_lock); 1419 1420 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq)); 1421 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0); 1422 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1423 CS42L43_PLL_REFCLK_EN_MASK, 0); 1424 1425 cs42l43->sdw_pll_active = false; 1426 1427 return 0; 1428 } 1429 1430 static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w, 1431 struct snd_kcontrol *kcontrol, int event) 1432 { 1433 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1434 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1435 struct cs42l43 *cs42l43 = priv->core; 1436 int ret; 1437 1438 mutex_lock(&cs42l43->pll_lock); 1439 1440 switch (event) { 1441 case SND_SOC_DAPM_PRE_PMU: 1442 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) { 1443 ret = clk_prepare_enable(priv->mclk); 1444 if (ret) { 1445 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret); 1446 break; 1447 } 1448 } 1449 1450 ret = cs42l43_enable_pll(priv); 1451 break; 1452 case SND_SOC_DAPM_POST_PMD: 1453 ret = cs42l43_disable_pll(priv); 1454 1455 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) 1456 clk_disable_unprepare(priv->mclk); 1457 break; 1458 default: 1459 ret = 0; 1460 break; 1461 } 1462 1463 mutex_unlock(&cs42l43->pll_lock); 1464 1465 return ret; 1466 } 1467 1468 static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd, 1469 int event, int timeout_ms) 1470 { 1471 unsigned long time_left; 1472 1473 switch (event) { 1474 case SND_SOC_DAPM_PRE_PMU: 1475 reinit_completion(pmu); 1476 return 0; 1477 case SND_SOC_DAPM_PRE_PMD: 1478 reinit_completion(pmd); 1479 return 0; 1480 case SND_SOC_DAPM_POST_PMU: 1481 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms)); 1482 break; 1483 case SND_SOC_DAPM_POST_PMD: 1484 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms)); 1485 break; 1486 default: 1487 return 0; 1488 } 1489 1490 if (!time_left) 1491 return -ETIMEDOUT; 1492 else 1493 return 0; 1494 } 1495 1496 static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w, 1497 struct snd_kcontrol *kcontrol, int event) 1498 { 1499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1500 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1501 1502 return cs42l43_dapm_wait_completion(&priv->spkr_startup, 1503 &priv->spkr_shutdown, event, 1504 CS42L43_SPK_TIMEOUT_MS); 1505 } 1506 1507 static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w, 1508 struct snd_kcontrol *kcontrol, int event) 1509 { 1510 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1511 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1512 1513 return cs42l43_dapm_wait_completion(&priv->spkl_startup, 1514 &priv->spkl_shutdown, event, 1515 CS42L43_SPK_TIMEOUT_MS); 1516 } 1517 1518 static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w, 1519 struct snd_kcontrol *kcontrol, int event) 1520 { 1521 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1522 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1523 struct cs42l43 *cs42l43 = priv->core; 1524 unsigned int mask = 1 << w->shift; 1525 unsigned int val = 0; 1526 int ret; 1527 1528 switch (event) { 1529 case SND_SOC_DAPM_PRE_PMU: 1530 val = mask; 1531 fallthrough; 1532 case SND_SOC_DAPM_PRE_PMD: 1533 priv->hp_ena &= ~mask; 1534 priv->hp_ena |= val; 1535 1536 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1537 &priv->hp_shutdown, event, 1538 CS42L43_HP_TIMEOUT_MS); 1539 if (ret) 1540 return ret; 1541 1542 if (!priv->load_detect_running && !priv->hp_ilimited) 1543 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 1544 mask, val); 1545 break; 1546 case SND_SOC_DAPM_POST_PMU: 1547 case SND_SOC_DAPM_POST_PMD: 1548 if (priv->load_detect_running || priv->hp_ilimited) 1549 break; 1550 1551 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1552 &priv->hp_shutdown, event, 1553 CS42L43_HP_TIMEOUT_MS); 1554 if (ret) 1555 return ret; 1556 break; 1557 default: 1558 break; 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w, 1565 struct snd_kcontrol *kcontrol, int event) 1566 { 1567 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1568 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1569 struct cs42l43 *cs42l43 = priv->core; 1570 unsigned int reg, ramp, mute; 1571 unsigned int *val; 1572 int ret; 1573 1574 switch (w->shift) { 1575 case CS42L43_ADC1_EN_SHIFT: 1576 case CS42L43_PDM1_DIN_L_EN_SHIFT: 1577 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1578 ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1579 mute = CS42L43_DECIM1_MUTE_MASK; 1580 val = &priv->decim_cache[0]; 1581 break; 1582 case CS42L43_ADC2_EN_SHIFT: 1583 case CS42L43_PDM1_DIN_R_EN_SHIFT: 1584 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1585 ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1586 mute = CS42L43_DECIM2_MUTE_MASK; 1587 val = &priv->decim_cache[1]; 1588 break; 1589 case CS42L43_PDM2_DIN_L_EN_SHIFT: 1590 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1591 ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1592 mute = CS42L43_DECIM3_MUTE_MASK; 1593 val = &priv->decim_cache[2]; 1594 break; 1595 case CS42L43_PDM2_DIN_R_EN_SHIFT: 1596 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1597 ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1598 mute = CS42L43_DECIM4_MUTE_MASK; 1599 val = &priv->decim_cache[3]; 1600 break; 1601 default: 1602 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1603 return -EINVAL; 1604 } 1605 1606 switch (event) { 1607 case SND_SOC_DAPM_PRE_PMU: 1608 ret = regmap_read(cs42l43->regmap, reg, val); 1609 if (ret) { 1610 dev_err(priv->dev, 1611 "Failed to cache decimator settings: %d\n", 1612 ret); 1613 return ret; 1614 } 1615 1616 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute); 1617 break; 1618 case SND_SOC_DAPM_POST_PMU: 1619 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val); 1620 break; 1621 default: 1622 break; 1623 } 1624 1625 return 0; 1626 } 1627 1628 static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w, 1629 struct snd_kcontrol *kcontrol, int event) 1630 { 1631 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1632 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1633 struct cs42l43 *cs42l43 = priv->core; 1634 unsigned int mask = 1 << w->shift; 1635 unsigned int val = 0; 1636 int ret; 1637 1638 ret = cs42l43_mic_ev(w, kcontrol, event); 1639 if (ret) 1640 return ret; 1641 1642 switch (event) { 1643 case SND_SOC_DAPM_PRE_PMU: 1644 val = mask; 1645 fallthrough; 1646 case SND_SOC_DAPM_PRE_PMD: 1647 priv->adc_ena &= ~mask; 1648 priv->adc_ena |= val; 1649 1650 if (!priv->load_detect_running) 1651 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3, 1652 mask, val); 1653 fallthrough; 1654 default: 1655 return 0; 1656 } 1657 } 1658 1659 static const struct snd_soc_dapm_widget cs42l43_widgets[] = { 1660 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev, 1661 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1662 1663 SND_SOC_DAPM_INPUT("ADC1_IN1_P"), 1664 SND_SOC_DAPM_INPUT("ADC1_IN1_N"), 1665 SND_SOC_DAPM_INPUT("ADC1_IN2_P"), 1666 SND_SOC_DAPM_INPUT("ADC1_IN2_N"), 1667 SND_SOC_DAPM_INPUT("ADC2_IN_P"), 1668 SND_SOC_DAPM_INPUT("ADC2_IN_N"), 1669 1670 SND_SOC_DAPM_INPUT("PDM1_DIN"), 1671 SND_SOC_DAPM_INPUT("PDM2_DIN"), 1672 1673 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl), 1674 1675 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0, 1676 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1677 SND_SOC_DAPM_PRE_PMD), 1678 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0, 1679 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1680 SND_SOC_DAPM_PRE_PMD), 1681 1682 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT, 1683 0, NULL, 0, cs42l43_mic_ev, 1684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1685 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT, 1686 0, NULL, 0, cs42l43_mic_ev, 1687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1688 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT, 1689 0, NULL, 0, cs42l43_mic_ev, 1690 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1691 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT, 1692 0, NULL, 0, cs42l43_mic_ev, 1693 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1694 1695 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, 1696 &cs42l43_dec_mode_ctl[0]), 1697 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, 1698 &cs42l43_dec_mode_ctl[1]), 1699 1700 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), 1701 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), 1702 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0), 1703 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0), 1704 1705 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT, 1706 0, NULL, 0), 1707 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT, 1708 0, NULL, 0), 1709 1710 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, 1711 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0), 1712 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, 1713 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0), 1714 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, 1715 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0), 1716 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, 1717 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0), 1718 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, 1719 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0), 1720 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, 1721 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0), 1722 1723 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, 1724 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0), 1725 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1, 1726 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0), 1727 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2, 1728 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0), 1729 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3, 1730 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0), 1731 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4, 1732 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0), 1733 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5, 1734 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0), 1735 1736 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1737 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1738 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 1739 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 1740 1741 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1742 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1743 1744 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1745 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1746 1747 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1748 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1749 1750 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1751 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1752 1753 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1754 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1755 1756 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1757 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1758 1759 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0), 1760 1761 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0, 1762 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1763 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1764 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0, 1765 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1766 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1767 1768 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"), 1769 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"), 1770 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"), 1771 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"), 1772 1773 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT, 1774 0, NULL, 0), 1775 SND_SOC_DAPM_OUTPUT("SPDIF_TX"), 1776 1777 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0, 1778 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1779 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1780 SND_SOC_DAPM_OUTPUT("AMP3_OUT"), 1781 SND_SOC_DAPM_OUTPUT("AMP4_OUT"), 1782 1783 SND_SOC_DAPM_SIGGEN("Tone"), 1784 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT, 1785 0, NULL, 0), 1786 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL, 1787 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1788 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL, 1789 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1790 1791 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT, 1792 0, NULL, 0), 1793 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT, 1794 0, NULL, 0), 1795 1796 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL, 1797 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 1798 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL, 1799 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 1800 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL, 1801 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 1802 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL, 1803 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 1804 1805 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL, 1806 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 1807 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL, 1808 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 1809 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL, 1810 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 1811 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL, 1812 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 1813 1814 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4, 1815 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0), 1816 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4, 1817 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0), 1818 1819 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES, 1820 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0), 1821 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES, 1822 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0), 1823 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES, 1824 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0), 1825 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES, 1826 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0), 1827 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES, 1828 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0), 1829 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES, 1830 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0), 1831 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES, 1832 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0), 1833 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES, 1834 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0), 1835 1836 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT, 1837 0, NULL, 0), 1838 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT, 1839 0, NULL, 0, cs42l43_eq_ev, 1840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1841 1842 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, 1843 0, NULL, 0), 1844 CS42L43_DAPM_MUX("ASPTX1", asptx1), 1845 CS42L43_DAPM_MUX("ASPTX2", asptx2), 1846 CS42L43_DAPM_MUX("ASPTX3", asptx3), 1847 CS42L43_DAPM_MUX("ASPTX4", asptx4), 1848 CS42L43_DAPM_MUX("ASPTX5", asptx5), 1849 CS42L43_DAPM_MUX("ASPTX6", asptx6), 1850 1851 CS42L43_DAPM_MUX("DP1TX1", dp1tx1), 1852 CS42L43_DAPM_MUX("DP1TX2", dp1tx2), 1853 CS42L43_DAPM_MUX("DP1TX3", dp1tx3), 1854 CS42L43_DAPM_MUX("DP1TX4", dp1tx4), 1855 CS42L43_DAPM_MUX("DP2TX1", dp2tx1), 1856 CS42L43_DAPM_MUX("DP2TX2", dp2tx2), 1857 CS42L43_DAPM_MUX("DP3TX1", dp3tx1), 1858 CS42L43_DAPM_MUX("DP3TX2", dp3tx2), 1859 CS42L43_DAPM_MUX("DP4TX1", dp4tx1), 1860 CS42L43_DAPM_MUX("DP4TX2", dp4tx2), 1861 1862 CS42L43_DAPM_MUX("ASRC INT1", asrcint1), 1863 CS42L43_DAPM_MUX("ASRC INT2", asrcint2), 1864 CS42L43_DAPM_MUX("ASRC INT3", asrcint3), 1865 CS42L43_DAPM_MUX("ASRC INT4", asrcint4), 1866 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), 1867 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), 1868 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), 1869 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), 1870 1871 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), 1872 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), 1873 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), 1874 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), 1875 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), 1876 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), 1877 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), 1878 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), 1879 1880 CS42L43_DAPM_MUX("SPDIF1", spdif1), 1881 CS42L43_DAPM_MUX("SPDIF2", spdif2), 1882 1883 CS42L43_DAPM_MIXER("EQ1", eq1), 1884 CS42L43_DAPM_MIXER("EQ2", eq2), 1885 1886 CS42L43_DAPM_MIXER("Speaker L", amp1), 1887 CS42L43_DAPM_MIXER("Speaker R", amp2), 1888 1889 CS42L43_DAPM_MIXER("Headphone L", amp3), 1890 CS42L43_DAPM_MIXER("Headphone R", amp4), 1891 }; 1892 1893 static const struct snd_soc_dapm_route cs42l43_routes[] = { 1894 { "ADC1_IN1_P", NULL, "PLL" }, 1895 { "ADC1_IN1_N", NULL, "PLL" }, 1896 { "ADC1_IN2_P", NULL, "PLL" }, 1897 { "ADC1_IN2_N", NULL, "PLL" }, 1898 { "ADC2_IN_P", NULL, "PLL" }, 1899 { "ADC2_IN_N", NULL, "PLL" }, 1900 { "PDM1_DIN", NULL, "PLL" }, 1901 { "PDM2_DIN", NULL, "PLL" }, 1902 { "AMP1_OUT_P", NULL, "PLL" }, 1903 { "AMP1_OUT_N", NULL, "PLL" }, 1904 { "AMP2_OUT_P", NULL, "PLL" }, 1905 { "AMP2_OUT_N", NULL, "PLL" }, 1906 { "SPDIF_TX", NULL, "PLL" }, 1907 { "HP", NULL, "PLL" }, 1908 { "AMP3_OUT", NULL, "PLL" }, 1909 { "AMP4_OUT", NULL, "PLL" }, 1910 { "Tone 1", NULL, "PLL" }, 1911 { "Tone 2", NULL, "PLL" }, 1912 { "ASP Playback", NULL, "PLL" }, 1913 { "ASP Capture", NULL, "PLL" }, 1914 { "DP1 Capture", NULL, "PLL" }, 1915 { "DP2 Capture", NULL, "PLL" }, 1916 { "DP3 Capture", NULL, "PLL" }, 1917 { "DP4 Capture", NULL, "PLL" }, 1918 { "DP5 Playback", NULL, "PLL" }, 1919 { "DP6 Playback", NULL, "PLL" }, 1920 { "DP7 Playback", NULL, "PLL" }, 1921 1922 { "ADC1 Input", "IN1", "ADC1_IN1_P" }, 1923 { "ADC1 Input", "IN1", "ADC1_IN1_N" }, 1924 { "ADC1 Input", "IN2", "ADC1_IN2_P" }, 1925 { "ADC1 Input", "IN2", "ADC1_IN2_N" }, 1926 1927 { "ADC1", NULL, "ADC1 Input" }, 1928 { "ADC2", NULL, "ADC2_IN_P" }, 1929 { "ADC2", NULL, "ADC2_IN_N" }, 1930 1931 { "PDM1L", NULL, "PDM1_DIN" }, 1932 { "PDM1R", NULL, "PDM1_DIN" }, 1933 { "PDM2L", NULL, "PDM2_DIN" }, 1934 { "PDM2R", NULL, "PDM2_DIN" }, 1935 1936 { "Decimator 1 Mode", "PDM", "PDM1L" }, 1937 { "Decimator 1 Mode", "ADC", "ADC1" }, 1938 { "Decimator 2 Mode", "PDM", "PDM1R" }, 1939 { "Decimator 2 Mode", "ADC", "ADC2" }, 1940 1941 { "Decimator 1", NULL, "Decimator 1 Mode" }, 1942 { "Decimator 2", NULL, "Decimator 2 Mode" }, 1943 { "Decimator 3", NULL, "PDM2L" }, 1944 { "Decimator 4", NULL, "PDM2R" }, 1945 1946 { "ASP Capture", NULL, "ASPTX1" }, 1947 { "ASP Capture", NULL, "ASPTX2" }, 1948 { "ASP Capture", NULL, "ASPTX3" }, 1949 { "ASP Capture", NULL, "ASPTX4" }, 1950 { "ASP Capture", NULL, "ASPTX5" }, 1951 { "ASP Capture", NULL, "ASPTX6" }, 1952 { "ASPTX1", NULL, "BCLK" }, 1953 { "ASPTX2", NULL, "BCLK" }, 1954 { "ASPTX3", NULL, "BCLK" }, 1955 { "ASPTX4", NULL, "BCLK" }, 1956 { "ASPTX5", NULL, "BCLK" }, 1957 { "ASPTX6", NULL, "BCLK" }, 1958 1959 { "ASPRX1", NULL, "ASP Playback" }, 1960 { "ASPRX2", NULL, "ASP Playback" }, 1961 { "ASPRX3", NULL, "ASP Playback" }, 1962 { "ASPRX4", NULL, "ASP Playback" }, 1963 { "ASPRX5", NULL, "ASP Playback" }, 1964 { "ASPRX6", NULL, "ASP Playback" }, 1965 { "ASPRX1", NULL, "BCLK" }, 1966 { "ASPRX2", NULL, "BCLK" }, 1967 { "ASPRX3", NULL, "BCLK" }, 1968 { "ASPRX4", NULL, "BCLK" }, 1969 { "ASPRX5", NULL, "BCLK" }, 1970 { "ASPRX6", NULL, "BCLK" }, 1971 1972 { "DP1 Capture", NULL, "DP1TX1" }, 1973 { "DP1 Capture", NULL, "DP1TX2" }, 1974 { "DP1 Capture", NULL, "DP1TX3" }, 1975 { "DP1 Capture", NULL, "DP1TX4" }, 1976 1977 { "DP2 Capture", NULL, "DP2TX1" }, 1978 { "DP2 Capture", NULL, "DP2TX2" }, 1979 1980 { "DP3 Capture", NULL, "DP3TX1" }, 1981 { "DP3 Capture", NULL, "DP3TX2" }, 1982 1983 { "DP4 Capture", NULL, "DP4TX1" }, 1984 { "DP4 Capture", NULL, "DP4TX2" }, 1985 1986 { "DP5RX1", NULL, "DP5 Playback" }, 1987 { "DP5RX2", NULL, "DP5 Playback" }, 1988 1989 { "DP6RX1", NULL, "DP6 Playback" }, 1990 { "DP6RX2", NULL, "DP6 Playback" }, 1991 1992 { "DP7RX1", NULL, "DP7 Playback" }, 1993 { "DP7RX2", NULL, "DP7 Playback" }, 1994 1995 { "AMP1", NULL, "vdd-amp" }, 1996 { "AMP2", NULL, "vdd-amp" }, 1997 1998 { "AMP1_OUT_P", NULL, "AMP1" }, 1999 { "AMP1_OUT_N", NULL, "AMP1" }, 2000 { "AMP2_OUT_P", NULL, "AMP2" }, 2001 { "AMP2_OUT_N", NULL, "AMP2" }, 2002 2003 { "SPDIF_TX", NULL, "SPDIF" }, 2004 2005 { "AMP3_OUT", NULL, "HP" }, 2006 { "AMP4_OUT", NULL, "HP" }, 2007 2008 { "Tone 1", NULL, "Tone" }, 2009 { "Tone 1", NULL, "Tone Generator" }, 2010 { "Tone 2", NULL, "Tone" }, 2011 { "Tone 2", NULL, "Tone Generator" }, 2012 2013 { "ISRC1INT2", NULL, "ISRC1" }, 2014 { "ISRC1INT1", NULL, "ISRC1" }, 2015 { "ISRC1DEC2", NULL, "ISRC1" }, 2016 { "ISRC1DEC1", NULL, "ISRC1" }, 2017 2018 { "ISRC2INT2", NULL, "ISRC2" }, 2019 { "ISRC2INT1", NULL, "ISRC2" }, 2020 { "ISRC2DEC2", NULL, "ISRC2" }, 2021 { "ISRC2DEC1", NULL, "ISRC2" }, 2022 2023 { "ASRC_INT1", NULL, "ASRC_INT" }, 2024 { "ASRC_INT2", NULL, "ASRC_INT" }, 2025 { "ASRC_INT3", NULL, "ASRC_INT" }, 2026 { "ASRC_INT4", NULL, "ASRC_INT" }, 2027 { "ASRC_DEC1", NULL, "ASRC_DEC" }, 2028 { "ASRC_DEC2", NULL, "ASRC_DEC" }, 2029 { "ASRC_DEC3", NULL, "ASRC_DEC" }, 2030 { "ASRC_DEC4", NULL, "ASRC_DEC" }, 2031 2032 { "EQ", NULL, "EQ Clock" }, 2033 2034 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), 2035 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), 2036 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"), 2037 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"), 2038 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"), 2039 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"), 2040 2041 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"), 2042 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"), 2043 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"), 2044 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"), 2045 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"), 2046 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"), 2047 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"), 2048 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"), 2049 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"), 2050 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"), 2051 2052 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), 2053 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), 2054 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), 2055 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), 2056 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), 2057 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), 2058 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), 2059 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), 2060 2061 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 2062 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 2063 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 2064 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 2065 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 2066 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 2067 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 2068 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 2069 2070 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"), 2071 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"), 2072 2073 CS42L43_MIXER_ROUTES("EQ1", "EQ"), 2074 CS42L43_MIXER_ROUTES("EQ2", "EQ"), 2075 2076 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"), 2077 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"), 2078 2079 CS42L43_MIXER_ROUTES("Headphone L", "HP"), 2080 CS42L43_MIXER_ROUTES("Headphone R", "HP"), 2081 }; 2082 2083 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, 2084 int src, unsigned int freq, int dir) 2085 { 2086 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2087 struct cs42l43 *cs42l43 = priv->core; 2088 int ret; 2089 2090 mutex_lock(&cs42l43->pll_lock); 2091 ret = cs42l43_set_pll(priv, src, freq); 2092 mutex_unlock(&cs42l43->pll_lock); 2093 2094 return ret; 2095 } 2096 2097 static int cs42l43_component_probe(struct snd_soc_component *component) 2098 { 2099 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2100 struct cs42l43 *cs42l43 = priv->core; 2101 2102 snd_soc_component_init_regmap(component, cs42l43->regmap); 2103 2104 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots, 2105 ARRAY_SIZE(priv->tx_slots)); 2106 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots, 2107 ARRAY_SIZE(priv->rx_slots)); 2108 2109 priv->component = component; 2110 priv->constraint = cs42l43_constraint; 2111 2112 return 0; 2113 } 2114 2115 static void cs42l43_component_remove(struct snd_soc_component *component) 2116 { 2117 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2118 2119 cs42l43_set_jack(priv->component, NULL, NULL); 2120 2121 cancel_delayed_work_sync(&priv->bias_sense_timeout); 2122 cancel_delayed_work_sync(&priv->tip_sense_work); 2123 cancel_delayed_work_sync(&priv->button_press_work); 2124 cancel_work_sync(&priv->button_release_work); 2125 2126 cancel_work_sync(&priv->hp_ilimit_work); 2127 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work); 2128 2129 priv->component = NULL; 2130 } 2131 2132 static const struct snd_soc_component_driver cs42l43_component_drv = { 2133 .name = "cs42l43-codec", 2134 2135 .probe = cs42l43_component_probe, 2136 .remove = cs42l43_component_remove, 2137 .set_sysclk = cs42l43_set_sysclk, 2138 .set_jack = cs42l43_set_jack, 2139 2140 .endianness = 1, 2141 2142 .controls = cs42l43_controls, 2143 .num_controls = ARRAY_SIZE(cs42l43_controls), 2144 .dapm_widgets = cs42l43_widgets, 2145 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets), 2146 .dapm_routes = cs42l43_routes, 2147 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes), 2148 }; 2149 2150 struct cs42l43_irq { 2151 unsigned int irq; 2152 const char *name; 2153 irq_handler_t handler; 2154 }; 2155 2156 static const struct cs42l43_irq cs42l43_irqs[] = { 2157 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock }, 2158 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready }, 2159 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup }, 2160 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown }, 2161 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect }, 2162 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense }, 2163 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense }, 2164 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press }, 2165 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release }, 2166 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp }, 2167 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop }, 2168 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop }, 2169 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out }, 2170 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out }, 2171 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown }, 2172 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown }, 2173 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup }, 2174 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup }, 2175 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown }, 2176 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown }, 2177 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm }, 2178 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm }, 2179 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect }, 2180 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect }, 2181 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit }, 2182 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect }, 2183 }; 2184 2185 static int cs42l43_request_irq(struct cs42l43_codec *priv, 2186 struct irq_domain *dom, const char * const name, 2187 unsigned int irq, irq_handler_t handler, 2188 unsigned long flags) 2189 { 2190 int ret; 2191 2192 ret = irq_create_mapping(dom, irq); 2193 if (ret < 0) 2194 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name); 2195 2196 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name); 2197 2198 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler, 2199 IRQF_ONESHOT | flags, name, priv); 2200 if (ret) 2201 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name); 2202 2203 return 0; 2204 } 2205 2206 static int cs42l43_shutter_irq(struct cs42l43_codec *priv, 2207 struct irq_domain *dom, unsigned int shutter, 2208 const char * const open_name, 2209 const char * const close_name, 2210 irq_handler_t handler) 2211 { 2212 unsigned int open_irq, close_irq; 2213 int ret; 2214 2215 switch (shutter) { 2216 case 0x1: 2217 dev_warn(priv->dev, "Manual shutters, notifications not available\n"); 2218 return 0; 2219 case 0x2: 2220 open_irq = CS42L43_GPIO1_RISE; 2221 close_irq = CS42L43_GPIO1_FALL; 2222 break; 2223 case 0x4: 2224 open_irq = CS42L43_GPIO2_RISE; 2225 close_irq = CS42L43_GPIO2_FALL; 2226 break; 2227 case 0x8: 2228 open_irq = CS42L43_GPIO3_RISE; 2229 close_irq = CS42L43_GPIO3_FALL; 2230 break; 2231 default: 2232 return 0; 2233 } 2234 2235 ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED); 2236 if (ret) 2237 return ret; 2238 2239 return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED); 2240 } 2241 2242 static int cs42l43_codec_probe(struct platform_device *pdev) 2243 { 2244 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); 2245 struct cs42l43_codec *priv; 2246 struct irq_domain *dom; 2247 unsigned int val; 2248 int i, ret; 2249 2250 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY); 2251 if (!dom) 2252 return -EPROBE_DEFER; 2253 2254 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2255 if (!priv) 2256 return -ENOMEM; 2257 2258 priv->dev = &pdev->dev; 2259 priv->core = cs42l43; 2260 2261 platform_set_drvdata(pdev, priv); 2262 2263 mutex_init(&priv->jack_lock); 2264 mutex_init(&priv->spk_vu_lock); 2265 2266 init_completion(&priv->hp_startup); 2267 init_completion(&priv->hp_shutdown); 2268 init_completion(&priv->spkr_shutdown); 2269 init_completion(&priv->spkl_shutdown); 2270 init_completion(&priv->spkr_startup); 2271 init_completion(&priv->spkl_startup); 2272 init_completion(&priv->pll_ready); 2273 init_completion(&priv->type_detect); 2274 init_completion(&priv->load_detect); 2275 2276 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work); 2277 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout); 2278 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work); 2279 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work); 2280 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work); 2281 INIT_WORK(&priv->hp_ilimit_work, cs42l43_hp_ilimit_work); 2282 2283 pm_runtime_set_autosuspend_delay(priv->dev, 100); 2284 pm_runtime_use_autosuspend(priv->dev); 2285 pm_runtime_set_active(priv->dev); 2286 pm_runtime_get_noresume(priv->dev); 2287 2288 ret = devm_pm_runtime_enable(priv->dev); 2289 if (ret) 2290 goto err_pm; 2291 2292 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) { 2293 ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name, 2294 cs42l43_irqs[i].irq, 2295 cs42l43_irqs[i].handler, 0); 2296 if (ret) 2297 goto err_pm; 2298 } 2299 2300 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 2301 if (ret) { 2302 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret); 2303 goto err_pm; 2304 } 2305 2306 ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK, 2307 "mic shutter open", "mic shutter close", 2308 cs42l43_mic_shutter); 2309 if (ret) 2310 goto err_pm; 2311 2312 ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >> 2313 CS42L43_SPK_SHUTTER_CFG_SHIFT, 2314 "spk shutter open", "spk shutter close", 2315 cs42l43_spk_shutter); 2316 if (ret) 2317 goto err_pm; 2318 2319 // Don't use devm as we need to get against the MFD device 2320 priv->mclk = clk_get_optional(cs42l43->dev, "mclk"); 2321 if (IS_ERR(priv->mclk)) { 2322 ret = PTR_ERR(priv->mclk); 2323 dev_err_probe(priv->dev, ret, "Failed to get mclk\n"); 2324 goto err_pm; 2325 } 2326 2327 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv, 2328 cs42l43_dais, ARRAY_SIZE(cs42l43_dais)); 2329 if (ret) { 2330 dev_err_probe(priv->dev, ret, "Failed to register component\n"); 2331 goto err_clk; 2332 } 2333 2334 pm_runtime_mark_last_busy(priv->dev); 2335 pm_runtime_put_autosuspend(priv->dev); 2336 2337 return 0; 2338 2339 err_clk: 2340 clk_put(priv->mclk); 2341 err_pm: 2342 pm_runtime_put_sync(priv->dev); 2343 2344 return ret; 2345 } 2346 2347 static void cs42l43_codec_remove(struct platform_device *pdev) 2348 { 2349 struct cs42l43_codec *priv = platform_get_drvdata(pdev); 2350 2351 clk_put(priv->mclk); 2352 } 2353 2354 static int cs42l43_codec_runtime_resume(struct device *dev) 2355 { 2356 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2357 2358 dev_dbg(priv->dev, "Runtime resume\n"); 2359 2360 // Toggle the speaker volume update incase the speaker volume was synced 2361 cs42l43_spk_vu_sync(priv); 2362 2363 return 0; 2364 } 2365 2366 static int cs42l43_codec_suspend(struct device *dev) 2367 { 2368 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2369 struct cs42l43 *cs42l43 = priv->core; 2370 2371 disable_irq(cs42l43->irq); 2372 2373 return 0; 2374 } 2375 2376 static int cs42l43_codec_suspend_noirq(struct device *dev) 2377 { 2378 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2379 struct cs42l43 *cs42l43 = priv->core; 2380 2381 enable_irq(cs42l43->irq); 2382 2383 return 0; 2384 } 2385 2386 static int cs42l43_codec_resume(struct device *dev) 2387 { 2388 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2389 struct cs42l43 *cs42l43 = priv->core; 2390 2391 enable_irq(cs42l43->irq); 2392 2393 return 0; 2394 } 2395 2396 static int cs42l43_codec_resume_noirq(struct device *dev) 2397 { 2398 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2399 struct cs42l43 *cs42l43 = priv->core; 2400 2401 disable_irq(cs42l43->irq); 2402 2403 return 0; 2404 } 2405 2406 static const struct dev_pm_ops cs42l43_codec_pm_ops = { 2407 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume) 2408 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend_noirq, cs42l43_codec_resume_noirq) 2409 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL) 2410 }; 2411 2412 static const struct platform_device_id cs42l43_codec_id_table[] = { 2413 { "cs42l43-codec", }, 2414 {} 2415 }; 2416 MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table); 2417 2418 static struct platform_driver cs42l43_codec_driver = { 2419 .driver = { 2420 .name = "cs42l43-codec", 2421 .pm = pm_ptr(&cs42l43_codec_pm_ops), 2422 }, 2423 2424 .probe = cs42l43_codec_probe, 2425 .remove_new = cs42l43_codec_remove, 2426 .id_table = cs42l43_codec_id_table, 2427 }; 2428 module_platform_driver(cs42l43_codec_driver); 2429 2430 MODULE_IMPORT_NS(SND_SOC_CS42L43); 2431 2432 MODULE_DESCRIPTION("CS42L43 CODEC Driver"); 2433 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); 2434 MODULE_LICENSE("GPL"); 2435