1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/types.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/gpio.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <linux/acpi.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/soc-dapm.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <dt-bindings/sound/cs42l42.h> 35 36 #include "cs42l42.h" 37 #include "cirrus_legacy.h" 38 39 static const char * const cs42l42_supply_names[] = { 40 "VA", 41 "VP", 42 "VCP", 43 "VD_FILT", 44 "VL", 45 }; 46 47 static const struct reg_default cs42l42_reg_defaults[] = { 48 { CS42L42_FRZ_CTL, 0x00 }, 49 { CS42L42_SRC_CTL, 0x10 }, 50 { CS42L42_MCLK_CTL, 0x02 }, 51 { CS42L42_SFTRAMP_RATE, 0xA4 }, 52 { CS42L42_SLOW_START_ENABLE, 0x70 }, 53 { CS42L42_I2C_DEBOUNCE, 0x88 }, 54 { CS42L42_I2C_STRETCH, 0x03 }, 55 { CS42L42_I2C_TIMEOUT, 0xB7 }, 56 { CS42L42_PWR_CTL1, 0xFF }, 57 { CS42L42_PWR_CTL2, 0x84 }, 58 { CS42L42_PWR_CTL3, 0x20 }, 59 { CS42L42_RSENSE_CTL1, 0x40 }, 60 { CS42L42_RSENSE_CTL2, 0x00 }, 61 { CS42L42_OSC_SWITCH, 0x00 }, 62 { CS42L42_RSENSE_CTL3, 0x1B }, 63 { CS42L42_TSENSE_CTL, 0x1B }, 64 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 65 { CS42L42_HSDET_CTL1, 0x77 }, 66 { CS42L42_HSDET_CTL2, 0x00 }, 67 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 68 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 69 { CS42L42_MCLK_SRC_SEL, 0x00 }, 70 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 71 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 72 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 73 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 74 { CS42L42_FSYNC_P_UPPER, 0x00 }, 75 { CS42L42_ASP_CLK_CFG, 0x00 }, 76 { CS42L42_ASP_FRM_CFG, 0x10 }, 77 { CS42L42_FS_RATE_EN, 0x00 }, 78 { CS42L42_IN_ASRC_CLK, 0x00 }, 79 { CS42L42_OUT_ASRC_CLK, 0x00 }, 80 { CS42L42_PLL_DIV_CFG1, 0x00 }, 81 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 82 { CS42L42_MIXER_INT_MASK, 0x0F }, 83 { CS42L42_SRC_INT_MASK, 0x0F }, 84 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 85 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 86 { CS42L42_CODEC_INT_MASK, 0x03 }, 87 { CS42L42_SRCPL_INT_MASK, 0x7F }, 88 { CS42L42_VPMON_INT_MASK, 0x01 }, 89 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 90 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 91 { CS42L42_PLL_CTL1, 0x00 }, 92 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 93 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 94 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 95 { CS42L42_PLL_DIV_INT, 0x40 }, 96 { CS42L42_PLL_CTL3, 0x10 }, 97 { CS42L42_PLL_CAL_RATIO, 0x80 }, 98 { CS42L42_PLL_CTL4, 0x03 }, 99 { CS42L42_LOAD_DET_EN, 0x00 }, 100 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 101 { CS42L42_WAKE_CTL, 0xC0 }, 102 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 103 { CS42L42_TIPSENSE_CTL, 0x02 }, 104 { CS42L42_MISC_DET_CTL, 0x03 }, 105 { CS42L42_MIC_DET_CTL1, 0x1F }, 106 { CS42L42_MIC_DET_CTL2, 0x2F }, 107 { CS42L42_DET_INT1_MASK, 0xE0 }, 108 { CS42L42_DET_INT2_MASK, 0xFF }, 109 { CS42L42_HS_BIAS_CTL, 0xC2 }, 110 { CS42L42_ADC_CTL, 0x00 }, 111 { CS42L42_ADC_VOLUME, 0x00 }, 112 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 113 { CS42L42_DAC_CTL1, 0x00 }, 114 { CS42L42_DAC_CTL2, 0x02 }, 115 { CS42L42_HP_CTL, 0x0D }, 116 { CS42L42_CLASSH_CTL, 0x07 }, 117 { CS42L42_MIXER_CHA_VOL, 0x3F }, 118 { CS42L42_MIXER_ADC_VOL, 0x3F }, 119 { CS42L42_MIXER_CHB_VOL, 0x3F }, 120 { CS42L42_EQ_COEF_IN0, 0x00 }, 121 { CS42L42_EQ_COEF_IN1, 0x00 }, 122 { CS42L42_EQ_COEF_IN2, 0x00 }, 123 { CS42L42_EQ_COEF_IN3, 0x00 }, 124 { CS42L42_EQ_COEF_RW, 0x00 }, 125 { CS42L42_EQ_COEF_OUT0, 0x00 }, 126 { CS42L42_EQ_COEF_OUT1, 0x00 }, 127 { CS42L42_EQ_COEF_OUT2, 0x00 }, 128 { CS42L42_EQ_COEF_OUT3, 0x00 }, 129 { CS42L42_EQ_INIT_STAT, 0x00 }, 130 { CS42L42_EQ_START_FILT, 0x00 }, 131 { CS42L42_EQ_MUTE_CTL, 0x00 }, 132 { CS42L42_SP_RX_CH_SEL, 0x04 }, 133 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 134 { CS42L42_SP_RX_FS, 0x8C }, 135 { CS42l42_SPDIF_CH_SEL, 0x0E }, 136 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 137 { CS42L42_SP_TX_FS, 0xCC }, 138 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 139 { CS42L42_SRC_SDIN_FS, 0x40 }, 140 { CS42L42_SRC_SDOUT_FS, 0x40 }, 141 { CS42L42_SPDIF_CTL1, 0x01 }, 142 { CS42L42_SPDIF_CTL2, 0x00 }, 143 { CS42L42_SPDIF_CTL3, 0x00 }, 144 { CS42L42_SPDIF_CTL4, 0x42 }, 145 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 146 { CS42L42_ASP_TX_CH_EN, 0x00 }, 147 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 148 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 149 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 150 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 151 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 152 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 153 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 154 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 155 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 156 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 157 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 158 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 159 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 160 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 161 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 162 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 163 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 164 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 167 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 170 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 172 }; 173 174 bool cs42l42_readable_register(struct device *dev, unsigned int reg) 175 { 176 switch (reg) { 177 case CS42L42_PAGE_REGISTER: 178 case CS42L42_DEVID_AB: 179 case CS42L42_DEVID_CD: 180 case CS42L42_DEVID_E: 181 case CS42L42_FABID: 182 case CS42L42_REVID: 183 case CS42L42_FRZ_CTL: 184 case CS42L42_SRC_CTL: 185 case CS42L42_MCLK_STATUS: 186 case CS42L42_MCLK_CTL: 187 case CS42L42_SFTRAMP_RATE: 188 case CS42L42_SLOW_START_ENABLE: 189 case CS42L42_I2C_DEBOUNCE: 190 case CS42L42_I2C_STRETCH: 191 case CS42L42_I2C_TIMEOUT: 192 case CS42L42_PWR_CTL1: 193 case CS42L42_PWR_CTL2: 194 case CS42L42_PWR_CTL3: 195 case CS42L42_RSENSE_CTL1: 196 case CS42L42_RSENSE_CTL2: 197 case CS42L42_OSC_SWITCH: 198 case CS42L42_OSC_SWITCH_STATUS: 199 case CS42L42_RSENSE_CTL3: 200 case CS42L42_TSENSE_CTL: 201 case CS42L42_TSRS_INT_DISABLE: 202 case CS42L42_TRSENSE_STATUS: 203 case CS42L42_HSDET_CTL1: 204 case CS42L42_HSDET_CTL2: 205 case CS42L42_HS_SWITCH_CTL: 206 case CS42L42_HS_DET_STATUS: 207 case CS42L42_HS_CLAMP_DISABLE: 208 case CS42L42_MCLK_SRC_SEL: 209 case CS42L42_SPDIF_CLK_CFG: 210 case CS42L42_FSYNC_PW_LOWER: 211 case CS42L42_FSYNC_PW_UPPER: 212 case CS42L42_FSYNC_P_LOWER: 213 case CS42L42_FSYNC_P_UPPER: 214 case CS42L42_ASP_CLK_CFG: 215 case CS42L42_ASP_FRM_CFG: 216 case CS42L42_FS_RATE_EN: 217 case CS42L42_IN_ASRC_CLK: 218 case CS42L42_OUT_ASRC_CLK: 219 case CS42L42_PLL_DIV_CFG1: 220 case CS42L42_ADC_OVFL_STATUS: 221 case CS42L42_MIXER_STATUS: 222 case CS42L42_SRC_STATUS: 223 case CS42L42_ASP_RX_STATUS: 224 case CS42L42_ASP_TX_STATUS: 225 case CS42L42_CODEC_STATUS: 226 case CS42L42_DET_INT_STATUS1: 227 case CS42L42_DET_INT_STATUS2: 228 case CS42L42_SRCPL_INT_STATUS: 229 case CS42L42_VPMON_STATUS: 230 case CS42L42_PLL_LOCK_STATUS: 231 case CS42L42_TSRS_PLUG_STATUS: 232 case CS42L42_ADC_OVFL_INT_MASK: 233 case CS42L42_MIXER_INT_MASK: 234 case CS42L42_SRC_INT_MASK: 235 case CS42L42_ASP_RX_INT_MASK: 236 case CS42L42_ASP_TX_INT_MASK: 237 case CS42L42_CODEC_INT_MASK: 238 case CS42L42_SRCPL_INT_MASK: 239 case CS42L42_VPMON_INT_MASK: 240 case CS42L42_PLL_LOCK_INT_MASK: 241 case CS42L42_TSRS_PLUG_INT_MASK: 242 case CS42L42_PLL_CTL1: 243 case CS42L42_PLL_DIV_FRAC0: 244 case CS42L42_PLL_DIV_FRAC1: 245 case CS42L42_PLL_DIV_FRAC2: 246 case CS42L42_PLL_DIV_INT: 247 case CS42L42_PLL_CTL3: 248 case CS42L42_PLL_CAL_RATIO: 249 case CS42L42_PLL_CTL4: 250 case CS42L42_LOAD_DET_RCSTAT: 251 case CS42L42_LOAD_DET_DONE: 252 case CS42L42_LOAD_DET_EN: 253 case CS42L42_HSBIAS_SC_AUTOCTL: 254 case CS42L42_WAKE_CTL: 255 case CS42L42_ADC_DISABLE_MUTE: 256 case CS42L42_TIPSENSE_CTL: 257 case CS42L42_MISC_DET_CTL: 258 case CS42L42_MIC_DET_CTL1: 259 case CS42L42_MIC_DET_CTL2: 260 case CS42L42_DET_STATUS1: 261 case CS42L42_DET_STATUS2: 262 case CS42L42_DET_INT1_MASK: 263 case CS42L42_DET_INT2_MASK: 264 case CS42L42_HS_BIAS_CTL: 265 case CS42L42_ADC_CTL: 266 case CS42L42_ADC_VOLUME: 267 case CS42L42_ADC_WNF_HPF_CTL: 268 case CS42L42_DAC_CTL1: 269 case CS42L42_DAC_CTL2: 270 case CS42L42_HP_CTL: 271 case CS42L42_CLASSH_CTL: 272 case CS42L42_MIXER_CHA_VOL: 273 case CS42L42_MIXER_ADC_VOL: 274 case CS42L42_MIXER_CHB_VOL: 275 case CS42L42_EQ_COEF_IN0: 276 case CS42L42_EQ_COEF_IN1: 277 case CS42L42_EQ_COEF_IN2: 278 case CS42L42_EQ_COEF_IN3: 279 case CS42L42_EQ_COEF_RW: 280 case CS42L42_EQ_COEF_OUT0: 281 case CS42L42_EQ_COEF_OUT1: 282 case CS42L42_EQ_COEF_OUT2: 283 case CS42L42_EQ_COEF_OUT3: 284 case CS42L42_EQ_INIT_STAT: 285 case CS42L42_EQ_START_FILT: 286 case CS42L42_EQ_MUTE_CTL: 287 case CS42L42_SP_RX_CH_SEL: 288 case CS42L42_SP_RX_ISOC_CTL: 289 case CS42L42_SP_RX_FS: 290 case CS42l42_SPDIF_CH_SEL: 291 case CS42L42_SP_TX_ISOC_CTL: 292 case CS42L42_SP_TX_FS: 293 case CS42L42_SPDIF_SW_CTL1: 294 case CS42L42_SRC_SDIN_FS: 295 case CS42L42_SRC_SDOUT_FS: 296 case CS42L42_SOFT_RESET_REBOOT: 297 case CS42L42_SPDIF_CTL1: 298 case CS42L42_SPDIF_CTL2: 299 case CS42L42_SPDIF_CTL3: 300 case CS42L42_SPDIF_CTL4: 301 case CS42L42_ASP_TX_SZ_EN: 302 case CS42L42_ASP_TX_CH_EN: 303 case CS42L42_ASP_TX_CH_AP_RES: 304 case CS42L42_ASP_TX_CH1_BIT_MSB: 305 case CS42L42_ASP_TX_CH1_BIT_LSB: 306 case CS42L42_ASP_TX_HIZ_DLY_CFG: 307 case CS42L42_ASP_TX_CH2_BIT_MSB: 308 case CS42L42_ASP_TX_CH2_BIT_LSB: 309 case CS42L42_ASP_RX_DAI0_EN: 310 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 311 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 312 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 313 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 314 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 315 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 316 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 317 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 318 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 319 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 320 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 321 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 322 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 323 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 324 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 325 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 326 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 327 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 328 case CS42L42_SUB_REVID: 329 return true; 330 default: 331 return false; 332 } 333 } 334 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE); 335 336 bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 337 { 338 switch (reg) { 339 case CS42L42_DEVID_AB: 340 case CS42L42_DEVID_CD: 341 case CS42L42_DEVID_E: 342 case CS42L42_MCLK_STATUS: 343 case CS42L42_OSC_SWITCH_STATUS: 344 case CS42L42_TRSENSE_STATUS: 345 case CS42L42_HS_DET_STATUS: 346 case CS42L42_ADC_OVFL_STATUS: 347 case CS42L42_MIXER_STATUS: 348 case CS42L42_SRC_STATUS: 349 case CS42L42_ASP_RX_STATUS: 350 case CS42L42_ASP_TX_STATUS: 351 case CS42L42_CODEC_STATUS: 352 case CS42L42_DET_INT_STATUS1: 353 case CS42L42_DET_INT_STATUS2: 354 case CS42L42_SRCPL_INT_STATUS: 355 case CS42L42_VPMON_STATUS: 356 case CS42L42_PLL_LOCK_STATUS: 357 case CS42L42_TSRS_PLUG_STATUS: 358 case CS42L42_LOAD_DET_RCSTAT: 359 case CS42L42_LOAD_DET_DONE: 360 case CS42L42_DET_STATUS1: 361 case CS42L42_DET_STATUS2: 362 case CS42L42_SOFT_RESET_REBOOT: 363 return true; 364 default: 365 return false; 366 } 367 } 368 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE); 369 370 const struct regmap_range_cfg cs42l42_page_range = { 371 .name = "Pages", 372 .range_min = 0, 373 .range_max = CS42L42_MAX_REGISTER, 374 .selector_reg = CS42L42_PAGE_REGISTER, 375 .selector_mask = 0xff, 376 .selector_shift = 0, 377 .window_start = 0, 378 .window_len = 256, 379 }; 380 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE); 381 382 const struct regmap_config cs42l42_regmap = { 383 .reg_bits = 8, 384 .val_bits = 8, 385 386 .readable_reg = cs42l42_readable_register, 387 .volatile_reg = cs42l42_volatile_register, 388 389 .ranges = &cs42l42_page_range, 390 .num_ranges = 1, 391 392 .max_register = CS42L42_MAX_REGISTER, 393 .reg_defaults = cs42l42_reg_defaults, 394 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 395 .cache_type = REGCACHE_MAPLE, 396 397 .use_single_read = true, 398 .use_single_write = true, 399 }; 400 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE); 401 402 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 403 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 404 405 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 406 struct snd_ctl_elem_value *ucontrol) 407 { 408 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 409 u8 val; 410 411 /* all bits of SLOW_START_EN must change together */ 412 switch (ucontrol->value.integer.value[0]) { 413 case 0: 414 val = 0; 415 break; 416 case 1: 417 val = CS42L42_SLOW_START_EN_MASK; 418 break; 419 default: 420 return -EINVAL; 421 } 422 423 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 424 CS42L42_SLOW_START_EN_MASK, val); 425 } 426 427 static const char * const cs42l42_hpf_freq_text[] = { 428 "1.86Hz", "120Hz", "235Hz", "466Hz" 429 }; 430 431 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 432 CS42L42_ADC_HPF_CF_SHIFT, 433 cs42l42_hpf_freq_text); 434 435 static const char * const cs42l42_wnf3_freq_text[] = { 436 "160Hz", "180Hz", "200Hz", "220Hz", 437 "240Hz", "260Hz", "280Hz", "300Hz" 438 }; 439 440 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 441 CS42L42_ADC_WNF_CF_SHIFT, 442 cs42l42_wnf3_freq_text); 443 444 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 445 /* ADC Volume and Filter Controls */ 446 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 447 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 448 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 449 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 450 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 451 CS42L42_ADC_INV_SHIFT, true, false), 452 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 453 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 454 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 455 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 456 CS42L42_ADC_WNF_EN_SHIFT, true, false), 457 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 458 CS42L42_ADC_HPF_EN_SHIFT, true, false), 459 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 460 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 461 462 /* DAC Volume and Filter Controls */ 463 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 464 CS42L42_DACA_INV_SHIFT, true, false), 465 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 466 CS42L42_DACB_INV_SHIFT, true, false), 467 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 468 CS42L42_DAC_HPF_EN_SHIFT, true, false), 469 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 470 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 471 0x3f, 1, mixer_tlv), 472 473 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 474 CS42L42_SLOW_START_EN_SHIFT, true, false, 475 snd_soc_get_volsw, cs42l42_slow_start_put), 476 }; 477 478 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 479 struct snd_kcontrol *kcontrol, int event) 480 { 481 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 482 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 483 484 switch (event) { 485 case SND_SOC_DAPM_PRE_PMU: 486 cs42l42->hp_adc_up_pending = true; 487 break; 488 case SND_SOC_DAPM_POST_PMU: 489 /* Only need one delay if HP and ADC are both powering-up */ 490 if (cs42l42->hp_adc_up_pending) { 491 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 492 CS42L42_HP_ADC_EN_TIME_US + 1000); 493 cs42l42->hp_adc_up_pending = false; 494 } 495 break; 496 default: 497 break; 498 } 499 500 return 0; 501 } 502 503 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 504 /* Playback Path */ 505 SND_SOC_DAPM_OUTPUT("HP"), 506 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 507 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 508 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 509 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 510 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 511 512 /* Playback Requirements */ 513 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 514 515 /* Capture Path */ 516 SND_SOC_DAPM_INPUT("HS"), 517 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 518 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 519 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 520 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 521 522 /* Capture Requirements */ 523 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 524 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 525 526 /* Playback/Capture Requirements */ 527 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 528 529 /* Soundwire SRC power control */ 530 SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0), 531 SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0), 532 }; 533 534 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 535 /* Playback Path */ 536 {"HP", NULL, "DAC"}, 537 {"DAC", NULL, "MIXER"}, 538 {"MIXER", NULL, "SDIN1"}, 539 {"MIXER", NULL, "SDIN2"}, 540 {"SDIN1", NULL, "Playback"}, 541 {"SDIN2", NULL, "Playback"}, 542 543 /* Playback Requirements */ 544 {"SDIN1", NULL, "ASP DAI0"}, 545 {"SDIN2", NULL, "ASP DAI0"}, 546 {"SDIN1", NULL, "SCLK"}, 547 {"SDIN2", NULL, "SCLK"}, 548 549 /* Capture Path */ 550 {"ADC", NULL, "HS"}, 551 { "SDOUT1", NULL, "ADC" }, 552 { "SDOUT2", NULL, "ADC" }, 553 { "Capture", NULL, "SDOUT1" }, 554 { "Capture", NULL, "SDOUT2" }, 555 556 /* Capture Requirements */ 557 { "SDOUT1", NULL, "ASP DAO0" }, 558 { "SDOUT2", NULL, "ASP DAO0" }, 559 { "SDOUT1", NULL, "SCLK" }, 560 { "SDOUT2", NULL, "SCLK" }, 561 { "SDOUT1", NULL, "ASP TX EN" }, 562 { "SDOUT2", NULL, "ASP TX EN" }, 563 }; 564 565 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 566 { 567 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 568 569 /* Prevent race with interrupt handler */ 570 mutex_lock(&cs42l42->irq_lock); 571 cs42l42->jack = jk; 572 573 if (jk) { 574 switch (cs42l42->hs_type) { 575 case CS42L42_PLUG_CTIA: 576 case CS42L42_PLUG_OMTP: 577 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET); 578 break; 579 case CS42L42_PLUG_HEADPHONE: 580 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE); 581 break; 582 default: 583 break; 584 } 585 } 586 mutex_unlock(&cs42l42->irq_lock); 587 588 return 0; 589 } 590 591 const struct snd_soc_component_driver cs42l42_soc_component = { 592 .set_jack = cs42l42_set_jack, 593 .dapm_widgets = cs42l42_dapm_widgets, 594 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 595 .dapm_routes = cs42l42_audio_map, 596 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 597 .controls = cs42l42_snd_controls, 598 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 599 .endianness = 1, 600 }; 601 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE); 602 603 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 604 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 605 { 606 .reg = CS42L42_OSC_SWITCH, 607 .def = CS42L42_SCLK_PRESENT_MASK, 608 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 609 }, 610 }; 611 612 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 613 static const struct reg_sequence cs42l42_to_osc_seq[] = { 614 { 615 .reg = CS42L42_OSC_SWITCH, 616 .def = 0, 617 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 618 }, 619 }; 620 621 struct cs42l42_pll_params { 622 u32 sclk; 623 u8 mclk_src_sel; 624 u8 sclk_prediv; 625 u8 pll_div_int; 626 u32 pll_div_frac; 627 u8 pll_mode; 628 u8 pll_divout; 629 u32 mclk_int; 630 u8 pll_cal_ratio; 631 u8 n; 632 }; 633 634 /* 635 * Common PLL Settings for given SCLK 636 * Table 4-5 from the Datasheet 637 */ 638 static const struct cs42l42_pll_params pll_ratio_table[] = { 639 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 640 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 641 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 642 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 643 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 644 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 645 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 646 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 647 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 648 { 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 649 { 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 650 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 651 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 652 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 653 { 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}, 654 { 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 655 { 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 656 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 657 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 658 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 659 { 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 660 { 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, 661 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 662 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 663 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 664 }; 665 666 int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk, 667 unsigned int sample_rate) 668 { 669 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 670 int i; 671 672 /* Don't reconfigure if there is an audio stream running */ 673 if (cs42l42->stream_use) { 674 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 675 return 0; 676 else 677 return -EBUSY; 678 } 679 680 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 681 /* MCLKint must be a multiple of the sample rate */ 682 if (pll_ratio_table[i].mclk_int % sample_rate) 683 continue; 684 685 if (pll_ratio_table[i].sclk == clk) { 686 cs42l42->pll_config = i; 687 688 /* Configure the internal sample rate */ 689 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 690 CS42L42_INTERNAL_FS_MASK, 691 ((pll_ratio_table[i].mclk_int != 692 12000000) && 693 (pll_ratio_table[i].mclk_int != 694 24000000)) << 695 CS42L42_INTERNAL_FS_SHIFT); 696 if (pll_ratio_table[i].mclk_src_sel == 0) { 697 /* Pass the clock straight through */ 698 snd_soc_component_update_bits(component, 699 CS42L42_PLL_CTL1, 700 CS42L42_PLL_START_MASK, 0); 701 } else { 702 /* Configure PLL per table 4-5 */ 703 snd_soc_component_update_bits(component, 704 CS42L42_PLL_DIV_CFG1, 705 CS42L42_SCLK_PREDIV_MASK, 706 pll_ratio_table[i].sclk_prediv 707 << CS42L42_SCLK_PREDIV_SHIFT); 708 snd_soc_component_update_bits(component, 709 CS42L42_PLL_DIV_INT, 710 CS42L42_PLL_DIV_INT_MASK, 711 pll_ratio_table[i].pll_div_int 712 << CS42L42_PLL_DIV_INT_SHIFT); 713 snd_soc_component_update_bits(component, 714 CS42L42_PLL_DIV_FRAC0, 715 CS42L42_PLL_DIV_FRAC_MASK, 716 CS42L42_FRAC0_VAL( 717 pll_ratio_table[i].pll_div_frac) 718 << CS42L42_PLL_DIV_FRAC_SHIFT); 719 snd_soc_component_update_bits(component, 720 CS42L42_PLL_DIV_FRAC1, 721 CS42L42_PLL_DIV_FRAC_MASK, 722 CS42L42_FRAC1_VAL( 723 pll_ratio_table[i].pll_div_frac) 724 << CS42L42_PLL_DIV_FRAC_SHIFT); 725 snd_soc_component_update_bits(component, 726 CS42L42_PLL_DIV_FRAC2, 727 CS42L42_PLL_DIV_FRAC_MASK, 728 CS42L42_FRAC2_VAL( 729 pll_ratio_table[i].pll_div_frac) 730 << CS42L42_PLL_DIV_FRAC_SHIFT); 731 snd_soc_component_update_bits(component, 732 CS42L42_PLL_CTL4, 733 CS42L42_PLL_MODE_MASK, 734 pll_ratio_table[i].pll_mode 735 << CS42L42_PLL_MODE_SHIFT); 736 snd_soc_component_update_bits(component, 737 CS42L42_PLL_CTL3, 738 CS42L42_PLL_DIVOUT_MASK, 739 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 740 << CS42L42_PLL_DIVOUT_SHIFT); 741 snd_soc_component_update_bits(component, 742 CS42L42_PLL_CAL_RATIO, 743 CS42L42_PLL_CAL_RATIO_MASK, 744 pll_ratio_table[i].pll_cal_ratio 745 << CS42L42_PLL_CAL_RATIO_SHIFT); 746 } 747 return 0; 748 } 749 } 750 751 return -EINVAL; 752 } 753 EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE); 754 755 void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 756 { 757 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 758 unsigned int fs; 759 760 /* Don't reconfigure if there is an audio stream running */ 761 if (cs42l42->stream_use) 762 return; 763 764 /* SRC MCLK must be as close as possible to 125 * sample rate */ 765 if (sample_rate <= 48000) 766 fs = CS42L42_CLK_IASRC_SEL_6; 767 else 768 fs = CS42L42_CLK_IASRC_SEL_12; 769 770 /* Set the sample rates (96k or lower) */ 771 snd_soc_component_update_bits(component, 772 CS42L42_FS_RATE_EN, 773 CS42L42_FS_EN_MASK, 774 (CS42L42_FS_EN_IASRC_96K | 775 CS42L42_FS_EN_OASRC_96K) << 776 CS42L42_FS_EN_SHIFT); 777 778 snd_soc_component_update_bits(component, 779 CS42L42_IN_ASRC_CLK, 780 CS42L42_CLK_IASRC_SEL_MASK, 781 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 782 snd_soc_component_update_bits(component, 783 CS42L42_OUT_ASRC_CLK, 784 CS42L42_CLK_OASRC_SEL_MASK, 785 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 786 } 787 EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE); 788 789 static int cs42l42_asp_config(struct snd_soc_component *component, 790 unsigned int sclk, unsigned int sample_rate) 791 { 792 u32 fsync = sclk / sample_rate; 793 794 /* Set up the LRCLK */ 795 if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) { 796 dev_err(component->dev, 797 "Unsupported sclk %d/sample rate %d\n", 798 sclk, 799 sample_rate); 800 return -EINVAL; 801 } 802 /* Set the LRCLK period */ 803 snd_soc_component_update_bits(component, 804 CS42L42_FSYNC_P_LOWER, 805 CS42L42_FSYNC_PERIOD_MASK, 806 CS42L42_FRAC0_VAL(fsync - 1) << 807 CS42L42_FSYNC_PERIOD_SHIFT); 808 snd_soc_component_update_bits(component, 809 CS42L42_FSYNC_P_UPPER, 810 CS42L42_FSYNC_PERIOD_MASK, 811 CS42L42_FRAC1_VAL(fsync - 1) << 812 CS42L42_FSYNC_PERIOD_SHIFT); 813 /* Set the LRCLK to 50% duty cycle */ 814 fsync = fsync / 2; 815 snd_soc_component_update_bits(component, 816 CS42L42_FSYNC_PW_LOWER, 817 CS42L42_FSYNC_PULSE_WIDTH_MASK, 818 CS42L42_FRAC0_VAL(fsync - 1) << 819 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 820 snd_soc_component_update_bits(component, 821 CS42L42_FSYNC_PW_UPPER, 822 CS42L42_FSYNC_PULSE_WIDTH_MASK, 823 CS42L42_FRAC1_VAL(fsync - 1) << 824 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 825 826 return 0; 827 } 828 829 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 830 { 831 struct snd_soc_component *component = codec_dai->component; 832 u32 asp_cfg_val = 0; 833 834 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 835 case SND_SOC_DAIFMT_CBS_CFM: 836 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 837 CS42L42_ASP_MODE_SHIFT; 838 break; 839 case SND_SOC_DAIFMT_CBS_CFS: 840 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 841 CS42L42_ASP_MODE_SHIFT; 842 break; 843 default: 844 return -EINVAL; 845 } 846 847 /* interface format */ 848 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 849 case SND_SOC_DAIFMT_I2S: 850 /* 851 * 5050 mode, frame starts on falling edge of LRCLK, 852 * frame delayed by 1.0 SCLKs 853 */ 854 snd_soc_component_update_bits(component, 855 CS42L42_ASP_FRM_CFG, 856 CS42L42_ASP_STP_MASK | 857 CS42L42_ASP_5050_MASK | 858 CS42L42_ASP_FSD_MASK, 859 CS42L42_ASP_5050_MASK | 860 (CS42L42_ASP_FSD_1_0 << 861 CS42L42_ASP_FSD_SHIFT)); 862 break; 863 default: 864 return -EINVAL; 865 } 866 867 /* Bitclock/frame inversion */ 868 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 869 case SND_SOC_DAIFMT_NB_NF: 870 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 871 break; 872 case SND_SOC_DAIFMT_NB_IF: 873 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 874 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 875 break; 876 case SND_SOC_DAIFMT_IB_NF: 877 break; 878 case SND_SOC_DAIFMT_IB_IF: 879 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 880 break; 881 } 882 883 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 884 CS42L42_ASP_SCPOL_MASK | 885 CS42L42_ASP_LCPOL_MASK, 886 asp_cfg_val); 887 888 return 0; 889 } 890 891 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 892 { 893 struct snd_soc_component *component = dai->component; 894 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 895 896 /* 897 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 898 * a standard I2S frame. If the machine driver sets SCLK it must be 899 * legal. 900 */ 901 if (cs42l42->sclk) 902 return 0; 903 904 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 905 return snd_pcm_hw_constraint_minmax(substream->runtime, 906 SNDRV_PCM_HW_PARAM_RATE, 907 44100, 96000); 908 } 909 910 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 911 struct snd_pcm_hw_params *params, 912 struct snd_soc_dai *dai) 913 { 914 struct snd_soc_component *component = dai->component; 915 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 916 unsigned int channels = params_channels(params); 917 unsigned int width = (params_width(params) / 8) - 1; 918 unsigned int sample_rate = params_rate(params); 919 unsigned int slot_width = 0; 920 unsigned int val = 0; 921 unsigned int bclk; 922 int ret; 923 924 if (cs42l42->bclk_ratio) { 925 /* machine driver has set the BCLK/samp-rate ratio */ 926 bclk = cs42l42->bclk_ratio * params_rate(params); 927 } else if (cs42l42->sclk) { 928 /* machine driver has set the SCLK */ 929 bclk = cs42l42->sclk; 930 } else { 931 /* 932 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 933 * more than assumed (which would result in overclocking). 934 */ 935 if (params_width(params) == 24) 936 slot_width = 32; 937 938 /* I2S frame always has multiple of 2 channels */ 939 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); 940 } 941 942 switch (substream->stream) { 943 case SNDRV_PCM_STREAM_CAPTURE: 944 /* channel 2 on high LRCLK */ 945 val = CS42L42_ASP_TX_CH2_AP_MASK | 946 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 947 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 948 949 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 950 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 951 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 952 break; 953 case SNDRV_PCM_STREAM_PLAYBACK: 954 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 955 /* channel 1 on low LRCLK */ 956 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 957 CS42L42_ASP_RX_CH_AP_MASK | 958 CS42L42_ASP_RX_CH_RES_MASK, val); 959 /* Channel 2 on high LRCLK */ 960 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 961 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 962 CS42L42_ASP_RX_CH_AP_MASK | 963 CS42L42_ASP_RX_CH_RES_MASK, val); 964 965 /* Channel B comes from the last active channel */ 966 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 967 CS42L42_SP_RX_CHB_SEL_MASK, 968 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 969 970 /* Both LRCLK slots must be enabled */ 971 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 972 CS42L42_ASP_RX0_CH_EN_MASK, 973 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 974 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 975 break; 976 default: 977 break; 978 } 979 980 ret = cs42l42_pll_config(component, bclk, sample_rate); 981 if (ret) 982 return ret; 983 984 ret = cs42l42_asp_config(component, bclk, sample_rate); 985 if (ret) 986 return ret; 987 988 cs42l42_src_config(component, sample_rate); 989 990 return 0; 991 } 992 993 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 994 int clk_id, unsigned int freq, int dir) 995 { 996 struct snd_soc_component *component = dai->component; 997 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 998 int i; 999 1000 if (freq == 0) { 1001 cs42l42->sclk = 0; 1002 return 0; 1003 } 1004 1005 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 1006 if (pll_ratio_table[i].sclk == freq) { 1007 cs42l42->sclk = freq; 1008 return 0; 1009 } 1010 } 1011 1012 dev_err(component->dev, "SCLK %u not supported\n", freq); 1013 1014 return -EINVAL; 1015 } 1016 1017 static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai, 1018 unsigned int bclk_ratio) 1019 { 1020 struct snd_soc_component *component = dai->component; 1021 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1022 1023 cs42l42->bclk_ratio = bclk_ratio; 1024 1025 return 0; 1026 } 1027 1028 int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1029 { 1030 struct snd_soc_component *component = dai->component; 1031 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 1032 unsigned int regval; 1033 int ret; 1034 1035 if (mute) { 1036 /* Mute the headphone */ 1037 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1038 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1039 CS42L42_HP_ANA_AMUTE_MASK | 1040 CS42L42_HP_ANA_BMUTE_MASK, 1041 CS42L42_HP_ANA_AMUTE_MASK | 1042 CS42L42_HP_ANA_BMUTE_MASK); 1043 1044 cs42l42->stream_use &= ~(1 << stream); 1045 if (!cs42l42->stream_use) { 1046 /* 1047 * Switch to the internal oscillator. 1048 * SCLK must remain running until after this clock switch. 1049 * Without a source of clock the I2C bus doesn't work. 1050 */ 1051 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 1052 ARRAY_SIZE(cs42l42_to_osc_seq)); 1053 1054 /* Must disconnect PLL before stopping it */ 1055 snd_soc_component_update_bits(component, 1056 CS42L42_MCLK_SRC_SEL, 1057 CS42L42_MCLK_SRC_SEL_MASK, 1058 0); 1059 usleep_range(100, 200); 1060 1061 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1062 CS42L42_PLL_START_MASK, 0); 1063 } 1064 } else { 1065 if (!cs42l42->stream_use) { 1066 /* SCLK must be running before codec unmute. 1067 * 1068 * PLL must not be started with ADC and HP both off 1069 * otherwise the FILT+ supply will not charge properly. 1070 * DAPM widgets power-up before stream unmute so at least 1071 * one of the "DAC" or "ADC" widgets will already have 1072 * powered-up. 1073 */ 1074 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1075 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1076 CS42L42_PLL_START_MASK, 1); 1077 1078 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1079 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1080 CS42L42_PLL_DIVOUT_TIME_US * 2); 1081 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1082 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1083 CS42L42_PLL_DIVOUT_MASK, 1084 regval << 1085 CS42L42_PLL_DIVOUT_SHIFT); 1086 } 1087 1088 ret = regmap_read_poll_timeout(cs42l42->regmap, 1089 CS42L42_PLL_LOCK_STATUS, 1090 regval, 1091 (regval & 1), 1092 CS42L42_PLL_LOCK_POLL_US, 1093 CS42L42_PLL_LOCK_TIMEOUT_US); 1094 if (ret < 0) 1095 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1096 1097 /* PLL must be running to drive glitchless switch logic */ 1098 snd_soc_component_update_bits(component, 1099 CS42L42_MCLK_SRC_SEL, 1100 CS42L42_MCLK_SRC_SEL_MASK, 1101 CS42L42_MCLK_SRC_SEL_MASK); 1102 } 1103 1104 /* Mark SCLK as present, turn off internal oscillator */ 1105 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1106 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1107 } 1108 cs42l42->stream_use |= 1 << stream; 1109 1110 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1111 /* Un-mute the headphone */ 1112 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1113 CS42L42_HP_ANA_AMUTE_MASK | 1114 CS42L42_HP_ANA_BMUTE_MASK, 1115 0); 1116 } 1117 } 1118 1119 return 0; 1120 } 1121 EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE); 1122 1123 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1124 SNDRV_PCM_FMTBIT_S24_LE |\ 1125 SNDRV_PCM_FMTBIT_S32_LE) 1126 1127 static const struct snd_soc_dai_ops cs42l42_ops = { 1128 .startup = cs42l42_dai_startup, 1129 .hw_params = cs42l42_pcm_hw_params, 1130 .set_fmt = cs42l42_set_dai_fmt, 1131 .set_sysclk = cs42l42_set_sysclk, 1132 .set_bclk_ratio = cs42l42_set_bclk_ratio, 1133 .mute_stream = cs42l42_mute_stream, 1134 }; 1135 1136 struct snd_soc_dai_driver cs42l42_dai = { 1137 .name = "cs42l42", 1138 .playback = { 1139 .stream_name = "Playback", 1140 .channels_min = 1, 1141 .channels_max = 2, 1142 .rates = SNDRV_PCM_RATE_8000_96000, 1143 .formats = CS42L42_FORMATS, 1144 }, 1145 .capture = { 1146 .stream_name = "Capture", 1147 .channels_min = 1, 1148 .channels_max = 2, 1149 .rates = SNDRV_PCM_RATE_8000_96000, 1150 .formats = CS42L42_FORMATS, 1151 }, 1152 .symmetric_rate = 1, 1153 .symmetric_sample_bits = 1, 1154 .ops = &cs42l42_ops, 1155 }; 1156 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE); 1157 1158 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1159 { 1160 unsigned int hs_det_status; 1161 unsigned int hs_det_comp1; 1162 unsigned int hs_det_comp2; 1163 unsigned int hs_det_sw; 1164 1165 /* Set hs detect to manual, active mode */ 1166 regmap_update_bits(cs42l42->regmap, 1167 CS42L42_HSDET_CTL2, 1168 CS42L42_HSDET_CTRL_MASK | 1169 CS42L42_HSDET_SET_MASK | 1170 CS42L42_HSBIAS_REF_MASK | 1171 CS42L42_HSDET_AUTO_TIME_MASK, 1172 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1173 (0 << CS42L42_HSDET_SET_SHIFT) | 1174 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1175 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1176 1177 /* Configure HS DET comparator reference levels. */ 1178 regmap_update_bits(cs42l42->regmap, 1179 CS42L42_HSDET_CTL1, 1180 CS42L42_HSDET_COMP1_LVL_MASK | 1181 CS42L42_HSDET_COMP2_LVL_MASK, 1182 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1183 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1184 1185 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1186 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1187 1188 msleep(100); 1189 1190 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1191 1192 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1193 CS42L42_HSDET_COMP1_OUT_SHIFT; 1194 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1195 CS42L42_HSDET_COMP2_OUT_SHIFT; 1196 1197 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1198 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1199 1200 msleep(100); 1201 1202 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1203 1204 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1205 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1206 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1207 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1208 1209 /* Use Comparator 1 with 1.25V Threshold. */ 1210 switch (hs_det_comp1) { 1211 case CS42L42_HSDET_COMP_TYPE1: 1212 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1213 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1214 break; 1215 case CS42L42_HSDET_COMP_TYPE2: 1216 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1217 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1218 break; 1219 default: 1220 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1221 switch (hs_det_comp2) { 1222 case CS42L42_HSDET_COMP_TYPE1: 1223 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1224 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1225 break; 1226 case CS42L42_HSDET_COMP_TYPE2: 1227 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1228 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1229 break; 1230 /* Detect Type 3 and Type 4 Headsets as Headphones */ 1231 default: 1232 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1233 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1234 break; 1235 } 1236 } 1237 1238 /* Set Switches */ 1239 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1240 1241 /* Set HSDET mode to Manual—Disabled */ 1242 regmap_update_bits(cs42l42->regmap, 1243 CS42L42_HSDET_CTL2, 1244 CS42L42_HSDET_CTRL_MASK | 1245 CS42L42_HSDET_SET_MASK | 1246 CS42L42_HSBIAS_REF_MASK | 1247 CS42L42_HSDET_AUTO_TIME_MASK, 1248 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1249 (0 << CS42L42_HSDET_SET_SHIFT) | 1250 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1251 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1252 1253 /* Configure HS DET comparator reference levels. */ 1254 regmap_update_bits(cs42l42->regmap, 1255 CS42L42_HSDET_CTL1, 1256 CS42L42_HSDET_COMP1_LVL_MASK | 1257 CS42L42_HSDET_COMP2_LVL_MASK, 1258 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1259 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1260 } 1261 1262 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1263 { 1264 unsigned int hs_det_status; 1265 unsigned int int_status; 1266 1267 /* Read and save the hs detection result */ 1268 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1269 1270 /* Mask the auto detect interrupt */ 1271 regmap_update_bits(cs42l42->regmap, 1272 CS42L42_CODEC_INT_MASK, 1273 CS42L42_PDN_DONE_MASK | 1274 CS42L42_HSDET_AUTO_DONE_MASK, 1275 (1 << CS42L42_PDN_DONE_SHIFT) | 1276 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1277 1278 1279 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1280 CS42L42_HSDET_TYPE_SHIFT; 1281 1282 /* Set hs detect to automatic, disabled mode */ 1283 regmap_update_bits(cs42l42->regmap, 1284 CS42L42_HSDET_CTL2, 1285 CS42L42_HSDET_CTRL_MASK | 1286 CS42L42_HSDET_SET_MASK | 1287 CS42L42_HSBIAS_REF_MASK | 1288 CS42L42_HSDET_AUTO_TIME_MASK, 1289 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1290 (2 << CS42L42_HSDET_SET_SHIFT) | 1291 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1292 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1293 1294 /* Run Manual detection if auto detect has not found a headset. 1295 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1296 * to ensure that a headset mic is detected in all cases. 1297 */ 1298 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1299 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1300 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1301 cs42l42_manual_hs_type_detect(cs42l42); 1302 } 1303 1304 /* Set up button detection */ 1305 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1306 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1307 /* Set auto HS bias settings to default */ 1308 regmap_update_bits(cs42l42->regmap, 1309 CS42L42_HSBIAS_SC_AUTOCTL, 1310 CS42L42_HSBIAS_SENSE_EN_MASK | 1311 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1312 CS42L42_TIP_SENSE_EN_MASK | 1313 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1314 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1315 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1316 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1317 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1318 1319 /* Set up hs detect level sensitivity */ 1320 regmap_update_bits(cs42l42->regmap, 1321 CS42L42_MIC_DET_CTL1, 1322 CS42L42_LATCH_TO_VP_MASK | 1323 CS42L42_EVENT_STAT_SEL_MASK | 1324 CS42L42_HS_DET_LEVEL_MASK, 1325 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1326 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1327 (cs42l42->bias_thresholds[0] << 1328 CS42L42_HS_DET_LEVEL_SHIFT)); 1329 1330 /* Set auto HS bias settings to default */ 1331 regmap_update_bits(cs42l42->regmap, 1332 CS42L42_HSBIAS_SC_AUTOCTL, 1333 CS42L42_HSBIAS_SENSE_EN_MASK | 1334 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1335 CS42L42_TIP_SENSE_EN_MASK | 1336 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1337 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1338 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1339 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1340 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1341 1342 /* Turn on level detect circuitry */ 1343 regmap_update_bits(cs42l42->regmap, 1344 CS42L42_MISC_DET_CTL, 1345 CS42L42_HSBIAS_CTL_MASK | 1346 CS42L42_PDN_MIC_LVL_DET_MASK, 1347 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1348 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1349 1350 msleep(cs42l42->btn_det_init_dbnce); 1351 1352 /* Clear any button interrupts before unmasking them */ 1353 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1354 &int_status); 1355 1356 /* Unmask button detect interrupts */ 1357 regmap_update_bits(cs42l42->regmap, 1358 CS42L42_DET_INT2_MASK, 1359 CS42L42_M_DETECT_TF_MASK | 1360 CS42L42_M_DETECT_FT_MASK | 1361 CS42L42_M_HSBIAS_HIZ_MASK | 1362 CS42L42_M_SHORT_RLS_MASK | 1363 CS42L42_M_SHORT_DET_MASK, 1364 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1365 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1366 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1367 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1368 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1369 } else { 1370 /* Make sure button detect and HS bias circuits are off */ 1371 regmap_update_bits(cs42l42->regmap, 1372 CS42L42_MISC_DET_CTL, 1373 CS42L42_HSBIAS_CTL_MASK | 1374 CS42L42_PDN_MIC_LVL_DET_MASK, 1375 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1376 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1377 } 1378 1379 regmap_update_bits(cs42l42->regmap, 1380 CS42L42_DAC_CTL2, 1381 CS42L42_HPOUT_PULLDOWN_MASK | 1382 CS42L42_HPOUT_LOAD_MASK | 1383 CS42L42_HPOUT_CLAMP_MASK | 1384 CS42L42_DAC_HPF_EN_MASK | 1385 CS42L42_DAC_MON_EN_MASK, 1386 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1387 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1388 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1389 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1390 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1391 1392 /* Unmask tip sense interrupts */ 1393 regmap_update_bits(cs42l42->regmap, 1394 CS42L42_TSRS_PLUG_INT_MASK, 1395 CS42L42_TS_PLUG_MASK | 1396 CS42L42_TS_UNPLUG_MASK, 1397 (0 << CS42L42_TS_PLUG_SHIFT) | 1398 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1399 } 1400 1401 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1402 { 1403 /* Mask tip sense interrupts */ 1404 regmap_update_bits(cs42l42->regmap, 1405 CS42L42_TSRS_PLUG_INT_MASK, 1406 CS42L42_TS_PLUG_MASK | 1407 CS42L42_TS_UNPLUG_MASK, 1408 (1 << CS42L42_TS_PLUG_SHIFT) | 1409 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1410 1411 /* Make sure button detect and HS bias circuits are off */ 1412 regmap_update_bits(cs42l42->regmap, 1413 CS42L42_MISC_DET_CTL, 1414 CS42L42_HSBIAS_CTL_MASK | 1415 CS42L42_PDN_MIC_LVL_DET_MASK, 1416 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1417 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1418 1419 /* Set auto HS bias settings to default */ 1420 regmap_update_bits(cs42l42->regmap, 1421 CS42L42_HSBIAS_SC_AUTOCTL, 1422 CS42L42_HSBIAS_SENSE_EN_MASK | 1423 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1424 CS42L42_TIP_SENSE_EN_MASK | 1425 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1426 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1427 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1428 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1429 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1430 1431 /* Set hs detect to manual, disabled mode */ 1432 regmap_update_bits(cs42l42->regmap, 1433 CS42L42_HSDET_CTL2, 1434 CS42L42_HSDET_CTRL_MASK | 1435 CS42L42_HSDET_SET_MASK | 1436 CS42L42_HSBIAS_REF_MASK | 1437 CS42L42_HSDET_AUTO_TIME_MASK, 1438 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1439 (2 << CS42L42_HSDET_SET_SHIFT) | 1440 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1441 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1442 1443 regmap_update_bits(cs42l42->regmap, 1444 CS42L42_DAC_CTL2, 1445 CS42L42_HPOUT_PULLDOWN_MASK | 1446 CS42L42_HPOUT_LOAD_MASK | 1447 CS42L42_HPOUT_CLAMP_MASK | 1448 CS42L42_DAC_HPF_EN_MASK | 1449 CS42L42_DAC_MON_EN_MASK, 1450 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1451 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1452 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1453 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1454 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1455 1456 /* Power up HS bias to 2.7V */ 1457 regmap_update_bits(cs42l42->regmap, 1458 CS42L42_MISC_DET_CTL, 1459 CS42L42_HSBIAS_CTL_MASK | 1460 CS42L42_PDN_MIC_LVL_DET_MASK, 1461 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1462 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1463 1464 /* Wait for HS bias to ramp up */ 1465 msleep(cs42l42->hs_bias_ramp_time); 1466 1467 /* Unmask auto detect interrupt */ 1468 regmap_update_bits(cs42l42->regmap, 1469 CS42L42_CODEC_INT_MASK, 1470 CS42L42_PDN_DONE_MASK | 1471 CS42L42_HSDET_AUTO_DONE_MASK, 1472 (1 << CS42L42_PDN_DONE_SHIFT) | 1473 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1474 1475 /* Set hs detect to automatic, enabled mode */ 1476 regmap_update_bits(cs42l42->regmap, 1477 CS42L42_HSDET_CTL2, 1478 CS42L42_HSDET_CTRL_MASK | 1479 CS42L42_HSDET_SET_MASK | 1480 CS42L42_HSBIAS_REF_MASK | 1481 CS42L42_HSDET_AUTO_TIME_MASK, 1482 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1483 (2 << CS42L42_HSDET_SET_SHIFT) | 1484 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1485 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1486 } 1487 1488 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1489 { 1490 /* Mask button detect interrupts */ 1491 regmap_update_bits(cs42l42->regmap, 1492 CS42L42_DET_INT2_MASK, 1493 CS42L42_M_DETECT_TF_MASK | 1494 CS42L42_M_DETECT_FT_MASK | 1495 CS42L42_M_HSBIAS_HIZ_MASK | 1496 CS42L42_M_SHORT_RLS_MASK | 1497 CS42L42_M_SHORT_DET_MASK, 1498 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1499 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1500 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1501 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1502 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1503 1504 /* Ground HS bias */ 1505 regmap_update_bits(cs42l42->regmap, 1506 CS42L42_MISC_DET_CTL, 1507 CS42L42_HSBIAS_CTL_MASK | 1508 CS42L42_PDN_MIC_LVL_DET_MASK, 1509 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1510 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1511 1512 /* Set auto HS bias settings to default */ 1513 regmap_update_bits(cs42l42->regmap, 1514 CS42L42_HSBIAS_SC_AUTOCTL, 1515 CS42L42_HSBIAS_SENSE_EN_MASK | 1516 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1517 CS42L42_TIP_SENSE_EN_MASK | 1518 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1519 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1520 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1521 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1522 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1523 1524 /* Set hs detect to manual, disabled mode */ 1525 regmap_update_bits(cs42l42->regmap, 1526 CS42L42_HSDET_CTL2, 1527 CS42L42_HSDET_CTRL_MASK | 1528 CS42L42_HSDET_SET_MASK | 1529 CS42L42_HSBIAS_REF_MASK | 1530 CS42L42_HSDET_AUTO_TIME_MASK, 1531 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1532 (2 << CS42L42_HSDET_SET_SHIFT) | 1533 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1534 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1535 } 1536 1537 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1538 { 1539 int bias_level; 1540 unsigned int detect_status; 1541 1542 /* Mask button detect interrupts */ 1543 regmap_update_bits(cs42l42->regmap, 1544 CS42L42_DET_INT2_MASK, 1545 CS42L42_M_DETECT_TF_MASK | 1546 CS42L42_M_DETECT_FT_MASK | 1547 CS42L42_M_HSBIAS_HIZ_MASK | 1548 CS42L42_M_SHORT_RLS_MASK | 1549 CS42L42_M_SHORT_DET_MASK, 1550 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1551 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1552 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1553 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1554 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1555 1556 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1557 cs42l42->btn_det_event_dbnce * 2000); 1558 1559 /* Test all 4 level detect biases */ 1560 bias_level = 1; 1561 do { 1562 /* Adjust button detect level sensitivity */ 1563 regmap_update_bits(cs42l42->regmap, 1564 CS42L42_MIC_DET_CTL1, 1565 CS42L42_LATCH_TO_VP_MASK | 1566 CS42L42_EVENT_STAT_SEL_MASK | 1567 CS42L42_HS_DET_LEVEL_MASK, 1568 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1569 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1570 (cs42l42->bias_thresholds[bias_level] << 1571 CS42L42_HS_DET_LEVEL_SHIFT)); 1572 1573 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1574 &detect_status); 1575 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1576 (++bias_level < CS42L42_NUM_BIASES)); 1577 1578 switch (bias_level) { 1579 case 1: /* Function C button press */ 1580 bias_level = SND_JACK_BTN_2; 1581 dev_dbg(cs42l42->dev, "Function C button press\n"); 1582 break; 1583 case 2: /* Function B button press */ 1584 bias_level = SND_JACK_BTN_1; 1585 dev_dbg(cs42l42->dev, "Function B button press\n"); 1586 break; 1587 case 3: /* Function D button press */ 1588 bias_level = SND_JACK_BTN_3; 1589 dev_dbg(cs42l42->dev, "Function D button press\n"); 1590 break; 1591 case 4: /* Function A button press */ 1592 bias_level = SND_JACK_BTN_0; 1593 dev_dbg(cs42l42->dev, "Function A button press\n"); 1594 break; 1595 default: 1596 bias_level = 0; 1597 break; 1598 } 1599 1600 /* Set button detect level sensitivity back to default */ 1601 regmap_update_bits(cs42l42->regmap, 1602 CS42L42_MIC_DET_CTL1, 1603 CS42L42_LATCH_TO_VP_MASK | 1604 CS42L42_EVENT_STAT_SEL_MASK | 1605 CS42L42_HS_DET_LEVEL_MASK, 1606 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1607 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1608 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1609 1610 /* Clear any button interrupts before unmasking them */ 1611 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1612 &detect_status); 1613 1614 /* Unmask button detect interrupts */ 1615 regmap_update_bits(cs42l42->regmap, 1616 CS42L42_DET_INT2_MASK, 1617 CS42L42_M_DETECT_TF_MASK | 1618 CS42L42_M_DETECT_FT_MASK | 1619 CS42L42_M_HSBIAS_HIZ_MASK | 1620 CS42L42_M_SHORT_RLS_MASK | 1621 CS42L42_M_SHORT_DET_MASK, 1622 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1623 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1624 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1625 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1626 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1627 1628 return bias_level; 1629 } 1630 1631 struct cs42l42_irq_params { 1632 u16 status_addr; 1633 u16 mask_addr; 1634 u8 mask; 1635 }; 1636 1637 static const struct cs42l42_irq_params irq_params_table[] = { 1638 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1639 CS42L42_ADC_OVFL_VAL_MASK}, 1640 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1641 CS42L42_MIXER_VAL_MASK}, 1642 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1643 CS42L42_SRC_VAL_MASK}, 1644 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1645 CS42L42_ASP_RX_VAL_MASK}, 1646 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1647 CS42L42_ASP_TX_VAL_MASK}, 1648 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1649 CS42L42_CODEC_VAL_MASK}, 1650 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1651 CS42L42_DET_INT_VAL1_MASK}, 1652 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1653 CS42L42_DET_INT_VAL2_MASK}, 1654 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1655 CS42L42_SRCPL_VAL_MASK}, 1656 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1657 CS42L42_VPMON_VAL_MASK}, 1658 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1659 CS42L42_PLL_LOCK_VAL_MASK}, 1660 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1661 CS42L42_TSRS_PLUG_VAL_MASK} 1662 }; 1663 1664 irqreturn_t cs42l42_irq_thread(int irq, void *data) 1665 { 1666 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1667 unsigned int stickies[12]; 1668 unsigned int masks[12]; 1669 unsigned int current_plug_status; 1670 unsigned int current_button_status; 1671 unsigned int i; 1672 1673 pm_runtime_get_sync(cs42l42->dev); 1674 mutex_lock(&cs42l42->irq_lock); 1675 if (cs42l42->suspended || !cs42l42->init_done) { 1676 mutex_unlock(&cs42l42->irq_lock); 1677 pm_runtime_put_autosuspend(cs42l42->dev); 1678 return IRQ_NONE; 1679 } 1680 1681 /* Read sticky registers to clear interurpt */ 1682 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1683 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1684 &(stickies[i])); 1685 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1686 &(masks[i])); 1687 stickies[i] = stickies[i] & (~masks[i]) & 1688 irq_params_table[i].mask; 1689 } 1690 1691 /* Read tip sense status before handling type detect */ 1692 current_plug_status = (stickies[11] & 1693 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1694 CS42L42_TS_PLUG_SHIFT; 1695 1696 /* Read button sense status */ 1697 current_button_status = stickies[7] & 1698 (CS42L42_M_DETECT_TF_MASK | 1699 CS42L42_M_DETECT_FT_MASK | 1700 CS42L42_M_HSBIAS_HIZ_MASK); 1701 1702 /* 1703 * Check auto-detect status. Don't assume a previous unplug event has 1704 * cleared the flags. If the jack is unplugged and plugged during 1705 * system suspend there won't have been an unplug event. 1706 */ 1707 if ((~masks[5]) & irq_params_table[5].mask) { 1708 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1709 cs42l42_process_hs_type_detect(cs42l42); 1710 switch (cs42l42->hs_type) { 1711 case CS42L42_PLUG_CTIA: 1712 case CS42L42_PLUG_OMTP: 1713 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1714 SND_JACK_HEADSET | 1715 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1716 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1717 break; 1718 case CS42L42_PLUG_HEADPHONE: 1719 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1720 SND_JACK_HEADSET | 1721 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1722 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1723 break; 1724 default: 1725 break; 1726 } 1727 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1728 } 1729 } 1730 1731 /* Check tip sense status */ 1732 if ((~masks[11]) & irq_params_table[11].mask) { 1733 switch (current_plug_status) { 1734 case CS42L42_TS_PLUG: 1735 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1736 cs42l42->plug_state = CS42L42_TS_PLUG; 1737 cs42l42_init_hs_type_detect(cs42l42); 1738 } 1739 break; 1740 1741 case CS42L42_TS_UNPLUG: 1742 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1743 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1744 cs42l42_cancel_hs_type_detect(cs42l42); 1745 1746 snd_soc_jack_report(cs42l42->jack, 0, 1747 SND_JACK_HEADSET | 1748 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1749 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1750 1751 dev_dbg(cs42l42->dev, "Unplug event\n"); 1752 } 1753 break; 1754 1755 default: 1756 cs42l42->plug_state = CS42L42_TS_TRANS; 1757 } 1758 } 1759 1760 /* Check button detect status */ 1761 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1762 if (!(current_button_status & 1763 CS42L42_M_HSBIAS_HIZ_MASK)) { 1764 1765 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1766 dev_dbg(cs42l42->dev, "Button released\n"); 1767 snd_soc_jack_report(cs42l42->jack, 0, 1768 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1769 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1770 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1771 snd_soc_jack_report(cs42l42->jack, 1772 cs42l42_handle_button_press(cs42l42), 1773 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1774 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1775 } 1776 } 1777 } 1778 1779 mutex_unlock(&cs42l42->irq_lock); 1780 pm_runtime_mark_last_busy(cs42l42->dev); 1781 pm_runtime_put_autosuspend(cs42l42->dev); 1782 1783 return IRQ_HANDLED; 1784 } 1785 EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE); 1786 1787 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1788 { 1789 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1790 CS42L42_ADC_OVFL_MASK, 1791 (1 << CS42L42_ADC_OVFL_SHIFT)); 1792 1793 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1794 CS42L42_MIX_CHB_OVFL_MASK | 1795 CS42L42_MIX_CHA_OVFL_MASK | 1796 CS42L42_EQ_OVFL_MASK | 1797 CS42L42_EQ_BIQUAD_OVFL_MASK, 1798 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1799 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1800 (1 << CS42L42_EQ_OVFL_SHIFT) | 1801 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1802 1803 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1804 CS42L42_SRC_ILK_MASK | 1805 CS42L42_SRC_OLK_MASK | 1806 CS42L42_SRC_IUNLK_MASK | 1807 CS42L42_SRC_OUNLK_MASK, 1808 (1 << CS42L42_SRC_ILK_SHIFT) | 1809 (1 << CS42L42_SRC_OLK_SHIFT) | 1810 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1811 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1812 1813 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1814 CS42L42_ASPRX_NOLRCK_MASK | 1815 CS42L42_ASPRX_EARLY_MASK | 1816 CS42L42_ASPRX_LATE_MASK | 1817 CS42L42_ASPRX_ERROR_MASK | 1818 CS42L42_ASPRX_OVLD_MASK, 1819 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1820 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1821 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1822 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1823 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1824 1825 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1826 CS42L42_ASPTX_NOLRCK_MASK | 1827 CS42L42_ASPTX_EARLY_MASK | 1828 CS42L42_ASPTX_LATE_MASK | 1829 CS42L42_ASPTX_SMERROR_MASK, 1830 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1831 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1832 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1833 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1834 1835 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1836 CS42L42_PDN_DONE_MASK | 1837 CS42L42_HSDET_AUTO_DONE_MASK, 1838 (1 << CS42L42_PDN_DONE_SHIFT) | 1839 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1840 1841 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1842 CS42L42_SRCPL_ADC_LK_MASK | 1843 CS42L42_SRCPL_DAC_LK_MASK | 1844 CS42L42_SRCPL_ADC_UNLK_MASK | 1845 CS42L42_SRCPL_DAC_UNLK_MASK, 1846 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1847 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1848 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1849 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1850 1851 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1852 CS42L42_TIP_SENSE_UNPLUG_MASK | 1853 CS42L42_TIP_SENSE_PLUG_MASK | 1854 CS42L42_HSBIAS_SENSE_MASK, 1855 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1856 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1857 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1858 1859 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1860 CS42L42_M_DETECT_TF_MASK | 1861 CS42L42_M_DETECT_FT_MASK | 1862 CS42L42_M_HSBIAS_HIZ_MASK | 1863 CS42L42_M_SHORT_RLS_MASK | 1864 CS42L42_M_SHORT_DET_MASK, 1865 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1866 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1867 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1868 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1869 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1870 1871 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1872 CS42L42_VPMON_MASK, 1873 (1 << CS42L42_VPMON_SHIFT)); 1874 1875 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1876 CS42L42_PLL_LOCK_MASK, 1877 (1 << CS42L42_PLL_LOCK_SHIFT)); 1878 1879 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1880 CS42L42_RS_PLUG_MASK | 1881 CS42L42_RS_UNPLUG_MASK | 1882 CS42L42_TS_PLUG_MASK | 1883 CS42L42_TS_UNPLUG_MASK, 1884 (1 << CS42L42_RS_PLUG_SHIFT) | 1885 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1886 (0 << CS42L42_TS_PLUG_SHIFT) | 1887 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1888 } 1889 1890 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1891 { 1892 unsigned int reg; 1893 1894 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1895 1896 /* 1897 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the 1898 * FILT+ supply will not charge properly. 1899 */ 1900 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1901 CS42L42_DETECT_MODE_MASK, 0); 1902 1903 /* Latch analog controls to VP power domain */ 1904 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1905 CS42L42_LATCH_TO_VP_MASK | 1906 CS42L42_EVENT_STAT_SEL_MASK | 1907 CS42L42_HS_DET_LEVEL_MASK, 1908 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1909 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1910 (cs42l42->bias_thresholds[0] << 1911 CS42L42_HS_DET_LEVEL_SHIFT)); 1912 1913 /* Remove ground noise-suppression clamps */ 1914 regmap_update_bits(cs42l42->regmap, 1915 CS42L42_HS_CLAMP_DISABLE, 1916 CS42L42_HS_CLAMP_DISABLE_MASK, 1917 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1918 1919 /* Enable the tip sense circuit */ 1920 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1921 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1922 1923 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1924 CS42L42_TIP_SENSE_CTRL_MASK | 1925 CS42L42_TIP_SENSE_INV_MASK | 1926 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1927 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1928 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1929 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1930 1931 /* Save the initial status of the tip sense */ 1932 regmap_read(cs42l42->regmap, 1933 CS42L42_TSRS_PLUG_STATUS, 1934 ®); 1935 cs42l42->plug_state = (((char) reg) & 1936 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1937 CS42L42_TS_PLUG_SHIFT; 1938 } 1939 1940 static const unsigned int threshold_defaults[] = { 1941 CS42L42_HS_DET_LEVEL_15, 1942 CS42L42_HS_DET_LEVEL_8, 1943 CS42L42_HS_DET_LEVEL_4, 1944 CS42L42_HS_DET_LEVEL_1 1945 }; 1946 1947 static int cs42l42_handle_device_data(struct device *dev, 1948 struct cs42l42_private *cs42l42) 1949 { 1950 unsigned int val; 1951 u32 thresholds[CS42L42_NUM_BIASES]; 1952 int ret; 1953 int i; 1954 1955 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1956 if (!ret) { 1957 switch (val) { 1958 case CS42L42_TS_INV_EN: 1959 case CS42L42_TS_INV_DIS: 1960 cs42l42->ts_inv = val; 1961 break; 1962 default: 1963 dev_err(dev, 1964 "Wrong cirrus,ts-inv DT value %d\n", 1965 val); 1966 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1967 } 1968 } else { 1969 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1970 } 1971 1972 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1973 if (!ret) { 1974 switch (val) { 1975 case CS42L42_TS_DBNCE_0: 1976 case CS42L42_TS_DBNCE_125: 1977 case CS42L42_TS_DBNCE_250: 1978 case CS42L42_TS_DBNCE_500: 1979 case CS42L42_TS_DBNCE_750: 1980 case CS42L42_TS_DBNCE_1000: 1981 case CS42L42_TS_DBNCE_1250: 1982 case CS42L42_TS_DBNCE_1500: 1983 cs42l42->ts_dbnc_rise = val; 1984 break; 1985 default: 1986 dev_err(dev, 1987 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1988 val); 1989 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1990 } 1991 } else { 1992 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1993 } 1994 1995 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1996 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1997 (cs42l42->ts_dbnc_rise << 1998 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1999 2000 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 2001 if (!ret) { 2002 switch (val) { 2003 case CS42L42_TS_DBNCE_0: 2004 case CS42L42_TS_DBNCE_125: 2005 case CS42L42_TS_DBNCE_250: 2006 case CS42L42_TS_DBNCE_500: 2007 case CS42L42_TS_DBNCE_750: 2008 case CS42L42_TS_DBNCE_1000: 2009 case CS42L42_TS_DBNCE_1250: 2010 case CS42L42_TS_DBNCE_1500: 2011 cs42l42->ts_dbnc_fall = val; 2012 break; 2013 default: 2014 dev_err(dev, 2015 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 2016 val); 2017 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2018 } 2019 } else { 2020 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 2021 } 2022 2023 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 2024 CS42L42_TS_FALL_DBNCE_TIME_MASK, 2025 (cs42l42->ts_dbnc_fall << 2026 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 2027 2028 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 2029 if (!ret) { 2030 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 2031 cs42l42->btn_det_init_dbnce = val; 2032 else { 2033 dev_err(dev, 2034 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 2035 val); 2036 cs42l42->btn_det_init_dbnce = 2037 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2038 } 2039 } else { 2040 cs42l42->btn_det_init_dbnce = 2041 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 2042 } 2043 2044 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 2045 if (!ret) { 2046 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 2047 cs42l42->btn_det_event_dbnce = val; 2048 else { 2049 dev_err(dev, 2050 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 2051 cs42l42->btn_det_event_dbnce = 2052 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2053 } 2054 } else { 2055 cs42l42->btn_det_event_dbnce = 2056 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2057 } 2058 2059 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 2060 thresholds, ARRAY_SIZE(thresholds)); 2061 if (!ret) { 2062 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 2063 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 2064 cs42l42->bias_thresholds[i] = thresholds[i]; 2065 else { 2066 dev_err(dev, 2067 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 2068 thresholds[i]); 2069 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2070 } 2071 } 2072 } else { 2073 for (i = 0; i < CS42L42_NUM_BIASES; i++) 2074 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2075 } 2076 2077 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 2078 if (!ret) { 2079 switch (val) { 2080 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 2081 cs42l42->hs_bias_ramp_rate = val; 2082 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 2083 break; 2084 case CS42L42_HSBIAS_RAMP_FAST: 2085 cs42l42->hs_bias_ramp_rate = val; 2086 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 2087 break; 2088 case CS42L42_HSBIAS_RAMP_SLOW: 2089 cs42l42->hs_bias_ramp_rate = val; 2090 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2091 break; 2092 case CS42L42_HSBIAS_RAMP_SLOWEST: 2093 cs42l42->hs_bias_ramp_rate = val; 2094 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 2095 break; 2096 default: 2097 dev_err(dev, 2098 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2099 val); 2100 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2101 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2102 } 2103 } else { 2104 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2105 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2106 } 2107 2108 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2109 CS42L42_HSBIAS_RAMP_MASK, 2110 (cs42l42->hs_bias_ramp_rate << 2111 CS42L42_HSBIAS_RAMP_SHIFT)); 2112 2113 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2114 cs42l42->hs_bias_sense_en = 0; 2115 else 2116 cs42l42->hs_bias_sense_en = 1; 2117 2118 return 0; 2119 } 2120 2121 /* Datasheet suspend sequence */ 2122 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { 2123 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), 2124 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), 2125 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), 2126 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), 2127 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), 2128 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), 2129 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), 2130 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), 2131 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), 2132 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), 2133 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), 2134 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), 2135 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), 2136 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), 2137 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), 2138 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), 2139 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), 2140 REG_SEQ0(CS42L42_HP_CTL, 0x0F), 2141 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), 2142 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), 2143 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), 2144 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), 2145 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), 2146 REG_SEQ0(CS42L42_DAC_CTL2, 0x02), 2147 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), 2148 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), 2149 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), 2150 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), 2151 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) 2152 }; 2153 2154 int cs42l42_suspend(struct device *dev) 2155 { 2156 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2157 unsigned int reg; 2158 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; 2159 int i, ret; 2160 2161 if (!cs42l42->init_done) 2162 return 0; 2163 2164 /* 2165 * Wait for threaded irq handler to be idle and stop it processing 2166 * future interrupts. This ensures a safe disable if the interrupt 2167 * is shared. 2168 */ 2169 mutex_lock(&cs42l42->irq_lock); 2170 cs42l42->suspended = true; 2171 2172 /* Save register values that will be overwritten by shutdown sequence */ 2173 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { 2174 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®); 2175 save_regs[i] = (u8)reg; 2176 } 2177 2178 /* Shutdown codec */ 2179 regmap_multi_reg_write(cs42l42->regmap, 2180 cs42l42_shutdown_seq, 2181 ARRAY_SIZE(cs42l42_shutdown_seq)); 2182 2183 /* All interrupt sources are now disabled */ 2184 mutex_unlock(&cs42l42->irq_lock); 2185 2186 /* Wait for power-down complete */ 2187 msleep(CS42L42_PDN_DONE_TIME_MS); 2188 ret = regmap_read_poll_timeout(cs42l42->regmap, 2189 CS42L42_CODEC_STATUS, reg, 2190 (reg & CS42L42_PDN_DONE_MASK), 2191 CS42L42_PDN_DONE_POLL_US, 2192 CS42L42_PDN_DONE_TIMEOUT_US); 2193 if (ret) 2194 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret); 2195 2196 /* Discharge FILT+ */ 2197 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2198 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); 2199 msleep(CS42L42_FILT_DISCHARGE_TIME_MS); 2200 2201 regcache_cache_only(cs42l42->regmap, true); 2202 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2203 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2204 2205 /* Restore register values to the regmap cache */ 2206 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) 2207 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]); 2208 2209 /* The cached address page register value is now stale */ 2210 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); 2211 2212 dev_dbg(dev, "System suspended\n"); 2213 2214 return 0; 2215 2216 } 2217 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE); 2218 2219 int cs42l42_resume(struct device *dev) 2220 { 2221 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2222 int ret; 2223 2224 if (!cs42l42->init_done) 2225 return 0; 2226 2227 /* 2228 * If jack was unplugged and re-plugged during suspend it could 2229 * have changed type but the tip-sense state hasn't changed. 2230 * Force a plugged state to be re-evaluated. 2231 */ 2232 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) 2233 cs42l42->plug_state = CS42L42_TS_TRANS; 2234 2235 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2236 if (ret != 0) { 2237 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2238 return ret; 2239 } 2240 2241 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2242 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2243 2244 dev_dbg(dev, "System resume powered up\n"); 2245 2246 return 0; 2247 } 2248 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE); 2249 2250 void cs42l42_resume_restore(struct device *dev) 2251 { 2252 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2253 2254 regcache_cache_only(cs42l42->regmap, false); 2255 regcache_mark_dirty(cs42l42->regmap); 2256 2257 mutex_lock(&cs42l42->irq_lock); 2258 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 2259 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 2260 regcache_sync(cs42l42->regmap); 2261 2262 cs42l42->suspended = false; 2263 mutex_unlock(&cs42l42->irq_lock); 2264 2265 dev_dbg(dev, "System resumed\n"); 2266 } 2267 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE); 2268 2269 static int __maybe_unused cs42l42_i2c_resume(struct device *dev) 2270 { 2271 int ret; 2272 2273 ret = cs42l42_resume(dev); 2274 if (ret) 2275 return ret; 2276 2277 cs42l42_resume_restore(dev); 2278 2279 return 0; 2280 } 2281 2282 int cs42l42_common_probe(struct cs42l42_private *cs42l42, 2283 const struct snd_soc_component_driver *component_drv, 2284 struct snd_soc_dai_driver *dai) 2285 { 2286 int ret, i; 2287 2288 dev_set_drvdata(cs42l42->dev, cs42l42); 2289 mutex_init(&cs42l42->irq_lock); 2290 2291 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); 2292 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2293 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2294 2295 ret = devm_regulator_bulk_get(cs42l42->dev, 2296 ARRAY_SIZE(cs42l42->supplies), 2297 cs42l42->supplies); 2298 if (ret != 0) { 2299 dev_err(cs42l42->dev, 2300 "Failed to request supplies: %d\n", ret); 2301 return ret; 2302 } 2303 2304 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2305 cs42l42->supplies); 2306 if (ret != 0) { 2307 dev_err(cs42l42->dev, 2308 "Failed to enable supplies: %d\n", ret); 2309 return ret; 2310 } 2311 2312 /* Reset the Device */ 2313 cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev, 2314 "reset", GPIOD_OUT_LOW); 2315 if (IS_ERR(cs42l42->reset_gpio)) { 2316 ret = PTR_ERR(cs42l42->reset_gpio); 2317 goto err_disable_noreset; 2318 } 2319 2320 if (cs42l42->reset_gpio) { 2321 dev_dbg(cs42l42->dev, "Found reset GPIO\n"); 2322 2323 /* 2324 * ACPI can override the default GPIO state we requested 2325 * so ensure that we start with RESET low. 2326 */ 2327 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2328 2329 /* Ensure minimum reset pulse width */ 2330 usleep_range(10, 500); 2331 2332 /* 2333 * On SoundWire keep the chip in reset until we get an UNATTACH 2334 * notification from the SoundWire core. This acts as a 2335 * synchronization point to reject stale ATTACH notifications 2336 * if the chip was already enumerated before we reset it. 2337 */ 2338 if (cs42l42->sdw_peripheral) 2339 cs42l42->sdw_waiting_first_unattach = true; 2340 else 2341 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2342 } 2343 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2344 2345 /* Request IRQ if one was specified */ 2346 if (cs42l42->irq) { 2347 ret = request_threaded_irq(cs42l42->irq, 2348 NULL, cs42l42_irq_thread, 2349 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2350 "cs42l42", cs42l42); 2351 if (ret) { 2352 dev_err_probe(cs42l42->dev, ret, 2353 "Failed to request IRQ\n"); 2354 goto err_disable_noirq; 2355 } 2356 } 2357 2358 /* Register codec now so it can EPROBE_DEFER */ 2359 ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1); 2360 if (ret < 0) 2361 goto err; 2362 2363 return 0; 2364 2365 err: 2366 if (cs42l42->irq) 2367 free_irq(cs42l42->irq, cs42l42); 2368 2369 err_disable_noirq: 2370 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2371 err_disable_noreset: 2372 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2373 2374 return ret; 2375 } 2376 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE); 2377 2378 int cs42l42_init(struct cs42l42_private *cs42l42) 2379 { 2380 unsigned int reg; 2381 int devid, ret; 2382 2383 /* initialize codec */ 2384 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2385 if (devid < 0) { 2386 ret = devid; 2387 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret); 2388 goto err_disable; 2389 } 2390 2391 if (devid != cs42l42->devid) { 2392 ret = -ENODEV; 2393 dev_err(cs42l42->dev, 2394 "CS42L%x Device ID (%X). Expected %X\n", 2395 cs42l42->devid & 0xff, devid, cs42l42->devid); 2396 goto err_disable; 2397 } 2398 2399 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2400 if (ret < 0) { 2401 dev_err(cs42l42->dev, "Get Revision ID failed\n"); 2402 goto err_shutdown; 2403 } 2404 2405 dev_info(cs42l42->dev, 2406 "Cirrus Logic CS42L%x, Revision: %02X\n", 2407 cs42l42->devid & 0xff, reg & 0xFF); 2408 2409 /* Power up the codec */ 2410 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2411 CS42L42_ASP_DAO_PDN_MASK | 2412 CS42L42_ASP_DAI_PDN_MASK | 2413 CS42L42_MIXER_PDN_MASK | 2414 CS42L42_EQ_PDN_MASK | 2415 CS42L42_HP_PDN_MASK | 2416 CS42L42_ADC_PDN_MASK | 2417 CS42L42_PDN_ALL_MASK, 2418 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2419 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2420 (1 << CS42L42_MIXER_PDN_SHIFT) | 2421 (1 << CS42L42_EQ_PDN_SHIFT) | 2422 (1 << CS42L42_HP_PDN_SHIFT) | 2423 (1 << CS42L42_ADC_PDN_SHIFT) | 2424 (0 << CS42L42_PDN_ALL_SHIFT)); 2425 2426 ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42); 2427 if (ret != 0) 2428 goto err_shutdown; 2429 2430 /* 2431 * SRC power is linked to ASP power so doesn't work in Soundwire mode. 2432 * Override it and use DAPM to control SRC power for Soundwire. 2433 */ 2434 if (cs42l42->sdw_peripheral) { 2435 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2436 CS42L42_SRC_PDN_OVERRIDE_MASK | 2437 CS42L42_DAC_SRC_PDNB_MASK | 2438 CS42L42_ADC_SRC_PDNB_MASK, 2439 CS42L42_SRC_PDN_OVERRIDE_MASK); 2440 } 2441 2442 /* Setup headset detection */ 2443 cs42l42_setup_hs_type_detect(cs42l42); 2444 2445 /* 2446 * Set init_done before unmasking interrupts so any triggered 2447 * immediately will be handled. 2448 */ 2449 cs42l42->init_done = true; 2450 2451 /* Mask/Unmask Interrupts */ 2452 cs42l42_set_interrupt_masks(cs42l42); 2453 2454 return 0; 2455 2456 err_shutdown: 2457 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2458 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2459 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2460 2461 err_disable: 2462 if (cs42l42->irq) 2463 free_irq(cs42l42->irq, cs42l42); 2464 2465 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2466 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2467 cs42l42->supplies); 2468 return ret; 2469 } 2470 EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE); 2471 2472 void cs42l42_common_remove(struct cs42l42_private *cs42l42) 2473 { 2474 if (cs42l42->irq) 2475 free_irq(cs42l42->irq, cs42l42); 2476 2477 /* 2478 * The driver might not have control of reset and power supplies, 2479 * so ensure that the chip internals are powered down. 2480 */ 2481 if (cs42l42->init_done) { 2482 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2483 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2484 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2485 } 2486 2487 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2488 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2489 } 2490 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE); 2491 2492 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2493 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2494 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2495 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2496 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2497 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2498 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2499 MODULE_LICENSE("GPL"); 2500