1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/types.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/tlv.h> 35 #include <dt-bindings/sound/cs42l42.h> 36 37 #include "cs42l42.h" 38 #include "cirrus_legacy.h" 39 40 static const char * const cs42l42_supply_names[] = { 41 "VA", 42 "VP", 43 "VCP", 44 "VD_FILT", 45 "VL", 46 }; 47 48 static const struct reg_default cs42l42_reg_defaults[] = { 49 { CS42L42_FRZ_CTL, 0x00 }, 50 { CS42L42_SRC_CTL, 0x10 }, 51 { CS42L42_MCLK_CTL, 0x02 }, 52 { CS42L42_SFTRAMP_RATE, 0xA4 }, 53 { CS42L42_SLOW_START_ENABLE, 0x70 }, 54 { CS42L42_I2C_DEBOUNCE, 0x88 }, 55 { CS42L42_I2C_STRETCH, 0x03 }, 56 { CS42L42_I2C_TIMEOUT, 0xB7 }, 57 { CS42L42_PWR_CTL1, 0xFF }, 58 { CS42L42_PWR_CTL2, 0x84 }, 59 { CS42L42_PWR_CTL3, 0x20 }, 60 { CS42L42_RSENSE_CTL1, 0x40 }, 61 { CS42L42_RSENSE_CTL2, 0x00 }, 62 { CS42L42_OSC_SWITCH, 0x00 }, 63 { CS42L42_RSENSE_CTL3, 0x1B }, 64 { CS42L42_TSENSE_CTL, 0x1B }, 65 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 66 { CS42L42_HSDET_CTL1, 0x77 }, 67 { CS42L42_HSDET_CTL2, 0x00 }, 68 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 69 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 70 { CS42L42_MCLK_SRC_SEL, 0x00 }, 71 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 72 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 73 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 74 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 75 { CS42L42_FSYNC_P_UPPER, 0x00 }, 76 { CS42L42_ASP_CLK_CFG, 0x00 }, 77 { CS42L42_ASP_FRM_CFG, 0x10 }, 78 { CS42L42_FS_RATE_EN, 0x00 }, 79 { CS42L42_IN_ASRC_CLK, 0x00 }, 80 { CS42L42_OUT_ASRC_CLK, 0x00 }, 81 { CS42L42_PLL_DIV_CFG1, 0x00 }, 82 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 83 { CS42L42_MIXER_INT_MASK, 0x0F }, 84 { CS42L42_SRC_INT_MASK, 0x0F }, 85 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 86 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 87 { CS42L42_CODEC_INT_MASK, 0x03 }, 88 { CS42L42_SRCPL_INT_MASK, 0x7F }, 89 { CS42L42_VPMON_INT_MASK, 0x01 }, 90 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 91 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 92 { CS42L42_PLL_CTL1, 0x00 }, 93 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 94 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 95 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 96 { CS42L42_PLL_DIV_INT, 0x40 }, 97 { CS42L42_PLL_CTL3, 0x10 }, 98 { CS42L42_PLL_CAL_RATIO, 0x80 }, 99 { CS42L42_PLL_CTL4, 0x03 }, 100 { CS42L42_LOAD_DET_EN, 0x00 }, 101 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 102 { CS42L42_WAKE_CTL, 0xC0 }, 103 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 104 { CS42L42_TIPSENSE_CTL, 0x02 }, 105 { CS42L42_MISC_DET_CTL, 0x03 }, 106 { CS42L42_MIC_DET_CTL1, 0x1F }, 107 { CS42L42_MIC_DET_CTL2, 0x2F }, 108 { CS42L42_DET_INT1_MASK, 0xE0 }, 109 { CS42L42_DET_INT2_MASK, 0xFF }, 110 { CS42L42_HS_BIAS_CTL, 0xC2 }, 111 { CS42L42_ADC_CTL, 0x00 }, 112 { CS42L42_ADC_VOLUME, 0x00 }, 113 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 114 { CS42L42_DAC_CTL1, 0x00 }, 115 { CS42L42_DAC_CTL2, 0x02 }, 116 { CS42L42_HP_CTL, 0x0D }, 117 { CS42L42_CLASSH_CTL, 0x07 }, 118 { CS42L42_MIXER_CHA_VOL, 0x3F }, 119 { CS42L42_MIXER_ADC_VOL, 0x3F }, 120 { CS42L42_MIXER_CHB_VOL, 0x3F }, 121 { CS42L42_EQ_COEF_IN0, 0x00 }, 122 { CS42L42_EQ_COEF_IN1, 0x00 }, 123 { CS42L42_EQ_COEF_IN2, 0x00 }, 124 { CS42L42_EQ_COEF_IN3, 0x00 }, 125 { CS42L42_EQ_COEF_RW, 0x00 }, 126 { CS42L42_EQ_COEF_OUT0, 0x00 }, 127 { CS42L42_EQ_COEF_OUT1, 0x00 }, 128 { CS42L42_EQ_COEF_OUT2, 0x00 }, 129 { CS42L42_EQ_COEF_OUT3, 0x00 }, 130 { CS42L42_EQ_INIT_STAT, 0x00 }, 131 { CS42L42_EQ_START_FILT, 0x00 }, 132 { CS42L42_EQ_MUTE_CTL, 0x00 }, 133 { CS42L42_SP_RX_CH_SEL, 0x04 }, 134 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 135 { CS42L42_SP_RX_FS, 0x8C }, 136 { CS42l42_SPDIF_CH_SEL, 0x0E }, 137 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 138 { CS42L42_SP_TX_FS, 0xCC }, 139 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 140 { CS42L42_SRC_SDIN_FS, 0x40 }, 141 { CS42L42_SRC_SDOUT_FS, 0x40 }, 142 { CS42L42_SPDIF_CTL1, 0x01 }, 143 { CS42L42_SPDIF_CTL2, 0x00 }, 144 { CS42L42_SPDIF_CTL3, 0x00 }, 145 { CS42L42_SPDIF_CTL4, 0x42 }, 146 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 147 { CS42L42_ASP_TX_CH_EN, 0x00 }, 148 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 149 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 150 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 151 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 152 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 153 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 154 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 155 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 156 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 157 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 158 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 159 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 160 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 161 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 162 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 163 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 164 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 165 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 167 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 168 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 170 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 171 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 173 }; 174 175 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 176 { 177 switch (reg) { 178 case CS42L42_PAGE_REGISTER: 179 case CS42L42_DEVID_AB: 180 case CS42L42_DEVID_CD: 181 case CS42L42_DEVID_E: 182 case CS42L42_FABID: 183 case CS42L42_REVID: 184 case CS42L42_FRZ_CTL: 185 case CS42L42_SRC_CTL: 186 case CS42L42_MCLK_STATUS: 187 case CS42L42_MCLK_CTL: 188 case CS42L42_SFTRAMP_RATE: 189 case CS42L42_SLOW_START_ENABLE: 190 case CS42L42_I2C_DEBOUNCE: 191 case CS42L42_I2C_STRETCH: 192 case CS42L42_I2C_TIMEOUT: 193 case CS42L42_PWR_CTL1: 194 case CS42L42_PWR_CTL2: 195 case CS42L42_PWR_CTL3: 196 case CS42L42_RSENSE_CTL1: 197 case CS42L42_RSENSE_CTL2: 198 case CS42L42_OSC_SWITCH: 199 case CS42L42_OSC_SWITCH_STATUS: 200 case CS42L42_RSENSE_CTL3: 201 case CS42L42_TSENSE_CTL: 202 case CS42L42_TSRS_INT_DISABLE: 203 case CS42L42_TRSENSE_STATUS: 204 case CS42L42_HSDET_CTL1: 205 case CS42L42_HSDET_CTL2: 206 case CS42L42_HS_SWITCH_CTL: 207 case CS42L42_HS_DET_STATUS: 208 case CS42L42_HS_CLAMP_DISABLE: 209 case CS42L42_MCLK_SRC_SEL: 210 case CS42L42_SPDIF_CLK_CFG: 211 case CS42L42_FSYNC_PW_LOWER: 212 case CS42L42_FSYNC_PW_UPPER: 213 case CS42L42_FSYNC_P_LOWER: 214 case CS42L42_FSYNC_P_UPPER: 215 case CS42L42_ASP_CLK_CFG: 216 case CS42L42_ASP_FRM_CFG: 217 case CS42L42_FS_RATE_EN: 218 case CS42L42_IN_ASRC_CLK: 219 case CS42L42_OUT_ASRC_CLK: 220 case CS42L42_PLL_DIV_CFG1: 221 case CS42L42_ADC_OVFL_STATUS: 222 case CS42L42_MIXER_STATUS: 223 case CS42L42_SRC_STATUS: 224 case CS42L42_ASP_RX_STATUS: 225 case CS42L42_ASP_TX_STATUS: 226 case CS42L42_CODEC_STATUS: 227 case CS42L42_DET_INT_STATUS1: 228 case CS42L42_DET_INT_STATUS2: 229 case CS42L42_SRCPL_INT_STATUS: 230 case CS42L42_VPMON_STATUS: 231 case CS42L42_PLL_LOCK_STATUS: 232 case CS42L42_TSRS_PLUG_STATUS: 233 case CS42L42_ADC_OVFL_INT_MASK: 234 case CS42L42_MIXER_INT_MASK: 235 case CS42L42_SRC_INT_MASK: 236 case CS42L42_ASP_RX_INT_MASK: 237 case CS42L42_ASP_TX_INT_MASK: 238 case CS42L42_CODEC_INT_MASK: 239 case CS42L42_SRCPL_INT_MASK: 240 case CS42L42_VPMON_INT_MASK: 241 case CS42L42_PLL_LOCK_INT_MASK: 242 case CS42L42_TSRS_PLUG_INT_MASK: 243 case CS42L42_PLL_CTL1: 244 case CS42L42_PLL_DIV_FRAC0: 245 case CS42L42_PLL_DIV_FRAC1: 246 case CS42L42_PLL_DIV_FRAC2: 247 case CS42L42_PLL_DIV_INT: 248 case CS42L42_PLL_CTL3: 249 case CS42L42_PLL_CAL_RATIO: 250 case CS42L42_PLL_CTL4: 251 case CS42L42_LOAD_DET_RCSTAT: 252 case CS42L42_LOAD_DET_DONE: 253 case CS42L42_LOAD_DET_EN: 254 case CS42L42_HSBIAS_SC_AUTOCTL: 255 case CS42L42_WAKE_CTL: 256 case CS42L42_ADC_DISABLE_MUTE: 257 case CS42L42_TIPSENSE_CTL: 258 case CS42L42_MISC_DET_CTL: 259 case CS42L42_MIC_DET_CTL1: 260 case CS42L42_MIC_DET_CTL2: 261 case CS42L42_DET_STATUS1: 262 case CS42L42_DET_STATUS2: 263 case CS42L42_DET_INT1_MASK: 264 case CS42L42_DET_INT2_MASK: 265 case CS42L42_HS_BIAS_CTL: 266 case CS42L42_ADC_CTL: 267 case CS42L42_ADC_VOLUME: 268 case CS42L42_ADC_WNF_HPF_CTL: 269 case CS42L42_DAC_CTL1: 270 case CS42L42_DAC_CTL2: 271 case CS42L42_HP_CTL: 272 case CS42L42_CLASSH_CTL: 273 case CS42L42_MIXER_CHA_VOL: 274 case CS42L42_MIXER_ADC_VOL: 275 case CS42L42_MIXER_CHB_VOL: 276 case CS42L42_EQ_COEF_IN0: 277 case CS42L42_EQ_COEF_IN1: 278 case CS42L42_EQ_COEF_IN2: 279 case CS42L42_EQ_COEF_IN3: 280 case CS42L42_EQ_COEF_RW: 281 case CS42L42_EQ_COEF_OUT0: 282 case CS42L42_EQ_COEF_OUT1: 283 case CS42L42_EQ_COEF_OUT2: 284 case CS42L42_EQ_COEF_OUT3: 285 case CS42L42_EQ_INIT_STAT: 286 case CS42L42_EQ_START_FILT: 287 case CS42L42_EQ_MUTE_CTL: 288 case CS42L42_SP_RX_CH_SEL: 289 case CS42L42_SP_RX_ISOC_CTL: 290 case CS42L42_SP_RX_FS: 291 case CS42l42_SPDIF_CH_SEL: 292 case CS42L42_SP_TX_ISOC_CTL: 293 case CS42L42_SP_TX_FS: 294 case CS42L42_SPDIF_SW_CTL1: 295 case CS42L42_SRC_SDIN_FS: 296 case CS42L42_SRC_SDOUT_FS: 297 case CS42L42_SPDIF_CTL1: 298 case CS42L42_SPDIF_CTL2: 299 case CS42L42_SPDIF_CTL3: 300 case CS42L42_SPDIF_CTL4: 301 case CS42L42_ASP_TX_SZ_EN: 302 case CS42L42_ASP_TX_CH_EN: 303 case CS42L42_ASP_TX_CH_AP_RES: 304 case CS42L42_ASP_TX_CH1_BIT_MSB: 305 case CS42L42_ASP_TX_CH1_BIT_LSB: 306 case CS42L42_ASP_TX_HIZ_DLY_CFG: 307 case CS42L42_ASP_TX_CH2_BIT_MSB: 308 case CS42L42_ASP_TX_CH2_BIT_LSB: 309 case CS42L42_ASP_RX_DAI0_EN: 310 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 311 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 312 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 313 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 314 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 315 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 316 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 317 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 318 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 319 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 320 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 321 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 322 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 323 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 324 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 325 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 326 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 327 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 328 case CS42L42_SUB_REVID: 329 return true; 330 default: 331 return false; 332 } 333 } 334 335 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 336 { 337 switch (reg) { 338 case CS42L42_DEVID_AB: 339 case CS42L42_DEVID_CD: 340 case CS42L42_DEVID_E: 341 case CS42L42_MCLK_STATUS: 342 case CS42L42_OSC_SWITCH_STATUS: 343 case CS42L42_TRSENSE_STATUS: 344 case CS42L42_HS_DET_STATUS: 345 case CS42L42_ADC_OVFL_STATUS: 346 case CS42L42_MIXER_STATUS: 347 case CS42L42_SRC_STATUS: 348 case CS42L42_ASP_RX_STATUS: 349 case CS42L42_ASP_TX_STATUS: 350 case CS42L42_CODEC_STATUS: 351 case CS42L42_DET_INT_STATUS1: 352 case CS42L42_DET_INT_STATUS2: 353 case CS42L42_SRCPL_INT_STATUS: 354 case CS42L42_VPMON_STATUS: 355 case CS42L42_PLL_LOCK_STATUS: 356 case CS42L42_TSRS_PLUG_STATUS: 357 case CS42L42_LOAD_DET_RCSTAT: 358 case CS42L42_LOAD_DET_DONE: 359 case CS42L42_DET_STATUS1: 360 case CS42L42_DET_STATUS2: 361 return true; 362 default: 363 return false; 364 } 365 } 366 367 static const struct regmap_range_cfg cs42l42_page_range = { 368 .name = "Pages", 369 .range_min = 0, 370 .range_max = CS42L42_MAX_REGISTER, 371 .selector_reg = CS42L42_PAGE_REGISTER, 372 .selector_mask = 0xff, 373 .selector_shift = 0, 374 .window_start = 0, 375 .window_len = 256, 376 }; 377 378 static const struct regmap_config cs42l42_regmap = { 379 .reg_bits = 8, 380 .val_bits = 8, 381 382 .readable_reg = cs42l42_readable_register, 383 .volatile_reg = cs42l42_volatile_register, 384 385 .ranges = &cs42l42_page_range, 386 .num_ranges = 1, 387 388 .max_register = CS42L42_MAX_REGISTER, 389 .reg_defaults = cs42l42_reg_defaults, 390 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 391 .cache_type = REGCACHE_RBTREE, 392 393 .use_single_read = true, 394 .use_single_write = true, 395 }; 396 397 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 398 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 399 400 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 401 struct snd_ctl_elem_value *ucontrol) 402 { 403 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 404 u8 val; 405 406 /* all bits of SLOW_START_EN must change together */ 407 switch (ucontrol->value.integer.value[0]) { 408 case 0: 409 val = 0; 410 break; 411 case 1: 412 val = CS42L42_SLOW_START_EN_MASK; 413 break; 414 default: 415 return -EINVAL; 416 } 417 418 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 419 CS42L42_SLOW_START_EN_MASK, val); 420 } 421 422 static const char * const cs42l42_hpf_freq_text[] = { 423 "1.86Hz", "120Hz", "235Hz", "466Hz" 424 }; 425 426 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 427 CS42L42_ADC_HPF_CF_SHIFT, 428 cs42l42_hpf_freq_text); 429 430 static const char * const cs42l42_wnf3_freq_text[] = { 431 "160Hz", "180Hz", "200Hz", "220Hz", 432 "240Hz", "260Hz", "280Hz", "300Hz" 433 }; 434 435 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 436 CS42L42_ADC_WNF_CF_SHIFT, 437 cs42l42_wnf3_freq_text); 438 439 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 440 /* ADC Volume and Filter Controls */ 441 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 442 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 443 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 444 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 445 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 446 CS42L42_ADC_INV_SHIFT, true, false), 447 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 448 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 449 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 450 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 451 CS42L42_ADC_WNF_EN_SHIFT, true, false), 452 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 453 CS42L42_ADC_HPF_EN_SHIFT, true, false), 454 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 455 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 456 457 /* DAC Volume and Filter Controls */ 458 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 459 CS42L42_DACA_INV_SHIFT, true, false), 460 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 461 CS42L42_DACB_INV_SHIFT, true, false), 462 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 463 CS42L42_DAC_HPF_EN_SHIFT, true, false), 464 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 465 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 466 0x3f, 1, mixer_tlv), 467 468 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 469 CS42L42_SLOW_START_EN_SHIFT, true, false, 470 snd_soc_get_volsw, cs42l42_slow_start_put), 471 }; 472 473 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 474 struct snd_kcontrol *kcontrol, int event) 475 { 476 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 477 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 478 479 switch (event) { 480 case SND_SOC_DAPM_PRE_PMU: 481 cs42l42->hp_adc_up_pending = true; 482 break; 483 case SND_SOC_DAPM_POST_PMU: 484 /* Only need one delay if HP and ADC are both powering-up */ 485 if (cs42l42->hp_adc_up_pending) { 486 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 487 CS42L42_HP_ADC_EN_TIME_US + 1000); 488 cs42l42->hp_adc_up_pending = false; 489 } 490 break; 491 default: 492 break; 493 } 494 495 return 0; 496 } 497 498 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 499 /* Playback Path */ 500 SND_SOC_DAPM_OUTPUT("HP"), 501 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 502 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 503 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 504 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 505 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 506 507 /* Playback Requirements */ 508 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 509 510 /* Capture Path */ 511 SND_SOC_DAPM_INPUT("HS"), 512 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 513 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 514 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 515 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 516 517 /* Capture Requirements */ 518 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 519 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 520 521 /* Playback/Capture Requirements */ 522 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 523 }; 524 525 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 526 /* Playback Path */ 527 {"HP", NULL, "DAC"}, 528 {"DAC", NULL, "MIXER"}, 529 {"MIXER", NULL, "SDIN1"}, 530 {"MIXER", NULL, "SDIN2"}, 531 {"SDIN1", NULL, "Playback"}, 532 {"SDIN2", NULL, "Playback"}, 533 534 /* Playback Requirements */ 535 {"SDIN1", NULL, "ASP DAI0"}, 536 {"SDIN2", NULL, "ASP DAI0"}, 537 {"SDIN1", NULL, "SCLK"}, 538 {"SDIN2", NULL, "SCLK"}, 539 540 /* Capture Path */ 541 {"ADC", NULL, "HS"}, 542 { "SDOUT1", NULL, "ADC" }, 543 { "SDOUT2", NULL, "ADC" }, 544 { "Capture", NULL, "SDOUT1" }, 545 { "Capture", NULL, "SDOUT2" }, 546 547 /* Capture Requirements */ 548 { "SDOUT1", NULL, "ASP DAO0" }, 549 { "SDOUT2", NULL, "ASP DAO0" }, 550 { "SDOUT1", NULL, "SCLK" }, 551 { "SDOUT2", NULL, "SCLK" }, 552 { "SDOUT1", NULL, "ASP TX EN" }, 553 { "SDOUT2", NULL, "ASP TX EN" }, 554 }; 555 556 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 557 { 558 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 559 560 /* Prevent race with interrupt handler */ 561 mutex_lock(&cs42l42->irq_lock); 562 cs42l42->jack = jk; 563 564 if (jk) { 565 switch (cs42l42->hs_type) { 566 case CS42L42_PLUG_CTIA: 567 case CS42L42_PLUG_OMTP: 568 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET); 569 break; 570 case CS42L42_PLUG_HEADPHONE: 571 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE); 572 break; 573 default: 574 break; 575 } 576 } 577 mutex_unlock(&cs42l42->irq_lock); 578 579 return 0; 580 } 581 582 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 583 .set_jack = cs42l42_set_jack, 584 .dapm_widgets = cs42l42_dapm_widgets, 585 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 586 .dapm_routes = cs42l42_audio_map, 587 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 588 .controls = cs42l42_snd_controls, 589 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 590 .idle_bias_on = 1, 591 .endianness = 1, 592 }; 593 594 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 595 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 596 { 597 .reg = CS42L42_OSC_SWITCH, 598 .def = CS42L42_SCLK_PRESENT_MASK, 599 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 600 }, 601 }; 602 603 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 604 static const struct reg_sequence cs42l42_to_osc_seq[] = { 605 { 606 .reg = CS42L42_OSC_SWITCH, 607 .def = 0, 608 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 609 }, 610 }; 611 612 struct cs42l42_pll_params { 613 u32 sclk; 614 u8 mclk_src_sel; 615 u8 sclk_prediv; 616 u8 pll_div_int; 617 u32 pll_div_frac; 618 u8 pll_mode; 619 u8 pll_divout; 620 u32 mclk_int; 621 u8 pll_cal_ratio; 622 u8 n; 623 }; 624 625 /* 626 * Common PLL Settings for given SCLK 627 * Table 4-5 from the Datasheet 628 */ 629 static const struct cs42l42_pll_params pll_ratio_table[] = { 630 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 631 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 632 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 633 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 634 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 635 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 636 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 637 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 638 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 639 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 640 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 641 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 642 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 643 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 644 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 645 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 646 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 647 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 648 }; 649 650 static int cs42l42_pll_config(struct snd_soc_component *component) 651 { 652 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 653 int i; 654 u32 clk; 655 u32 fsync; 656 657 if (!cs42l42->sclk) 658 clk = cs42l42->bclk; 659 else 660 clk = cs42l42->sclk; 661 662 /* Don't reconfigure if there is an audio stream running */ 663 if (cs42l42->stream_use) { 664 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 665 return 0; 666 else 667 return -EBUSY; 668 } 669 670 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 671 if (pll_ratio_table[i].sclk == clk) { 672 cs42l42->pll_config = i; 673 674 /* Configure the internal sample rate */ 675 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 676 CS42L42_INTERNAL_FS_MASK, 677 ((pll_ratio_table[i].mclk_int != 678 12000000) && 679 (pll_ratio_table[i].mclk_int != 680 24000000)) << 681 CS42L42_INTERNAL_FS_SHIFT); 682 683 /* Set up the LRCLK */ 684 fsync = clk / cs42l42->srate; 685 if (((fsync * cs42l42->srate) != clk) 686 || ((fsync % 2) != 0)) { 687 dev_err(component->dev, 688 "Unsupported sclk %d/sample rate %d\n", 689 clk, 690 cs42l42->srate); 691 return -EINVAL; 692 } 693 /* Set the LRCLK period */ 694 snd_soc_component_update_bits(component, 695 CS42L42_FSYNC_P_LOWER, 696 CS42L42_FSYNC_PERIOD_MASK, 697 CS42L42_FRAC0_VAL(fsync - 1) << 698 CS42L42_FSYNC_PERIOD_SHIFT); 699 snd_soc_component_update_bits(component, 700 CS42L42_FSYNC_P_UPPER, 701 CS42L42_FSYNC_PERIOD_MASK, 702 CS42L42_FRAC1_VAL(fsync - 1) << 703 CS42L42_FSYNC_PERIOD_SHIFT); 704 /* Set the LRCLK to 50% duty cycle */ 705 fsync = fsync / 2; 706 snd_soc_component_update_bits(component, 707 CS42L42_FSYNC_PW_LOWER, 708 CS42L42_FSYNC_PULSE_WIDTH_MASK, 709 CS42L42_FRAC0_VAL(fsync - 1) << 710 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 711 snd_soc_component_update_bits(component, 712 CS42L42_FSYNC_PW_UPPER, 713 CS42L42_FSYNC_PULSE_WIDTH_MASK, 714 CS42L42_FRAC1_VAL(fsync - 1) << 715 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 716 if (pll_ratio_table[i].mclk_src_sel == 0) { 717 /* Pass the clock straight through */ 718 snd_soc_component_update_bits(component, 719 CS42L42_PLL_CTL1, 720 CS42L42_PLL_START_MASK, 0); 721 } else { 722 /* Configure PLL per table 4-5 */ 723 snd_soc_component_update_bits(component, 724 CS42L42_PLL_DIV_CFG1, 725 CS42L42_SCLK_PREDIV_MASK, 726 pll_ratio_table[i].sclk_prediv 727 << CS42L42_SCLK_PREDIV_SHIFT); 728 snd_soc_component_update_bits(component, 729 CS42L42_PLL_DIV_INT, 730 CS42L42_PLL_DIV_INT_MASK, 731 pll_ratio_table[i].pll_div_int 732 << CS42L42_PLL_DIV_INT_SHIFT); 733 snd_soc_component_update_bits(component, 734 CS42L42_PLL_DIV_FRAC0, 735 CS42L42_PLL_DIV_FRAC_MASK, 736 CS42L42_FRAC0_VAL( 737 pll_ratio_table[i].pll_div_frac) 738 << CS42L42_PLL_DIV_FRAC_SHIFT); 739 snd_soc_component_update_bits(component, 740 CS42L42_PLL_DIV_FRAC1, 741 CS42L42_PLL_DIV_FRAC_MASK, 742 CS42L42_FRAC1_VAL( 743 pll_ratio_table[i].pll_div_frac) 744 << CS42L42_PLL_DIV_FRAC_SHIFT); 745 snd_soc_component_update_bits(component, 746 CS42L42_PLL_DIV_FRAC2, 747 CS42L42_PLL_DIV_FRAC_MASK, 748 CS42L42_FRAC2_VAL( 749 pll_ratio_table[i].pll_div_frac) 750 << CS42L42_PLL_DIV_FRAC_SHIFT); 751 snd_soc_component_update_bits(component, 752 CS42L42_PLL_CTL4, 753 CS42L42_PLL_MODE_MASK, 754 pll_ratio_table[i].pll_mode 755 << CS42L42_PLL_MODE_SHIFT); 756 snd_soc_component_update_bits(component, 757 CS42L42_PLL_CTL3, 758 CS42L42_PLL_DIVOUT_MASK, 759 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 760 << CS42L42_PLL_DIVOUT_SHIFT); 761 snd_soc_component_update_bits(component, 762 CS42L42_PLL_CAL_RATIO, 763 CS42L42_PLL_CAL_RATIO_MASK, 764 pll_ratio_table[i].pll_cal_ratio 765 << CS42L42_PLL_CAL_RATIO_SHIFT); 766 } 767 return 0; 768 } 769 } 770 771 return -EINVAL; 772 } 773 774 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 775 { 776 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 777 unsigned int fs; 778 779 /* Don't reconfigure if there is an audio stream running */ 780 if (cs42l42->stream_use) 781 return; 782 783 /* SRC MCLK must be as close as possible to 125 * sample rate */ 784 if (sample_rate <= 48000) 785 fs = CS42L42_CLK_IASRC_SEL_6; 786 else 787 fs = CS42L42_CLK_IASRC_SEL_12; 788 789 /* Set the sample rates (96k or lower) */ 790 snd_soc_component_update_bits(component, 791 CS42L42_FS_RATE_EN, 792 CS42L42_FS_EN_MASK, 793 (CS42L42_FS_EN_IASRC_96K | 794 CS42L42_FS_EN_OASRC_96K) << 795 CS42L42_FS_EN_SHIFT); 796 797 snd_soc_component_update_bits(component, 798 CS42L42_IN_ASRC_CLK, 799 CS42L42_CLK_IASRC_SEL_MASK, 800 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 801 snd_soc_component_update_bits(component, 802 CS42L42_OUT_ASRC_CLK, 803 CS42L42_CLK_OASRC_SEL_MASK, 804 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 805 } 806 807 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 808 { 809 struct snd_soc_component *component = codec_dai->component; 810 u32 asp_cfg_val = 0; 811 812 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 813 case SND_SOC_DAIFMT_CBS_CFM: 814 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 815 CS42L42_ASP_MODE_SHIFT; 816 break; 817 case SND_SOC_DAIFMT_CBS_CFS: 818 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 819 CS42L42_ASP_MODE_SHIFT; 820 break; 821 default: 822 return -EINVAL; 823 } 824 825 /* interface format */ 826 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 827 case SND_SOC_DAIFMT_I2S: 828 /* 829 * 5050 mode, frame starts on falling edge of LRCLK, 830 * frame delayed by 1.0 SCLKs 831 */ 832 snd_soc_component_update_bits(component, 833 CS42L42_ASP_FRM_CFG, 834 CS42L42_ASP_STP_MASK | 835 CS42L42_ASP_5050_MASK | 836 CS42L42_ASP_FSD_MASK, 837 CS42L42_ASP_5050_MASK | 838 (CS42L42_ASP_FSD_1_0 << 839 CS42L42_ASP_FSD_SHIFT)); 840 break; 841 default: 842 return -EINVAL; 843 } 844 845 /* Bitclock/frame inversion */ 846 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 847 case SND_SOC_DAIFMT_NB_NF: 848 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 849 break; 850 case SND_SOC_DAIFMT_NB_IF: 851 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 852 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 853 break; 854 case SND_SOC_DAIFMT_IB_NF: 855 break; 856 case SND_SOC_DAIFMT_IB_IF: 857 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 858 break; 859 } 860 861 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 862 CS42L42_ASP_SCPOL_MASK | 863 CS42L42_ASP_LCPOL_MASK, 864 asp_cfg_val); 865 866 return 0; 867 } 868 869 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 870 { 871 struct snd_soc_component *component = dai->component; 872 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 873 874 /* 875 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 876 * a standard I2S frame. If the machine driver sets SCLK it must be 877 * legal. 878 */ 879 if (cs42l42->sclk) 880 return 0; 881 882 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 883 return snd_pcm_hw_constraint_minmax(substream->runtime, 884 SNDRV_PCM_HW_PARAM_RATE, 885 44100, 96000); 886 } 887 888 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 889 struct snd_pcm_hw_params *params, 890 struct snd_soc_dai *dai) 891 { 892 struct snd_soc_component *component = dai->component; 893 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 894 unsigned int channels = params_channels(params); 895 unsigned int width = (params_width(params) / 8) - 1; 896 unsigned int slot_width = 0; 897 unsigned int val = 0; 898 int ret; 899 900 cs42l42->srate = params_rate(params); 901 902 /* 903 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 904 * more than assumed (which would result in overclocking). 905 */ 906 if (params_width(params) == 24) 907 slot_width = 32; 908 909 /* I2S frame always has multiple of 2 channels */ 910 cs42l42->bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2); 911 912 switch (substream->stream) { 913 case SNDRV_PCM_STREAM_CAPTURE: 914 /* channel 2 on high LRCLK */ 915 val = CS42L42_ASP_TX_CH2_AP_MASK | 916 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 917 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 918 919 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 920 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 921 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 922 break; 923 case SNDRV_PCM_STREAM_PLAYBACK: 924 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 925 /* channel 1 on low LRCLK */ 926 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 927 CS42L42_ASP_RX_CH_AP_MASK | 928 CS42L42_ASP_RX_CH_RES_MASK, val); 929 /* Channel 2 on high LRCLK */ 930 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 931 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 932 CS42L42_ASP_RX_CH_AP_MASK | 933 CS42L42_ASP_RX_CH_RES_MASK, val); 934 935 /* Channel B comes from the last active channel */ 936 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 937 CS42L42_SP_RX_CHB_SEL_MASK, 938 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 939 940 /* Both LRCLK slots must be enabled */ 941 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 942 CS42L42_ASP_RX0_CH_EN_MASK, 943 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 944 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 945 break; 946 default: 947 break; 948 } 949 950 ret = cs42l42_pll_config(component); 951 if (ret) 952 return ret; 953 954 cs42l42_src_config(component, params_rate(params)); 955 956 return 0; 957 } 958 959 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 960 int clk_id, unsigned int freq, int dir) 961 { 962 struct snd_soc_component *component = dai->component; 963 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 964 int i; 965 966 if (freq == 0) { 967 cs42l42->sclk = 0; 968 return 0; 969 } 970 971 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 972 if (pll_ratio_table[i].sclk == freq) { 973 cs42l42->sclk = freq; 974 return 0; 975 } 976 } 977 978 dev_err(component->dev, "SCLK %u not supported\n", freq); 979 980 return -EINVAL; 981 } 982 983 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 984 { 985 struct snd_soc_component *component = dai->component; 986 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 987 unsigned int regval; 988 int ret; 989 990 if (mute) { 991 /* Mute the headphone */ 992 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 993 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 994 CS42L42_HP_ANA_AMUTE_MASK | 995 CS42L42_HP_ANA_BMUTE_MASK, 996 CS42L42_HP_ANA_AMUTE_MASK | 997 CS42L42_HP_ANA_BMUTE_MASK); 998 999 cs42l42->stream_use &= ~(1 << stream); 1000 if (!cs42l42->stream_use) { 1001 /* 1002 * Switch to the internal oscillator. 1003 * SCLK must remain running until after this clock switch. 1004 * Without a source of clock the I2C bus doesn't work. 1005 */ 1006 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 1007 ARRAY_SIZE(cs42l42_to_osc_seq)); 1008 1009 /* Must disconnect PLL before stopping it */ 1010 snd_soc_component_update_bits(component, 1011 CS42L42_MCLK_SRC_SEL, 1012 CS42L42_MCLK_SRC_SEL_MASK, 1013 0); 1014 usleep_range(100, 200); 1015 1016 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1017 CS42L42_PLL_START_MASK, 0); 1018 } 1019 } else { 1020 if (!cs42l42->stream_use) { 1021 /* SCLK must be running before codec unmute. 1022 * 1023 * PLL must not be started with ADC and HP both off 1024 * otherwise the FILT+ supply will not charge properly. 1025 * DAPM widgets power-up before stream unmute so at least 1026 * one of the "DAC" or "ADC" widgets will already have 1027 * powered-up. 1028 */ 1029 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1030 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1031 CS42L42_PLL_START_MASK, 1); 1032 1033 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1034 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1035 CS42L42_PLL_DIVOUT_TIME_US * 2); 1036 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1037 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1038 CS42L42_PLL_DIVOUT_MASK, 1039 regval << 1040 CS42L42_PLL_DIVOUT_SHIFT); 1041 } 1042 1043 ret = regmap_read_poll_timeout(cs42l42->regmap, 1044 CS42L42_PLL_LOCK_STATUS, 1045 regval, 1046 (regval & 1), 1047 CS42L42_PLL_LOCK_POLL_US, 1048 CS42L42_PLL_LOCK_TIMEOUT_US); 1049 if (ret < 0) 1050 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1051 1052 /* PLL must be running to drive glitchless switch logic */ 1053 snd_soc_component_update_bits(component, 1054 CS42L42_MCLK_SRC_SEL, 1055 CS42L42_MCLK_SRC_SEL_MASK, 1056 CS42L42_MCLK_SRC_SEL_MASK); 1057 } 1058 1059 /* Mark SCLK as present, turn off internal oscillator */ 1060 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1061 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1062 } 1063 cs42l42->stream_use |= 1 << stream; 1064 1065 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1066 /* Un-mute the headphone */ 1067 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1068 CS42L42_HP_ANA_AMUTE_MASK | 1069 CS42L42_HP_ANA_BMUTE_MASK, 1070 0); 1071 } 1072 } 1073 1074 return 0; 1075 } 1076 1077 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1078 SNDRV_PCM_FMTBIT_S24_LE |\ 1079 SNDRV_PCM_FMTBIT_S32_LE) 1080 1081 static const struct snd_soc_dai_ops cs42l42_ops = { 1082 .startup = cs42l42_dai_startup, 1083 .hw_params = cs42l42_pcm_hw_params, 1084 .set_fmt = cs42l42_set_dai_fmt, 1085 .set_sysclk = cs42l42_set_sysclk, 1086 .mute_stream = cs42l42_mute_stream, 1087 }; 1088 1089 static struct snd_soc_dai_driver cs42l42_dai = { 1090 .name = "cs42l42", 1091 .playback = { 1092 .stream_name = "Playback", 1093 .channels_min = 1, 1094 .channels_max = 2, 1095 .rates = SNDRV_PCM_RATE_8000_96000, 1096 .formats = CS42L42_FORMATS, 1097 }, 1098 .capture = { 1099 .stream_name = "Capture", 1100 .channels_min = 1, 1101 .channels_max = 2, 1102 .rates = SNDRV_PCM_RATE_8000_96000, 1103 .formats = CS42L42_FORMATS, 1104 }, 1105 .symmetric_rate = 1, 1106 .symmetric_sample_bits = 1, 1107 .ops = &cs42l42_ops, 1108 }; 1109 1110 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1111 { 1112 unsigned int hs_det_status; 1113 unsigned int hs_det_comp1; 1114 unsigned int hs_det_comp2; 1115 unsigned int hs_det_sw; 1116 1117 /* Set hs detect to manual, active mode */ 1118 regmap_update_bits(cs42l42->regmap, 1119 CS42L42_HSDET_CTL2, 1120 CS42L42_HSDET_CTRL_MASK | 1121 CS42L42_HSDET_SET_MASK | 1122 CS42L42_HSBIAS_REF_MASK | 1123 CS42L42_HSDET_AUTO_TIME_MASK, 1124 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1125 (0 << CS42L42_HSDET_SET_SHIFT) | 1126 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1127 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1128 1129 /* Configure HS DET comparator reference levels. */ 1130 regmap_update_bits(cs42l42->regmap, 1131 CS42L42_HSDET_CTL1, 1132 CS42L42_HSDET_COMP1_LVL_MASK | 1133 CS42L42_HSDET_COMP2_LVL_MASK, 1134 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1135 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1136 1137 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1138 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1139 1140 msleep(100); 1141 1142 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1143 1144 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1145 CS42L42_HSDET_COMP1_OUT_SHIFT; 1146 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1147 CS42L42_HSDET_COMP2_OUT_SHIFT; 1148 1149 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1150 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1151 1152 msleep(100); 1153 1154 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1155 1156 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1157 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1158 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1159 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1160 1161 /* Use Comparator 1 with 1.25V Threshold. */ 1162 switch (hs_det_comp1) { 1163 case CS42L42_HSDET_COMP_TYPE1: 1164 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1165 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1166 break; 1167 case CS42L42_HSDET_COMP_TYPE2: 1168 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1169 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1170 break; 1171 default: 1172 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1173 switch (hs_det_comp2) { 1174 case CS42L42_HSDET_COMP_TYPE1: 1175 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1176 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1177 break; 1178 case CS42L42_HSDET_COMP_TYPE2: 1179 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1180 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1181 break; 1182 case CS42L42_HSDET_COMP_TYPE3: 1183 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1184 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1185 break; 1186 default: 1187 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1188 hs_det_sw = CS42L42_HSDET_SW_TYPE4; 1189 break; 1190 } 1191 } 1192 1193 /* Set Switches */ 1194 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1195 1196 /* Set HSDET mode to Manual—Disabled */ 1197 regmap_update_bits(cs42l42->regmap, 1198 CS42L42_HSDET_CTL2, 1199 CS42L42_HSDET_CTRL_MASK | 1200 CS42L42_HSDET_SET_MASK | 1201 CS42L42_HSBIAS_REF_MASK | 1202 CS42L42_HSDET_AUTO_TIME_MASK, 1203 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1204 (0 << CS42L42_HSDET_SET_SHIFT) | 1205 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1206 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1207 1208 /* Configure HS DET comparator reference levels. */ 1209 regmap_update_bits(cs42l42->regmap, 1210 CS42L42_HSDET_CTL1, 1211 CS42L42_HSDET_COMP1_LVL_MASK | 1212 CS42L42_HSDET_COMP2_LVL_MASK, 1213 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1214 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1215 } 1216 1217 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1218 { 1219 unsigned int hs_det_status; 1220 unsigned int int_status; 1221 1222 /* Read and save the hs detection result */ 1223 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1224 1225 /* Mask the auto detect interrupt */ 1226 regmap_update_bits(cs42l42->regmap, 1227 CS42L42_CODEC_INT_MASK, 1228 CS42L42_PDN_DONE_MASK | 1229 CS42L42_HSDET_AUTO_DONE_MASK, 1230 (1 << CS42L42_PDN_DONE_SHIFT) | 1231 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1232 1233 1234 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1235 CS42L42_HSDET_TYPE_SHIFT; 1236 1237 /* Set hs detect to automatic, disabled mode */ 1238 regmap_update_bits(cs42l42->regmap, 1239 CS42L42_HSDET_CTL2, 1240 CS42L42_HSDET_CTRL_MASK | 1241 CS42L42_HSDET_SET_MASK | 1242 CS42L42_HSBIAS_REF_MASK | 1243 CS42L42_HSDET_AUTO_TIME_MASK, 1244 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1245 (2 << CS42L42_HSDET_SET_SHIFT) | 1246 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1247 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1248 1249 /* Run Manual detection if auto detect has not found a headset. 1250 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1251 * to ensure that a headset mic is detected in all cases. 1252 */ 1253 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1254 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1255 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1256 cs42l42_manual_hs_type_detect(cs42l42); 1257 } 1258 1259 /* Set up button detection */ 1260 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1261 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1262 /* Set auto HS bias settings to default */ 1263 regmap_update_bits(cs42l42->regmap, 1264 CS42L42_HSBIAS_SC_AUTOCTL, 1265 CS42L42_HSBIAS_SENSE_EN_MASK | 1266 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1267 CS42L42_TIP_SENSE_EN_MASK | 1268 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1269 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1270 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1271 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1272 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1273 1274 /* Set up hs detect level sensitivity */ 1275 regmap_update_bits(cs42l42->regmap, 1276 CS42L42_MIC_DET_CTL1, 1277 CS42L42_LATCH_TO_VP_MASK | 1278 CS42L42_EVENT_STAT_SEL_MASK | 1279 CS42L42_HS_DET_LEVEL_MASK, 1280 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1281 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1282 (cs42l42->bias_thresholds[0] << 1283 CS42L42_HS_DET_LEVEL_SHIFT)); 1284 1285 /* Set auto HS bias settings to default */ 1286 regmap_update_bits(cs42l42->regmap, 1287 CS42L42_HSBIAS_SC_AUTOCTL, 1288 CS42L42_HSBIAS_SENSE_EN_MASK | 1289 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1290 CS42L42_TIP_SENSE_EN_MASK | 1291 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1292 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1293 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1294 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1295 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1296 1297 /* Turn on level detect circuitry */ 1298 regmap_update_bits(cs42l42->regmap, 1299 CS42L42_MISC_DET_CTL, 1300 CS42L42_HSBIAS_CTL_MASK | 1301 CS42L42_PDN_MIC_LVL_DET_MASK, 1302 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1303 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1304 1305 msleep(cs42l42->btn_det_init_dbnce); 1306 1307 /* Clear any button interrupts before unmasking them */ 1308 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1309 &int_status); 1310 1311 /* Unmask button detect interrupts */ 1312 regmap_update_bits(cs42l42->regmap, 1313 CS42L42_DET_INT2_MASK, 1314 CS42L42_M_DETECT_TF_MASK | 1315 CS42L42_M_DETECT_FT_MASK | 1316 CS42L42_M_HSBIAS_HIZ_MASK | 1317 CS42L42_M_SHORT_RLS_MASK | 1318 CS42L42_M_SHORT_DET_MASK, 1319 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1320 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1321 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1322 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1323 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1324 } else { 1325 /* Make sure button detect and HS bias circuits are off */ 1326 regmap_update_bits(cs42l42->regmap, 1327 CS42L42_MISC_DET_CTL, 1328 CS42L42_HSBIAS_CTL_MASK | 1329 CS42L42_PDN_MIC_LVL_DET_MASK, 1330 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1331 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1332 } 1333 1334 regmap_update_bits(cs42l42->regmap, 1335 CS42L42_DAC_CTL2, 1336 CS42L42_HPOUT_PULLDOWN_MASK | 1337 CS42L42_HPOUT_LOAD_MASK | 1338 CS42L42_HPOUT_CLAMP_MASK | 1339 CS42L42_DAC_HPF_EN_MASK | 1340 CS42L42_DAC_MON_EN_MASK, 1341 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1342 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1343 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1344 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1345 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1346 1347 /* Unmask tip sense interrupts */ 1348 regmap_update_bits(cs42l42->regmap, 1349 CS42L42_TSRS_PLUG_INT_MASK, 1350 CS42L42_TS_PLUG_MASK | 1351 CS42L42_TS_UNPLUG_MASK, 1352 (0 << CS42L42_TS_PLUG_SHIFT) | 1353 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1354 } 1355 1356 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1357 { 1358 /* Mask tip sense interrupts */ 1359 regmap_update_bits(cs42l42->regmap, 1360 CS42L42_TSRS_PLUG_INT_MASK, 1361 CS42L42_TS_PLUG_MASK | 1362 CS42L42_TS_UNPLUG_MASK, 1363 (1 << CS42L42_TS_PLUG_SHIFT) | 1364 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1365 1366 /* Make sure button detect and HS bias circuits are off */ 1367 regmap_update_bits(cs42l42->regmap, 1368 CS42L42_MISC_DET_CTL, 1369 CS42L42_HSBIAS_CTL_MASK | 1370 CS42L42_PDN_MIC_LVL_DET_MASK, 1371 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1372 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1373 1374 /* Set auto HS bias settings to default */ 1375 regmap_update_bits(cs42l42->regmap, 1376 CS42L42_HSBIAS_SC_AUTOCTL, 1377 CS42L42_HSBIAS_SENSE_EN_MASK | 1378 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1379 CS42L42_TIP_SENSE_EN_MASK | 1380 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1381 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1382 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1383 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1384 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1385 1386 /* Set hs detect to manual, disabled mode */ 1387 regmap_update_bits(cs42l42->regmap, 1388 CS42L42_HSDET_CTL2, 1389 CS42L42_HSDET_CTRL_MASK | 1390 CS42L42_HSDET_SET_MASK | 1391 CS42L42_HSBIAS_REF_MASK | 1392 CS42L42_HSDET_AUTO_TIME_MASK, 1393 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1394 (2 << CS42L42_HSDET_SET_SHIFT) | 1395 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1396 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1397 1398 regmap_update_bits(cs42l42->regmap, 1399 CS42L42_DAC_CTL2, 1400 CS42L42_HPOUT_PULLDOWN_MASK | 1401 CS42L42_HPOUT_LOAD_MASK | 1402 CS42L42_HPOUT_CLAMP_MASK | 1403 CS42L42_DAC_HPF_EN_MASK | 1404 CS42L42_DAC_MON_EN_MASK, 1405 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1406 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1407 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1408 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1409 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1410 1411 /* Power up HS bias to 2.7V */ 1412 regmap_update_bits(cs42l42->regmap, 1413 CS42L42_MISC_DET_CTL, 1414 CS42L42_HSBIAS_CTL_MASK | 1415 CS42L42_PDN_MIC_LVL_DET_MASK, 1416 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1417 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1418 1419 /* Wait for HS bias to ramp up */ 1420 msleep(cs42l42->hs_bias_ramp_time); 1421 1422 /* Unmask auto detect interrupt */ 1423 regmap_update_bits(cs42l42->regmap, 1424 CS42L42_CODEC_INT_MASK, 1425 CS42L42_PDN_DONE_MASK | 1426 CS42L42_HSDET_AUTO_DONE_MASK, 1427 (1 << CS42L42_PDN_DONE_SHIFT) | 1428 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1429 1430 /* Set hs detect to automatic, enabled mode */ 1431 regmap_update_bits(cs42l42->regmap, 1432 CS42L42_HSDET_CTL2, 1433 CS42L42_HSDET_CTRL_MASK | 1434 CS42L42_HSDET_SET_MASK | 1435 CS42L42_HSBIAS_REF_MASK | 1436 CS42L42_HSDET_AUTO_TIME_MASK, 1437 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1438 (2 << CS42L42_HSDET_SET_SHIFT) | 1439 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1440 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1441 } 1442 1443 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1444 { 1445 /* Mask button detect interrupts */ 1446 regmap_update_bits(cs42l42->regmap, 1447 CS42L42_DET_INT2_MASK, 1448 CS42L42_M_DETECT_TF_MASK | 1449 CS42L42_M_DETECT_FT_MASK | 1450 CS42L42_M_HSBIAS_HIZ_MASK | 1451 CS42L42_M_SHORT_RLS_MASK | 1452 CS42L42_M_SHORT_DET_MASK, 1453 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1454 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1455 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1456 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1457 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1458 1459 /* Ground HS bias */ 1460 regmap_update_bits(cs42l42->regmap, 1461 CS42L42_MISC_DET_CTL, 1462 CS42L42_HSBIAS_CTL_MASK | 1463 CS42L42_PDN_MIC_LVL_DET_MASK, 1464 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1465 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1466 1467 /* Set auto HS bias settings to default */ 1468 regmap_update_bits(cs42l42->regmap, 1469 CS42L42_HSBIAS_SC_AUTOCTL, 1470 CS42L42_HSBIAS_SENSE_EN_MASK | 1471 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1472 CS42L42_TIP_SENSE_EN_MASK | 1473 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1474 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1475 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1476 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1477 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1478 1479 /* Set hs detect to manual, disabled mode */ 1480 regmap_update_bits(cs42l42->regmap, 1481 CS42L42_HSDET_CTL2, 1482 CS42L42_HSDET_CTRL_MASK | 1483 CS42L42_HSDET_SET_MASK | 1484 CS42L42_HSBIAS_REF_MASK | 1485 CS42L42_HSDET_AUTO_TIME_MASK, 1486 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1487 (2 << CS42L42_HSDET_SET_SHIFT) | 1488 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1489 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1490 } 1491 1492 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1493 { 1494 int bias_level; 1495 unsigned int detect_status; 1496 1497 /* Mask button detect interrupts */ 1498 regmap_update_bits(cs42l42->regmap, 1499 CS42L42_DET_INT2_MASK, 1500 CS42L42_M_DETECT_TF_MASK | 1501 CS42L42_M_DETECT_FT_MASK | 1502 CS42L42_M_HSBIAS_HIZ_MASK | 1503 CS42L42_M_SHORT_RLS_MASK | 1504 CS42L42_M_SHORT_DET_MASK, 1505 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1506 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1507 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1508 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1509 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1510 1511 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1512 cs42l42->btn_det_event_dbnce * 2000); 1513 1514 /* Test all 4 level detect biases */ 1515 bias_level = 1; 1516 do { 1517 /* Adjust button detect level sensitivity */ 1518 regmap_update_bits(cs42l42->regmap, 1519 CS42L42_MIC_DET_CTL1, 1520 CS42L42_LATCH_TO_VP_MASK | 1521 CS42L42_EVENT_STAT_SEL_MASK | 1522 CS42L42_HS_DET_LEVEL_MASK, 1523 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1524 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1525 (cs42l42->bias_thresholds[bias_level] << 1526 CS42L42_HS_DET_LEVEL_SHIFT)); 1527 1528 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1529 &detect_status); 1530 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1531 (++bias_level < CS42L42_NUM_BIASES)); 1532 1533 switch (bias_level) { 1534 case 1: /* Function C button press */ 1535 bias_level = SND_JACK_BTN_2; 1536 dev_dbg(cs42l42->dev, "Function C button press\n"); 1537 break; 1538 case 2: /* Function B button press */ 1539 bias_level = SND_JACK_BTN_1; 1540 dev_dbg(cs42l42->dev, "Function B button press\n"); 1541 break; 1542 case 3: /* Function D button press */ 1543 bias_level = SND_JACK_BTN_3; 1544 dev_dbg(cs42l42->dev, "Function D button press\n"); 1545 break; 1546 case 4: /* Function A button press */ 1547 bias_level = SND_JACK_BTN_0; 1548 dev_dbg(cs42l42->dev, "Function A button press\n"); 1549 break; 1550 default: 1551 bias_level = 0; 1552 break; 1553 } 1554 1555 /* Set button detect level sensitivity back to default */ 1556 regmap_update_bits(cs42l42->regmap, 1557 CS42L42_MIC_DET_CTL1, 1558 CS42L42_LATCH_TO_VP_MASK | 1559 CS42L42_EVENT_STAT_SEL_MASK | 1560 CS42L42_HS_DET_LEVEL_MASK, 1561 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1562 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1563 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1564 1565 /* Clear any button interrupts before unmasking them */ 1566 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1567 &detect_status); 1568 1569 /* Unmask button detect interrupts */ 1570 regmap_update_bits(cs42l42->regmap, 1571 CS42L42_DET_INT2_MASK, 1572 CS42L42_M_DETECT_TF_MASK | 1573 CS42L42_M_DETECT_FT_MASK | 1574 CS42L42_M_HSBIAS_HIZ_MASK | 1575 CS42L42_M_SHORT_RLS_MASK | 1576 CS42L42_M_SHORT_DET_MASK, 1577 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1578 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1579 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1580 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1581 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1582 1583 return bias_level; 1584 } 1585 1586 struct cs42l42_irq_params { 1587 u16 status_addr; 1588 u16 mask_addr; 1589 u8 mask; 1590 }; 1591 1592 static const struct cs42l42_irq_params irq_params_table[] = { 1593 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1594 CS42L42_ADC_OVFL_VAL_MASK}, 1595 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1596 CS42L42_MIXER_VAL_MASK}, 1597 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1598 CS42L42_SRC_VAL_MASK}, 1599 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1600 CS42L42_ASP_RX_VAL_MASK}, 1601 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1602 CS42L42_ASP_TX_VAL_MASK}, 1603 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1604 CS42L42_CODEC_VAL_MASK}, 1605 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1606 CS42L42_DET_INT_VAL1_MASK}, 1607 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1608 CS42L42_DET_INT_VAL2_MASK}, 1609 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1610 CS42L42_SRCPL_VAL_MASK}, 1611 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1612 CS42L42_VPMON_VAL_MASK}, 1613 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1614 CS42L42_PLL_LOCK_VAL_MASK}, 1615 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1616 CS42L42_TSRS_PLUG_VAL_MASK} 1617 }; 1618 1619 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1620 { 1621 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1622 unsigned int stickies[12]; 1623 unsigned int masks[12]; 1624 unsigned int current_plug_status; 1625 unsigned int current_button_status; 1626 unsigned int i; 1627 int report = 0; 1628 1629 mutex_lock(&cs42l42->irq_lock); 1630 if (cs42l42->suspended) { 1631 mutex_unlock(&cs42l42->irq_lock); 1632 return IRQ_NONE; 1633 } 1634 1635 /* Read sticky registers to clear interurpt */ 1636 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1637 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1638 &(stickies[i])); 1639 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1640 &(masks[i])); 1641 stickies[i] = stickies[i] & (~masks[i]) & 1642 irq_params_table[i].mask; 1643 } 1644 1645 /* Read tip sense status before handling type detect */ 1646 current_plug_status = (stickies[11] & 1647 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1648 CS42L42_TS_PLUG_SHIFT; 1649 1650 /* Read button sense status */ 1651 current_button_status = stickies[7] & 1652 (CS42L42_M_DETECT_TF_MASK | 1653 CS42L42_M_DETECT_FT_MASK | 1654 CS42L42_M_HSBIAS_HIZ_MASK); 1655 1656 /* 1657 * Check auto-detect status. Don't assume a previous unplug event has 1658 * cleared the flags. If the jack is unplugged and plugged during 1659 * system suspend there won't have been an unplug event. 1660 */ 1661 if ((~masks[5]) & irq_params_table[5].mask) { 1662 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1663 cs42l42_process_hs_type_detect(cs42l42); 1664 switch (cs42l42->hs_type) { 1665 case CS42L42_PLUG_CTIA: 1666 case CS42L42_PLUG_OMTP: 1667 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1668 SND_JACK_HEADSET | 1669 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1670 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1671 break; 1672 case CS42L42_PLUG_HEADPHONE: 1673 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1674 SND_JACK_HEADSET | 1675 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1676 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1677 break; 1678 default: 1679 break; 1680 } 1681 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1682 } 1683 } 1684 1685 /* Check tip sense status */ 1686 if ((~masks[11]) & irq_params_table[11].mask) { 1687 switch (current_plug_status) { 1688 case CS42L42_TS_PLUG: 1689 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1690 cs42l42->plug_state = CS42L42_TS_PLUG; 1691 cs42l42_init_hs_type_detect(cs42l42); 1692 } 1693 break; 1694 1695 case CS42L42_TS_UNPLUG: 1696 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1697 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1698 cs42l42_cancel_hs_type_detect(cs42l42); 1699 1700 snd_soc_jack_report(cs42l42->jack, 0, 1701 SND_JACK_HEADSET | 1702 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1703 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1704 1705 dev_dbg(cs42l42->dev, "Unplug event\n"); 1706 } 1707 break; 1708 1709 default: 1710 cs42l42->plug_state = CS42L42_TS_TRANS; 1711 } 1712 } 1713 1714 /* Check button detect status */ 1715 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1716 if (!(current_button_status & 1717 CS42L42_M_HSBIAS_HIZ_MASK)) { 1718 1719 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1720 dev_dbg(cs42l42->dev, "Button released\n"); 1721 report = 0; 1722 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1723 report = cs42l42_handle_button_press(cs42l42); 1724 1725 } 1726 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1727 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1728 } 1729 } 1730 1731 mutex_unlock(&cs42l42->irq_lock); 1732 1733 return IRQ_HANDLED; 1734 } 1735 1736 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1737 { 1738 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1739 CS42L42_ADC_OVFL_MASK, 1740 (1 << CS42L42_ADC_OVFL_SHIFT)); 1741 1742 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1743 CS42L42_MIX_CHB_OVFL_MASK | 1744 CS42L42_MIX_CHA_OVFL_MASK | 1745 CS42L42_EQ_OVFL_MASK | 1746 CS42L42_EQ_BIQUAD_OVFL_MASK, 1747 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1748 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1749 (1 << CS42L42_EQ_OVFL_SHIFT) | 1750 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1751 1752 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1753 CS42L42_SRC_ILK_MASK | 1754 CS42L42_SRC_OLK_MASK | 1755 CS42L42_SRC_IUNLK_MASK | 1756 CS42L42_SRC_OUNLK_MASK, 1757 (1 << CS42L42_SRC_ILK_SHIFT) | 1758 (1 << CS42L42_SRC_OLK_SHIFT) | 1759 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1760 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1761 1762 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1763 CS42L42_ASPRX_NOLRCK_MASK | 1764 CS42L42_ASPRX_EARLY_MASK | 1765 CS42L42_ASPRX_LATE_MASK | 1766 CS42L42_ASPRX_ERROR_MASK | 1767 CS42L42_ASPRX_OVLD_MASK, 1768 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1769 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1770 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1771 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1772 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1773 1774 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1775 CS42L42_ASPTX_NOLRCK_MASK | 1776 CS42L42_ASPTX_EARLY_MASK | 1777 CS42L42_ASPTX_LATE_MASK | 1778 CS42L42_ASPTX_SMERROR_MASK, 1779 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1780 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1781 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1782 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1783 1784 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1785 CS42L42_PDN_DONE_MASK | 1786 CS42L42_HSDET_AUTO_DONE_MASK, 1787 (1 << CS42L42_PDN_DONE_SHIFT) | 1788 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1789 1790 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1791 CS42L42_SRCPL_ADC_LK_MASK | 1792 CS42L42_SRCPL_DAC_LK_MASK | 1793 CS42L42_SRCPL_ADC_UNLK_MASK | 1794 CS42L42_SRCPL_DAC_UNLK_MASK, 1795 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1796 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1797 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1798 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1799 1800 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1801 CS42L42_TIP_SENSE_UNPLUG_MASK | 1802 CS42L42_TIP_SENSE_PLUG_MASK | 1803 CS42L42_HSBIAS_SENSE_MASK, 1804 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1805 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1806 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1807 1808 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1809 CS42L42_M_DETECT_TF_MASK | 1810 CS42L42_M_DETECT_FT_MASK | 1811 CS42L42_M_HSBIAS_HIZ_MASK | 1812 CS42L42_M_SHORT_RLS_MASK | 1813 CS42L42_M_SHORT_DET_MASK, 1814 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1815 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1816 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1817 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1818 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1819 1820 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1821 CS42L42_VPMON_MASK, 1822 (1 << CS42L42_VPMON_SHIFT)); 1823 1824 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1825 CS42L42_PLL_LOCK_MASK, 1826 (1 << CS42L42_PLL_LOCK_SHIFT)); 1827 1828 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1829 CS42L42_RS_PLUG_MASK | 1830 CS42L42_RS_UNPLUG_MASK | 1831 CS42L42_TS_PLUG_MASK | 1832 CS42L42_TS_UNPLUG_MASK, 1833 (1 << CS42L42_RS_PLUG_SHIFT) | 1834 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1835 (0 << CS42L42_TS_PLUG_SHIFT) | 1836 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1837 } 1838 1839 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1840 { 1841 unsigned int reg; 1842 1843 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1844 1845 /* 1846 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the 1847 * FILT+ supply will not charge properly. 1848 */ 1849 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1850 CS42L42_DETECT_MODE_MASK, 0); 1851 1852 /* Latch analog controls to VP power domain */ 1853 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1854 CS42L42_LATCH_TO_VP_MASK | 1855 CS42L42_EVENT_STAT_SEL_MASK | 1856 CS42L42_HS_DET_LEVEL_MASK, 1857 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1858 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1859 (cs42l42->bias_thresholds[0] << 1860 CS42L42_HS_DET_LEVEL_SHIFT)); 1861 1862 /* Remove ground noise-suppression clamps */ 1863 regmap_update_bits(cs42l42->regmap, 1864 CS42L42_HS_CLAMP_DISABLE, 1865 CS42L42_HS_CLAMP_DISABLE_MASK, 1866 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1867 1868 /* Enable the tip sense circuit */ 1869 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1870 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1871 1872 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1873 CS42L42_TIP_SENSE_CTRL_MASK | 1874 CS42L42_TIP_SENSE_INV_MASK | 1875 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1876 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1877 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1878 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1879 1880 /* Save the initial status of the tip sense */ 1881 regmap_read(cs42l42->regmap, 1882 CS42L42_TSRS_PLUG_STATUS, 1883 ®); 1884 cs42l42->plug_state = (((char) reg) & 1885 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1886 CS42L42_TS_PLUG_SHIFT; 1887 } 1888 1889 static const unsigned int threshold_defaults[] = { 1890 CS42L42_HS_DET_LEVEL_15, 1891 CS42L42_HS_DET_LEVEL_8, 1892 CS42L42_HS_DET_LEVEL_4, 1893 CS42L42_HS_DET_LEVEL_1 1894 }; 1895 1896 static int cs42l42_handle_device_data(struct device *dev, 1897 struct cs42l42_private *cs42l42) 1898 { 1899 unsigned int val; 1900 u32 thresholds[CS42L42_NUM_BIASES]; 1901 int ret; 1902 int i; 1903 1904 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1905 if (!ret) { 1906 switch (val) { 1907 case CS42L42_TS_INV_EN: 1908 case CS42L42_TS_INV_DIS: 1909 cs42l42->ts_inv = val; 1910 break; 1911 default: 1912 dev_err(dev, 1913 "Wrong cirrus,ts-inv DT value %d\n", 1914 val); 1915 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1916 } 1917 } else { 1918 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1919 } 1920 1921 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1922 if (!ret) { 1923 switch (val) { 1924 case CS42L42_TS_DBNCE_0: 1925 case CS42L42_TS_DBNCE_125: 1926 case CS42L42_TS_DBNCE_250: 1927 case CS42L42_TS_DBNCE_500: 1928 case CS42L42_TS_DBNCE_750: 1929 case CS42L42_TS_DBNCE_1000: 1930 case CS42L42_TS_DBNCE_1250: 1931 case CS42L42_TS_DBNCE_1500: 1932 cs42l42->ts_dbnc_rise = val; 1933 break; 1934 default: 1935 dev_err(dev, 1936 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1937 val); 1938 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1939 } 1940 } else { 1941 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1942 } 1943 1944 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1945 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1946 (cs42l42->ts_dbnc_rise << 1947 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1948 1949 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1950 if (!ret) { 1951 switch (val) { 1952 case CS42L42_TS_DBNCE_0: 1953 case CS42L42_TS_DBNCE_125: 1954 case CS42L42_TS_DBNCE_250: 1955 case CS42L42_TS_DBNCE_500: 1956 case CS42L42_TS_DBNCE_750: 1957 case CS42L42_TS_DBNCE_1000: 1958 case CS42L42_TS_DBNCE_1250: 1959 case CS42L42_TS_DBNCE_1500: 1960 cs42l42->ts_dbnc_fall = val; 1961 break; 1962 default: 1963 dev_err(dev, 1964 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1965 val); 1966 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1967 } 1968 } else { 1969 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1970 } 1971 1972 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1973 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1974 (cs42l42->ts_dbnc_fall << 1975 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1976 1977 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1978 if (!ret) { 1979 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1980 cs42l42->btn_det_init_dbnce = val; 1981 else { 1982 dev_err(dev, 1983 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1984 val); 1985 cs42l42->btn_det_init_dbnce = 1986 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1987 } 1988 } else { 1989 cs42l42->btn_det_init_dbnce = 1990 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1991 } 1992 1993 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1994 if (!ret) { 1995 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1996 cs42l42->btn_det_event_dbnce = val; 1997 else { 1998 dev_err(dev, 1999 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 2000 cs42l42->btn_det_event_dbnce = 2001 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2002 } 2003 } else { 2004 cs42l42->btn_det_event_dbnce = 2005 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 2006 } 2007 2008 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 2009 thresholds, ARRAY_SIZE(thresholds)); 2010 if (!ret) { 2011 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 2012 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 2013 cs42l42->bias_thresholds[i] = thresholds[i]; 2014 else { 2015 dev_err(dev, 2016 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 2017 thresholds[i]); 2018 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2019 } 2020 } 2021 } else { 2022 for (i = 0; i < CS42L42_NUM_BIASES; i++) 2023 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 2024 } 2025 2026 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 2027 if (!ret) { 2028 switch (val) { 2029 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 2030 cs42l42->hs_bias_ramp_rate = val; 2031 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 2032 break; 2033 case CS42L42_HSBIAS_RAMP_FAST: 2034 cs42l42->hs_bias_ramp_rate = val; 2035 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 2036 break; 2037 case CS42L42_HSBIAS_RAMP_SLOW: 2038 cs42l42->hs_bias_ramp_rate = val; 2039 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2040 break; 2041 case CS42L42_HSBIAS_RAMP_SLOWEST: 2042 cs42l42->hs_bias_ramp_rate = val; 2043 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 2044 break; 2045 default: 2046 dev_err(dev, 2047 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2048 val); 2049 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2050 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2051 } 2052 } else { 2053 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2054 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2055 } 2056 2057 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2058 CS42L42_HSBIAS_RAMP_MASK, 2059 (cs42l42->hs_bias_ramp_rate << 2060 CS42L42_HSBIAS_RAMP_SHIFT)); 2061 2062 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2063 cs42l42->hs_bias_sense_en = 0; 2064 else 2065 cs42l42->hs_bias_sense_en = 1; 2066 2067 return 0; 2068 } 2069 2070 /* Datasheet suspend sequence */ 2071 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { 2072 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), 2073 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), 2074 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), 2075 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), 2076 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), 2077 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), 2078 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), 2079 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), 2080 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), 2081 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), 2082 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), 2083 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), 2084 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), 2085 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), 2086 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), 2087 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), 2088 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), 2089 REG_SEQ0(CS42L42_HP_CTL, 0x0F), 2090 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), 2091 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), 2092 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), 2093 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), 2094 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), 2095 REG_SEQ0(CS42L42_DAC_CTL2, 0x02), 2096 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), 2097 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), 2098 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), 2099 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), 2100 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) 2101 }; 2102 2103 static int __maybe_unused cs42l42_suspend(struct device *dev) 2104 { 2105 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2106 unsigned int reg; 2107 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; 2108 int i, ret; 2109 2110 /* 2111 * Wait for threaded irq handler to be idle and stop it processing 2112 * future interrupts. This ensures a safe disable if the interrupt 2113 * is shared. 2114 */ 2115 mutex_lock(&cs42l42->irq_lock); 2116 cs42l42->suspended = true; 2117 2118 /* Save register values that will be overwritten by shutdown sequence */ 2119 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { 2120 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®); 2121 save_regs[i] = (u8)reg; 2122 } 2123 2124 /* Shutdown codec */ 2125 regmap_multi_reg_write(cs42l42->regmap, 2126 cs42l42_shutdown_seq, 2127 ARRAY_SIZE(cs42l42_shutdown_seq)); 2128 2129 /* All interrupt sources are now disabled */ 2130 mutex_unlock(&cs42l42->irq_lock); 2131 2132 /* Wait for power-down complete */ 2133 msleep(CS42L42_PDN_DONE_TIME_MS); 2134 ret = regmap_read_poll_timeout(cs42l42->regmap, 2135 CS42L42_CODEC_STATUS, reg, 2136 (reg & CS42L42_PDN_DONE_MASK), 2137 CS42L42_PDN_DONE_POLL_US, 2138 CS42L42_PDN_DONE_TIMEOUT_US); 2139 if (ret) 2140 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret); 2141 2142 /* Discharge FILT+ */ 2143 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2, 2144 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); 2145 msleep(CS42L42_FILT_DISCHARGE_TIME_MS); 2146 2147 regcache_cache_only(cs42l42->regmap, true); 2148 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2149 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2150 2151 /* Restore register values to the regmap cache */ 2152 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) 2153 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]); 2154 2155 /* The cached address page register value is now stale */ 2156 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); 2157 2158 dev_dbg(dev, "System suspended\n"); 2159 2160 return 0; 2161 2162 } 2163 2164 static int __maybe_unused cs42l42_resume(struct device *dev) 2165 { 2166 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 2167 int ret; 2168 2169 /* 2170 * If jack was unplugged and re-plugged during suspend it could 2171 * have changed type but the tip-sense state hasn't changed. 2172 * Force a plugged state to be re-evaluated. 2173 */ 2174 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) 2175 cs42l42->plug_state = CS42L42_TS_TRANS; 2176 2177 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2178 if (ret != 0) { 2179 dev_err(dev, "Failed to enable supplies: %d\n", ret); 2180 return ret; 2181 } 2182 2183 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2184 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2185 2186 regcache_cache_only(cs42l42->regmap, false); 2187 regcache_mark_dirty(cs42l42->regmap); 2188 2189 mutex_lock(&cs42l42->irq_lock); 2190 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 2191 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 2192 regcache_sync(cs42l42->regmap); 2193 2194 cs42l42->suspended = false; 2195 mutex_unlock(&cs42l42->irq_lock); 2196 2197 dev_dbg(dev, "System resumed\n"); 2198 2199 return 0; 2200 } 2201 2202 static int cs42l42_i2c_probe(struct i2c_client *i2c_client) 2203 { 2204 struct cs42l42_private *cs42l42; 2205 int ret, i, devid; 2206 unsigned int reg; 2207 2208 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 2209 GFP_KERNEL); 2210 if (!cs42l42) 2211 return -ENOMEM; 2212 2213 cs42l42->dev = &i2c_client->dev; 2214 i2c_set_clientdata(i2c_client, cs42l42); 2215 mutex_init(&cs42l42->irq_lock); 2216 2217 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 2218 if (IS_ERR(cs42l42->regmap)) { 2219 ret = PTR_ERR(cs42l42->regmap); 2220 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 2221 return ret; 2222 } 2223 2224 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); 2225 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2226 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2227 2228 ret = devm_regulator_bulk_get(&i2c_client->dev, 2229 ARRAY_SIZE(cs42l42->supplies), 2230 cs42l42->supplies); 2231 if (ret != 0) { 2232 dev_err(&i2c_client->dev, 2233 "Failed to request supplies: %d\n", ret); 2234 return ret; 2235 } 2236 2237 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2238 cs42l42->supplies); 2239 if (ret != 0) { 2240 dev_err(&i2c_client->dev, 2241 "Failed to enable supplies: %d\n", ret); 2242 return ret; 2243 } 2244 2245 /* Reset the Device */ 2246 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 2247 "reset", GPIOD_OUT_LOW); 2248 if (IS_ERR(cs42l42->reset_gpio)) { 2249 ret = PTR_ERR(cs42l42->reset_gpio); 2250 goto err_disable_noreset; 2251 } 2252 2253 if (cs42l42->reset_gpio) { 2254 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 2255 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2256 } 2257 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2258 2259 /* Request IRQ if one was specified */ 2260 if (i2c_client->irq) { 2261 ret = request_threaded_irq(i2c_client->irq, 2262 NULL, cs42l42_irq_thread, 2263 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2264 "cs42l42", cs42l42); 2265 if (ret == -EPROBE_DEFER) { 2266 goto err_disable_noirq; 2267 } else if (ret != 0) { 2268 dev_err(&i2c_client->dev, 2269 "Failed to request IRQ: %d\n", ret); 2270 goto err_disable_noirq; 2271 } 2272 } 2273 2274 /* initialize codec */ 2275 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2276 if (devid < 0) { 2277 ret = devid; 2278 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 2279 goto err_disable; 2280 } 2281 2282 if (devid != CS42L42_CHIP_ID) { 2283 ret = -ENODEV; 2284 dev_err(&i2c_client->dev, 2285 "CS42L42 Device ID (%X). Expected %X\n", 2286 devid, CS42L42_CHIP_ID); 2287 goto err_disable; 2288 } 2289 2290 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2291 if (ret < 0) { 2292 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 2293 goto err_shutdown; 2294 } 2295 2296 dev_info(&i2c_client->dev, 2297 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 2298 2299 /* Power up the codec */ 2300 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2301 CS42L42_ASP_DAO_PDN_MASK | 2302 CS42L42_ASP_DAI_PDN_MASK | 2303 CS42L42_MIXER_PDN_MASK | 2304 CS42L42_EQ_PDN_MASK | 2305 CS42L42_HP_PDN_MASK | 2306 CS42L42_ADC_PDN_MASK | 2307 CS42L42_PDN_ALL_MASK, 2308 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2309 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2310 (1 << CS42L42_MIXER_PDN_SHIFT) | 2311 (1 << CS42L42_EQ_PDN_SHIFT) | 2312 (1 << CS42L42_HP_PDN_SHIFT) | 2313 (1 << CS42L42_ADC_PDN_SHIFT) | 2314 (0 << CS42L42_PDN_ALL_SHIFT)); 2315 2316 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 2317 if (ret != 0) 2318 goto err_shutdown; 2319 2320 /* Setup headset detection */ 2321 cs42l42_setup_hs_type_detect(cs42l42); 2322 2323 /* Mask/Unmask Interrupts */ 2324 cs42l42_set_interrupt_masks(cs42l42); 2325 2326 /* Register codec for machine driver */ 2327 ret = devm_snd_soc_register_component(&i2c_client->dev, 2328 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 2329 if (ret < 0) 2330 goto err_shutdown; 2331 2332 return 0; 2333 2334 err_shutdown: 2335 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2336 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2337 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2338 2339 err_disable: 2340 if (i2c_client->irq) 2341 free_irq(i2c_client->irq, cs42l42); 2342 2343 err_disable_noirq: 2344 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2345 err_disable_noreset: 2346 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2347 cs42l42->supplies); 2348 return ret; 2349 } 2350 2351 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 2352 { 2353 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 2354 2355 if (i2c_client->irq) 2356 free_irq(i2c_client->irq, cs42l42); 2357 2358 /* 2359 * The driver might not have control of reset and power supplies, 2360 * so ensure that the chip internals are powered down. 2361 */ 2362 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2363 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2364 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2365 2366 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2367 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2368 2369 return 0; 2370 } 2371 2372 static const struct dev_pm_ops cs42l42_pm_ops = { 2373 SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_resume) 2374 }; 2375 2376 #ifdef CONFIG_OF 2377 static const struct of_device_id cs42l42_of_match[] = { 2378 { .compatible = "cirrus,cs42l42", }, 2379 {} 2380 }; 2381 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2382 #endif 2383 2384 #ifdef CONFIG_ACPI 2385 static const struct acpi_device_id cs42l42_acpi_match[] = { 2386 {"10134242", 0,}, 2387 {} 2388 }; 2389 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2390 #endif 2391 2392 static const struct i2c_device_id cs42l42_id[] = { 2393 {"cs42l42", 0}, 2394 {} 2395 }; 2396 2397 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2398 2399 static struct i2c_driver cs42l42_i2c_driver = { 2400 .driver = { 2401 .name = "cs42l42", 2402 .pm = &cs42l42_pm_ops, 2403 .of_match_table = of_match_ptr(cs42l42_of_match), 2404 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2405 }, 2406 .id_table = cs42l42_id, 2407 .probe_new = cs42l42_i2c_probe, 2408 .remove = cs42l42_i2c_remove, 2409 }; 2410 2411 module_i2c_driver(cs42l42_i2c_driver); 2412 2413 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2414 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2415 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2416 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2417 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2418 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2419 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2420 MODULE_LICENSE("GPL"); 2421