1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/platform_device.h> 24 #include <linux/property.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/of_device.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <sound/initval.h> 34 #include <sound/tlv.h> 35 #include <dt-bindings/sound/cs42l42.h> 36 37 #include "cs42l42.h" 38 #include "cirrus_legacy.h" 39 40 static const struct reg_default cs42l42_reg_defaults[] = { 41 { CS42L42_FRZ_CTL, 0x00 }, 42 { CS42L42_SRC_CTL, 0x10 }, 43 { CS42L42_MCLK_CTL, 0x02 }, 44 { CS42L42_SFTRAMP_RATE, 0xA4 }, 45 { CS42L42_SLOW_START_ENABLE, 0x70 }, 46 { CS42L42_I2C_DEBOUNCE, 0x88 }, 47 { CS42L42_I2C_STRETCH, 0x03 }, 48 { CS42L42_I2C_TIMEOUT, 0xB7 }, 49 { CS42L42_PWR_CTL1, 0xFF }, 50 { CS42L42_PWR_CTL2, 0x84 }, 51 { CS42L42_PWR_CTL3, 0x20 }, 52 { CS42L42_RSENSE_CTL1, 0x40 }, 53 { CS42L42_RSENSE_CTL2, 0x00 }, 54 { CS42L42_OSC_SWITCH, 0x00 }, 55 { CS42L42_RSENSE_CTL3, 0x1B }, 56 { CS42L42_TSENSE_CTL, 0x1B }, 57 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 58 { CS42L42_HSDET_CTL1, 0x77 }, 59 { CS42L42_HSDET_CTL2, 0x00 }, 60 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 61 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 62 { CS42L42_MCLK_SRC_SEL, 0x00 }, 63 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 64 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 65 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 66 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 67 { CS42L42_FSYNC_P_UPPER, 0x00 }, 68 { CS42L42_ASP_CLK_CFG, 0x00 }, 69 { CS42L42_ASP_FRM_CFG, 0x10 }, 70 { CS42L42_FS_RATE_EN, 0x00 }, 71 { CS42L42_IN_ASRC_CLK, 0x00 }, 72 { CS42L42_OUT_ASRC_CLK, 0x00 }, 73 { CS42L42_PLL_DIV_CFG1, 0x00 }, 74 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 75 { CS42L42_MIXER_INT_MASK, 0x0F }, 76 { CS42L42_SRC_INT_MASK, 0x0F }, 77 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 78 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 79 { CS42L42_CODEC_INT_MASK, 0x03 }, 80 { CS42L42_SRCPL_INT_MASK, 0x7F }, 81 { CS42L42_VPMON_INT_MASK, 0x01 }, 82 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 83 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 84 { CS42L42_PLL_CTL1, 0x00 }, 85 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 86 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 87 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 88 { CS42L42_PLL_DIV_INT, 0x40 }, 89 { CS42L42_PLL_CTL3, 0x10 }, 90 { CS42L42_PLL_CAL_RATIO, 0x80 }, 91 { CS42L42_PLL_CTL4, 0x03 }, 92 { CS42L42_LOAD_DET_EN, 0x00 }, 93 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 94 { CS42L42_WAKE_CTL, 0xC0 }, 95 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 96 { CS42L42_TIPSENSE_CTL, 0x02 }, 97 { CS42L42_MISC_DET_CTL, 0x03 }, 98 { CS42L42_MIC_DET_CTL1, 0x1F }, 99 { CS42L42_MIC_DET_CTL2, 0x2F }, 100 { CS42L42_DET_INT1_MASK, 0xE0 }, 101 { CS42L42_DET_INT2_MASK, 0xFF }, 102 { CS42L42_HS_BIAS_CTL, 0xC2 }, 103 { CS42L42_ADC_CTL, 0x00 }, 104 { CS42L42_ADC_VOLUME, 0x00 }, 105 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 106 { CS42L42_DAC_CTL1, 0x00 }, 107 { CS42L42_DAC_CTL2, 0x02 }, 108 { CS42L42_HP_CTL, 0x0D }, 109 { CS42L42_CLASSH_CTL, 0x07 }, 110 { CS42L42_MIXER_CHA_VOL, 0x3F }, 111 { CS42L42_MIXER_ADC_VOL, 0x3F }, 112 { CS42L42_MIXER_CHB_VOL, 0x3F }, 113 { CS42L42_EQ_COEF_IN0, 0x00 }, 114 { CS42L42_EQ_COEF_IN1, 0x00 }, 115 { CS42L42_EQ_COEF_IN2, 0x00 }, 116 { CS42L42_EQ_COEF_IN3, 0x00 }, 117 { CS42L42_EQ_COEF_RW, 0x00 }, 118 { CS42L42_EQ_COEF_OUT0, 0x00 }, 119 { CS42L42_EQ_COEF_OUT1, 0x00 }, 120 { CS42L42_EQ_COEF_OUT2, 0x00 }, 121 { CS42L42_EQ_COEF_OUT3, 0x00 }, 122 { CS42L42_EQ_INIT_STAT, 0x00 }, 123 { CS42L42_EQ_START_FILT, 0x00 }, 124 { CS42L42_EQ_MUTE_CTL, 0x00 }, 125 { CS42L42_SP_RX_CH_SEL, 0x04 }, 126 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 127 { CS42L42_SP_RX_FS, 0x8C }, 128 { CS42l42_SPDIF_CH_SEL, 0x0E }, 129 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 130 { CS42L42_SP_TX_FS, 0xCC }, 131 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 132 { CS42L42_SRC_SDIN_FS, 0x40 }, 133 { CS42L42_SRC_SDOUT_FS, 0x40 }, 134 { CS42L42_SPDIF_CTL1, 0x01 }, 135 { CS42L42_SPDIF_CTL2, 0x00 }, 136 { CS42L42_SPDIF_CTL3, 0x00 }, 137 { CS42L42_SPDIF_CTL4, 0x42 }, 138 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 139 { CS42L42_ASP_TX_CH_EN, 0x00 }, 140 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 141 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 142 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 143 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 144 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 145 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 146 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 147 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 148 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 149 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 150 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 151 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 152 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 153 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 154 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 155 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 156 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 157 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 158 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 159 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 160 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 161 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 162 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 163 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 164 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 165 }; 166 167 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 168 { 169 switch (reg) { 170 case CS42L42_PAGE_REGISTER: 171 case CS42L42_DEVID_AB: 172 case CS42L42_DEVID_CD: 173 case CS42L42_DEVID_E: 174 case CS42L42_FABID: 175 case CS42L42_REVID: 176 case CS42L42_FRZ_CTL: 177 case CS42L42_SRC_CTL: 178 case CS42L42_MCLK_STATUS: 179 case CS42L42_MCLK_CTL: 180 case CS42L42_SFTRAMP_RATE: 181 case CS42L42_SLOW_START_ENABLE: 182 case CS42L42_I2C_DEBOUNCE: 183 case CS42L42_I2C_STRETCH: 184 case CS42L42_I2C_TIMEOUT: 185 case CS42L42_PWR_CTL1: 186 case CS42L42_PWR_CTL2: 187 case CS42L42_PWR_CTL3: 188 case CS42L42_RSENSE_CTL1: 189 case CS42L42_RSENSE_CTL2: 190 case CS42L42_OSC_SWITCH: 191 case CS42L42_OSC_SWITCH_STATUS: 192 case CS42L42_RSENSE_CTL3: 193 case CS42L42_TSENSE_CTL: 194 case CS42L42_TSRS_INT_DISABLE: 195 case CS42L42_TRSENSE_STATUS: 196 case CS42L42_HSDET_CTL1: 197 case CS42L42_HSDET_CTL2: 198 case CS42L42_HS_SWITCH_CTL: 199 case CS42L42_HS_DET_STATUS: 200 case CS42L42_HS_CLAMP_DISABLE: 201 case CS42L42_MCLK_SRC_SEL: 202 case CS42L42_SPDIF_CLK_CFG: 203 case CS42L42_FSYNC_PW_LOWER: 204 case CS42L42_FSYNC_PW_UPPER: 205 case CS42L42_FSYNC_P_LOWER: 206 case CS42L42_FSYNC_P_UPPER: 207 case CS42L42_ASP_CLK_CFG: 208 case CS42L42_ASP_FRM_CFG: 209 case CS42L42_FS_RATE_EN: 210 case CS42L42_IN_ASRC_CLK: 211 case CS42L42_OUT_ASRC_CLK: 212 case CS42L42_PLL_DIV_CFG1: 213 case CS42L42_ADC_OVFL_STATUS: 214 case CS42L42_MIXER_STATUS: 215 case CS42L42_SRC_STATUS: 216 case CS42L42_ASP_RX_STATUS: 217 case CS42L42_ASP_TX_STATUS: 218 case CS42L42_CODEC_STATUS: 219 case CS42L42_DET_INT_STATUS1: 220 case CS42L42_DET_INT_STATUS2: 221 case CS42L42_SRCPL_INT_STATUS: 222 case CS42L42_VPMON_STATUS: 223 case CS42L42_PLL_LOCK_STATUS: 224 case CS42L42_TSRS_PLUG_STATUS: 225 case CS42L42_ADC_OVFL_INT_MASK: 226 case CS42L42_MIXER_INT_MASK: 227 case CS42L42_SRC_INT_MASK: 228 case CS42L42_ASP_RX_INT_MASK: 229 case CS42L42_ASP_TX_INT_MASK: 230 case CS42L42_CODEC_INT_MASK: 231 case CS42L42_SRCPL_INT_MASK: 232 case CS42L42_VPMON_INT_MASK: 233 case CS42L42_PLL_LOCK_INT_MASK: 234 case CS42L42_TSRS_PLUG_INT_MASK: 235 case CS42L42_PLL_CTL1: 236 case CS42L42_PLL_DIV_FRAC0: 237 case CS42L42_PLL_DIV_FRAC1: 238 case CS42L42_PLL_DIV_FRAC2: 239 case CS42L42_PLL_DIV_INT: 240 case CS42L42_PLL_CTL3: 241 case CS42L42_PLL_CAL_RATIO: 242 case CS42L42_PLL_CTL4: 243 case CS42L42_LOAD_DET_RCSTAT: 244 case CS42L42_LOAD_DET_DONE: 245 case CS42L42_LOAD_DET_EN: 246 case CS42L42_HSBIAS_SC_AUTOCTL: 247 case CS42L42_WAKE_CTL: 248 case CS42L42_ADC_DISABLE_MUTE: 249 case CS42L42_TIPSENSE_CTL: 250 case CS42L42_MISC_DET_CTL: 251 case CS42L42_MIC_DET_CTL1: 252 case CS42L42_MIC_DET_CTL2: 253 case CS42L42_DET_STATUS1: 254 case CS42L42_DET_STATUS2: 255 case CS42L42_DET_INT1_MASK: 256 case CS42L42_DET_INT2_MASK: 257 case CS42L42_HS_BIAS_CTL: 258 case CS42L42_ADC_CTL: 259 case CS42L42_ADC_VOLUME: 260 case CS42L42_ADC_WNF_HPF_CTL: 261 case CS42L42_DAC_CTL1: 262 case CS42L42_DAC_CTL2: 263 case CS42L42_HP_CTL: 264 case CS42L42_CLASSH_CTL: 265 case CS42L42_MIXER_CHA_VOL: 266 case CS42L42_MIXER_ADC_VOL: 267 case CS42L42_MIXER_CHB_VOL: 268 case CS42L42_EQ_COEF_IN0: 269 case CS42L42_EQ_COEF_IN1: 270 case CS42L42_EQ_COEF_IN2: 271 case CS42L42_EQ_COEF_IN3: 272 case CS42L42_EQ_COEF_RW: 273 case CS42L42_EQ_COEF_OUT0: 274 case CS42L42_EQ_COEF_OUT1: 275 case CS42L42_EQ_COEF_OUT2: 276 case CS42L42_EQ_COEF_OUT3: 277 case CS42L42_EQ_INIT_STAT: 278 case CS42L42_EQ_START_FILT: 279 case CS42L42_EQ_MUTE_CTL: 280 case CS42L42_SP_RX_CH_SEL: 281 case CS42L42_SP_RX_ISOC_CTL: 282 case CS42L42_SP_RX_FS: 283 case CS42l42_SPDIF_CH_SEL: 284 case CS42L42_SP_TX_ISOC_CTL: 285 case CS42L42_SP_TX_FS: 286 case CS42L42_SPDIF_SW_CTL1: 287 case CS42L42_SRC_SDIN_FS: 288 case CS42L42_SRC_SDOUT_FS: 289 case CS42L42_SPDIF_CTL1: 290 case CS42L42_SPDIF_CTL2: 291 case CS42L42_SPDIF_CTL3: 292 case CS42L42_SPDIF_CTL4: 293 case CS42L42_ASP_TX_SZ_EN: 294 case CS42L42_ASP_TX_CH_EN: 295 case CS42L42_ASP_TX_CH_AP_RES: 296 case CS42L42_ASP_TX_CH1_BIT_MSB: 297 case CS42L42_ASP_TX_CH1_BIT_LSB: 298 case CS42L42_ASP_TX_HIZ_DLY_CFG: 299 case CS42L42_ASP_TX_CH2_BIT_MSB: 300 case CS42L42_ASP_TX_CH2_BIT_LSB: 301 case CS42L42_ASP_RX_DAI0_EN: 302 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 303 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 304 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 305 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 306 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 307 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 308 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 309 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 310 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 311 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 312 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 313 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 314 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 315 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 316 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 317 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 318 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 319 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 320 case CS42L42_SUB_REVID: 321 return true; 322 default: 323 return false; 324 } 325 } 326 327 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 328 { 329 switch (reg) { 330 case CS42L42_DEVID_AB: 331 case CS42L42_DEVID_CD: 332 case CS42L42_DEVID_E: 333 case CS42L42_MCLK_STATUS: 334 case CS42L42_OSC_SWITCH_STATUS: 335 case CS42L42_TRSENSE_STATUS: 336 case CS42L42_HS_DET_STATUS: 337 case CS42L42_ADC_OVFL_STATUS: 338 case CS42L42_MIXER_STATUS: 339 case CS42L42_SRC_STATUS: 340 case CS42L42_ASP_RX_STATUS: 341 case CS42L42_ASP_TX_STATUS: 342 case CS42L42_CODEC_STATUS: 343 case CS42L42_DET_INT_STATUS1: 344 case CS42L42_DET_INT_STATUS2: 345 case CS42L42_SRCPL_INT_STATUS: 346 case CS42L42_VPMON_STATUS: 347 case CS42L42_PLL_LOCK_STATUS: 348 case CS42L42_TSRS_PLUG_STATUS: 349 case CS42L42_LOAD_DET_RCSTAT: 350 case CS42L42_LOAD_DET_DONE: 351 case CS42L42_DET_STATUS1: 352 case CS42L42_DET_STATUS2: 353 return true; 354 default: 355 return false; 356 } 357 } 358 359 static const struct regmap_range_cfg cs42l42_page_range = { 360 .name = "Pages", 361 .range_min = 0, 362 .range_max = CS42L42_MAX_REGISTER, 363 .selector_reg = CS42L42_PAGE_REGISTER, 364 .selector_mask = 0xff, 365 .selector_shift = 0, 366 .window_start = 0, 367 .window_len = 256, 368 }; 369 370 static const struct regmap_config cs42l42_regmap = { 371 .reg_bits = 8, 372 .val_bits = 8, 373 374 .readable_reg = cs42l42_readable_register, 375 .volatile_reg = cs42l42_volatile_register, 376 377 .ranges = &cs42l42_page_range, 378 .num_ranges = 1, 379 380 .max_register = CS42L42_MAX_REGISTER, 381 .reg_defaults = cs42l42_reg_defaults, 382 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 383 .cache_type = REGCACHE_RBTREE, 384 385 .use_single_read = true, 386 .use_single_write = true, 387 }; 388 389 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); 390 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 391 392 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, 393 struct snd_ctl_elem_value *ucontrol) 394 { 395 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 396 u8 val; 397 398 /* all bits of SLOW_START_EN much change together */ 399 switch (ucontrol->value.integer.value[0]) { 400 case 0: 401 val = 0; 402 break; 403 case 1: 404 val = CS42L42_SLOW_START_EN_MASK; 405 break; 406 default: 407 return -EINVAL; 408 } 409 410 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, 411 CS42L42_SLOW_START_EN_MASK, val); 412 } 413 414 static const char * const cs42l42_hpf_freq_text[] = { 415 "1.86Hz", "120Hz", "235Hz", "466Hz" 416 }; 417 418 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 419 CS42L42_ADC_HPF_CF_SHIFT, 420 cs42l42_hpf_freq_text); 421 422 static const char * const cs42l42_wnf3_freq_text[] = { 423 "160Hz", "180Hz", "200Hz", "220Hz", 424 "240Hz", "260Hz", "280Hz", "300Hz" 425 }; 426 427 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 428 CS42L42_ADC_WNF_CF_SHIFT, 429 cs42l42_wnf3_freq_text); 430 431 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 432 /* ADC Volume and Filter Controls */ 433 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 434 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), 435 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 436 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 437 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 438 CS42L42_ADC_INV_SHIFT, true, false), 439 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 440 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 441 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv), 442 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 443 CS42L42_ADC_WNF_EN_SHIFT, true, false), 444 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 445 CS42L42_ADC_HPF_EN_SHIFT, true, false), 446 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 447 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 448 449 /* DAC Volume and Filter Controls */ 450 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 451 CS42L42_DACA_INV_SHIFT, true, false), 452 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 453 CS42L42_DACB_INV_SHIFT, true, false), 454 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 455 CS42L42_DAC_HPF_EN_SHIFT, true, false), 456 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 457 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 458 0x3f, 1, mixer_tlv), 459 460 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE, 461 CS42L42_SLOW_START_EN_SHIFT, true, false, 462 snd_soc_get_volsw, cs42l42_slow_start_put), 463 }; 464 465 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, 466 struct snd_kcontrol *kcontrol, int event) 467 { 468 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 469 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 470 471 switch (event) { 472 case SND_SOC_DAPM_PRE_PMU: 473 cs42l42->hp_adc_up_pending = true; 474 break; 475 case SND_SOC_DAPM_POST_PMU: 476 /* Only need one delay if HP and ADC are both powering-up */ 477 if (cs42l42->hp_adc_up_pending) { 478 usleep_range(CS42L42_HP_ADC_EN_TIME_US, 479 CS42L42_HP_ADC_EN_TIME_US + 1000); 480 cs42l42->hp_adc_up_pending = false; 481 } 482 break; 483 default: 484 break; 485 } 486 487 return 0; 488 } 489 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 491 /* Playback Path */ 492 SND_SOC_DAPM_OUTPUT("HP"), 493 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, 494 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 495 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 496 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0), 497 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0), 498 499 /* Playback Requirements */ 500 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 501 502 /* Capture Path */ 503 SND_SOC_DAPM_INPUT("HS"), 504 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, 505 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 506 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 507 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 508 509 /* Capture Requirements */ 510 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 511 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 512 513 /* Playback/Capture Requirements */ 514 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 515 }; 516 517 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 518 /* Playback Path */ 519 {"HP", NULL, "DAC"}, 520 {"DAC", NULL, "MIXER"}, 521 {"MIXER", NULL, "SDIN1"}, 522 {"MIXER", NULL, "SDIN2"}, 523 {"SDIN1", NULL, "Playback"}, 524 {"SDIN2", NULL, "Playback"}, 525 526 /* Playback Requirements */ 527 {"SDIN1", NULL, "ASP DAI0"}, 528 {"SDIN2", NULL, "ASP DAI0"}, 529 {"SDIN1", NULL, "SCLK"}, 530 {"SDIN2", NULL, "SCLK"}, 531 532 /* Capture Path */ 533 {"ADC", NULL, "HS"}, 534 { "SDOUT1", NULL, "ADC" }, 535 { "SDOUT2", NULL, "ADC" }, 536 { "Capture", NULL, "SDOUT1" }, 537 { "Capture", NULL, "SDOUT2" }, 538 539 /* Capture Requirements */ 540 { "SDOUT1", NULL, "ASP DAO0" }, 541 { "SDOUT2", NULL, "ASP DAO0" }, 542 { "SDOUT1", NULL, "SCLK" }, 543 { "SDOUT2", NULL, "SCLK" }, 544 { "SDOUT1", NULL, "ASP TX EN" }, 545 { "SDOUT2", NULL, "ASP TX EN" }, 546 }; 547 548 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) 549 { 550 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 551 552 cs42l42->jack = jk; 553 554 return 0; 555 } 556 557 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 558 .set_jack = cs42l42_set_jack, 559 .dapm_widgets = cs42l42_dapm_widgets, 560 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 561 .dapm_routes = cs42l42_audio_map, 562 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 563 .controls = cs42l42_snd_controls, 564 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 565 .idle_bias_on = 1, 566 .endianness = 1, 567 .non_legacy_dai_naming = 1, 568 }; 569 570 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ 571 static const struct reg_sequence cs42l42_to_sclk_seq[] = { 572 { 573 .reg = CS42L42_OSC_SWITCH, 574 .def = CS42L42_SCLK_PRESENT_MASK, 575 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 576 }, 577 }; 578 579 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ 580 static const struct reg_sequence cs42l42_to_osc_seq[] = { 581 { 582 .reg = CS42L42_OSC_SWITCH, 583 .def = 0, 584 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, 585 }, 586 }; 587 588 struct cs42l42_pll_params { 589 u32 sclk; 590 u8 mclk_src_sel; 591 u8 sclk_prediv; 592 u8 pll_div_int; 593 u32 pll_div_frac; 594 u8 pll_mode; 595 u8 pll_divout; 596 u32 mclk_int; 597 u8 pll_cal_ratio; 598 u8 n; 599 }; 600 601 /* 602 * Common PLL Settings for given SCLK 603 * Table 4-5 from the Datasheet 604 */ 605 static const struct cs42l42_pll_params pll_ratio_table[] = { 606 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, 607 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, 608 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, 609 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, 610 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 611 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 612 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 613 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, 614 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, 615 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 616 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 617 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, 618 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, 619 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, 620 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, 621 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, 622 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, 623 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} 624 }; 625 626 static int cs42l42_pll_config(struct snd_soc_component *component) 627 { 628 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 629 int i; 630 u32 clk; 631 u32 fsync; 632 633 if (!cs42l42->sclk) 634 clk = cs42l42->bclk; 635 else 636 clk = cs42l42->sclk; 637 638 /* Don't reconfigure if there is an audio stream running */ 639 if (cs42l42->stream_use) { 640 if (pll_ratio_table[cs42l42->pll_config].sclk == clk) 641 return 0; 642 else 643 return -EBUSY; 644 } 645 646 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 647 if (pll_ratio_table[i].sclk == clk) { 648 cs42l42->pll_config = i; 649 650 /* Configure the internal sample rate */ 651 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 652 CS42L42_INTERNAL_FS_MASK, 653 ((pll_ratio_table[i].mclk_int != 654 12000000) && 655 (pll_ratio_table[i].mclk_int != 656 24000000)) << 657 CS42L42_INTERNAL_FS_SHIFT); 658 659 /* Set up the LRCLK */ 660 fsync = clk / cs42l42->srate; 661 if (((fsync * cs42l42->srate) != clk) 662 || ((fsync % 2) != 0)) { 663 dev_err(component->dev, 664 "Unsupported sclk %d/sample rate %d\n", 665 clk, 666 cs42l42->srate); 667 return -EINVAL; 668 } 669 /* Set the LRCLK period */ 670 snd_soc_component_update_bits(component, 671 CS42L42_FSYNC_P_LOWER, 672 CS42L42_FSYNC_PERIOD_MASK, 673 CS42L42_FRAC0_VAL(fsync - 1) << 674 CS42L42_FSYNC_PERIOD_SHIFT); 675 snd_soc_component_update_bits(component, 676 CS42L42_FSYNC_P_UPPER, 677 CS42L42_FSYNC_PERIOD_MASK, 678 CS42L42_FRAC1_VAL(fsync - 1) << 679 CS42L42_FSYNC_PERIOD_SHIFT); 680 /* Set the LRCLK to 50% duty cycle */ 681 fsync = fsync / 2; 682 snd_soc_component_update_bits(component, 683 CS42L42_FSYNC_PW_LOWER, 684 CS42L42_FSYNC_PULSE_WIDTH_MASK, 685 CS42L42_FRAC0_VAL(fsync - 1) << 686 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 687 snd_soc_component_update_bits(component, 688 CS42L42_FSYNC_PW_UPPER, 689 CS42L42_FSYNC_PULSE_WIDTH_MASK, 690 CS42L42_FRAC1_VAL(fsync - 1) << 691 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 692 if (pll_ratio_table[i].mclk_src_sel == 0) { 693 /* Pass the clock straight through */ 694 snd_soc_component_update_bits(component, 695 CS42L42_PLL_CTL1, 696 CS42L42_PLL_START_MASK, 0); 697 } else { 698 /* Configure PLL per table 4-5 */ 699 snd_soc_component_update_bits(component, 700 CS42L42_PLL_DIV_CFG1, 701 CS42L42_SCLK_PREDIV_MASK, 702 pll_ratio_table[i].sclk_prediv 703 << CS42L42_SCLK_PREDIV_SHIFT); 704 snd_soc_component_update_bits(component, 705 CS42L42_PLL_DIV_INT, 706 CS42L42_PLL_DIV_INT_MASK, 707 pll_ratio_table[i].pll_div_int 708 << CS42L42_PLL_DIV_INT_SHIFT); 709 snd_soc_component_update_bits(component, 710 CS42L42_PLL_DIV_FRAC0, 711 CS42L42_PLL_DIV_FRAC_MASK, 712 CS42L42_FRAC0_VAL( 713 pll_ratio_table[i].pll_div_frac) 714 << CS42L42_PLL_DIV_FRAC_SHIFT); 715 snd_soc_component_update_bits(component, 716 CS42L42_PLL_DIV_FRAC1, 717 CS42L42_PLL_DIV_FRAC_MASK, 718 CS42L42_FRAC1_VAL( 719 pll_ratio_table[i].pll_div_frac) 720 << CS42L42_PLL_DIV_FRAC_SHIFT); 721 snd_soc_component_update_bits(component, 722 CS42L42_PLL_DIV_FRAC2, 723 CS42L42_PLL_DIV_FRAC_MASK, 724 CS42L42_FRAC2_VAL( 725 pll_ratio_table[i].pll_div_frac) 726 << CS42L42_PLL_DIV_FRAC_SHIFT); 727 snd_soc_component_update_bits(component, 728 CS42L42_PLL_CTL4, 729 CS42L42_PLL_MODE_MASK, 730 pll_ratio_table[i].pll_mode 731 << CS42L42_PLL_MODE_SHIFT); 732 snd_soc_component_update_bits(component, 733 CS42L42_PLL_CTL3, 734 CS42L42_PLL_DIVOUT_MASK, 735 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) 736 << CS42L42_PLL_DIVOUT_SHIFT); 737 snd_soc_component_update_bits(component, 738 CS42L42_PLL_CAL_RATIO, 739 CS42L42_PLL_CAL_RATIO_MASK, 740 pll_ratio_table[i].pll_cal_ratio 741 << CS42L42_PLL_CAL_RATIO_SHIFT); 742 } 743 return 0; 744 } 745 } 746 747 return -EINVAL; 748 } 749 750 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) 751 { 752 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 753 unsigned int fs; 754 755 /* Don't reconfigure if there is an audio stream running */ 756 if (cs42l42->stream_use) 757 return; 758 759 /* SRC MCLK must be as close as possible to 125 * sample rate */ 760 if (sample_rate <= 48000) 761 fs = CS42L42_CLK_IASRC_SEL_6; 762 else 763 fs = CS42L42_CLK_IASRC_SEL_12; 764 765 /* Set the sample rates (96k or lower) */ 766 snd_soc_component_update_bits(component, 767 CS42L42_FS_RATE_EN, 768 CS42L42_FS_EN_MASK, 769 (CS42L42_FS_EN_IASRC_96K | 770 CS42L42_FS_EN_OASRC_96K) << 771 CS42L42_FS_EN_SHIFT); 772 773 snd_soc_component_update_bits(component, 774 CS42L42_IN_ASRC_CLK, 775 CS42L42_CLK_IASRC_SEL_MASK, 776 fs << CS42L42_CLK_IASRC_SEL_SHIFT); 777 snd_soc_component_update_bits(component, 778 CS42L42_OUT_ASRC_CLK, 779 CS42L42_CLK_OASRC_SEL_MASK, 780 fs << CS42L42_CLK_OASRC_SEL_SHIFT); 781 } 782 783 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 784 { 785 struct snd_soc_component *component = codec_dai->component; 786 u32 asp_cfg_val = 0; 787 788 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 789 case SND_SOC_DAIFMT_CBS_CFM: 790 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 791 CS42L42_ASP_MODE_SHIFT; 792 break; 793 case SND_SOC_DAIFMT_CBS_CFS: 794 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 795 CS42L42_ASP_MODE_SHIFT; 796 break; 797 default: 798 return -EINVAL; 799 } 800 801 /* interface format */ 802 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 803 case SND_SOC_DAIFMT_I2S: 804 /* 805 * 5050 mode, frame starts on falling edge of LRCLK, 806 * frame delayed by 1.0 SCLKs 807 */ 808 snd_soc_component_update_bits(component, 809 CS42L42_ASP_FRM_CFG, 810 CS42L42_ASP_STP_MASK | 811 CS42L42_ASP_5050_MASK | 812 CS42L42_ASP_FSD_MASK, 813 CS42L42_ASP_5050_MASK | 814 (CS42L42_ASP_FSD_1_0 << 815 CS42L42_ASP_FSD_SHIFT)); 816 break; 817 default: 818 return -EINVAL; 819 } 820 821 /* Bitclock/frame inversion */ 822 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 823 case SND_SOC_DAIFMT_NB_NF: 824 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 825 break; 826 case SND_SOC_DAIFMT_NB_IF: 827 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 828 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 829 break; 830 case SND_SOC_DAIFMT_IB_NF: 831 break; 832 case SND_SOC_DAIFMT_IB_IF: 833 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 834 break; 835 } 836 837 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 838 CS42L42_ASP_SCPOL_MASK | 839 CS42L42_ASP_LCPOL_MASK, 840 asp_cfg_val); 841 842 return 0; 843 } 844 845 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 846 { 847 struct snd_soc_component *component = dai->component; 848 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 849 850 /* 851 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with 852 * a standard I2S frame. If the machine driver sets SCLK it must be 853 * legal. 854 */ 855 if (cs42l42->sclk) 856 return 0; 857 858 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ 859 return snd_pcm_hw_constraint_minmax(substream->runtime, 860 SNDRV_PCM_HW_PARAM_RATE, 861 44100, 96000); 862 } 863 864 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 865 struct snd_pcm_hw_params *params, 866 struct snd_soc_dai *dai) 867 { 868 struct snd_soc_component *component = dai->component; 869 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 870 unsigned int channels = params_channels(params); 871 unsigned int width = (params_width(params) / 8) - 1; 872 unsigned int val = 0; 873 int ret; 874 875 cs42l42->srate = params_rate(params); 876 cs42l42->bclk = snd_soc_params_to_bclk(params); 877 878 /* I2S frame always has 2 channels even for mono audio */ 879 if (channels == 1) 880 cs42l42->bclk *= 2; 881 882 /* 883 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being 884 * more than assumed (which would result in overclocking). 885 */ 886 if (params_width(params) == 24) 887 cs42l42->bclk = (cs42l42->bclk / 3) * 4; 888 889 switch (substream->stream) { 890 case SNDRV_PCM_STREAM_CAPTURE: 891 /* channel 2 on high LRCLK */ 892 val = CS42L42_ASP_TX_CH2_AP_MASK | 893 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | 894 (width << CS42L42_ASP_TX_CH1_RES_SHIFT); 895 896 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 897 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 898 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 899 break; 900 case SNDRV_PCM_STREAM_PLAYBACK: 901 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 902 /* channel 1 on low LRCLK */ 903 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 904 CS42L42_ASP_RX_CH_AP_MASK | 905 CS42L42_ASP_RX_CH_RES_MASK, val); 906 /* Channel 2 on high LRCLK */ 907 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 908 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 909 CS42L42_ASP_RX_CH_AP_MASK | 910 CS42L42_ASP_RX_CH_RES_MASK, val); 911 912 /* Channel B comes from the last active channel */ 913 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, 914 CS42L42_SP_RX_CHB_SEL_MASK, 915 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); 916 917 /* Both LRCLK slots must be enabled */ 918 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, 919 CS42L42_ASP_RX0_CH_EN_MASK, 920 BIT(CS42L42_ASP_RX0_CH1_SHIFT) | 921 BIT(CS42L42_ASP_RX0_CH2_SHIFT)); 922 break; 923 default: 924 break; 925 } 926 927 ret = cs42l42_pll_config(component); 928 if (ret) 929 return ret; 930 931 cs42l42_src_config(component, params_rate(params)); 932 933 return 0; 934 } 935 936 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 937 int clk_id, unsigned int freq, int dir) 938 { 939 struct snd_soc_component *component = dai->component; 940 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 941 int i; 942 943 if (freq == 0) { 944 cs42l42->sclk = 0; 945 return 0; 946 } 947 948 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 949 if (pll_ratio_table[i].sclk == freq) { 950 cs42l42->sclk = freq; 951 return 0; 952 } 953 } 954 955 dev_err(component->dev, "SCLK %u not supported\n", freq); 956 957 return -EINVAL; 958 } 959 960 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 961 { 962 struct snd_soc_component *component = dai->component; 963 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 964 unsigned int regval; 965 int ret; 966 967 if (mute) { 968 /* Mute the headphone */ 969 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 970 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 971 CS42L42_HP_ANA_AMUTE_MASK | 972 CS42L42_HP_ANA_BMUTE_MASK, 973 CS42L42_HP_ANA_AMUTE_MASK | 974 CS42L42_HP_ANA_BMUTE_MASK); 975 976 cs42l42->stream_use &= ~(1 << stream); 977 if (!cs42l42->stream_use) { 978 /* 979 * Switch to the internal oscillator. 980 * SCLK must remain running until after this clock switch. 981 * Without a source of clock the I2C bus doesn't work. 982 */ 983 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq, 984 ARRAY_SIZE(cs42l42_to_osc_seq)); 985 986 /* Must disconnect PLL before stopping it */ 987 snd_soc_component_update_bits(component, 988 CS42L42_MCLK_SRC_SEL, 989 CS42L42_MCLK_SRC_SEL_MASK, 990 0); 991 usleep_range(100, 200); 992 993 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 994 CS42L42_PLL_START_MASK, 0); 995 } 996 } else { 997 if (!cs42l42->stream_use) { 998 /* SCLK must be running before codec unmute */ 999 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { 1000 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 1001 CS42L42_PLL_START_MASK, 1); 1002 1003 if (pll_ratio_table[cs42l42->pll_config].n > 1) { 1004 usleep_range(CS42L42_PLL_DIVOUT_TIME_US, 1005 CS42L42_PLL_DIVOUT_TIME_US * 2); 1006 regval = pll_ratio_table[cs42l42->pll_config].pll_divout; 1007 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, 1008 CS42L42_PLL_DIVOUT_MASK, 1009 regval << 1010 CS42L42_PLL_DIVOUT_SHIFT); 1011 } 1012 1013 ret = regmap_read_poll_timeout(cs42l42->regmap, 1014 CS42L42_PLL_LOCK_STATUS, 1015 regval, 1016 (regval & 1), 1017 CS42L42_PLL_LOCK_POLL_US, 1018 CS42L42_PLL_LOCK_TIMEOUT_US); 1019 if (ret < 0) 1020 dev_warn(component->dev, "PLL failed to lock: %d\n", ret); 1021 1022 /* PLL must be running to drive glitchless switch logic */ 1023 snd_soc_component_update_bits(component, 1024 CS42L42_MCLK_SRC_SEL, 1025 CS42L42_MCLK_SRC_SEL_MASK, 1026 CS42L42_MCLK_SRC_SEL_MASK); 1027 } 1028 1029 /* Mark SCLK as present, turn off internal oscillator */ 1030 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, 1031 ARRAY_SIZE(cs42l42_to_sclk_seq)); 1032 } 1033 cs42l42->stream_use |= 1 << stream; 1034 1035 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1036 /* Un-mute the headphone */ 1037 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 1038 CS42L42_HP_ANA_AMUTE_MASK | 1039 CS42L42_HP_ANA_BMUTE_MASK, 1040 0); 1041 } 1042 } 1043 1044 return 0; 1045 } 1046 1047 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1048 SNDRV_PCM_FMTBIT_S24_LE |\ 1049 SNDRV_PCM_FMTBIT_S32_LE) 1050 1051 static const struct snd_soc_dai_ops cs42l42_ops = { 1052 .startup = cs42l42_dai_startup, 1053 .hw_params = cs42l42_pcm_hw_params, 1054 .set_fmt = cs42l42_set_dai_fmt, 1055 .set_sysclk = cs42l42_set_sysclk, 1056 .mute_stream = cs42l42_mute_stream, 1057 }; 1058 1059 static struct snd_soc_dai_driver cs42l42_dai = { 1060 .name = "cs42l42", 1061 .playback = { 1062 .stream_name = "Playback", 1063 .channels_min = 1, 1064 .channels_max = 2, 1065 .rates = SNDRV_PCM_RATE_8000_96000, 1066 .formats = CS42L42_FORMATS, 1067 }, 1068 .capture = { 1069 .stream_name = "Capture", 1070 .channels_min = 1, 1071 .channels_max = 2, 1072 .rates = SNDRV_PCM_RATE_8000_96000, 1073 .formats = CS42L42_FORMATS, 1074 }, 1075 .symmetric_rate = 1, 1076 .symmetric_sample_bits = 1, 1077 .ops = &cs42l42_ops, 1078 }; 1079 1080 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) 1081 { 1082 unsigned int hs_det_status; 1083 unsigned int hs_det_comp1; 1084 unsigned int hs_det_comp2; 1085 unsigned int hs_det_sw; 1086 1087 /* Set hs detect to manual, active mode */ 1088 regmap_update_bits(cs42l42->regmap, 1089 CS42L42_HSDET_CTL2, 1090 CS42L42_HSDET_CTRL_MASK | 1091 CS42L42_HSDET_SET_MASK | 1092 CS42L42_HSBIAS_REF_MASK | 1093 CS42L42_HSDET_AUTO_TIME_MASK, 1094 (1 << CS42L42_HSDET_CTRL_SHIFT) | 1095 (0 << CS42L42_HSDET_SET_SHIFT) | 1096 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1097 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1098 1099 /* Configure HS DET comparator reference levels. */ 1100 regmap_update_bits(cs42l42->regmap, 1101 CS42L42_HSDET_CTL1, 1102 CS42L42_HSDET_COMP1_LVL_MASK | 1103 CS42L42_HSDET_COMP2_LVL_MASK, 1104 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1105 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1106 1107 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 1108 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 1109 1110 msleep(100); 1111 1112 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1113 1114 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1115 CS42L42_HSDET_COMP1_OUT_SHIFT; 1116 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1117 CS42L42_HSDET_COMP2_OUT_SHIFT; 1118 1119 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 1120 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 1121 1122 msleep(100); 1123 1124 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1125 1126 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 1127 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 1128 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 1129 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 1130 1131 /* Use Comparator 1 with 1.25V Threshold. */ 1132 switch (hs_det_comp1) { 1133 case CS42L42_HSDET_COMP_TYPE1: 1134 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1135 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1136 break; 1137 case CS42L42_HSDET_COMP_TYPE2: 1138 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1139 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1140 break; 1141 default: 1142 /* Fallback to Comparator 2 with 1.75V Threshold. */ 1143 switch (hs_det_comp2) { 1144 case CS42L42_HSDET_COMP_TYPE1: 1145 cs42l42->hs_type = CS42L42_PLUG_CTIA; 1146 hs_det_sw = CS42L42_HSDET_SW_TYPE1; 1147 break; 1148 case CS42L42_HSDET_COMP_TYPE2: 1149 cs42l42->hs_type = CS42L42_PLUG_OMTP; 1150 hs_det_sw = CS42L42_HSDET_SW_TYPE2; 1151 break; 1152 case CS42L42_HSDET_COMP_TYPE3: 1153 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; 1154 hs_det_sw = CS42L42_HSDET_SW_TYPE3; 1155 break; 1156 default: 1157 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1158 hs_det_sw = CS42L42_HSDET_SW_TYPE4; 1159 break; 1160 } 1161 } 1162 1163 /* Set Switches */ 1164 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw); 1165 1166 /* Set HSDET mode to Manual—Disabled */ 1167 regmap_update_bits(cs42l42->regmap, 1168 CS42L42_HSDET_CTL2, 1169 CS42L42_HSDET_CTRL_MASK | 1170 CS42L42_HSDET_SET_MASK | 1171 CS42L42_HSBIAS_REF_MASK | 1172 CS42L42_HSDET_AUTO_TIME_MASK, 1173 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1174 (0 << CS42L42_HSDET_SET_SHIFT) | 1175 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1176 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1177 1178 /* Configure HS DET comparator reference levels. */ 1179 regmap_update_bits(cs42l42->regmap, 1180 CS42L42_HSDET_CTL1, 1181 CS42L42_HSDET_COMP1_LVL_MASK | 1182 CS42L42_HSDET_COMP2_LVL_MASK, 1183 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 1184 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 1185 } 1186 1187 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 1188 { 1189 unsigned int hs_det_status; 1190 unsigned int int_status; 1191 1192 /* Read and save the hs detection result */ 1193 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 1194 1195 /* Mask the auto detect interrupt */ 1196 regmap_update_bits(cs42l42->regmap, 1197 CS42L42_CODEC_INT_MASK, 1198 CS42L42_PDN_DONE_MASK | 1199 CS42L42_HSDET_AUTO_DONE_MASK, 1200 (1 << CS42L42_PDN_DONE_SHIFT) | 1201 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1202 1203 1204 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 1205 CS42L42_HSDET_TYPE_SHIFT; 1206 1207 /* Set hs detect to automatic, disabled mode */ 1208 regmap_update_bits(cs42l42->regmap, 1209 CS42L42_HSDET_CTL2, 1210 CS42L42_HSDET_CTRL_MASK | 1211 CS42L42_HSDET_SET_MASK | 1212 CS42L42_HSBIAS_REF_MASK | 1213 CS42L42_HSDET_AUTO_TIME_MASK, 1214 (2 << CS42L42_HSDET_CTRL_SHIFT) | 1215 (2 << CS42L42_HSDET_SET_SHIFT) | 1216 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1217 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1218 1219 /* Run Manual detection if auto detect has not found a headset. 1220 * We Re-Run with Manual Detection if the original detection was invalid or headphones, 1221 * to ensure that a headset mic is detected in all cases. 1222 */ 1223 if (cs42l42->hs_type == CS42L42_PLUG_INVALID || 1224 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { 1225 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n"); 1226 cs42l42_manual_hs_type_detect(cs42l42); 1227 } 1228 1229 /* Set up button detection */ 1230 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 1231 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 1232 /* Set auto HS bias settings to default */ 1233 regmap_update_bits(cs42l42->regmap, 1234 CS42L42_HSBIAS_SC_AUTOCTL, 1235 CS42L42_HSBIAS_SENSE_EN_MASK | 1236 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1237 CS42L42_TIP_SENSE_EN_MASK | 1238 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1239 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1240 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1241 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1242 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1243 1244 /* Set up hs detect level sensitivity */ 1245 regmap_update_bits(cs42l42->regmap, 1246 CS42L42_MIC_DET_CTL1, 1247 CS42L42_LATCH_TO_VP_MASK | 1248 CS42L42_EVENT_STAT_SEL_MASK | 1249 CS42L42_HS_DET_LEVEL_MASK, 1250 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1251 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1252 (cs42l42->bias_thresholds[0] << 1253 CS42L42_HS_DET_LEVEL_SHIFT)); 1254 1255 /* Set auto HS bias settings to default */ 1256 regmap_update_bits(cs42l42->regmap, 1257 CS42L42_HSBIAS_SC_AUTOCTL, 1258 CS42L42_HSBIAS_SENSE_EN_MASK | 1259 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1260 CS42L42_TIP_SENSE_EN_MASK | 1261 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1262 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1263 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1264 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1265 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1266 1267 /* Turn on level detect circuitry */ 1268 regmap_update_bits(cs42l42->regmap, 1269 CS42L42_MISC_DET_CTL, 1270 CS42L42_HSBIAS_CTL_MASK | 1271 CS42L42_PDN_MIC_LVL_DET_MASK, 1272 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1273 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1274 1275 msleep(cs42l42->btn_det_init_dbnce); 1276 1277 /* Clear any button interrupts before unmasking them */ 1278 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1279 &int_status); 1280 1281 /* Unmask button detect interrupts */ 1282 regmap_update_bits(cs42l42->regmap, 1283 CS42L42_DET_INT2_MASK, 1284 CS42L42_M_DETECT_TF_MASK | 1285 CS42L42_M_DETECT_FT_MASK | 1286 CS42L42_M_HSBIAS_HIZ_MASK | 1287 CS42L42_M_SHORT_RLS_MASK | 1288 CS42L42_M_SHORT_DET_MASK, 1289 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1290 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1291 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1292 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1293 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1294 } else { 1295 /* Make sure button detect and HS bias circuits are off */ 1296 regmap_update_bits(cs42l42->regmap, 1297 CS42L42_MISC_DET_CTL, 1298 CS42L42_HSBIAS_CTL_MASK | 1299 CS42L42_PDN_MIC_LVL_DET_MASK, 1300 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1301 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1302 } 1303 1304 regmap_update_bits(cs42l42->regmap, 1305 CS42L42_DAC_CTL2, 1306 CS42L42_HPOUT_PULLDOWN_MASK | 1307 CS42L42_HPOUT_LOAD_MASK | 1308 CS42L42_HPOUT_CLAMP_MASK | 1309 CS42L42_DAC_HPF_EN_MASK | 1310 CS42L42_DAC_MON_EN_MASK, 1311 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1312 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1313 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1314 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1315 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1316 1317 /* Unmask tip sense interrupts */ 1318 regmap_update_bits(cs42l42->regmap, 1319 CS42L42_TSRS_PLUG_INT_MASK, 1320 CS42L42_TS_PLUG_MASK | 1321 CS42L42_TS_UNPLUG_MASK, 1322 (0 << CS42L42_TS_PLUG_SHIFT) | 1323 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1324 } 1325 1326 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1327 { 1328 /* Mask tip sense interrupts */ 1329 regmap_update_bits(cs42l42->regmap, 1330 CS42L42_TSRS_PLUG_INT_MASK, 1331 CS42L42_TS_PLUG_MASK | 1332 CS42L42_TS_UNPLUG_MASK, 1333 (1 << CS42L42_TS_PLUG_SHIFT) | 1334 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1335 1336 /* Make sure button detect and HS bias circuits are off */ 1337 regmap_update_bits(cs42l42->regmap, 1338 CS42L42_MISC_DET_CTL, 1339 CS42L42_HSBIAS_CTL_MASK | 1340 CS42L42_PDN_MIC_LVL_DET_MASK, 1341 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1342 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1343 1344 /* Set auto HS bias settings to default */ 1345 regmap_update_bits(cs42l42->regmap, 1346 CS42L42_HSBIAS_SC_AUTOCTL, 1347 CS42L42_HSBIAS_SENSE_EN_MASK | 1348 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1349 CS42L42_TIP_SENSE_EN_MASK | 1350 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1351 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1352 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1353 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1354 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1355 1356 /* Set hs detect to manual, disabled mode */ 1357 regmap_update_bits(cs42l42->regmap, 1358 CS42L42_HSDET_CTL2, 1359 CS42L42_HSDET_CTRL_MASK | 1360 CS42L42_HSDET_SET_MASK | 1361 CS42L42_HSBIAS_REF_MASK | 1362 CS42L42_HSDET_AUTO_TIME_MASK, 1363 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1364 (2 << CS42L42_HSDET_SET_SHIFT) | 1365 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1366 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1367 1368 regmap_update_bits(cs42l42->regmap, 1369 CS42L42_DAC_CTL2, 1370 CS42L42_HPOUT_PULLDOWN_MASK | 1371 CS42L42_HPOUT_LOAD_MASK | 1372 CS42L42_HPOUT_CLAMP_MASK | 1373 CS42L42_DAC_HPF_EN_MASK | 1374 CS42L42_DAC_MON_EN_MASK, 1375 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1376 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1377 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1378 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1379 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1380 1381 /* Power up HS bias to 2.7V */ 1382 regmap_update_bits(cs42l42->regmap, 1383 CS42L42_MISC_DET_CTL, 1384 CS42L42_HSBIAS_CTL_MASK | 1385 CS42L42_PDN_MIC_LVL_DET_MASK, 1386 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1387 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1388 1389 /* Wait for HS bias to ramp up */ 1390 msleep(cs42l42->hs_bias_ramp_time); 1391 1392 /* Unmask auto detect interrupt */ 1393 regmap_update_bits(cs42l42->regmap, 1394 CS42L42_CODEC_INT_MASK, 1395 CS42L42_PDN_DONE_MASK | 1396 CS42L42_HSDET_AUTO_DONE_MASK, 1397 (1 << CS42L42_PDN_DONE_SHIFT) | 1398 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1399 1400 /* Set hs detect to automatic, enabled mode */ 1401 regmap_update_bits(cs42l42->regmap, 1402 CS42L42_HSDET_CTL2, 1403 CS42L42_HSDET_CTRL_MASK | 1404 CS42L42_HSDET_SET_MASK | 1405 CS42L42_HSBIAS_REF_MASK | 1406 CS42L42_HSDET_AUTO_TIME_MASK, 1407 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1408 (2 << CS42L42_HSDET_SET_SHIFT) | 1409 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1410 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1411 } 1412 1413 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1414 { 1415 /* Mask button detect interrupts */ 1416 regmap_update_bits(cs42l42->regmap, 1417 CS42L42_DET_INT2_MASK, 1418 CS42L42_M_DETECT_TF_MASK | 1419 CS42L42_M_DETECT_FT_MASK | 1420 CS42L42_M_HSBIAS_HIZ_MASK | 1421 CS42L42_M_SHORT_RLS_MASK | 1422 CS42L42_M_SHORT_DET_MASK, 1423 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1424 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1425 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1426 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1427 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1428 1429 /* Ground HS bias */ 1430 regmap_update_bits(cs42l42->regmap, 1431 CS42L42_MISC_DET_CTL, 1432 CS42L42_HSBIAS_CTL_MASK | 1433 CS42L42_PDN_MIC_LVL_DET_MASK, 1434 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1435 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1436 1437 /* Set auto HS bias settings to default */ 1438 regmap_update_bits(cs42l42->regmap, 1439 CS42L42_HSBIAS_SC_AUTOCTL, 1440 CS42L42_HSBIAS_SENSE_EN_MASK | 1441 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1442 CS42L42_TIP_SENSE_EN_MASK | 1443 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1444 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1445 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1446 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1447 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1448 1449 /* Set hs detect to manual, disabled mode */ 1450 regmap_update_bits(cs42l42->regmap, 1451 CS42L42_HSDET_CTL2, 1452 CS42L42_HSDET_CTRL_MASK | 1453 CS42L42_HSDET_SET_MASK | 1454 CS42L42_HSBIAS_REF_MASK | 1455 CS42L42_HSDET_AUTO_TIME_MASK, 1456 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1457 (2 << CS42L42_HSDET_SET_SHIFT) | 1458 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1459 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1460 } 1461 1462 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1463 { 1464 int bias_level; 1465 unsigned int detect_status; 1466 1467 /* Mask button detect interrupts */ 1468 regmap_update_bits(cs42l42->regmap, 1469 CS42L42_DET_INT2_MASK, 1470 CS42L42_M_DETECT_TF_MASK | 1471 CS42L42_M_DETECT_FT_MASK | 1472 CS42L42_M_HSBIAS_HIZ_MASK | 1473 CS42L42_M_SHORT_RLS_MASK | 1474 CS42L42_M_SHORT_DET_MASK, 1475 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1476 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1477 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1478 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1479 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1480 1481 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1482 cs42l42->btn_det_event_dbnce * 2000); 1483 1484 /* Test all 4 level detect biases */ 1485 bias_level = 1; 1486 do { 1487 /* Adjust button detect level sensitivity */ 1488 regmap_update_bits(cs42l42->regmap, 1489 CS42L42_MIC_DET_CTL1, 1490 CS42L42_LATCH_TO_VP_MASK | 1491 CS42L42_EVENT_STAT_SEL_MASK | 1492 CS42L42_HS_DET_LEVEL_MASK, 1493 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1494 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1495 (cs42l42->bias_thresholds[bias_level] << 1496 CS42L42_HS_DET_LEVEL_SHIFT)); 1497 1498 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1499 &detect_status); 1500 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1501 (++bias_level < CS42L42_NUM_BIASES)); 1502 1503 switch (bias_level) { 1504 case 1: /* Function C button press */ 1505 bias_level = SND_JACK_BTN_2; 1506 dev_dbg(cs42l42->dev, "Function C button press\n"); 1507 break; 1508 case 2: /* Function B button press */ 1509 bias_level = SND_JACK_BTN_1; 1510 dev_dbg(cs42l42->dev, "Function B button press\n"); 1511 break; 1512 case 3: /* Function D button press */ 1513 bias_level = SND_JACK_BTN_3; 1514 dev_dbg(cs42l42->dev, "Function D button press\n"); 1515 break; 1516 case 4: /* Function A button press */ 1517 bias_level = SND_JACK_BTN_0; 1518 dev_dbg(cs42l42->dev, "Function A button press\n"); 1519 break; 1520 default: 1521 bias_level = 0; 1522 break; 1523 } 1524 1525 /* Set button detect level sensitivity back to default */ 1526 regmap_update_bits(cs42l42->regmap, 1527 CS42L42_MIC_DET_CTL1, 1528 CS42L42_LATCH_TO_VP_MASK | 1529 CS42L42_EVENT_STAT_SEL_MASK | 1530 CS42L42_HS_DET_LEVEL_MASK, 1531 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1532 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1533 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1534 1535 /* Clear any button interrupts before unmasking them */ 1536 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1537 &detect_status); 1538 1539 /* Unmask button detect interrupts */ 1540 regmap_update_bits(cs42l42->regmap, 1541 CS42L42_DET_INT2_MASK, 1542 CS42L42_M_DETECT_TF_MASK | 1543 CS42L42_M_DETECT_FT_MASK | 1544 CS42L42_M_HSBIAS_HIZ_MASK | 1545 CS42L42_M_SHORT_RLS_MASK | 1546 CS42L42_M_SHORT_DET_MASK, 1547 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1548 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1549 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1550 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1551 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1552 1553 return bias_level; 1554 } 1555 1556 struct cs42l42_irq_params { 1557 u16 status_addr; 1558 u16 mask_addr; 1559 u8 mask; 1560 }; 1561 1562 static const struct cs42l42_irq_params irq_params_table[] = { 1563 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1564 CS42L42_ADC_OVFL_VAL_MASK}, 1565 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1566 CS42L42_MIXER_VAL_MASK}, 1567 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1568 CS42L42_SRC_VAL_MASK}, 1569 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1570 CS42L42_ASP_RX_VAL_MASK}, 1571 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1572 CS42L42_ASP_TX_VAL_MASK}, 1573 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1574 CS42L42_CODEC_VAL_MASK}, 1575 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1576 CS42L42_DET_INT_VAL1_MASK}, 1577 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1578 CS42L42_DET_INT_VAL2_MASK}, 1579 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1580 CS42L42_SRCPL_VAL_MASK}, 1581 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1582 CS42L42_VPMON_VAL_MASK}, 1583 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1584 CS42L42_PLL_LOCK_VAL_MASK}, 1585 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1586 CS42L42_TSRS_PLUG_VAL_MASK} 1587 }; 1588 1589 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1590 { 1591 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1592 unsigned int stickies[12]; 1593 unsigned int masks[12]; 1594 unsigned int current_plug_status; 1595 unsigned int current_button_status; 1596 unsigned int i; 1597 int report = 0; 1598 1599 1600 /* Read sticky registers to clear interurpt */ 1601 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1602 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1603 &(stickies[i])); 1604 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1605 &(masks[i])); 1606 stickies[i] = stickies[i] & (~masks[i]) & 1607 irq_params_table[i].mask; 1608 } 1609 1610 /* Read tip sense status before handling type detect */ 1611 current_plug_status = (stickies[11] & 1612 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1613 CS42L42_TS_PLUG_SHIFT; 1614 1615 /* Read button sense status */ 1616 current_button_status = stickies[7] & 1617 (CS42L42_M_DETECT_TF_MASK | 1618 CS42L42_M_DETECT_FT_MASK | 1619 CS42L42_M_HSBIAS_HIZ_MASK); 1620 1621 /* Check auto-detect status */ 1622 if ((~masks[5]) & irq_params_table[5].mask) { 1623 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1624 cs42l42_process_hs_type_detect(cs42l42); 1625 switch (cs42l42->hs_type) { 1626 case CS42L42_PLUG_CTIA: 1627 case CS42L42_PLUG_OMTP: 1628 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET, 1629 SND_JACK_HEADSET); 1630 break; 1631 case CS42L42_PLUG_HEADPHONE: 1632 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE, 1633 SND_JACK_HEADPHONE); 1634 break; 1635 default: 1636 break; 1637 } 1638 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type); 1639 } 1640 } 1641 1642 /* Check tip sense status */ 1643 if ((~masks[11]) & irq_params_table[11].mask) { 1644 switch (current_plug_status) { 1645 case CS42L42_TS_PLUG: 1646 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1647 cs42l42->plug_state = CS42L42_TS_PLUG; 1648 cs42l42_init_hs_type_detect(cs42l42); 1649 } 1650 break; 1651 1652 case CS42L42_TS_UNPLUG: 1653 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1654 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1655 cs42l42_cancel_hs_type_detect(cs42l42); 1656 1657 snd_soc_jack_report(cs42l42->jack, 0, 1658 SND_JACK_HEADSET | 1659 SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1660 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1661 1662 dev_dbg(cs42l42->dev, "Unplug event\n"); 1663 } 1664 break; 1665 1666 default: 1667 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1668 cs42l42->plug_state = CS42L42_TS_TRANS; 1669 } 1670 } 1671 1672 /* Check button detect status */ 1673 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { 1674 if (!(current_button_status & 1675 CS42L42_M_HSBIAS_HIZ_MASK)) { 1676 1677 if (current_button_status & CS42L42_M_DETECT_TF_MASK) { 1678 dev_dbg(cs42l42->dev, "Button released\n"); 1679 report = 0; 1680 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { 1681 report = cs42l42_handle_button_press(cs42l42); 1682 1683 } 1684 snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | 1685 SND_JACK_BTN_2 | SND_JACK_BTN_3); 1686 } 1687 } 1688 1689 return IRQ_HANDLED; 1690 } 1691 1692 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1693 { 1694 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1695 CS42L42_ADC_OVFL_MASK, 1696 (1 << CS42L42_ADC_OVFL_SHIFT)); 1697 1698 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1699 CS42L42_MIX_CHB_OVFL_MASK | 1700 CS42L42_MIX_CHA_OVFL_MASK | 1701 CS42L42_EQ_OVFL_MASK | 1702 CS42L42_EQ_BIQUAD_OVFL_MASK, 1703 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1704 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1705 (1 << CS42L42_EQ_OVFL_SHIFT) | 1706 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1707 1708 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1709 CS42L42_SRC_ILK_MASK | 1710 CS42L42_SRC_OLK_MASK | 1711 CS42L42_SRC_IUNLK_MASK | 1712 CS42L42_SRC_OUNLK_MASK, 1713 (1 << CS42L42_SRC_ILK_SHIFT) | 1714 (1 << CS42L42_SRC_OLK_SHIFT) | 1715 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1716 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1717 1718 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1719 CS42L42_ASPRX_NOLRCK_MASK | 1720 CS42L42_ASPRX_EARLY_MASK | 1721 CS42L42_ASPRX_LATE_MASK | 1722 CS42L42_ASPRX_ERROR_MASK | 1723 CS42L42_ASPRX_OVLD_MASK, 1724 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1725 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1726 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1727 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1728 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1729 1730 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1731 CS42L42_ASPTX_NOLRCK_MASK | 1732 CS42L42_ASPTX_EARLY_MASK | 1733 CS42L42_ASPTX_LATE_MASK | 1734 CS42L42_ASPTX_SMERROR_MASK, 1735 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1736 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1737 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1738 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1739 1740 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1741 CS42L42_PDN_DONE_MASK | 1742 CS42L42_HSDET_AUTO_DONE_MASK, 1743 (1 << CS42L42_PDN_DONE_SHIFT) | 1744 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1745 1746 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1747 CS42L42_SRCPL_ADC_LK_MASK | 1748 CS42L42_SRCPL_DAC_LK_MASK | 1749 CS42L42_SRCPL_ADC_UNLK_MASK | 1750 CS42L42_SRCPL_DAC_UNLK_MASK, 1751 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1752 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1753 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1754 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1755 1756 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1757 CS42L42_TIP_SENSE_UNPLUG_MASK | 1758 CS42L42_TIP_SENSE_PLUG_MASK | 1759 CS42L42_HSBIAS_SENSE_MASK, 1760 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1761 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1762 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1763 1764 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1765 CS42L42_M_DETECT_TF_MASK | 1766 CS42L42_M_DETECT_FT_MASK | 1767 CS42L42_M_HSBIAS_HIZ_MASK | 1768 CS42L42_M_SHORT_RLS_MASK | 1769 CS42L42_M_SHORT_DET_MASK, 1770 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1771 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1772 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1773 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1774 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1775 1776 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1777 CS42L42_VPMON_MASK, 1778 (1 << CS42L42_VPMON_SHIFT)); 1779 1780 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1781 CS42L42_PLL_LOCK_MASK, 1782 (1 << CS42L42_PLL_LOCK_SHIFT)); 1783 1784 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1785 CS42L42_RS_PLUG_MASK | 1786 CS42L42_RS_UNPLUG_MASK | 1787 CS42L42_TS_PLUG_MASK | 1788 CS42L42_TS_UNPLUG_MASK, 1789 (1 << CS42L42_RS_PLUG_SHIFT) | 1790 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1791 (0 << CS42L42_TS_PLUG_SHIFT) | 1792 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1793 } 1794 1795 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1796 { 1797 unsigned int reg; 1798 1799 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1800 1801 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL, 1802 CS42L42_DETECT_MODE_MASK, 0); 1803 1804 /* Latch analog controls to VP power domain */ 1805 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1806 CS42L42_LATCH_TO_VP_MASK | 1807 CS42L42_EVENT_STAT_SEL_MASK | 1808 CS42L42_HS_DET_LEVEL_MASK, 1809 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1810 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1811 (cs42l42->bias_thresholds[0] << 1812 CS42L42_HS_DET_LEVEL_SHIFT)); 1813 1814 /* Remove ground noise-suppression clamps */ 1815 regmap_update_bits(cs42l42->regmap, 1816 CS42L42_HS_CLAMP_DISABLE, 1817 CS42L42_HS_CLAMP_DISABLE_MASK, 1818 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1819 1820 /* Enable the tip sense circuit */ 1821 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1822 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); 1823 1824 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1825 CS42L42_TIP_SENSE_CTRL_MASK | 1826 CS42L42_TIP_SENSE_INV_MASK | 1827 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1828 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1829 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | 1830 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1831 1832 /* Save the initial status of the tip sense */ 1833 regmap_read(cs42l42->regmap, 1834 CS42L42_TSRS_PLUG_STATUS, 1835 ®); 1836 cs42l42->plug_state = (((char) reg) & 1837 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1838 CS42L42_TS_PLUG_SHIFT; 1839 } 1840 1841 static const unsigned int threshold_defaults[] = { 1842 CS42L42_HS_DET_LEVEL_15, 1843 CS42L42_HS_DET_LEVEL_8, 1844 CS42L42_HS_DET_LEVEL_4, 1845 CS42L42_HS_DET_LEVEL_1 1846 }; 1847 1848 static int cs42l42_handle_device_data(struct device *dev, 1849 struct cs42l42_private *cs42l42) 1850 { 1851 unsigned int val; 1852 u32 thresholds[CS42L42_NUM_BIASES]; 1853 int ret; 1854 int i; 1855 1856 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val); 1857 if (!ret) { 1858 switch (val) { 1859 case CS42L42_TS_INV_EN: 1860 case CS42L42_TS_INV_DIS: 1861 cs42l42->ts_inv = val; 1862 break; 1863 default: 1864 dev_err(dev, 1865 "Wrong cirrus,ts-inv DT value %d\n", 1866 val); 1867 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1868 } 1869 } else { 1870 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1871 } 1872 1873 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val); 1874 if (!ret) { 1875 switch (val) { 1876 case CS42L42_TS_DBNCE_0: 1877 case CS42L42_TS_DBNCE_125: 1878 case CS42L42_TS_DBNCE_250: 1879 case CS42L42_TS_DBNCE_500: 1880 case CS42L42_TS_DBNCE_750: 1881 case CS42L42_TS_DBNCE_1000: 1882 case CS42L42_TS_DBNCE_1250: 1883 case CS42L42_TS_DBNCE_1500: 1884 cs42l42->ts_dbnc_rise = val; 1885 break; 1886 default: 1887 dev_err(dev, 1888 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1889 val); 1890 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1891 } 1892 } else { 1893 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1894 } 1895 1896 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1897 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1898 (cs42l42->ts_dbnc_rise << 1899 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1900 1901 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val); 1902 if (!ret) { 1903 switch (val) { 1904 case CS42L42_TS_DBNCE_0: 1905 case CS42L42_TS_DBNCE_125: 1906 case CS42L42_TS_DBNCE_250: 1907 case CS42L42_TS_DBNCE_500: 1908 case CS42L42_TS_DBNCE_750: 1909 case CS42L42_TS_DBNCE_1000: 1910 case CS42L42_TS_DBNCE_1250: 1911 case CS42L42_TS_DBNCE_1500: 1912 cs42l42->ts_dbnc_fall = val; 1913 break; 1914 default: 1915 dev_err(dev, 1916 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1917 val); 1918 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1919 } 1920 } else { 1921 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1922 } 1923 1924 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1925 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1926 (cs42l42->ts_dbnc_fall << 1927 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1928 1929 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val); 1930 if (!ret) { 1931 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1932 cs42l42->btn_det_init_dbnce = val; 1933 else { 1934 dev_err(dev, 1935 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1936 val); 1937 cs42l42->btn_det_init_dbnce = 1938 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1939 } 1940 } else { 1941 cs42l42->btn_det_init_dbnce = 1942 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1943 } 1944 1945 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val); 1946 if (!ret) { 1947 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1948 cs42l42->btn_det_event_dbnce = val; 1949 else { 1950 dev_err(dev, 1951 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1952 cs42l42->btn_det_event_dbnce = 1953 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1954 } 1955 } else { 1956 cs42l42->btn_det_event_dbnce = 1957 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1958 } 1959 1960 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls", 1961 thresholds, ARRAY_SIZE(thresholds)); 1962 if (!ret) { 1963 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1964 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1965 cs42l42->bias_thresholds[i] = thresholds[i]; 1966 else { 1967 dev_err(dev, 1968 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1969 thresholds[i]); 1970 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1971 } 1972 } 1973 } else { 1974 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1975 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1976 } 1977 1978 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val); 1979 if (!ret) { 1980 switch (val) { 1981 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1982 cs42l42->hs_bias_ramp_rate = val; 1983 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1984 break; 1985 case CS42L42_HSBIAS_RAMP_FAST: 1986 cs42l42->hs_bias_ramp_rate = val; 1987 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1988 break; 1989 case CS42L42_HSBIAS_RAMP_SLOW: 1990 cs42l42->hs_bias_ramp_rate = val; 1991 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1992 break; 1993 case CS42L42_HSBIAS_RAMP_SLOWEST: 1994 cs42l42->hs_bias_ramp_rate = val; 1995 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1996 break; 1997 default: 1998 dev_err(dev, 1999 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 2000 val); 2001 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2002 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2003 } 2004 } else { 2005 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 2006 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 2007 } 2008 2009 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 2010 CS42L42_HSBIAS_RAMP_MASK, 2011 (cs42l42->hs_bias_ramp_rate << 2012 CS42L42_HSBIAS_RAMP_SHIFT)); 2013 2014 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable")) 2015 cs42l42->hs_bias_sense_en = 0; 2016 else 2017 cs42l42->hs_bias_sense_en = 1; 2018 2019 return 0; 2020 } 2021 2022 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 2023 const struct i2c_device_id *id) 2024 { 2025 struct cs42l42_private *cs42l42; 2026 int ret, i, devid; 2027 unsigned int reg; 2028 2029 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 2030 GFP_KERNEL); 2031 if (!cs42l42) 2032 return -ENOMEM; 2033 2034 cs42l42->dev = &i2c_client->dev; 2035 i2c_set_clientdata(i2c_client, cs42l42); 2036 2037 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 2038 if (IS_ERR(cs42l42->regmap)) { 2039 ret = PTR_ERR(cs42l42->regmap); 2040 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 2041 return ret; 2042 } 2043 2044 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 2045 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 2046 2047 ret = devm_regulator_bulk_get(&i2c_client->dev, 2048 ARRAY_SIZE(cs42l42->supplies), 2049 cs42l42->supplies); 2050 if (ret != 0) { 2051 dev_err(&i2c_client->dev, 2052 "Failed to request supplies: %d\n", ret); 2053 return ret; 2054 } 2055 2056 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 2057 cs42l42->supplies); 2058 if (ret != 0) { 2059 dev_err(&i2c_client->dev, 2060 "Failed to enable supplies: %d\n", ret); 2061 return ret; 2062 } 2063 2064 /* Reset the Device */ 2065 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 2066 "reset", GPIOD_OUT_LOW); 2067 if (IS_ERR(cs42l42->reset_gpio)) { 2068 ret = PTR_ERR(cs42l42->reset_gpio); 2069 goto err_disable_noreset; 2070 } 2071 2072 if (cs42l42->reset_gpio) { 2073 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 2074 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 2075 } 2076 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 2077 2078 /* Request IRQ if one was specified */ 2079 if (i2c_client->irq) { 2080 ret = request_threaded_irq(i2c_client->irq, 2081 NULL, cs42l42_irq_thread, 2082 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 2083 "cs42l42", cs42l42); 2084 if (ret == -EPROBE_DEFER) { 2085 goto err_disable_noirq; 2086 } else if (ret != 0) { 2087 dev_err(&i2c_client->dev, 2088 "Failed to request IRQ: %d\n", ret); 2089 goto err_disable_noirq; 2090 } 2091 } 2092 2093 /* initialize codec */ 2094 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB); 2095 if (devid < 0) { 2096 ret = devid; 2097 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 2098 goto err_disable; 2099 } 2100 2101 if (devid != CS42L42_CHIP_ID) { 2102 ret = -ENODEV; 2103 dev_err(&i2c_client->dev, 2104 "CS42L42 Device ID (%X). Expected %X\n", 2105 devid, CS42L42_CHIP_ID); 2106 goto err_disable; 2107 } 2108 2109 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 2110 if (ret < 0) { 2111 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 2112 goto err_shutdown; 2113 } 2114 2115 dev_info(&i2c_client->dev, 2116 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 2117 2118 /* Power up the codec */ 2119 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 2120 CS42L42_ASP_DAO_PDN_MASK | 2121 CS42L42_ASP_DAI_PDN_MASK | 2122 CS42L42_MIXER_PDN_MASK | 2123 CS42L42_EQ_PDN_MASK | 2124 CS42L42_HP_PDN_MASK | 2125 CS42L42_ADC_PDN_MASK | 2126 CS42L42_PDN_ALL_MASK, 2127 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 2128 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 2129 (1 << CS42L42_MIXER_PDN_SHIFT) | 2130 (1 << CS42L42_EQ_PDN_SHIFT) | 2131 (1 << CS42L42_HP_PDN_SHIFT) | 2132 (1 << CS42L42_ADC_PDN_SHIFT) | 2133 (0 << CS42L42_PDN_ALL_SHIFT)); 2134 2135 ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42); 2136 if (ret != 0) 2137 goto err_shutdown; 2138 2139 /* Setup headset detection */ 2140 cs42l42_setup_hs_type_detect(cs42l42); 2141 2142 /* Mask/Unmask Interrupts */ 2143 cs42l42_set_interrupt_masks(cs42l42); 2144 2145 /* Register codec for machine driver */ 2146 ret = devm_snd_soc_register_component(&i2c_client->dev, 2147 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 2148 if (ret < 0) 2149 goto err_shutdown; 2150 2151 return 0; 2152 2153 err_shutdown: 2154 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2155 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2156 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2157 2158 err_disable: 2159 if (i2c_client->irq) 2160 free_irq(i2c_client->irq, cs42l42); 2161 2162 err_disable_noirq: 2163 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2164 err_disable_noreset: 2165 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 2166 cs42l42->supplies); 2167 return ret; 2168 } 2169 2170 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 2171 { 2172 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 2173 2174 if (i2c_client->irq) 2175 free_irq(i2c_client->irq, cs42l42); 2176 2177 /* 2178 * The driver might not have control of reset and power supplies, 2179 * so ensure that the chip internals are powered down. 2180 */ 2181 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff); 2182 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff); 2183 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff); 2184 2185 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 2186 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies); 2187 2188 return 0; 2189 } 2190 2191 #ifdef CONFIG_OF 2192 static const struct of_device_id cs42l42_of_match[] = { 2193 { .compatible = "cirrus,cs42l42", }, 2194 {} 2195 }; 2196 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 2197 #endif 2198 2199 #ifdef CONFIG_ACPI 2200 static const struct acpi_device_id cs42l42_acpi_match[] = { 2201 {"10134242", 0,}, 2202 {} 2203 }; 2204 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match); 2205 #endif 2206 2207 static const struct i2c_device_id cs42l42_id[] = { 2208 {"cs42l42", 0}, 2209 {} 2210 }; 2211 2212 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 2213 2214 static struct i2c_driver cs42l42_i2c_driver = { 2215 .driver = { 2216 .name = "cs42l42", 2217 .of_match_table = of_match_ptr(cs42l42_of_match), 2218 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match), 2219 }, 2220 .id_table = cs42l42_id, 2221 .probe = cs42l42_i2c_probe, 2222 .remove = cs42l42_i2c_remove, 2223 }; 2224 2225 module_i2c_driver(cs42l42_i2c_driver); 2226 2227 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 2228 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 2229 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 2230 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 2231 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 2232 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 2233 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>"); 2234 MODULE_LICENSE("GPL"); 2235