1 // SPDX-License-Identifier: GPL-2.0-only 2 // cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver 3 // 4 // Copyright (C) 2022 Cirrus Logic, Inc. and 5 // Cirrus Logic International Semiconductor Ltd. 6 7 #include <linux/acpi.h> 8 #include <linux/device.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_registers.h> 16 #include <linux/soundwire/sdw_type.h> 17 #include <sound/pcm.h> 18 #include <sound/pcm_params.h> 19 #include <sound/sdw.h> 20 #include <sound/soc.h> 21 22 #include "cs42l42.h" 23 24 #define CS42L42_SDW_CAPTURE_PORT 1 25 #define CS42L42_SDW_PLAYBACK_PORT 2 26 27 /* Register addresses are offset when sent over SoundWire */ 28 #define CS42L42_SDW_ADDR_OFFSET 0x8000 29 30 #define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0 31 #define CS42L42_SDW_MEM_READ_DATA 0xd8 32 33 #define CS42L42_SDW_LAST_LATE BIT(3) 34 #define CS42L42_SDW_CMD_IN_PROGRESS BIT(2) 35 #define CS42L42_SDW_RDATA_RDY BIT(0) 36 37 #define CS42L42_DELAYED_READ_POLL_US 1 38 #define CS42L42_DELAYED_READ_TIMEOUT_US 100 39 40 static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = { 41 /* Playback Path */ 42 { "HP", NULL, "MIXER" }, 43 { "MIXER", NULL, "DACSRC" }, 44 { "DACSRC", NULL, "Playback" }, 45 46 /* Capture Path */ 47 { "ADCSRC", NULL, "HS" }, 48 { "Capture", NULL, "ADCSRC" }, 49 }; 50 51 static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream, 52 struct snd_soc_dai *dai) 53 { 54 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 55 56 if (!cs42l42->init_done) 57 return -ENODEV; 58 59 return 0; 60 } 61 62 static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream, 63 struct snd_pcm_hw_params *params, 64 struct snd_soc_dai *dai) 65 { 66 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 67 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 68 struct sdw_stream_config stream_config = {0}; 69 struct sdw_port_config port_config = {0}; 70 int ret; 71 72 if (!sdw_stream) 73 return -EINVAL; 74 75 /* Needed for PLL configuration when we are notified of new bus config */ 76 cs42l42->sample_rate = params_rate(params); 77 78 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 79 80 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 81 port_config.num = CS42L42_SDW_PLAYBACK_PORT; 82 else 83 port_config.num = CS42L42_SDW_CAPTURE_PORT; 84 85 ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1, 86 sdw_stream); 87 if (ret) { 88 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 89 return ret; 90 } 91 92 cs42l42_src_config(dai->component, params_rate(params)); 93 94 return 0; 95 } 96 97 static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream, 98 struct snd_soc_dai *dai) 99 { 100 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 101 102 dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate); 103 104 if (!cs42l42->sclk || !cs42l42->sample_rate) 105 return -EINVAL; 106 107 /* 108 * At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config() 109 * callback. This could only fail if the ACPI or machine driver are misconfigured to allow 110 * an unsupported SWIRE_CLK and sample_rate combination. 111 */ 112 113 return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate); 114 } 115 116 static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream, 117 struct snd_soc_dai *dai) 118 { 119 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component); 120 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 121 122 sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream); 123 cs42l42->sample_rate = 0; 124 125 return 0; 126 } 127 128 static int cs42l42_sdw_port_prep(struct sdw_slave *slave, 129 struct sdw_prepare_ch *prepare_ch, 130 enum sdw_port_prep_ops state) 131 { 132 struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev); 133 unsigned int pdn_mask; 134 135 if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT) 136 pdn_mask = CS42L42_HP_PDN_MASK; 137 else 138 pdn_mask = CS42L42_ADC_PDN_MASK; 139 140 if (state == SDW_OPS_PORT_PRE_PREP) { 141 dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask); 142 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask); 143 usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000); 144 } else if (state == SDW_OPS_PORT_POST_DEPREP) { 145 dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask); 146 regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask); 147 } 148 149 return 0; 150 } 151 152 static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 153 int direction) 154 { 155 if (!sdw_stream) 156 return 0; 157 158 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 159 160 return 0; 161 } 162 163 static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream, 164 struct snd_soc_dai *dai) 165 { 166 snd_soc_dai_set_dma_data(dai, substream, NULL); 167 } 168 169 static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = { 170 .startup = cs42l42_sdw_dai_startup, 171 .shutdown = cs42l42_sdw_dai_shutdown, 172 .hw_params = cs42l42_sdw_dai_hw_params, 173 .prepare = cs42l42_sdw_dai_prepare, 174 .hw_free = cs42l42_sdw_dai_hw_free, 175 .mute_stream = cs42l42_mute_stream, 176 .set_stream = cs42l42_sdw_dai_set_sdw_stream, 177 }; 178 179 static struct snd_soc_dai_driver cs42l42_sdw_dai = { 180 .name = "cs42l42-sdw", 181 .playback = { 182 .stream_name = "Playback", 183 .channels_min = 1, 184 .channels_max = 2, 185 /* Restrict which rates and formats are supported */ 186 .rates = SNDRV_PCM_RATE_8000_96000, 187 .formats = SNDRV_PCM_FMTBIT_S16_LE | 188 SNDRV_PCM_FMTBIT_S24_LE | 189 SNDRV_PCM_FMTBIT_S32_LE, 190 }, 191 .capture = { 192 .stream_name = "Capture", 193 .channels_min = 1, 194 .channels_max = 1, 195 /* Restrict which rates and formats are supported */ 196 .rates = SNDRV_PCM_RATE_8000_96000, 197 .formats = SNDRV_PCM_FMTBIT_S16_LE | 198 SNDRV_PCM_FMTBIT_S24_LE | 199 SNDRV_PCM_FMTBIT_S32_LE, 200 }, 201 .symmetric_rate = 1, 202 .ops = &cs42l42_sdw_dai_ops, 203 }; 204 205 static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match) 206 { 207 int ret, sdwret; 208 209 ret = read_poll_timeout(sdw_read_no_pm, sdwret, 210 (sdwret < 0) || ((sdwret & mask) == match), 211 CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US, 212 false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); 213 if (ret == 0) 214 ret = sdwret; 215 216 if (ret < 0) 217 dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n", 218 mask, match, ret); 219 220 return ret; 221 } 222 223 static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val) 224 { 225 struct sdw_slave *peripheral = context; 226 u8 data; 227 int ret; 228 229 reg += CS42L42_SDW_ADDR_OFFSET; 230 231 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0); 232 if (ret < 0) 233 return ret; 234 235 ret = sdw_read_no_pm(peripheral, reg); 236 if (ret < 0) { 237 dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret); 238 return ret; 239 } 240 241 data = (u8)ret; /* possible non-delayed read value */ 242 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS); 243 if (ret < 0) { 244 dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret); 245 return ret; 246 } 247 248 /* If read was not delayed we already have the result */ 249 if ((ret & CS42L42_SDW_LAST_LATE) == 0) { 250 *val = data; 251 return 0; 252 } 253 254 /* Poll for delayed read completion */ 255 if ((ret & CS42L42_SDW_RDATA_RDY) == 0) { 256 ret = cs42l42_sdw_poll_status(peripheral, 257 CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY); 258 if (ret < 0) 259 return ret; 260 } 261 262 ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA); 263 if (ret < 0) { 264 dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret); 265 return ret; 266 } 267 268 *val = (u8)ret; 269 270 return 0; 271 } 272 273 static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val) 274 { 275 struct sdw_slave *peripheral = context; 276 int ret; 277 278 ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0); 279 if (ret < 0) 280 return ret; 281 282 return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val); 283 } 284 285 /* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */ 286 static void cs42l42_sdw_init(struct sdw_slave *peripheral) 287 { 288 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 289 int ret; 290 291 regcache_cache_only(cs42l42->regmap, false); 292 293 ret = cs42l42_init(cs42l42); 294 if (ret < 0) { 295 regcache_cache_only(cs42l42->regmap, true); 296 goto err; 297 } 298 299 /* Write out any cached changes that happened between probe and attach */ 300 ret = regcache_sync(cs42l42->regmap); 301 if (ret < 0) 302 dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret); 303 304 /* Disable internal logic that makes clock-stop conditional */ 305 regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK); 306 307 err: 308 /* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */ 309 pm_runtime_put_autosuspend(cs42l42->dev); 310 } 311 312 static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral) 313 { 314 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 315 struct sdw_slave_prop *prop = &peripheral->prop; 316 struct sdw_dpn_prop *ports; 317 318 ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL); 319 if (!ports) 320 return -ENOMEM; 321 322 prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT); 323 prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT); 324 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; 325 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 326 327 /* DP1 - capture */ 328 ports[0].num = CS42L42_SDW_CAPTURE_PORT, 329 ports[0].type = SDW_DPN_FULL, 330 ports[0].ch_prep_timeout = 10, 331 prop->src_dpn_prop = &ports[0]; 332 333 /* DP2 - playback */ 334 ports[1].num = CS42L42_SDW_PLAYBACK_PORT, 335 ports[1].type = SDW_DPN_FULL, 336 ports[1].ch_prep_timeout = 10, 337 prop->sink_dpn_prop = &ports[1]; 338 339 return 0; 340 } 341 342 static int cs42l42_sdw_update_status(struct sdw_slave *peripheral, 343 enum sdw_slave_status status) 344 { 345 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 346 347 switch (status) { 348 case SDW_SLAVE_ATTACHED: 349 dev_dbg(cs42l42->dev, "ATTACHED\n"); 350 /* 351 * Initialise codec, this only needs to be done once. 352 * When resuming from suspend, resume callback will handle re-init of codec, 353 * using regcache_sync(). 354 */ 355 if (!cs42l42->init_done) 356 cs42l42_sdw_init(peripheral); 357 break; 358 case SDW_SLAVE_UNATTACHED: 359 dev_dbg(cs42l42->dev, "UNATTACHED\n"); 360 break; 361 default: 362 break; 363 } 364 365 return 0; 366 } 367 368 static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral, 369 struct sdw_bus_params *params) 370 { 371 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 372 unsigned int new_sclk = params->curr_dr_freq / 2; 373 374 /* The cs42l42 cannot support a glitchless SWIRE_CLK change. */ 375 if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) { 376 dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n"); 377 return -EBUSY; 378 } 379 380 cs42l42->sclk = new_sclk; 381 382 dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n", 383 cs42l42->sclk, params->col, params->row); 384 385 return 0; 386 } 387 388 static const struct sdw_slave_ops cs42l42_sdw_ops = { 389 /* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */ 390 .read_prop = cs42l42_sdw_read_prop, 391 .update_status = cs42l42_sdw_update_status, 392 .bus_config = cs42l42_sdw_bus_config, 393 .port_prep = cs42l42_sdw_port_prep, 394 }; 395 396 static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev) 397 { 398 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 399 400 dev_dbg(dev, "Runtime suspend\n"); 401 402 if (!cs42l42->init_done) 403 return 0; 404 405 /* The host controller could suspend, which would mean no register access */ 406 regcache_cache_only(cs42l42->regmap, true); 407 408 return 0; 409 } 410 411 static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = { 412 REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e), 413 }; 414 415 static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42) 416 { 417 struct sdw_slave *peripheral = cs42l42->sdw_peripheral; 418 419 if (!peripheral->unattach_request) 420 return 0; 421 422 /* Cannot access registers until master re-attaches. */ 423 dev_dbg(&peripheral->dev, "Wait for initialization_complete\n"); 424 if (!wait_for_completion_timeout(&peripheral->initialization_complete, 425 msecs_to_jiffies(5000))) { 426 dev_err(&peripheral->dev, "initialization_complete timed out\n"); 427 return -ETIMEDOUT; 428 } 429 430 peripheral->unattach_request = 0; 431 432 /* 433 * After a bus reset there must be a reconfiguration reset to 434 * reinitialize the internal state of CS42L42. 435 */ 436 regmap_multi_reg_write_bypassed(cs42l42->regmap, 437 cs42l42_soft_reboot_seq, 438 ARRAY_SIZE(cs42l42_soft_reboot_seq)); 439 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 440 regcache_mark_dirty(cs42l42->regmap); 441 442 return 0; 443 } 444 445 static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev) 446 { 447 static const unsigned int ts_dbnce_ms[] = { 0, 125, 250, 500, 750, 1000, 1250, 1500}; 448 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 449 unsigned int dbnce; 450 int ret; 451 452 dev_dbg(dev, "Runtime resume\n"); 453 454 if (!cs42l42->init_done) 455 return 0; 456 457 ret = cs42l42_sdw_handle_unattach(cs42l42); 458 if (ret < 0) { 459 return ret; 460 } else if (ret > 0) { 461 dbnce = max(cs42l42->ts_dbnc_rise, cs42l42->ts_dbnc_fall); 462 463 if (dbnce > 0) 464 msleep(ts_dbnce_ms[dbnce]); 465 } 466 467 regcache_cache_only(cs42l42->regmap, false); 468 469 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ 470 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); 471 regcache_sync(cs42l42->regmap); 472 473 return 0; 474 } 475 476 static int __maybe_unused cs42l42_sdw_resume(struct device *dev) 477 { 478 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 479 int ret; 480 481 dev_dbg(dev, "System resume\n"); 482 483 /* Power-up so it can re-enumerate */ 484 ret = cs42l42_resume(dev); 485 if (ret) 486 return ret; 487 488 /* Wait for re-attach */ 489 ret = cs42l42_sdw_handle_unattach(cs42l42); 490 if (ret < 0) 491 return ret; 492 493 cs42l42_resume_restore(dev); 494 495 return 0; 496 } 497 498 static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id) 499 { 500 struct snd_soc_component_driver *component_drv; 501 struct device *dev = &peripheral->dev; 502 struct cs42l42_private *cs42l42; 503 struct regmap_config *regmap_conf; 504 struct regmap *regmap; 505 int irq, ret; 506 507 cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL); 508 if (!cs42l42) 509 return -ENOMEM; 510 511 if (has_acpi_companion(dev)) 512 irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0); 513 else 514 irq = of_irq_get(dev->of_node, 0); 515 516 if (irq == -ENOENT) 517 irq = 0; 518 else if (irq < 0) 519 return dev_err_probe(dev, irq, "Failed to get IRQ\n"); 520 521 regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL); 522 if (!regmap_conf) 523 return -ENOMEM; 524 regmap_conf->reg_bits = 16; 525 regmap_conf->num_ranges = 0; 526 regmap_conf->reg_read = cs42l42_sdw_read; 527 regmap_conf->reg_write = cs42l42_sdw_write; 528 529 regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf); 530 if (IS_ERR(regmap)) 531 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n"); 532 533 /* Start in cache-only until device is enumerated */ 534 regcache_cache_only(regmap, true); 535 536 component_drv = devm_kmemdup(dev, 537 &cs42l42_soc_component, 538 sizeof(cs42l42_soc_component), 539 GFP_KERNEL); 540 if (!component_drv) 541 return -ENOMEM; 542 543 component_drv->dapm_routes = cs42l42_sdw_audio_map; 544 component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map); 545 546 cs42l42->dev = dev; 547 cs42l42->regmap = regmap; 548 cs42l42->sdw_peripheral = peripheral; 549 cs42l42->irq = irq; 550 cs42l42->devid = CS42L42_CHIP_ID; 551 552 /* 553 * pm_runtime is needed to control bus manager suspend, and to 554 * recover from an unattach_request when the manager suspends. 555 */ 556 pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000); 557 pm_runtime_use_autosuspend(cs42l42->dev); 558 pm_runtime_mark_last_busy(cs42l42->dev); 559 pm_runtime_set_active(cs42l42->dev); 560 pm_runtime_get_noresume(cs42l42->dev); 561 pm_runtime_enable(cs42l42->dev); 562 563 ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai); 564 if (ret < 0) 565 return ret; 566 567 return 0; 568 } 569 570 static int cs42l42_sdw_remove(struct sdw_slave *peripheral) 571 { 572 struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev); 573 574 cs42l42_common_remove(cs42l42); 575 pm_runtime_disable(cs42l42->dev); 576 577 return 0; 578 } 579 580 static const struct dev_pm_ops cs42l42_sdw_pm = { 581 SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume) 582 SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL) 583 }; 584 585 static const struct sdw_device_id cs42l42_sdw_id[] = { 586 SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0), 587 {}, 588 }; 589 MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id); 590 591 static struct sdw_driver cs42l42_sdw_driver = { 592 .driver = { 593 .name = "cs42l42-sdw", 594 .pm = &cs42l42_sdw_pm, 595 }, 596 .probe = cs42l42_sdw_probe, 597 .remove = cs42l42_sdw_remove, 598 .ops = &cs42l42_sdw_ops, 599 .id_table = cs42l42_sdw_id, 600 }; 601 602 module_sdw_driver(cs42l42_sdw_driver); 603 604 MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver"); 605 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 606 MODULE_LICENSE("GPL"); 607 MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE); 608