1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * CS4271 ASoC codec driver 4 * 5 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 6 * 7 * This driver support CS4271 codec being master or slave, working 8 * in control port mode, connected either via SPI or I2C. 9 * The data format accepted is I2S or left-justified. 10 * DAPM support not implemented. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/gpio/consumer.h> 18 #include <linux/of.h> 19 #include <linux/regulator/consumer.h> 20 #include <sound/pcm.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include <sound/cs4271.h> 24 #include "cs4271.h" 25 26 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 27 SNDRV_PCM_FMTBIT_S24_LE | \ 28 SNDRV_PCM_FMTBIT_S32_LE) 29 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 30 31 /* 32 * CS4271 registers 33 */ 34 #define CS4271_MODE1 0x01 /* Mode Control 1 */ 35 #define CS4271_DACCTL 0x02 /* DAC Control */ 36 #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */ 37 #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */ 38 #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */ 39 #define CS4271_ADCCTL 0x06 /* ADC Control */ 40 #define CS4271_MODE2 0x07 /* Mode Control 2 */ 41 #define CS4271_CHIPID 0x08 /* Chip ID */ 42 43 #define CS4271_FIRSTREG CS4271_MODE1 44 #define CS4271_LASTREG CS4271_MODE2 45 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) 46 47 /* Bit masks for the CS4271 registers */ 48 #define CS4271_MODE1_MODE_MASK 0xC0 49 #define CS4271_MODE1_MODE_1X 0x00 50 #define CS4271_MODE1_MODE_2X 0x80 51 #define CS4271_MODE1_MODE_4X 0xC0 52 53 #define CS4271_MODE1_DIV_MASK 0x30 54 #define CS4271_MODE1_DIV_1 0x00 55 #define CS4271_MODE1_DIV_15 0x10 56 #define CS4271_MODE1_DIV_2 0x20 57 #define CS4271_MODE1_DIV_3 0x30 58 59 #define CS4271_MODE1_MASTER 0x08 60 61 #define CS4271_MODE1_DAC_DIF_MASK 0x07 62 #define CS4271_MODE1_DAC_DIF_LJ 0x00 63 #define CS4271_MODE1_DAC_DIF_I2S 0x01 64 #define CS4271_MODE1_DAC_DIF_RJ16 0x02 65 #define CS4271_MODE1_DAC_DIF_RJ24 0x03 66 #define CS4271_MODE1_DAC_DIF_RJ20 0x04 67 #define CS4271_MODE1_DAC_DIF_RJ18 0x05 68 69 #define CS4271_DACCTL_AMUTE 0x80 70 #define CS4271_DACCTL_IF_SLOW 0x40 71 72 #define CS4271_DACCTL_DEM_MASK 0x30 73 #define CS4271_DACCTL_DEM_DIS 0x00 74 #define CS4271_DACCTL_DEM_441 0x10 75 #define CS4271_DACCTL_DEM_48 0x20 76 #define CS4271_DACCTL_DEM_32 0x30 77 78 #define CS4271_DACCTL_SVRU 0x08 79 #define CS4271_DACCTL_SRD 0x04 80 #define CS4271_DACCTL_INVA 0x02 81 #define CS4271_DACCTL_INVB 0x01 82 83 #define CS4271_DACVOL_BEQUA 0x40 84 #define CS4271_DACVOL_SOFT 0x20 85 #define CS4271_DACVOL_ZEROC 0x10 86 87 #define CS4271_DACVOL_ATAPI_MASK 0x0F 88 #define CS4271_DACVOL_ATAPI_M_M 0x00 89 #define CS4271_DACVOL_ATAPI_M_BR 0x01 90 #define CS4271_DACVOL_ATAPI_M_BL 0x02 91 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 92 #define CS4271_DACVOL_ATAPI_AR_M 0x04 93 #define CS4271_DACVOL_ATAPI_AR_BR 0x05 94 #define CS4271_DACVOL_ATAPI_AR_BL 0x06 95 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 96 #define CS4271_DACVOL_ATAPI_AL_M 0x08 97 #define CS4271_DACVOL_ATAPI_AL_BR 0x09 98 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A 99 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B 100 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C 101 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D 102 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E 103 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F 104 105 #define CS4271_VOLA_MUTE 0x80 106 #define CS4271_VOLA_VOL_MASK 0x7F 107 #define CS4271_VOLB_MUTE 0x80 108 #define CS4271_VOLB_VOL_MASK 0x7F 109 110 #define CS4271_ADCCTL_DITHER16 0x20 111 112 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 113 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 114 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 115 116 #define CS4271_ADCCTL_MUTEA 0x08 117 #define CS4271_ADCCTL_MUTEB 0x04 118 #define CS4271_ADCCTL_HPFDA 0x02 119 #define CS4271_ADCCTL_HPFDB 0x01 120 121 #define CS4271_MODE2_LOOP 0x10 122 #define CS4271_MODE2_MUTECAEQUB 0x08 123 #define CS4271_MODE2_FREEZE 0x04 124 #define CS4271_MODE2_CPEN 0x02 125 #define CS4271_MODE2_PDN 0x01 126 127 #define CS4271_CHIPID_PART_MASK 0xF0 128 #define CS4271_CHIPID_REV_MASK 0x0F 129 130 /* 131 * Default CS4271 power-up configuration 132 * Array contains non-existing in hw register at address 0 133 * Array do not include Chip ID, as codec driver does not use 134 * registers read operations at all 135 */ 136 static const struct reg_default cs4271_reg_defaults[] = { 137 { CS4271_MODE1, 0, }, 138 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, }, 139 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, }, 140 { CS4271_VOLA, 0, }, 141 { CS4271_VOLB, 0, }, 142 { CS4271_ADCCTL, 0, }, 143 { CS4271_MODE2, 0, }, 144 }; 145 146 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg) 147 { 148 return reg == CS4271_CHIPID; 149 } 150 151 static const char * const supply_names[] = { 152 "vd", "vl", "va" 153 }; 154 155 struct cs4271_private { 156 unsigned int mclk; 157 bool master; 158 bool deemph; 159 struct regmap *regmap; 160 /* Current sample rate for de-emphasis control */ 161 int rate; 162 /* GPIO driving Reset pin, if any */ 163 struct gpio_desc *reset; 164 /* enable soft reset workaround */ 165 bool enable_soft_reset; 166 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 167 struct clk *clk; 168 }; 169 170 static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = { 171 SND_SOC_DAPM_INPUT("AINA"), 172 SND_SOC_DAPM_INPUT("AINB"), 173 174 SND_SOC_DAPM_OUTPUT("AOUTA+"), 175 SND_SOC_DAPM_OUTPUT("AOUTA-"), 176 SND_SOC_DAPM_OUTPUT("AOUTB+"), 177 SND_SOC_DAPM_OUTPUT("AOUTB-"), 178 }; 179 180 static const struct snd_soc_dapm_route cs4271_dapm_routes[] = { 181 { "Capture", NULL, "AINA" }, 182 { "Capture", NULL, "AINB" }, 183 184 { "AOUTA+", NULL, "Playback" }, 185 { "AOUTA-", NULL, "Playback" }, 186 { "AOUTB+", NULL, "Playback" }, 187 { "AOUTB-", NULL, "Playback" }, 188 }; 189 190 /* 191 * @freq is the desired MCLK rate 192 * MCLK rate should (c) be the sample rate, multiplied by one of the 193 * ratios listed in cs4271_mclk_fs_ratios table 194 */ 195 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, 196 int clk_id, unsigned int freq, int dir) 197 { 198 struct snd_soc_component *component = codec_dai->component; 199 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 200 201 cs4271->mclk = freq; 202 return 0; 203 } 204 205 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, 206 unsigned int format) 207 { 208 struct snd_soc_component *component = codec_dai->component; 209 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 210 unsigned int val = 0; 211 int ret; 212 213 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 214 case SND_SOC_DAIFMT_CBC_CFC: 215 cs4271->master = false; 216 break; 217 case SND_SOC_DAIFMT_CBP_CFP: 218 cs4271->master = true; 219 val |= CS4271_MODE1_MASTER; 220 break; 221 default: 222 dev_err(component->dev, "Invalid DAI format\n"); 223 return -EINVAL; 224 } 225 226 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 227 case SND_SOC_DAIFMT_LEFT_J: 228 val |= CS4271_MODE1_DAC_DIF_LJ; 229 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 230 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); 231 if (ret < 0) 232 return ret; 233 break; 234 case SND_SOC_DAIFMT_I2S: 235 val |= CS4271_MODE1_DAC_DIF_I2S; 236 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 237 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); 238 if (ret < 0) 239 return ret; 240 break; 241 default: 242 dev_err(component->dev, "Invalid DAI format\n"); 243 return -EINVAL; 244 } 245 246 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 247 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); 248 if (ret < 0) 249 return ret; 250 return 0; 251 } 252 253 static int cs4271_deemph[] = {0, 44100, 48000, 32000}; 254 255 static int cs4271_set_deemph(struct snd_soc_component *component) 256 { 257 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 258 int i, ret; 259 int val = CS4271_DACCTL_DEM_DIS; 260 261 if (cs4271->deemph) { 262 /* Find closest de-emphasis freq */ 263 val = 1; 264 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) 265 if (abs(cs4271_deemph[i] - cs4271->rate) < 266 abs(cs4271_deemph[val] - cs4271->rate)) 267 val = i; 268 val <<= 4; 269 } 270 271 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL, 272 CS4271_DACCTL_DEM_MASK, val); 273 if (ret < 0) 274 return ret; 275 return 0; 276 } 277 278 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 279 struct snd_ctl_elem_value *ucontrol) 280 { 281 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 282 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 283 284 ucontrol->value.integer.value[0] = cs4271->deemph; 285 return 0; 286 } 287 288 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 289 struct snd_ctl_elem_value *ucontrol) 290 { 291 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 292 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 293 294 cs4271->deemph = ucontrol->value.integer.value[0]; 295 return cs4271_set_deemph(component); 296 } 297 298 struct cs4271_clk_cfg { 299 bool master; /* codec mode */ 300 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ 301 unsigned short ratio; /* MCLK / sample rate */ 302 u8 ratio_mask; /* ratio bit mask for Master mode */ 303 }; 304 305 static struct cs4271_clk_cfg cs4271_clk_tab[] = { 306 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 307 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, 308 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, 309 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, 310 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 311 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, 312 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, 313 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, 314 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 315 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, 316 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, 317 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, 318 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 319 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, 320 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, 321 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, 322 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, 323 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 324 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, 325 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, 326 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, 327 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, 328 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 329 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, 330 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, 331 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, 332 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, 333 }; 334 335 #define CS4271_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) 336 337 static int cs4271_hw_params(struct snd_pcm_substream *substream, 338 struct snd_pcm_hw_params *params, 339 struct snd_soc_dai *dai) 340 { 341 struct snd_soc_component *component = dai->component; 342 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 343 int i, ret; 344 unsigned int ratio, val; 345 346 if (cs4271->enable_soft_reset) { 347 /* 348 * Put the codec in soft reset and back again in case it's not 349 * currently streaming data. This way of bringing the codec in 350 * sync to the current clocks is not explicitly documented in 351 * the data sheet, but it seems to work fine, and in contrast 352 * to a read hardware reset, we don't have to sync back all 353 * registers every time. 354 */ 355 356 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 357 !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE)) || 358 (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 359 !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK))) { 360 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 361 CS4271_MODE2_PDN, 362 CS4271_MODE2_PDN); 363 if (ret < 0) 364 return ret; 365 366 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 367 CS4271_MODE2_PDN, 0); 368 if (ret < 0) 369 return ret; 370 } 371 } 372 373 cs4271->rate = params_rate(params); 374 375 /* Configure DAC */ 376 if (cs4271->rate < 50000) 377 val = CS4271_MODE1_MODE_1X; 378 else if (cs4271->rate < 100000) 379 val = CS4271_MODE1_MODE_2X; 380 else 381 val = CS4271_MODE1_MODE_4X; 382 383 ratio = cs4271->mclk / cs4271->rate; 384 for (i = 0; i < CS4271_NR_RATIOS; i++) 385 if ((cs4271_clk_tab[i].master == cs4271->master) && 386 (cs4271_clk_tab[i].speed_mode == val) && 387 (cs4271_clk_tab[i].ratio == ratio)) 388 break; 389 390 if (i == CS4271_NR_RATIOS) { 391 dev_err(component->dev, "Invalid sample rate\n"); 392 return -EINVAL; 393 } 394 395 val |= cs4271_clk_tab[i].ratio_mask; 396 397 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 398 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); 399 if (ret < 0) 400 return ret; 401 402 return cs4271_set_deemph(component); 403 } 404 405 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 406 { 407 struct snd_soc_component *component = dai->component; 408 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 409 int ret; 410 int val_a = 0; 411 int val_b = 0; 412 413 if (stream != SNDRV_PCM_STREAM_PLAYBACK) 414 return 0; 415 416 if (mute) { 417 val_a = CS4271_VOLA_MUTE; 418 val_b = CS4271_VOLB_MUTE; 419 } 420 421 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA, 422 CS4271_VOLA_MUTE, val_a); 423 if (ret < 0) 424 return ret; 425 426 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB, 427 CS4271_VOLB_MUTE, val_b); 428 if (ret < 0) 429 return ret; 430 431 return 0; 432 } 433 434 /* CS4271 controls */ 435 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); 436 437 static const struct snd_kcontrol_new cs4271_snd_controls[] = { 438 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, 439 0, 0x7F, 1, cs4271_dac_tlv), 440 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), 441 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), 442 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), 443 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 444 cs4271_get_deemph, cs4271_put_deemph), 445 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), 446 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), 447 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), 448 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), 449 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), 450 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), 451 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), 452 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), 453 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), 454 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, 455 7, 1, 1), 456 }; 457 458 static const struct snd_soc_dai_ops cs4271_dai_ops = { 459 .hw_params = cs4271_hw_params, 460 .set_sysclk = cs4271_set_dai_sysclk, 461 .set_fmt = cs4271_set_dai_fmt, 462 .mute_stream = cs4271_mute_stream, 463 }; 464 465 static struct snd_soc_dai_driver cs4271_dai = { 466 .name = "cs4271-hifi", 467 .playback = { 468 .stream_name = "Playback", 469 .channels_min = 2, 470 .channels_max = 2, 471 .rates = CS4271_PCM_RATES, 472 .formats = CS4271_PCM_FORMATS, 473 }, 474 .capture = { 475 .stream_name = "Capture", 476 .channels_min = 2, 477 .channels_max = 2, 478 .rates = CS4271_PCM_RATES, 479 .formats = CS4271_PCM_FORMATS, 480 }, 481 .ops = &cs4271_dai_ops, 482 .symmetric_rate = 1, 483 }; 484 485 static int cs4271_reset(struct snd_soc_component *component) 486 { 487 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 488 489 gpiod_direction_output(cs4271->reset, 1); 490 mdelay(1); 491 gpiod_set_value(cs4271->reset, 0); 492 mdelay(1); 493 494 return 0; 495 } 496 497 #ifdef CONFIG_PM 498 static int cs4271_soc_suspend(struct snd_soc_component *component) 499 { 500 int ret; 501 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 502 503 /* Set power-down bit */ 504 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 505 CS4271_MODE2_PDN, CS4271_MODE2_PDN); 506 if (ret < 0) 507 return ret; 508 509 regcache_mark_dirty(cs4271->regmap); 510 clk_disable_unprepare(cs4271->clk); 511 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); 512 513 return 0; 514 } 515 516 static int cs4271_soc_resume(struct snd_soc_component *component) 517 { 518 int ret; 519 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 520 521 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies), 522 cs4271->supplies); 523 if (ret < 0) { 524 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); 525 return ret; 526 } 527 528 ret = clk_prepare_enable(cs4271->clk); 529 if (ret) { 530 dev_err(component->dev, "Failed to enable clk: %d\n", ret); 531 return ret; 532 } 533 534 /* Do a proper reset after power up */ 535 cs4271_reset(component); 536 537 /* Restore codec state */ 538 ret = regcache_sync(cs4271->regmap); 539 if (ret < 0) 540 return ret; 541 542 /* then disable the power-down bit */ 543 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 544 CS4271_MODE2_PDN, 0); 545 if (ret < 0) 546 return ret; 547 548 return 0; 549 } 550 #else 551 #define cs4271_soc_suspend NULL 552 #define cs4271_soc_resume NULL 553 #endif /* CONFIG_PM */ 554 555 #ifdef CONFIG_OF 556 const struct of_device_id cs4271_dt_ids[] = { 557 { .compatible = "cirrus,cs4271", }, 558 { } 559 }; 560 MODULE_DEVICE_TABLE(of, cs4271_dt_ids); 561 EXPORT_SYMBOL_GPL(cs4271_dt_ids); 562 #endif 563 564 static int cs4271_component_probe(struct snd_soc_component *component) 565 { 566 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 567 struct cs4271_platform_data *cs4271plat = component->dev->platform_data; 568 int ret; 569 bool amutec_eq_bmutec; 570 571 amutec_eq_bmutec = of_property_read_bool(component->dev->of_node, 572 "cirrus,amutec-eq-bmutec"); 573 cs4271->enable_soft_reset = of_property_read_bool(component->dev->of_node, 574 "cirrus,enable-soft-reset"); 575 576 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies), 577 cs4271->supplies); 578 if (ret < 0) { 579 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); 580 return ret; 581 } 582 583 if (cs4271plat) { 584 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; 585 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; 586 } 587 588 ret = clk_prepare_enable(cs4271->clk); 589 if (ret) { 590 dev_err(component->dev, "Failed to enable clk: %d\n", ret); 591 goto err_disable_regulators; 592 } 593 594 /* Reset codec */ 595 cs4271_reset(component); 596 597 ret = regcache_sync(cs4271->regmap); 598 if (ret < 0) 599 goto err_disable_clk; 600 601 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 602 CS4271_MODE2_PDN | CS4271_MODE2_CPEN, 603 CS4271_MODE2_PDN | CS4271_MODE2_CPEN); 604 if (ret < 0) 605 goto err_disable_clk; 606 607 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 608 CS4271_MODE2_PDN, 0); 609 if (ret < 0) 610 goto err_disable_clk; 611 612 /* Power-up sequence requires 85 uS */ 613 udelay(85); 614 615 if (amutec_eq_bmutec) 616 regmap_update_bits(cs4271->regmap, CS4271_MODE2, 617 CS4271_MODE2_MUTECAEQUB, 618 CS4271_MODE2_MUTECAEQUB); 619 620 return 0; 621 622 err_disable_clk: 623 clk_disable_unprepare(cs4271->clk); 624 err_disable_regulators: 625 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); 626 return ret; 627 } 628 629 static void cs4271_component_remove(struct snd_soc_component *component) 630 { 631 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 632 633 /* Set codec to the reset state */ 634 gpiod_set_value(cs4271->reset, 1); 635 636 regcache_mark_dirty(cs4271->regmap); 637 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); 638 clk_disable_unprepare(cs4271->clk); 639 }; 640 641 static const struct snd_soc_component_driver soc_component_dev_cs4271 = { 642 .probe = cs4271_component_probe, 643 .remove = cs4271_component_remove, 644 .suspend = cs4271_soc_suspend, 645 .resume = cs4271_soc_resume, 646 .controls = cs4271_snd_controls, 647 .num_controls = ARRAY_SIZE(cs4271_snd_controls), 648 .dapm_widgets = cs4271_dapm_widgets, 649 .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets), 650 .dapm_routes = cs4271_dapm_routes, 651 .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes), 652 .idle_bias_on = 1, 653 .use_pmdown_time = 1, 654 .endianness = 1, 655 }; 656 657 static int cs4271_common_probe(struct device *dev, 658 struct cs4271_private **c) 659 { 660 struct cs4271_private *cs4271; 661 int i, ret; 662 663 cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL); 664 if (!cs4271) 665 return -ENOMEM; 666 667 cs4271->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); 668 if (IS_ERR(cs4271->reset)) 669 return dev_err_probe(dev, PTR_ERR(cs4271->reset), 670 "error retrieving RESET GPIO\n"); 671 gpiod_set_consumer_name(cs4271->reset, "CS4271 Reset"); 672 673 cs4271->clk = devm_clk_get_optional(dev, "mclk"); 674 if (IS_ERR(cs4271->clk)) 675 return dev_err_probe(dev, PTR_ERR(cs4271->clk), "Failed to get mclk\n"); 676 677 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 678 cs4271->supplies[i].supply = supply_names[i]; 679 680 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies), 681 cs4271->supplies); 682 683 if (ret < 0) { 684 dev_err(dev, "Failed to get regulators: %d\n", ret); 685 return ret; 686 } 687 688 *c = cs4271; 689 return 0; 690 } 691 692 const struct regmap_config cs4271_regmap_config = { 693 .max_register = CS4271_LASTREG, 694 695 .reg_defaults = cs4271_reg_defaults, 696 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 697 .cache_type = REGCACHE_FLAT, 698 .val_bits = 8, 699 .volatile_reg = cs4271_volatile_reg, 700 }; 701 EXPORT_SYMBOL_GPL(cs4271_regmap_config); 702 703 int cs4271_probe(struct device *dev, struct regmap *regmap) 704 { 705 struct cs4271_private *cs4271; 706 int ret; 707 708 if (IS_ERR(regmap)) 709 return PTR_ERR(regmap); 710 711 ret = cs4271_common_probe(dev, &cs4271); 712 if (ret < 0) 713 return ret; 714 715 dev_set_drvdata(dev, cs4271); 716 cs4271->regmap = regmap; 717 718 return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271, 719 &cs4271_dai, 1); 720 } 721 EXPORT_SYMBOL_GPL(cs4271_probe); 722 723 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); 724 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); 725 MODULE_LICENSE("GPL"); 726