1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * CS4271 ASoC codec driver 4 * 5 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 6 * 7 * This driver support CS4271 codec being master or slave, working 8 * in control port mode, connected either via SPI or I2C. 9 * The data format accepted is I2S or left-justified. 10 * DAPM support not implemented. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/regulator/consumer.h> 20 #include <sound/pcm.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include <sound/cs4271.h> 24 #include "cs4271.h" 25 26 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 27 SNDRV_PCM_FMTBIT_S24_LE | \ 28 SNDRV_PCM_FMTBIT_S32_LE) 29 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 30 31 /* 32 * CS4271 registers 33 */ 34 #define CS4271_MODE1 0x01 /* Mode Control 1 */ 35 #define CS4271_DACCTL 0x02 /* DAC Control */ 36 #define CS4271_DACVOL 0x03 /* DAC Volume & Mixing Control */ 37 #define CS4271_VOLA 0x04 /* DAC Channel A Volume Control */ 38 #define CS4271_VOLB 0x05 /* DAC Channel B Volume Control */ 39 #define CS4271_ADCCTL 0x06 /* ADC Control */ 40 #define CS4271_MODE2 0x07 /* Mode Control 2 */ 41 #define CS4271_CHIPID 0x08 /* Chip ID */ 42 43 #define CS4271_FIRSTREG CS4271_MODE1 44 #define CS4271_LASTREG CS4271_MODE2 45 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) 46 47 /* Bit masks for the CS4271 registers */ 48 #define CS4271_MODE1_MODE_MASK 0xC0 49 #define CS4271_MODE1_MODE_1X 0x00 50 #define CS4271_MODE1_MODE_2X 0x80 51 #define CS4271_MODE1_MODE_4X 0xC0 52 53 #define CS4271_MODE1_DIV_MASK 0x30 54 #define CS4271_MODE1_DIV_1 0x00 55 #define CS4271_MODE1_DIV_15 0x10 56 #define CS4271_MODE1_DIV_2 0x20 57 #define CS4271_MODE1_DIV_3 0x30 58 59 #define CS4271_MODE1_MASTER 0x08 60 61 #define CS4271_MODE1_DAC_DIF_MASK 0x07 62 #define CS4271_MODE1_DAC_DIF_LJ 0x00 63 #define CS4271_MODE1_DAC_DIF_I2S 0x01 64 #define CS4271_MODE1_DAC_DIF_RJ16 0x02 65 #define CS4271_MODE1_DAC_DIF_RJ24 0x03 66 #define CS4271_MODE1_DAC_DIF_RJ20 0x04 67 #define CS4271_MODE1_DAC_DIF_RJ18 0x05 68 69 #define CS4271_DACCTL_AMUTE 0x80 70 #define CS4271_DACCTL_IF_SLOW 0x40 71 72 #define CS4271_DACCTL_DEM_MASK 0x30 73 #define CS4271_DACCTL_DEM_DIS 0x00 74 #define CS4271_DACCTL_DEM_441 0x10 75 #define CS4271_DACCTL_DEM_48 0x20 76 #define CS4271_DACCTL_DEM_32 0x30 77 78 #define CS4271_DACCTL_SVRU 0x08 79 #define CS4271_DACCTL_SRD 0x04 80 #define CS4271_DACCTL_INVA 0x02 81 #define CS4271_DACCTL_INVB 0x01 82 83 #define CS4271_DACVOL_BEQUA 0x40 84 #define CS4271_DACVOL_SOFT 0x20 85 #define CS4271_DACVOL_ZEROC 0x10 86 87 #define CS4271_DACVOL_ATAPI_MASK 0x0F 88 #define CS4271_DACVOL_ATAPI_M_M 0x00 89 #define CS4271_DACVOL_ATAPI_M_BR 0x01 90 #define CS4271_DACVOL_ATAPI_M_BL 0x02 91 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 92 #define CS4271_DACVOL_ATAPI_AR_M 0x04 93 #define CS4271_DACVOL_ATAPI_AR_BR 0x05 94 #define CS4271_DACVOL_ATAPI_AR_BL 0x06 95 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 96 #define CS4271_DACVOL_ATAPI_AL_M 0x08 97 #define CS4271_DACVOL_ATAPI_AL_BR 0x09 98 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A 99 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B 100 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C 101 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D 102 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E 103 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F 104 105 #define CS4271_VOLA_MUTE 0x80 106 #define CS4271_VOLA_VOL_MASK 0x7F 107 #define CS4271_VOLB_MUTE 0x80 108 #define CS4271_VOLB_VOL_MASK 0x7F 109 110 #define CS4271_ADCCTL_DITHER16 0x20 111 112 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 113 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 114 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 115 116 #define CS4271_ADCCTL_MUTEA 0x08 117 #define CS4271_ADCCTL_MUTEB 0x04 118 #define CS4271_ADCCTL_HPFDA 0x02 119 #define CS4271_ADCCTL_HPFDB 0x01 120 121 #define CS4271_MODE2_LOOP 0x10 122 #define CS4271_MODE2_MUTECAEQUB 0x08 123 #define CS4271_MODE2_FREEZE 0x04 124 #define CS4271_MODE2_CPEN 0x02 125 #define CS4271_MODE2_PDN 0x01 126 127 #define CS4271_CHIPID_PART_MASK 0xF0 128 #define CS4271_CHIPID_REV_MASK 0x0F 129 130 /* 131 * Default CS4271 power-up configuration 132 * Array contains non-existing in hw register at address 0 133 * Array do not include Chip ID, as codec driver does not use 134 * registers read operations at all 135 */ 136 static const struct reg_default cs4271_reg_defaults[] = { 137 { CS4271_MODE1, 0, }, 138 { CS4271_DACCTL, CS4271_DACCTL_AMUTE, }, 139 { CS4271_DACVOL, CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, }, 140 { CS4271_VOLA, 0, }, 141 { CS4271_VOLB, 0, }, 142 { CS4271_ADCCTL, 0, }, 143 { CS4271_MODE2, 0, }, 144 }; 145 146 static bool cs4271_volatile_reg(struct device *dev, unsigned int reg) 147 { 148 return reg == CS4271_CHIPID; 149 } 150 151 static const char * const supply_names[] = { 152 "vd", "vl", "va" 153 }; 154 155 struct cs4271_private { 156 unsigned int mclk; 157 bool master; 158 bool deemph; 159 struct regmap *regmap; 160 /* Current sample rate for de-emphasis control */ 161 int rate; 162 /* GPIO driving Reset pin, if any */ 163 int gpio_nreset; 164 /* GPIO that disable serial bus, if any */ 165 int gpio_disable; 166 /* enable soft reset workaround */ 167 bool enable_soft_reset; 168 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 169 }; 170 171 static const struct snd_soc_dapm_widget cs4271_dapm_widgets[] = { 172 SND_SOC_DAPM_INPUT("AINA"), 173 SND_SOC_DAPM_INPUT("AINB"), 174 175 SND_SOC_DAPM_OUTPUT("AOUTA+"), 176 SND_SOC_DAPM_OUTPUT("AOUTA-"), 177 SND_SOC_DAPM_OUTPUT("AOUTB+"), 178 SND_SOC_DAPM_OUTPUT("AOUTB-"), 179 }; 180 181 static const struct snd_soc_dapm_route cs4271_dapm_routes[] = { 182 { "Capture", NULL, "AINA" }, 183 { "Capture", NULL, "AINB" }, 184 185 { "AOUTA+", NULL, "Playback" }, 186 { "AOUTA-", NULL, "Playback" }, 187 { "AOUTB+", NULL, "Playback" }, 188 { "AOUTB-", NULL, "Playback" }, 189 }; 190 191 /* 192 * @freq is the desired MCLK rate 193 * MCLK rate should (c) be the sample rate, multiplied by one of the 194 * ratios listed in cs4271_mclk_fs_ratios table 195 */ 196 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, 197 int clk_id, unsigned int freq, int dir) 198 { 199 struct snd_soc_component *component = codec_dai->component; 200 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 201 202 cs4271->mclk = freq; 203 return 0; 204 } 205 206 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, 207 unsigned int format) 208 { 209 struct snd_soc_component *component = codec_dai->component; 210 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 211 unsigned int val = 0; 212 int ret; 213 214 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 215 case SND_SOC_DAIFMT_CBS_CFS: 216 cs4271->master = false; 217 break; 218 case SND_SOC_DAIFMT_CBM_CFM: 219 cs4271->master = true; 220 val |= CS4271_MODE1_MASTER; 221 break; 222 default: 223 dev_err(component->dev, "Invalid DAI format\n"); 224 return -EINVAL; 225 } 226 227 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 228 case SND_SOC_DAIFMT_LEFT_J: 229 val |= CS4271_MODE1_DAC_DIF_LJ; 230 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 231 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); 232 if (ret < 0) 233 return ret; 234 break; 235 case SND_SOC_DAIFMT_I2S: 236 val |= CS4271_MODE1_DAC_DIF_I2S; 237 ret = regmap_update_bits(cs4271->regmap, CS4271_ADCCTL, 238 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); 239 if (ret < 0) 240 return ret; 241 break; 242 default: 243 dev_err(component->dev, "Invalid DAI format\n"); 244 return -EINVAL; 245 } 246 247 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 248 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); 249 if (ret < 0) 250 return ret; 251 return 0; 252 } 253 254 static int cs4271_deemph[] = {0, 44100, 48000, 32000}; 255 256 static int cs4271_set_deemph(struct snd_soc_component *component) 257 { 258 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 259 int i, ret; 260 int val = CS4271_DACCTL_DEM_DIS; 261 262 if (cs4271->deemph) { 263 /* Find closest de-emphasis freq */ 264 val = 1; 265 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) 266 if (abs(cs4271_deemph[i] - cs4271->rate) < 267 abs(cs4271_deemph[val] - cs4271->rate)) 268 val = i; 269 val <<= 4; 270 } 271 272 ret = regmap_update_bits(cs4271->regmap, CS4271_DACCTL, 273 CS4271_DACCTL_DEM_MASK, val); 274 if (ret < 0) 275 return ret; 276 return 0; 277 } 278 279 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 280 struct snd_ctl_elem_value *ucontrol) 281 { 282 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 283 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 284 285 ucontrol->value.integer.value[0] = cs4271->deemph; 286 return 0; 287 } 288 289 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 290 struct snd_ctl_elem_value *ucontrol) 291 { 292 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 293 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 294 295 cs4271->deemph = ucontrol->value.integer.value[0]; 296 return cs4271_set_deemph(component); 297 } 298 299 struct cs4271_clk_cfg { 300 bool master; /* codec mode */ 301 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ 302 unsigned short ratio; /* MCLK / sample rate */ 303 u8 ratio_mask; /* ratio bit mask for Master mode */ 304 }; 305 306 static struct cs4271_clk_cfg cs4271_clk_tab[] = { 307 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 308 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, 309 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, 310 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, 311 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 312 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, 313 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, 314 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, 315 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 316 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, 317 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, 318 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, 319 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 320 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, 321 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, 322 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, 323 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, 324 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 325 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, 326 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, 327 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, 328 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, 329 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 330 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, 331 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, 332 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, 333 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, 334 }; 335 336 #define CS4271_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) 337 338 static int cs4271_hw_params(struct snd_pcm_substream *substream, 339 struct snd_pcm_hw_params *params, 340 struct snd_soc_dai *dai) 341 { 342 struct snd_soc_component *component = dai->component; 343 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 344 int i, ret; 345 unsigned int ratio, val; 346 347 if (cs4271->enable_soft_reset) { 348 /* 349 * Put the codec in soft reset and back again in case it's not 350 * currently streaming data. This way of bringing the codec in 351 * sync to the current clocks is not explicitly documented in 352 * the data sheet, but it seems to work fine, and in contrast 353 * to a read hardware reset, we don't have to sync back all 354 * registers every time. 355 */ 356 357 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 358 !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_CAPTURE)) || 359 (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 360 !snd_soc_dai_stream_active(dai, SNDRV_PCM_STREAM_PLAYBACK))) { 361 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 362 CS4271_MODE2_PDN, 363 CS4271_MODE2_PDN); 364 if (ret < 0) 365 return ret; 366 367 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 368 CS4271_MODE2_PDN, 0); 369 if (ret < 0) 370 return ret; 371 } 372 } 373 374 cs4271->rate = params_rate(params); 375 376 /* Configure DAC */ 377 if (cs4271->rate < 50000) 378 val = CS4271_MODE1_MODE_1X; 379 else if (cs4271->rate < 100000) 380 val = CS4271_MODE1_MODE_2X; 381 else 382 val = CS4271_MODE1_MODE_4X; 383 384 ratio = cs4271->mclk / cs4271->rate; 385 for (i = 0; i < CS4271_NR_RATIOS; i++) 386 if ((cs4271_clk_tab[i].master == cs4271->master) && 387 (cs4271_clk_tab[i].speed_mode == val) && 388 (cs4271_clk_tab[i].ratio == ratio)) 389 break; 390 391 if (i == CS4271_NR_RATIOS) { 392 dev_err(component->dev, "Invalid sample rate\n"); 393 return -EINVAL; 394 } 395 396 val |= cs4271_clk_tab[i].ratio_mask; 397 398 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE1, 399 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); 400 if (ret < 0) 401 return ret; 402 403 return cs4271_set_deemph(component); 404 } 405 406 static int cs4271_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 407 { 408 struct snd_soc_component *component = dai->component; 409 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 410 int ret; 411 int val_a = 0; 412 int val_b = 0; 413 414 if (stream != SNDRV_PCM_STREAM_PLAYBACK) 415 return 0; 416 417 if (mute) { 418 val_a = CS4271_VOLA_MUTE; 419 val_b = CS4271_VOLB_MUTE; 420 } 421 422 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLA, 423 CS4271_VOLA_MUTE, val_a); 424 if (ret < 0) 425 return ret; 426 427 ret = regmap_update_bits(cs4271->regmap, CS4271_VOLB, 428 CS4271_VOLB_MUTE, val_b); 429 if (ret < 0) 430 return ret; 431 432 return 0; 433 } 434 435 /* CS4271 controls */ 436 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); 437 438 static const struct snd_kcontrol_new cs4271_snd_controls[] = { 439 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, 440 0, 0x7F, 1, cs4271_dac_tlv), 441 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), 442 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), 443 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), 444 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 445 cs4271_get_deemph, cs4271_put_deemph), 446 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), 447 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), 448 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), 449 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), 450 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), 451 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), 452 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), 453 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), 454 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), 455 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, 456 7, 1, 1), 457 }; 458 459 static const struct snd_soc_dai_ops cs4271_dai_ops = { 460 .hw_params = cs4271_hw_params, 461 .set_sysclk = cs4271_set_dai_sysclk, 462 .set_fmt = cs4271_set_dai_fmt, 463 .mute_stream = cs4271_mute_stream, 464 }; 465 466 static struct snd_soc_dai_driver cs4271_dai = { 467 .name = "cs4271-hifi", 468 .playback = { 469 .stream_name = "Playback", 470 .channels_min = 2, 471 .channels_max = 2, 472 .rates = CS4271_PCM_RATES, 473 .formats = CS4271_PCM_FORMATS, 474 }, 475 .capture = { 476 .stream_name = "Capture", 477 .channels_min = 2, 478 .channels_max = 2, 479 .rates = CS4271_PCM_RATES, 480 .formats = CS4271_PCM_FORMATS, 481 }, 482 .ops = &cs4271_dai_ops, 483 .symmetric_rate = 1, 484 }; 485 486 static int cs4271_reset(struct snd_soc_component *component) 487 { 488 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 489 490 if (gpio_is_valid(cs4271->gpio_nreset)) { 491 gpio_direction_output(cs4271->gpio_nreset, 0); 492 mdelay(1); 493 gpio_set_value(cs4271->gpio_nreset, 1); 494 mdelay(1); 495 } 496 497 return 0; 498 } 499 500 #ifdef CONFIG_PM 501 static int cs4271_soc_suspend(struct snd_soc_component *component) 502 { 503 int ret; 504 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 505 506 /* Set power-down bit */ 507 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 508 CS4271_MODE2_PDN, CS4271_MODE2_PDN); 509 if (ret < 0) 510 return ret; 511 512 regcache_mark_dirty(cs4271->regmap); 513 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); 514 515 return 0; 516 } 517 518 static int cs4271_soc_resume(struct snd_soc_component *component) 519 { 520 int ret; 521 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 522 523 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies), 524 cs4271->supplies); 525 if (ret < 0) { 526 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); 527 return ret; 528 } 529 530 /* Do a proper reset after power up */ 531 cs4271_reset(component); 532 533 /* Restore codec state */ 534 ret = regcache_sync(cs4271->regmap); 535 if (ret < 0) 536 return ret; 537 538 /* then disable the power-down bit */ 539 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 540 CS4271_MODE2_PDN, 0); 541 if (ret < 0) 542 return ret; 543 544 return 0; 545 } 546 #else 547 #define cs4271_soc_suspend NULL 548 #define cs4271_soc_resume NULL 549 #endif /* CONFIG_PM */ 550 551 #ifdef CONFIG_OF 552 const struct of_device_id cs4271_dt_ids[] = { 553 { .compatible = "cirrus,cs4271", }, 554 { } 555 }; 556 MODULE_DEVICE_TABLE(of, cs4271_dt_ids); 557 EXPORT_SYMBOL_GPL(cs4271_dt_ids); 558 #endif 559 560 static int cs4271_component_probe(struct snd_soc_component *component) 561 { 562 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 563 struct cs4271_platform_data *cs4271plat = component->dev->platform_data; 564 int ret; 565 bool amutec_eq_bmutec; 566 567 amutec_eq_bmutec = of_property_read_bool(component->dev->of_node, 568 "cirrus,amutec-eq-bmutec"); 569 cs4271->enable_soft_reset = of_property_read_bool(component->dev->of_node, 570 "cirrus,enable-soft-reset"); 571 572 ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies), 573 cs4271->supplies); 574 if (ret < 0) { 575 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); 576 return ret; 577 } 578 579 if (cs4271plat) { 580 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; 581 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset; 582 } 583 584 /* Reset codec */ 585 cs4271_reset(component); 586 587 ret = regcache_sync(cs4271->regmap); 588 if (ret < 0) 589 return ret; 590 591 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 592 CS4271_MODE2_PDN | CS4271_MODE2_CPEN, 593 CS4271_MODE2_PDN | CS4271_MODE2_CPEN); 594 if (ret < 0) 595 return ret; 596 ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, 597 CS4271_MODE2_PDN, 0); 598 if (ret < 0) 599 return ret; 600 /* Power-up sequence requires 85 uS */ 601 udelay(85); 602 603 if (amutec_eq_bmutec) 604 regmap_update_bits(cs4271->regmap, CS4271_MODE2, 605 CS4271_MODE2_MUTECAEQUB, 606 CS4271_MODE2_MUTECAEQUB); 607 608 return 0; 609 } 610 611 static void cs4271_component_remove(struct snd_soc_component *component) 612 { 613 struct cs4271_private *cs4271 = snd_soc_component_get_drvdata(component); 614 615 if (gpio_is_valid(cs4271->gpio_nreset)) 616 /* Set codec to the reset state */ 617 gpio_set_value(cs4271->gpio_nreset, 0); 618 619 regcache_mark_dirty(cs4271->regmap); 620 regulator_bulk_disable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); 621 }; 622 623 static const struct snd_soc_component_driver soc_component_dev_cs4271 = { 624 .probe = cs4271_component_probe, 625 .remove = cs4271_component_remove, 626 .suspend = cs4271_soc_suspend, 627 .resume = cs4271_soc_resume, 628 .controls = cs4271_snd_controls, 629 .num_controls = ARRAY_SIZE(cs4271_snd_controls), 630 .dapm_widgets = cs4271_dapm_widgets, 631 .num_dapm_widgets = ARRAY_SIZE(cs4271_dapm_widgets), 632 .dapm_routes = cs4271_dapm_routes, 633 .num_dapm_routes = ARRAY_SIZE(cs4271_dapm_routes), 634 .idle_bias_on = 1, 635 .use_pmdown_time = 1, 636 .endianness = 1, 637 }; 638 639 static int cs4271_common_probe(struct device *dev, 640 struct cs4271_private **c) 641 { 642 struct cs4271_platform_data *cs4271plat = dev->platform_data; 643 struct cs4271_private *cs4271; 644 int i, ret; 645 646 cs4271 = devm_kzalloc(dev, sizeof(*cs4271), GFP_KERNEL); 647 if (!cs4271) 648 return -ENOMEM; 649 650 cs4271->gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0); 651 652 if (cs4271plat) 653 cs4271->gpio_nreset = cs4271plat->gpio_nreset; 654 655 if (gpio_is_valid(cs4271->gpio_nreset)) { 656 ret = devm_gpio_request(dev, cs4271->gpio_nreset, 657 "CS4271 Reset"); 658 if (ret < 0) 659 return ret; 660 } 661 662 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 663 cs4271->supplies[i].supply = supply_names[i]; 664 665 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs4271->supplies), 666 cs4271->supplies); 667 668 if (ret < 0) { 669 dev_err(dev, "Failed to get regulators: %d\n", ret); 670 return ret; 671 } 672 673 *c = cs4271; 674 return 0; 675 } 676 677 const struct regmap_config cs4271_regmap_config = { 678 .max_register = CS4271_LASTREG, 679 680 .reg_defaults = cs4271_reg_defaults, 681 .num_reg_defaults = ARRAY_SIZE(cs4271_reg_defaults), 682 .cache_type = REGCACHE_FLAT, 683 .val_bits = 8, 684 .volatile_reg = cs4271_volatile_reg, 685 }; 686 EXPORT_SYMBOL_GPL(cs4271_regmap_config); 687 688 int cs4271_probe(struct device *dev, struct regmap *regmap) 689 { 690 struct cs4271_private *cs4271; 691 int ret; 692 693 if (IS_ERR(regmap)) 694 return PTR_ERR(regmap); 695 696 ret = cs4271_common_probe(dev, &cs4271); 697 if (ret < 0) 698 return ret; 699 700 dev_set_drvdata(dev, cs4271); 701 cs4271->regmap = regmap; 702 703 return devm_snd_soc_register_component(dev, &soc_component_dev_cs4271, 704 &cs4271_dai, 1); 705 } 706 EXPORT_SYMBOL_GPL(cs4271_probe); 707 708 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); 709 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); 710 MODULE_LICENSE("GPL"); 711