1 /* 2 * CS4271 ASoC codec driver 3 * 4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * This driver support CS4271 codec being master or slave, working 17 * in control port mode, connected either via SPI or I2C. 18 * The data format accepted is I2S or left-justified. 19 * DAPM support not implemented. 20 */ 21 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/delay.h> 25 #include <linux/gpio.h> 26 #include <linux/i2c.h> 27 #include <linux/spi/spi.h> 28 #include <linux/of_device.h> 29 #include <linux/of_gpio.h> 30 #include <sound/pcm.h> 31 #include <sound/soc.h> 32 #include <sound/tlv.h> 33 #include <sound/cs4271.h> 34 35 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE | \ 37 SNDRV_PCM_FMTBIT_S32_LE) 38 #define CS4271_PCM_RATES SNDRV_PCM_RATE_8000_192000 39 40 /* 41 * CS4271 registers 42 * High byte represents SPI chip address (0x10) + write command (0) 43 * Low byte - codec register address 44 */ 45 #define CS4271_MODE1 0x2001 /* Mode Control 1 */ 46 #define CS4271_DACCTL 0x2002 /* DAC Control */ 47 #define CS4271_DACVOL 0x2003 /* DAC Volume & Mixing Control */ 48 #define CS4271_VOLA 0x2004 /* DAC Channel A Volume Control */ 49 #define CS4271_VOLB 0x2005 /* DAC Channel B Volume Control */ 50 #define CS4271_ADCCTL 0x2006 /* ADC Control */ 51 #define CS4271_MODE2 0x2007 /* Mode Control 2 */ 52 #define CS4271_CHIPID 0x2008 /* Chip ID */ 53 54 #define CS4271_FIRSTREG CS4271_MODE1 55 #define CS4271_LASTREG CS4271_MODE2 56 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1) 57 58 /* Bit masks for the CS4271 registers */ 59 #define CS4271_MODE1_MODE_MASK 0xC0 60 #define CS4271_MODE1_MODE_1X 0x00 61 #define CS4271_MODE1_MODE_2X 0x80 62 #define CS4271_MODE1_MODE_4X 0xC0 63 64 #define CS4271_MODE1_DIV_MASK 0x30 65 #define CS4271_MODE1_DIV_1 0x00 66 #define CS4271_MODE1_DIV_15 0x10 67 #define CS4271_MODE1_DIV_2 0x20 68 #define CS4271_MODE1_DIV_3 0x30 69 70 #define CS4271_MODE1_MASTER 0x08 71 72 #define CS4271_MODE1_DAC_DIF_MASK 0x07 73 #define CS4271_MODE1_DAC_DIF_LJ 0x00 74 #define CS4271_MODE1_DAC_DIF_I2S 0x01 75 #define CS4271_MODE1_DAC_DIF_RJ16 0x02 76 #define CS4271_MODE1_DAC_DIF_RJ24 0x03 77 #define CS4271_MODE1_DAC_DIF_RJ20 0x04 78 #define CS4271_MODE1_DAC_DIF_RJ18 0x05 79 80 #define CS4271_DACCTL_AMUTE 0x80 81 #define CS4271_DACCTL_IF_SLOW 0x40 82 83 #define CS4271_DACCTL_DEM_MASK 0x30 84 #define CS4271_DACCTL_DEM_DIS 0x00 85 #define CS4271_DACCTL_DEM_441 0x10 86 #define CS4271_DACCTL_DEM_48 0x20 87 #define CS4271_DACCTL_DEM_32 0x30 88 89 #define CS4271_DACCTL_SVRU 0x08 90 #define CS4271_DACCTL_SRD 0x04 91 #define CS4271_DACCTL_INVA 0x02 92 #define CS4271_DACCTL_INVB 0x01 93 94 #define CS4271_DACVOL_BEQUA 0x40 95 #define CS4271_DACVOL_SOFT 0x20 96 #define CS4271_DACVOL_ZEROC 0x10 97 98 #define CS4271_DACVOL_ATAPI_MASK 0x0F 99 #define CS4271_DACVOL_ATAPI_M_M 0x00 100 #define CS4271_DACVOL_ATAPI_M_BR 0x01 101 #define CS4271_DACVOL_ATAPI_M_BL 0x02 102 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03 103 #define CS4271_DACVOL_ATAPI_AR_M 0x04 104 #define CS4271_DACVOL_ATAPI_AR_BR 0x05 105 #define CS4271_DACVOL_ATAPI_AR_BL 0x06 106 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07 107 #define CS4271_DACVOL_ATAPI_AL_M 0x08 108 #define CS4271_DACVOL_ATAPI_AL_BR 0x09 109 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A 110 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B 111 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C 112 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D 113 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E 114 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F 115 116 #define CS4271_VOLA_MUTE 0x80 117 #define CS4271_VOLA_VOL_MASK 0x7F 118 #define CS4271_VOLB_MUTE 0x80 119 #define CS4271_VOLB_VOL_MASK 0x7F 120 121 #define CS4271_ADCCTL_DITHER16 0x20 122 123 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10 124 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00 125 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10 126 127 #define CS4271_ADCCTL_MUTEA 0x08 128 #define CS4271_ADCCTL_MUTEB 0x04 129 #define CS4271_ADCCTL_HPFDA 0x02 130 #define CS4271_ADCCTL_HPFDB 0x01 131 132 #define CS4271_MODE2_LOOP 0x10 133 #define CS4271_MODE2_MUTECAEQUB 0x08 134 #define CS4271_MODE2_FREEZE 0x04 135 #define CS4271_MODE2_CPEN 0x02 136 #define CS4271_MODE2_PDN 0x01 137 138 #define CS4271_CHIPID_PART_MASK 0xF0 139 #define CS4271_CHIPID_REV_MASK 0x0F 140 141 /* 142 * Default CS4271 power-up configuration 143 * Array contains non-existing in hw register at address 0 144 * Array do not include Chip ID, as codec driver does not use 145 * registers read operations at all 146 */ 147 static const u8 cs4271_dflt_reg[CS4271_NR_REGS] = { 148 0, 149 0, 150 CS4271_DACCTL_AMUTE, 151 CS4271_DACVOL_SOFT | CS4271_DACVOL_ATAPI_AL_BR, 152 0, 153 0, 154 0, 155 0, 156 }; 157 158 struct cs4271_private { 159 /* SND_SOC_I2C or SND_SOC_SPI */ 160 enum snd_soc_control_type bus_type; 161 unsigned int mclk; 162 bool master; 163 bool deemph; 164 /* Current sample rate for de-emphasis control */ 165 int rate; 166 /* GPIO driving Reset pin, if any */ 167 int gpio_nreset; 168 /* GPIO that disable serial bus, if any */ 169 int gpio_disable; 170 }; 171 172 /* 173 * @freq is the desired MCLK rate 174 * MCLK rate should (c) be the sample rate, multiplied by one of the 175 * ratios listed in cs4271_mclk_fs_ratios table 176 */ 177 static int cs4271_set_dai_sysclk(struct snd_soc_dai *codec_dai, 178 int clk_id, unsigned int freq, int dir) 179 { 180 struct snd_soc_codec *codec = codec_dai->codec; 181 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 182 183 cs4271->mclk = freq; 184 return 0; 185 } 186 187 static int cs4271_set_dai_fmt(struct snd_soc_dai *codec_dai, 188 unsigned int format) 189 { 190 struct snd_soc_codec *codec = codec_dai->codec; 191 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 192 unsigned int val = 0; 193 int ret; 194 195 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 196 case SND_SOC_DAIFMT_CBS_CFS: 197 cs4271->master = 0; 198 break; 199 case SND_SOC_DAIFMT_CBM_CFM: 200 cs4271->master = 1; 201 val |= CS4271_MODE1_MASTER; 202 break; 203 default: 204 dev_err(codec->dev, "Invalid DAI format\n"); 205 return -EINVAL; 206 } 207 208 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { 209 case SND_SOC_DAIFMT_LEFT_J: 210 val |= CS4271_MODE1_DAC_DIF_LJ; 211 ret = snd_soc_update_bits(codec, CS4271_ADCCTL, 212 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_LJ); 213 if (ret < 0) 214 return ret; 215 break; 216 case SND_SOC_DAIFMT_I2S: 217 val |= CS4271_MODE1_DAC_DIF_I2S; 218 ret = snd_soc_update_bits(codec, CS4271_ADCCTL, 219 CS4271_ADCCTL_ADC_DIF_MASK, CS4271_ADCCTL_ADC_DIF_I2S); 220 if (ret < 0) 221 return ret; 222 break; 223 default: 224 dev_err(codec->dev, "Invalid DAI format\n"); 225 return -EINVAL; 226 } 227 228 ret = snd_soc_update_bits(codec, CS4271_MODE1, 229 CS4271_MODE1_DAC_DIF_MASK | CS4271_MODE1_MASTER, val); 230 if (ret < 0) 231 return ret; 232 return 0; 233 } 234 235 static int cs4271_deemph[] = {0, 44100, 48000, 32000}; 236 237 static int cs4271_set_deemph(struct snd_soc_codec *codec) 238 { 239 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 240 int i, ret; 241 int val = CS4271_DACCTL_DEM_DIS; 242 243 if (cs4271->deemph) { 244 /* Find closest de-emphasis freq */ 245 val = 1; 246 for (i = 2; i < ARRAY_SIZE(cs4271_deemph); i++) 247 if (abs(cs4271_deemph[i] - cs4271->rate) < 248 abs(cs4271_deemph[val] - cs4271->rate)) 249 val = i; 250 val <<= 4; 251 } 252 253 ret = snd_soc_update_bits(codec, CS4271_DACCTL, 254 CS4271_DACCTL_DEM_MASK, val); 255 if (ret < 0) 256 return ret; 257 return 0; 258 } 259 260 static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 261 struct snd_ctl_elem_value *ucontrol) 262 { 263 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 264 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 265 266 ucontrol->value.enumerated.item[0] = cs4271->deemph; 267 return 0; 268 } 269 270 static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 271 struct snd_ctl_elem_value *ucontrol) 272 { 273 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 274 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 275 276 cs4271->deemph = ucontrol->value.enumerated.item[0]; 277 return cs4271_set_deemph(codec); 278 } 279 280 struct cs4271_clk_cfg { 281 bool master; /* codec mode */ 282 u8 speed_mode; /* codec speed mode: 1x, 2x, 4x */ 283 unsigned short ratio; /* MCLK / sample rate */ 284 u8 ratio_mask; /* ratio bit mask for Master mode */ 285 }; 286 287 static struct cs4271_clk_cfg cs4271_clk_tab[] = { 288 {1, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 289 {1, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_15}, 290 {1, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_2}, 291 {1, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_3}, 292 {1, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 293 {1, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_15}, 294 {1, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_2}, 295 {1, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_3}, 296 {1, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 297 {1, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_15}, 298 {1, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_2}, 299 {1, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_3}, 300 {0, CS4271_MODE1_MODE_1X, 256, CS4271_MODE1_DIV_1}, 301 {0, CS4271_MODE1_MODE_1X, 384, CS4271_MODE1_DIV_1}, 302 {0, CS4271_MODE1_MODE_1X, 512, CS4271_MODE1_DIV_1}, 303 {0, CS4271_MODE1_MODE_1X, 768, CS4271_MODE1_DIV_2}, 304 {0, CS4271_MODE1_MODE_1X, 1024, CS4271_MODE1_DIV_2}, 305 {0, CS4271_MODE1_MODE_2X, 128, CS4271_MODE1_DIV_1}, 306 {0, CS4271_MODE1_MODE_2X, 192, CS4271_MODE1_DIV_1}, 307 {0, CS4271_MODE1_MODE_2X, 256, CS4271_MODE1_DIV_1}, 308 {0, CS4271_MODE1_MODE_2X, 384, CS4271_MODE1_DIV_2}, 309 {0, CS4271_MODE1_MODE_2X, 512, CS4271_MODE1_DIV_2}, 310 {0, CS4271_MODE1_MODE_4X, 64, CS4271_MODE1_DIV_1}, 311 {0, CS4271_MODE1_MODE_4X, 96, CS4271_MODE1_DIV_1}, 312 {0, CS4271_MODE1_MODE_4X, 128, CS4271_MODE1_DIV_1}, 313 {0, CS4271_MODE1_MODE_4X, 192, CS4271_MODE1_DIV_2}, 314 {0, CS4271_MODE1_MODE_4X, 256, CS4271_MODE1_DIV_2}, 315 }; 316 317 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab) 318 319 static int cs4271_hw_params(struct snd_pcm_substream *substream, 320 struct snd_pcm_hw_params *params, 321 struct snd_soc_dai *dai) 322 { 323 struct snd_soc_codec *codec = dai->codec; 324 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 325 int i, ret; 326 unsigned int ratio, val; 327 328 cs4271->rate = params_rate(params); 329 330 /* Configure DAC */ 331 if (cs4271->rate < 50000) 332 val = CS4271_MODE1_MODE_1X; 333 else if (cs4271->rate < 100000) 334 val = CS4271_MODE1_MODE_2X; 335 else 336 val = CS4271_MODE1_MODE_4X; 337 338 ratio = cs4271->mclk / cs4271->rate; 339 for (i = 0; i < CS4171_NR_RATIOS; i++) 340 if ((cs4271_clk_tab[i].master == cs4271->master) && 341 (cs4271_clk_tab[i].speed_mode == val) && 342 (cs4271_clk_tab[i].ratio == ratio)) 343 break; 344 345 if (i == CS4171_NR_RATIOS) { 346 dev_err(codec->dev, "Invalid sample rate\n"); 347 return -EINVAL; 348 } 349 350 val |= cs4271_clk_tab[i].ratio_mask; 351 352 ret = snd_soc_update_bits(codec, CS4271_MODE1, 353 CS4271_MODE1_MODE_MASK | CS4271_MODE1_DIV_MASK, val); 354 if (ret < 0) 355 return ret; 356 357 return cs4271_set_deemph(codec); 358 } 359 360 static int cs4271_digital_mute(struct snd_soc_dai *dai, int mute) 361 { 362 struct snd_soc_codec *codec = dai->codec; 363 int ret; 364 int val_a = 0; 365 int val_b = 0; 366 367 if (mute) { 368 val_a = CS4271_VOLA_MUTE; 369 val_b = CS4271_VOLB_MUTE; 370 } 371 372 ret = snd_soc_update_bits(codec, CS4271_VOLA, CS4271_VOLA_MUTE, val_a); 373 if (ret < 0) 374 return ret; 375 ret = snd_soc_update_bits(codec, CS4271_VOLB, CS4271_VOLB_MUTE, val_b); 376 if (ret < 0) 377 return ret; 378 379 return 0; 380 } 381 382 /* CS4271 controls */ 383 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv, -12700, 100, 0); 384 385 static const struct snd_kcontrol_new cs4271_snd_controls[] = { 386 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA, CS4271_VOLB, 387 0, 0x7F, 1, cs4271_dac_tlv), 388 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2, 4, 1, 0), 389 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL, 5, 1, 0), 390 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL, 4, 1, 0), 391 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 392 cs4271_get_deemph, cs4271_put_deemph), 393 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL, 7, 1, 0), 394 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL, 6, 1, 0), 395 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL, 3, 1, 0), 396 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL, 2, 1, 0), 397 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL, 1, 1, 0), 398 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL, 0, 1, 0), 399 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL, 3, 2, 1, 1), 400 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL, 5, 1, 0), 401 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL, 1, 0, 1, 1), 402 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA, CS4271_VOLB, 403 7, 1, 1), 404 }; 405 406 static const struct snd_soc_dai_ops cs4271_dai_ops = { 407 .hw_params = cs4271_hw_params, 408 .set_sysclk = cs4271_set_dai_sysclk, 409 .set_fmt = cs4271_set_dai_fmt, 410 .digital_mute = cs4271_digital_mute, 411 }; 412 413 static struct snd_soc_dai_driver cs4271_dai = { 414 .name = "cs4271-hifi", 415 .playback = { 416 .stream_name = "Playback", 417 .channels_min = 2, 418 .channels_max = 2, 419 .rates = CS4271_PCM_RATES, 420 .formats = CS4271_PCM_FORMATS, 421 }, 422 .capture = { 423 .stream_name = "Capture", 424 .channels_min = 2, 425 .channels_max = 2, 426 .rates = CS4271_PCM_RATES, 427 .formats = CS4271_PCM_FORMATS, 428 }, 429 .ops = &cs4271_dai_ops, 430 .symmetric_rates = 1, 431 }; 432 433 #ifdef CONFIG_PM 434 static int cs4271_soc_suspend(struct snd_soc_codec *codec) 435 { 436 int ret; 437 /* Set power-down bit */ 438 ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 439 CS4271_MODE2_PDN); 440 if (ret < 0) 441 return ret; 442 return 0; 443 } 444 445 static int cs4271_soc_resume(struct snd_soc_codec *codec) 446 { 447 int ret; 448 /* Restore codec state */ 449 ret = snd_soc_cache_sync(codec); 450 if (ret < 0) 451 return ret; 452 /* then disable the power-down bit */ 453 ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); 454 if (ret < 0) 455 return ret; 456 return 0; 457 } 458 #else 459 #define cs4271_soc_suspend NULL 460 #define cs4271_soc_resume NULL 461 #endif /* CONFIG_PM */ 462 463 #ifdef CONFIG_OF 464 static const struct of_device_id cs4271_dt_ids[] = { 465 { .compatible = "cirrus,cs4271", }, 466 { } 467 }; 468 MODULE_DEVICE_TABLE(of, cs4271_dt_ids); 469 #endif 470 471 static int cs4271_probe(struct snd_soc_codec *codec) 472 { 473 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 474 struct cs4271_platform_data *cs4271plat = codec->dev->platform_data; 475 int ret; 476 int gpio_nreset = -EINVAL; 477 478 #ifdef CONFIG_OF 479 if (of_match_device(cs4271_dt_ids, codec->dev)) 480 gpio_nreset = of_get_named_gpio(codec->dev->of_node, 481 "reset-gpio", 0); 482 #endif 483 484 if (cs4271plat && gpio_is_valid(cs4271plat->gpio_nreset)) 485 gpio_nreset = cs4271plat->gpio_nreset; 486 487 if (gpio_nreset >= 0) 488 if (gpio_request(gpio_nreset, "CS4271 Reset")) 489 gpio_nreset = -EINVAL; 490 if (gpio_nreset >= 0) { 491 /* Reset codec */ 492 gpio_direction_output(gpio_nreset, 0); 493 udelay(1); 494 gpio_set_value(gpio_nreset, 1); 495 /* Give the codec time to wake up */ 496 udelay(1); 497 } 498 499 cs4271->gpio_nreset = gpio_nreset; 500 501 /* 502 * In case of I2C, chip address specified in board data. 503 * So cache IO operations use 8 bit codec register address. 504 * In case of SPI, chip address and register address 505 * passed together as 16 bit value. 506 * Anyway, register address is masked with 0xFF inside 507 * soc-cache code. 508 */ 509 if (cs4271->bus_type == SND_SOC_SPI) 510 ret = snd_soc_codec_set_cache_io(codec, 16, 8, 511 cs4271->bus_type); 512 else 513 ret = snd_soc_codec_set_cache_io(codec, 8, 8, 514 cs4271->bus_type); 515 if (ret) { 516 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 517 return ret; 518 } 519 520 ret = snd_soc_update_bits(codec, CS4271_MODE2, 521 CS4271_MODE2_PDN | CS4271_MODE2_CPEN, 522 CS4271_MODE2_PDN | CS4271_MODE2_CPEN); 523 if (ret < 0) 524 return ret; 525 ret = snd_soc_update_bits(codec, CS4271_MODE2, CS4271_MODE2_PDN, 0); 526 if (ret < 0) 527 return ret; 528 /* Power-up sequence requires 85 uS */ 529 udelay(85); 530 531 return snd_soc_add_codec_controls(codec, cs4271_snd_controls, 532 ARRAY_SIZE(cs4271_snd_controls)); 533 } 534 535 static int cs4271_remove(struct snd_soc_codec *codec) 536 { 537 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 538 int gpio_nreset; 539 540 gpio_nreset = cs4271->gpio_nreset; 541 542 if (gpio_is_valid(gpio_nreset)) { 543 /* Set codec to the reset state */ 544 gpio_set_value(gpio_nreset, 0); 545 gpio_free(gpio_nreset); 546 } 547 548 return 0; 549 }; 550 551 static struct snd_soc_codec_driver soc_codec_dev_cs4271 = { 552 .probe = cs4271_probe, 553 .remove = cs4271_remove, 554 .suspend = cs4271_soc_suspend, 555 .resume = cs4271_soc_resume, 556 .reg_cache_default = cs4271_dflt_reg, 557 .reg_cache_size = ARRAY_SIZE(cs4271_dflt_reg), 558 .reg_word_size = sizeof(cs4271_dflt_reg[0]), 559 .compress_type = SND_SOC_FLAT_COMPRESSION, 560 }; 561 562 #if defined(CONFIG_SPI_MASTER) 563 static int __devinit cs4271_spi_probe(struct spi_device *spi) 564 { 565 struct cs4271_private *cs4271; 566 567 cs4271 = devm_kzalloc(&spi->dev, sizeof(*cs4271), GFP_KERNEL); 568 if (!cs4271) 569 return -ENOMEM; 570 571 spi_set_drvdata(spi, cs4271); 572 cs4271->bus_type = SND_SOC_SPI; 573 574 return snd_soc_register_codec(&spi->dev, &soc_codec_dev_cs4271, 575 &cs4271_dai, 1); 576 } 577 578 static int __devexit cs4271_spi_remove(struct spi_device *spi) 579 { 580 snd_soc_unregister_codec(&spi->dev); 581 return 0; 582 } 583 584 static struct spi_driver cs4271_spi_driver = { 585 .driver = { 586 .name = "cs4271", 587 .owner = THIS_MODULE, 588 .of_match_table = of_match_ptr(cs4271_dt_ids), 589 }, 590 .probe = cs4271_spi_probe, 591 .remove = __devexit_p(cs4271_spi_remove), 592 }; 593 #endif /* defined(CONFIG_SPI_MASTER) */ 594 595 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 596 static const struct i2c_device_id cs4271_i2c_id[] = { 597 {"cs4271", 0}, 598 {} 599 }; 600 MODULE_DEVICE_TABLE(i2c, cs4271_i2c_id); 601 602 static int __devinit cs4271_i2c_probe(struct i2c_client *client, 603 const struct i2c_device_id *id) 604 { 605 struct cs4271_private *cs4271; 606 607 cs4271 = devm_kzalloc(&client->dev, sizeof(*cs4271), GFP_KERNEL); 608 if (!cs4271) 609 return -ENOMEM; 610 611 i2c_set_clientdata(client, cs4271); 612 cs4271->bus_type = SND_SOC_I2C; 613 614 return snd_soc_register_codec(&client->dev, &soc_codec_dev_cs4271, 615 &cs4271_dai, 1); 616 } 617 618 static int __devexit cs4271_i2c_remove(struct i2c_client *client) 619 { 620 snd_soc_unregister_codec(&client->dev); 621 return 0; 622 } 623 624 static struct i2c_driver cs4271_i2c_driver = { 625 .driver = { 626 .name = "cs4271", 627 .owner = THIS_MODULE, 628 .of_match_table = of_match_ptr(cs4271_dt_ids), 629 }, 630 .id_table = cs4271_i2c_id, 631 .probe = cs4271_i2c_probe, 632 .remove = __devexit_p(cs4271_i2c_remove), 633 }; 634 #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */ 635 636 /* 637 * We only register our serial bus driver here without 638 * assignment to particular chip. So if any of the below 639 * fails, there is some problem with I2C or SPI subsystem. 640 * In most cases this module will be compiled with support 641 * of only one serial bus. 642 */ 643 static int __init cs4271_modinit(void) 644 { 645 int ret; 646 647 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 648 ret = i2c_add_driver(&cs4271_i2c_driver); 649 if (ret) { 650 pr_err("Failed to register CS4271 I2C driver: %d\n", ret); 651 return ret; 652 } 653 #endif 654 655 #if defined(CONFIG_SPI_MASTER) 656 ret = spi_register_driver(&cs4271_spi_driver); 657 if (ret) { 658 pr_err("Failed to register CS4271 SPI driver: %d\n", ret); 659 return ret; 660 } 661 #endif 662 663 return 0; 664 } 665 module_init(cs4271_modinit); 666 667 static void __exit cs4271_modexit(void) 668 { 669 #if defined(CONFIG_SPI_MASTER) 670 spi_unregister_driver(&cs4271_spi_driver); 671 #endif 672 673 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 674 i2c_del_driver(&cs4271_i2c_driver); 675 #endif 676 } 677 module_exit(cs4271_modexit); 678 679 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>"); 680 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver"); 681 MODULE_LICENSE("GPL"); 682