1 // SPDX-License-Identifier: GPL-2.0-only 2 // cs4234.c -- ALSA SoC CS4234 driver 3 // 4 // Copyright (C) 2020 Cirrus Logic, Inc. and 5 // Cirrus Logic International Semiconductor Ltd. 6 // 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/jiffies.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <linux/workqueue.h> 25 26 #include "cs4234.h" 27 28 struct cs4234 { 29 struct device *dev; 30 struct regmap *regmap; 31 struct gpio_desc *reset_gpio; 32 struct regulator_bulk_data core_supplies[2]; 33 int num_core_supplies; 34 struct completion vq_ramp_complete; 35 struct delayed_work vq_ramp_delay; 36 struct clk *mclk; 37 unsigned long mclk_rate; 38 unsigned long lrclk_rate; 39 unsigned int format; 40 struct snd_ratnum rate_dividers[2]; 41 struct snd_pcm_hw_constraint_ratnums rate_constraint; 42 }; 43 44 /* -89.92dB to +6.02dB with step of 0.38dB */ 45 static const DECLARE_TLV_DB_SCALE(dac_tlv, -8992, 38, 0); 46 47 static const char * const cs4234_dac14_delay_text[] = { 48 "0us", "100us", "150us", "200us", "225us", "250us", "275us", "300us", 49 "325us", "350us", "375us", "400us", "425us", "450us", "475us", "500us", 50 }; 51 static SOC_ENUM_SINGLE_DECL(cs4234_dac14_group_delay, CS4234_TPS_CTRL, 52 CS4234_GRP_DELAY_SHIFT, cs4234_dac14_delay_text); 53 54 static const char * const cs4234_noise_gate_text[] = { 55 "72dB", "78dB", "84dB", "90dB", "96dB", "102dB", "138dB", "Disabled", 56 }; 57 static SOC_ENUM_SINGLE_DECL(cs4234_ll_noise_gate, CS4234_LOW_LAT_CTRL1, 58 CS4234_LL_NG_SHIFT, cs4234_noise_gate_text); 59 static SOC_ENUM_SINGLE_DECL(cs4234_dac14_noise_gate, CS4234_DAC_CTRL1, 60 CS4234_DAC14_NG_SHIFT, cs4234_noise_gate_text); 61 static SOC_ENUM_SINGLE_DECL(cs4234_dac5_noise_gate, CS4234_DAC_CTRL2, 62 CS4234_DAC5_NG_SHIFT, cs4234_noise_gate_text); 63 64 static const char * const cs4234_dac5_config_fltr_sel_text[] = { 65 "Interpolation Filter", "Sample and Hold" 66 }; 67 static SOC_ENUM_SINGLE_DECL(cs4234_dac5_config_fltr_sel, CS4234_DAC_CTRL1, 68 CS4234_DAC5_CFG_FLTR_SHIFT, 69 cs4234_dac5_config_fltr_sel_text); 70 71 static const char * const cs4234_mute_delay_text[] = { 72 "1x", "4x", "16x", "64x", 73 }; 74 static SOC_ENUM_SINGLE_DECL(cs4234_mute_delay, CS4234_VOLUME_MODE, 75 CS4234_MUTE_DELAY_SHIFT, cs4234_mute_delay_text); 76 77 static const char * const cs4234_minmax_delay_text[] = { 78 "1x", "2x", "4x", "8x", "16x", "32x", "64x", "128x", 79 }; 80 static SOC_ENUM_SINGLE_DECL(cs4234_min_delay, CS4234_VOLUME_MODE, 81 CS4234_MIN_DELAY_SHIFT, cs4234_minmax_delay_text); 82 static SOC_ENUM_SINGLE_DECL(cs4234_max_delay, CS4234_VOLUME_MODE, 83 CS4234_MAX_DELAY_SHIFT, cs4234_minmax_delay_text); 84 85 static int cs4234_dac14_grp_delay_put(struct snd_kcontrol *kctrl, 86 struct snd_ctl_elem_value *uctrl) 87 { 88 struct snd_soc_component *component = snd_kcontrol_chip(kctrl); 89 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component); 90 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 91 unsigned int val = 0; 92 int ret = 0; 93 94 snd_soc_dapm_mutex_lock(dapm); 95 96 regmap_read(cs4234->regmap, CS4234_ADC_CTRL2, &val); 97 if ((val & 0x0F) != 0x0F) { // are all the ADCs powerdown 98 ret = -EBUSY; 99 dev_err(component->dev, "Can't change group delay while ADC are ON\n"); 100 goto exit; 101 } 102 103 regmap_read(cs4234->regmap, CS4234_DAC_CTRL4, &val); 104 if ((val & 0x1F) != 0x1F) { // are all the DACs powerdown 105 ret = -EBUSY; 106 dev_err(component->dev, "Can't change group delay while DAC are ON\n"); 107 goto exit; 108 } 109 110 ret = snd_soc_put_enum_double(kctrl, uctrl); 111 exit: 112 snd_soc_dapm_mutex_unlock(dapm); 113 114 return ret; 115 } 116 117 static void cs4234_vq_ramp_done(struct work_struct *work) 118 { 119 struct delayed_work *dw = to_delayed_work(work); 120 struct cs4234 *cs4234 = container_of(dw, struct cs4234, vq_ramp_delay); 121 122 complete_all(&cs4234->vq_ramp_complete); 123 } 124 125 static int cs4234_set_bias_level(struct snd_soc_component *component, 126 enum snd_soc_bias_level level) 127 { 128 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component); 129 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 130 131 switch (level) { 132 case SND_SOC_BIAS_PREPARE: 133 switch (snd_soc_dapm_get_bias_level(dapm)) { 134 case SND_SOC_BIAS_STANDBY: 135 wait_for_completion(&cs4234->vq_ramp_complete); 136 break; 137 default: 138 break; 139 } 140 break; 141 default: 142 break; 143 } 144 145 return 0; 146 } 147 148 static const struct snd_soc_dapm_widget cs4234_dapm_widgets[] = { 149 SND_SOC_DAPM_AIF_IN("SDRX1", NULL, 0, SND_SOC_NOPM, 0, 0), 150 SND_SOC_DAPM_AIF_IN("SDRX2", NULL, 1, SND_SOC_NOPM, 0, 0), 151 SND_SOC_DAPM_AIF_IN("SDRX3", NULL, 2, SND_SOC_NOPM, 0, 0), 152 SND_SOC_DAPM_AIF_IN("SDRX4", NULL, 3, SND_SOC_NOPM, 0, 0), 153 SND_SOC_DAPM_AIF_IN("SDRX5", NULL, 4, SND_SOC_NOPM, 0, 0), 154 155 SND_SOC_DAPM_DAC("DAC1", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC1_SHIFT, 1), 156 SND_SOC_DAPM_DAC("DAC2", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC2_SHIFT, 1), 157 SND_SOC_DAPM_DAC("DAC3", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC3_SHIFT, 1), 158 SND_SOC_DAPM_DAC("DAC4", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC4_SHIFT, 1), 159 SND_SOC_DAPM_DAC("DAC5", NULL, CS4234_DAC_CTRL4, CS4234_PDN_DAC5_SHIFT, 1), 160 161 SND_SOC_DAPM_OUTPUT("AOUT1"), 162 SND_SOC_DAPM_OUTPUT("AOUT2"), 163 SND_SOC_DAPM_OUTPUT("AOUT3"), 164 SND_SOC_DAPM_OUTPUT("AOUT4"), 165 SND_SOC_DAPM_OUTPUT("AOUT5"), 166 167 SND_SOC_DAPM_INPUT("AIN1"), 168 SND_SOC_DAPM_INPUT("AIN2"), 169 SND_SOC_DAPM_INPUT("AIN3"), 170 SND_SOC_DAPM_INPUT("AIN4"), 171 172 SND_SOC_DAPM_ADC("ADC1", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC1_SHIFT, 1), 173 SND_SOC_DAPM_ADC("ADC2", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC2_SHIFT, 1), 174 SND_SOC_DAPM_ADC("ADC3", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC3_SHIFT, 1), 175 SND_SOC_DAPM_ADC("ADC4", NULL, CS4234_ADC_CTRL2, CS4234_PDN_ADC4_SHIFT, 1), 176 177 SND_SOC_DAPM_AIF_OUT("SDTX1", NULL, 0, SND_SOC_NOPM, 0, 1), 178 SND_SOC_DAPM_AIF_OUT("SDTX2", NULL, 1, SND_SOC_NOPM, 0, 1), 179 SND_SOC_DAPM_AIF_OUT("SDTX3", NULL, 2, SND_SOC_NOPM, 0, 1), 180 SND_SOC_DAPM_AIF_OUT("SDTX4", NULL, 3, SND_SOC_NOPM, 0, 1), 181 }; 182 183 static const struct snd_soc_dapm_route cs4234_dapm_routes[] = { 184 /* Playback */ 185 { "AOUT1", NULL, "DAC1" }, 186 { "AOUT2", NULL, "DAC2" }, 187 { "AOUT3", NULL, "DAC3" }, 188 { "AOUT4", NULL, "DAC4" }, 189 { "AOUT5", NULL, "DAC5" }, 190 191 { "DAC1", NULL, "SDRX1" }, 192 { "DAC2", NULL, "SDRX2" }, 193 { "DAC3", NULL, "SDRX3" }, 194 { "DAC4", NULL, "SDRX4" }, 195 { "DAC5", NULL, "SDRX5" }, 196 197 { "SDRX1", NULL, "Playback" }, 198 { "SDRX2", NULL, "Playback" }, 199 { "SDRX3", NULL, "Playback" }, 200 { "SDRX4", NULL, "Playback" }, 201 { "SDRX5", NULL, "Playback" }, 202 203 /* Capture */ 204 { "ADC1", NULL, "AIN1" }, 205 { "ADC2", NULL, "AIN2" }, 206 { "ADC3", NULL, "AIN3" }, 207 { "ADC4", NULL, "AIN4" }, 208 209 { "SDTX1", NULL, "ADC1" }, 210 { "SDTX2", NULL, "ADC2" }, 211 { "SDTX3", NULL, "ADC3" }, 212 { "SDTX4", NULL, "ADC4" }, 213 214 { "Capture", NULL, "SDTX1" }, 215 { "Capture", NULL, "SDTX2" }, 216 { "Capture", NULL, "SDTX3" }, 217 { "Capture", NULL, "SDTX4" }, 218 }; 219 220 static const struct snd_kcontrol_new cs4234_snd_controls[] = { 221 SOC_SINGLE_TLV("Master Volume", CS4234_MASTER_VOL, 0, 0xff, 1, dac_tlv), 222 SOC_SINGLE_TLV("DAC1 Volume", CS4234_DAC1_VOL, 0, 0xff, 1, dac_tlv), 223 SOC_SINGLE_TLV("DAC2 Volume", CS4234_DAC2_VOL, 0, 0xff, 1, dac_tlv), 224 SOC_SINGLE_TLV("DAC3 Volume", CS4234_DAC3_VOL, 0, 0xff, 1, dac_tlv), 225 SOC_SINGLE_TLV("DAC4 Volume", CS4234_DAC4_VOL, 0, 0xff, 1, dac_tlv), 226 SOC_SINGLE_TLV("DAC5 Volume", CS4234_DAC5_VOL, 0, 0xff, 1, dac_tlv), 227 228 SOC_SINGLE("DAC5 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC5_ATT_SHIFT, 1, 1), 229 SOC_SINGLE("DAC1-4 Soft Ramp Switch", CS4234_DAC_CTRL3, CS4234_DAC14_ATT_SHIFT, 1, 1), 230 231 SOC_SINGLE("ADC HPF Switch", CS4234_ADC_CTRL1, CS4234_ENA_HPF_SHIFT, 1, 0), 232 233 SOC_ENUM_EXT("DAC1-4 Group Delay", cs4234_dac14_group_delay, 234 snd_soc_get_enum_double, cs4234_dac14_grp_delay_put), 235 236 SOC_SINGLE("ADC1 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC1_SHIFT, 1, 0), 237 SOC_SINGLE("ADC2 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC2_SHIFT, 1, 0), 238 SOC_SINGLE("ADC3 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC3_SHIFT, 1, 0), 239 SOC_SINGLE("ADC4 Invert Switch", CS4234_ADC_CTRL1, CS4234_INV_ADC4_SHIFT, 1, 0), 240 241 SOC_SINGLE("DAC1 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC1_SHIFT, 1, 0), 242 SOC_SINGLE("DAC2 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC2_SHIFT, 1, 0), 243 SOC_SINGLE("DAC3 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC3_SHIFT, 1, 0), 244 SOC_SINGLE("DAC4 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC4_SHIFT, 1, 0), 245 SOC_SINGLE("DAC5 Invert Switch", CS4234_DAC_CTRL2, CS4234_INV_DAC5_SHIFT, 1, 0), 246 247 SOC_SINGLE("ADC1 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC1_SHIFT, 1, 1), 248 SOC_SINGLE("ADC2 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC2_SHIFT, 1, 1), 249 SOC_SINGLE("ADC3 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC3_SHIFT, 1, 1), 250 SOC_SINGLE("ADC4 Switch", CS4234_ADC_CTRL2, CS4234_MUTE_ADC4_SHIFT, 1, 1), 251 252 SOC_SINGLE("DAC1 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC1_SHIFT, 1, 1), 253 SOC_SINGLE("DAC2 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC2_SHIFT, 1, 1), 254 SOC_SINGLE("DAC3 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC3_SHIFT, 1, 1), 255 SOC_SINGLE("DAC4 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC4_SHIFT, 1, 1), 256 SOC_SINGLE("DAC5 Switch", CS4234_DAC_CTRL3, CS4234_MUTE_DAC5_SHIFT, 1, 1), 257 SOC_SINGLE("Low-latency Switch", CS4234_DAC_CTRL3, CS4234_MUTE_LL_SHIFT, 1, 1), 258 259 SOC_SINGLE("DAC1 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1, 260 CS4234_INV_LL1_SHIFT, 1, 0), 261 SOC_SINGLE("DAC2 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1, 262 CS4234_INV_LL2_SHIFT, 1, 0), 263 SOC_SINGLE("DAC3 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1, 264 CS4234_INV_LL3_SHIFT, 1, 0), 265 SOC_SINGLE("DAC4 Low-latency Invert Switch", CS4234_LOW_LAT_CTRL1, 266 CS4234_INV_LL4_SHIFT, 1, 0), 267 268 SOC_ENUM("Low-latency Noise Gate", cs4234_ll_noise_gate), 269 SOC_ENUM("DAC1-4 Noise Gate", cs4234_dac14_noise_gate), 270 SOC_ENUM("DAC5 Noise Gate", cs4234_dac5_noise_gate), 271 272 SOC_SINGLE("DAC1-4 De-emphasis Switch", CS4234_DAC_CTRL1, 273 CS4234_DAC14_DE_SHIFT, 1, 0), 274 SOC_SINGLE("DAC5 De-emphasis Switch", CS4234_DAC_CTRL1, 275 CS4234_DAC5_DE_SHIFT, 1, 0), 276 277 SOC_SINGLE("DAC5 Master Controlled Switch", CS4234_DAC_CTRL1, 278 CS4234_DAC5_MVC_SHIFT, 1, 0), 279 280 SOC_ENUM("DAC5 Filter", cs4234_dac5_config_fltr_sel), 281 282 SOC_ENUM("Mute Delay", cs4234_mute_delay), 283 SOC_ENUM("Ramp Minimum Delay", cs4234_min_delay), 284 SOC_ENUM("Ramp Maximum Delay", cs4234_max_delay), 285 286 }; 287 288 static int cs4234_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int format) 289 { 290 struct snd_soc_component *component = codec_dai->component; 291 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component); 292 unsigned int sp_ctrl = 0; 293 294 cs4234->format = format & SND_SOC_DAIFMT_FORMAT_MASK; 295 switch (cs4234->format) { 296 case SND_SOC_DAIFMT_LEFT_J: 297 sp_ctrl |= CS4234_LEFT_J << CS4234_SP_FORMAT_SHIFT; 298 break; 299 case SND_SOC_DAIFMT_I2S: 300 sp_ctrl |= CS4234_I2S << CS4234_SP_FORMAT_SHIFT; 301 break; 302 case SND_SOC_DAIFMT_DSP_A: /* TDM mode in datasheet */ 303 sp_ctrl |= CS4234_TDM << CS4234_SP_FORMAT_SHIFT; 304 break; 305 default: 306 dev_err(component->dev, "Unsupported dai format\n"); 307 return -EINVAL; 308 } 309 310 switch (format & SND_SOC_DAIFMT_MASTER_MASK) { 311 case SND_SOC_DAIFMT_CBC_CFC: 312 break; 313 case SND_SOC_DAIFMT_CBP_CFP: 314 if (cs4234->format == SND_SOC_DAIFMT_DSP_A) { 315 dev_err(component->dev, "Unsupported DSP A format in master mode\n"); 316 return -EINVAL; 317 } 318 sp_ctrl |= CS4234_MST_SLV_MASK; 319 break; 320 default: 321 dev_err(component->dev, "Unsupported master/slave mode\n"); 322 return -EINVAL; 323 } 324 325 switch (format & SND_SOC_DAIFMT_INV_MASK) { 326 case SND_SOC_DAIFMT_NB_NF: 327 break; 328 case SND_SOC_DAIFMT_IB_NF: 329 sp_ctrl |= CS4234_INVT_SCLK_MASK; 330 break; 331 default: 332 dev_err(component->dev, "Unsupported inverted clock setting\n"); 333 return -EINVAL; 334 } 335 336 regmap_update_bits(cs4234->regmap, CS4234_SP_CTRL, 337 CS4234_SP_FORMAT_MASK | CS4234_MST_SLV_MASK | CS4234_INVT_SCLK_MASK, 338 sp_ctrl); 339 340 return 0; 341 } 342 343 static int cs4234_dai_hw_params(struct snd_pcm_substream *sub, 344 struct snd_pcm_hw_params *params, 345 struct snd_soc_dai *dai) 346 { 347 struct snd_soc_component *component = dai->component; 348 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component); 349 unsigned int mclk_mult, double_speed = 0; 350 int ret = 0, rate_ad, sample_width; 351 352 cs4234->lrclk_rate = params_rate(params); 353 mclk_mult = cs4234->mclk_rate / cs4234->lrclk_rate; 354 355 if (cs4234->lrclk_rate > 48000) { 356 double_speed = 1; 357 mclk_mult *= 2; 358 } 359 360 switch (mclk_mult) { 361 case 256: 362 case 384: 363 case 512: 364 regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, 365 CS4234_SPEED_MODE_MASK, 366 double_speed << CS4234_SPEED_MODE_SHIFT); 367 regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, 368 CS4234_MCLK_RATE_MASK, 369 ((mclk_mult / 128) - 2) << CS4234_MCLK_RATE_SHIFT); 370 break; 371 default: 372 dev_err(component->dev, "Unsupported mclk/lrclk rate\n"); 373 return -EINVAL; 374 } 375 376 switch (cs4234->lrclk_rate) { 377 case 48000: 378 case 96000: 379 rate_ad = CS4234_48K; 380 break; 381 case 44100: 382 case 88200: 383 rate_ad = CS4234_44K1; 384 break; 385 case 32000: 386 case 64000: 387 rate_ad = CS4234_32K; 388 break; 389 default: 390 dev_err(component->dev, "Unsupported LR clock\n"); 391 return -EINVAL; 392 } 393 regmap_update_bits(cs4234->regmap, CS4234_CLOCK_SP, CS4234_BASE_RATE_MASK, 394 rate_ad << CS4234_BASE_RATE_SHIFT); 395 396 sample_width = params_width(params); 397 switch (sample_width) { 398 case 16: 399 sample_width = 0; 400 break; 401 case 18: 402 sample_width = 1; 403 break; 404 case 20: 405 sample_width = 2; 406 break; 407 case 24: 408 sample_width = 3; 409 break; 410 default: 411 dev_err(component->dev, "Unsupported sample width\n"); 412 return -EINVAL; 413 } 414 if (sub->stream == SNDRV_PCM_STREAM_CAPTURE) 415 regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH, 416 CS4234_SDOUTX_SW_MASK, 417 sample_width << CS4234_SDOUTX_SW_SHIFT); 418 else 419 regmap_update_bits(cs4234->regmap, CS4234_SAMPLE_WIDTH, 420 CS4234_INPUT_SW_MASK | CS4234_LOW_LAT_SW_MASK | CS4234_DAC5_SW_MASK, 421 sample_width << CS4234_INPUT_SW_SHIFT | 422 sample_width << CS4234_LOW_LAT_SW_SHIFT | 423 sample_width << CS4234_DAC5_SW_SHIFT); 424 425 return ret; 426 } 427 428 /* Scale MCLK rate by 64 to avoid overflow in the ratnum calculation */ 429 #define CS4234_MCLK_SCALE 64 430 431 static const struct snd_ratnum cs4234_dividers[] = { 432 { 433 .num = 0, 434 .den_min = 256 / CS4234_MCLK_SCALE, 435 .den_max = 512 / CS4234_MCLK_SCALE, 436 .den_step = 128 / CS4234_MCLK_SCALE, 437 }, 438 { 439 .num = 0, 440 .den_min = 128 / CS4234_MCLK_SCALE, 441 .den_max = 192 / CS4234_MCLK_SCALE, 442 .den_step = 64 / CS4234_MCLK_SCALE, 443 }, 444 }; 445 446 static int cs4234_dai_rule_rate(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 447 { 448 struct cs4234 *cs4234 = rule->private; 449 int mclk = cs4234->mclk_rate; 450 struct snd_interval ranges[] = { 451 { /* Single Speed Mode */ 452 .min = mclk / clamp(mclk / 30000, 256, 512), 453 .max = mclk / clamp(mclk / 50000, 256, 512), 454 }, 455 { /* Double Speed Mode */ 456 .min = mclk / clamp(mclk / 60000, 128, 256), 457 .max = mclk / clamp(mclk / 100000, 128, 256), 458 }, 459 }; 460 461 return snd_interval_ranges(hw_param_interval(params, rule->var), 462 ARRAY_SIZE(ranges), ranges, 0); 463 } 464 465 static int cs4234_dai_startup(struct snd_pcm_substream *sub, struct snd_soc_dai *dai) 466 { 467 struct snd_soc_component *comp = dai->component; 468 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(comp); 469 int i, ret; 470 471 switch (cs4234->format) { 472 case SND_SOC_DAIFMT_LEFT_J: 473 case SND_SOC_DAIFMT_I2S: 474 cs4234->rate_constraint.nrats = 2; 475 476 /* 477 * Playback only supports 24-bit samples in these modes. 478 * Note: SNDRV_PCM_HW_PARAM_SAMPLE_BITS constrains the physical 479 * width, which we don't care about, so constrain the format. 480 */ 481 if (sub->stream == SNDRV_PCM_STREAM_PLAYBACK) { 482 ret = snd_pcm_hw_constraint_mask64( 483 sub->runtime, 484 SNDRV_PCM_HW_PARAM_FORMAT, 485 SNDRV_PCM_FMTBIT_S24_LE | 486 SNDRV_PCM_FMTBIT_S24_3LE); 487 if (ret < 0) 488 return ret; 489 490 ret = snd_pcm_hw_constraint_minmax(sub->runtime, 491 SNDRV_PCM_HW_PARAM_CHANNELS, 492 1, 4); 493 if (ret < 0) 494 return ret; 495 } 496 497 break; 498 case SND_SOC_DAIFMT_DSP_A: 499 cs4234->rate_constraint.nrats = 1; 500 break; 501 default: 502 dev_err(comp->dev, "Startup unsupported DAI format\n"); 503 return -EINVAL; 504 } 505 506 for (i = 0; i < cs4234->rate_constraint.nrats; i++) 507 cs4234->rate_dividers[i].num = cs4234->mclk_rate / CS4234_MCLK_SCALE; 508 509 ret = snd_pcm_hw_constraint_ratnums(sub->runtime, 0, 510 SNDRV_PCM_HW_PARAM_RATE, 511 &cs4234->rate_constraint); 512 if (ret < 0) 513 return ret; 514 515 /* 516 * MCLK/rate may be a valid ratio but out-of-spec (e.g. 24576000/64000) 517 * so this rule limits the range of sample rate for given MCLK. 518 */ 519 return snd_pcm_hw_rule_add(sub->runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 520 cs4234_dai_rule_rate, cs4234, -1); 521 } 522 523 static int cs4234_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 524 unsigned int rx_mask, int slots, int slot_width) 525 { 526 struct snd_soc_component *component = dai->component; 527 struct cs4234 *cs4234 = snd_soc_component_get_drvdata(component); 528 unsigned int slot_offset, dac5_slot, dac5_mask_group; 529 uint8_t dac5_masks[4]; 530 531 if (slot_width != 32) { 532 dev_err(component->dev, "Unsupported slot width\n"); 533 return -EINVAL; 534 } 535 536 /* Either 4 or 5 consecutive bits, DAC5 is optional */ 537 slot_offset = ffs(tx_mask) - 1; 538 tx_mask >>= slot_offset; 539 if ((slot_offset % 4) || ((tx_mask != 0x0F) && (tx_mask != 0x1F))) { 540 dev_err(component->dev, "Unsupported tx slots allocation\n"); 541 return -EINVAL; 542 } 543 544 regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_DAC14_SRC_MASK, 545 (slot_offset / 4) << CS4234_DAC14_SRC_SHIFT); 546 regmap_update_bits(cs4234->regmap, CS4234_SP_DATA_SEL, CS4234_LL_SRC_MASK, 547 (slot_offset / 4) << CS4234_LL_SRC_SHIFT); 548 549 if (tx_mask == 0x1F) { 550 dac5_slot = slot_offset + 4; 551 memset(dac5_masks, 0xFF, sizeof(dac5_masks)); 552 dac5_mask_group = dac5_slot / 8; 553 dac5_slot %= 8; 554 dac5_masks[dac5_mask_group] ^= BIT(7 - dac5_slot); 555 regmap_bulk_write(cs4234->regmap, 556 CS4234_SDIN1_MASK1, 557 dac5_masks, 558 ARRAY_SIZE(dac5_masks)); 559 } 560 561 return 0; 562 } 563 564 static const struct snd_soc_dai_ops cs4234_dai_ops = { 565 .set_fmt = cs4234_dai_set_fmt, 566 .hw_params = cs4234_dai_hw_params, 567 .startup = cs4234_dai_startup, 568 .set_tdm_slot = cs4234_dai_set_tdm_slot, 569 }; 570 571 static struct snd_soc_dai_driver cs4234_dai[] = { 572 { 573 .name = "cs4234-dai", 574 .playback = { 575 .stream_name = "Playback", 576 .channels_min = 1, 577 .channels_max = 5, 578 .rates = CS4234_PCM_RATES, 579 .formats = CS4234_FORMATS, 580 }, 581 .capture = { 582 .stream_name = "Capture", 583 .channels_min = 1, 584 .channels_max = 4, 585 .rates = CS4234_PCM_RATES, 586 .formats = CS4234_FORMATS, 587 }, 588 .ops = &cs4234_dai_ops, 589 .symmetric_rate = 1, 590 }, 591 }; 592 593 static const struct reg_default cs4234_default_reg[] = { 594 { CS4234_CLOCK_SP, 0x04}, 595 { CS4234_SAMPLE_WIDTH, 0xFF}, 596 { CS4234_SP_CTRL, 0x48}, 597 { CS4234_SP_DATA_SEL, 0x01}, 598 { CS4234_SDIN1_MASK1, 0xFF}, 599 { CS4234_SDIN1_MASK2, 0xFF}, 600 { CS4234_SDIN2_MASK1, 0xFF}, 601 { CS4234_SDIN2_MASK2, 0xFF}, 602 { CS4234_TPS_CTRL, 0x00}, 603 { CS4234_ADC_CTRL1, 0xC0}, 604 { CS4234_ADC_CTRL2, 0xFF}, 605 { CS4234_LOW_LAT_CTRL1, 0xE0}, 606 { CS4234_DAC_CTRL1, 0xE0}, 607 { CS4234_DAC_CTRL2, 0xE0}, 608 { CS4234_DAC_CTRL3, 0xBF}, 609 { CS4234_DAC_CTRL4, 0x1F}, 610 { CS4234_VOLUME_MODE, 0x87}, 611 { CS4234_MASTER_VOL, 0x10}, 612 { CS4234_DAC1_VOL, 0x10}, 613 { CS4234_DAC2_VOL, 0x10}, 614 { CS4234_DAC3_VOL, 0x10}, 615 { CS4234_DAC4_VOL, 0x10}, 616 { CS4234_DAC5_VOL, 0x10}, 617 { CS4234_INT_CTRL, 0x40}, 618 { CS4234_INT_MASK1, 0x10}, 619 { CS4234_INT_MASK2, 0x20}, 620 }; 621 622 static bool cs4234_readable_register(struct device *dev, unsigned int reg) 623 { 624 switch (reg) { 625 case CS4234_DEVID_AB ... CS4234_DEVID_EF: 626 case CS4234_REVID ... CS4234_DAC5_VOL: 627 case CS4234_INT_CTRL ... CS4234_MAX_REGISTER: 628 return true; 629 default: 630 return false; 631 } 632 } 633 634 static bool cs4234_volatile_reg(struct device *dev, unsigned int reg) 635 { 636 switch (reg) { 637 case CS4234_INT_NOTIFY1: 638 case CS4234_INT_NOTIFY2: 639 return true; 640 default: 641 return false; 642 } 643 } 644 645 static bool cs4234_writeable_register(struct device *dev, unsigned int reg) 646 { 647 switch (reg) { 648 case CS4234_DEVID_AB ... CS4234_REVID: 649 case CS4234_INT_NOTIFY1 ... CS4234_INT_NOTIFY2: 650 return false; 651 default: 652 return true; 653 } 654 } 655 656 static const struct snd_soc_component_driver soc_component_cs4234 = { 657 .dapm_widgets = cs4234_dapm_widgets, 658 .num_dapm_widgets = ARRAY_SIZE(cs4234_dapm_widgets), 659 .dapm_routes = cs4234_dapm_routes, 660 .num_dapm_routes = ARRAY_SIZE(cs4234_dapm_routes), 661 .controls = cs4234_snd_controls, 662 .num_controls = ARRAY_SIZE(cs4234_snd_controls), 663 .set_bias_level = cs4234_set_bias_level, 664 .idle_bias_on = 1, 665 .suspend_bias_off = 1, 666 .endianness = 1, 667 }; 668 669 static const struct regmap_config cs4234_regmap = { 670 .reg_bits = 8, 671 .val_bits = 8, 672 673 .max_register = CS4234_MAX_REGISTER, 674 .readable_reg = cs4234_readable_register, 675 .volatile_reg = cs4234_volatile_reg, 676 .writeable_reg = cs4234_writeable_register, 677 .reg_defaults = cs4234_default_reg, 678 .num_reg_defaults = ARRAY_SIZE(cs4234_default_reg), 679 .cache_type = REGCACHE_MAPLE, 680 .use_single_read = true, 681 .use_single_write = true, 682 }; 683 684 static const char * const cs4234_core_supplies[] = { 685 "VA", 686 "VL", 687 }; 688 689 static void cs4234_shutdown(struct cs4234 *cs4234) 690 { 691 cancel_delayed_work_sync(&cs4234->vq_ramp_delay); 692 reinit_completion(&cs4234->vq_ramp_complete); 693 694 regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK, 695 CS4234_VQ_RAMP_MASK); 696 msleep(50); 697 regcache_cache_only(cs4234->regmap, true); 698 /* Clear VQ Ramp Bit in cache for the next PowerUp */ 699 regmap_update_bits(cs4234->regmap, CS4234_DAC_CTRL4, CS4234_VQ_RAMP_MASK, 0); 700 gpiod_set_value_cansleep(cs4234->reset_gpio, 0); 701 regulator_bulk_disable(cs4234->num_core_supplies, cs4234->core_supplies); 702 clk_disable_unprepare(cs4234->mclk); 703 } 704 705 static int cs4234_powerup(struct cs4234 *cs4234) 706 { 707 int ret; 708 709 ret = clk_prepare_enable(cs4234->mclk); 710 if (ret) { 711 dev_err(cs4234->dev, "Failed to enable mclk: %d\n", ret); 712 return ret; 713 } 714 715 ret = regulator_bulk_enable(cs4234->num_core_supplies, cs4234->core_supplies); 716 if (ret) { 717 dev_err(cs4234->dev, "Failed to enable core supplies: %d\n", ret); 718 clk_disable_unprepare(cs4234->mclk); 719 return ret; 720 } 721 722 usleep_range(CS4234_HOLD_RESET_TIME_US, 2 * CS4234_HOLD_RESET_TIME_US); 723 gpiod_set_value_cansleep(cs4234->reset_gpio, 1); 724 725 /* Make sure hardware reset done 2 ms + (3000/MCLK) */ 726 usleep_range(CS4234_BOOT_TIME_US, CS4234_BOOT_TIME_US * 2); 727 728 queue_delayed_work(system_power_efficient_wq, 729 &cs4234->vq_ramp_delay, 730 msecs_to_jiffies(CS4234_VQ_CHARGE_MS)); 731 732 return 0; 733 } 734 735 static int cs4234_i2c_probe(struct i2c_client *i2c_client) 736 { 737 struct cs4234 *cs4234; 738 struct device *dev = &i2c_client->dev; 739 unsigned int revid; 740 uint32_t devid; 741 uint8_t ids[3]; 742 int ret = 0, i; 743 744 cs4234 = devm_kzalloc(dev, sizeof(*cs4234), GFP_KERNEL); 745 if (!cs4234) 746 return -ENOMEM; 747 i2c_set_clientdata(i2c_client, cs4234); 748 cs4234->dev = dev; 749 init_completion(&cs4234->vq_ramp_complete); 750 INIT_DELAYED_WORK(&cs4234->vq_ramp_delay, cs4234_vq_ramp_done); 751 752 cs4234->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 753 if (IS_ERR(cs4234->reset_gpio)) 754 return PTR_ERR(cs4234->reset_gpio); 755 756 BUILD_BUG_ON(ARRAY_SIZE(cs4234->core_supplies) < ARRAY_SIZE(cs4234_core_supplies)); 757 758 cs4234->num_core_supplies = ARRAY_SIZE(cs4234_core_supplies); 759 for (i = 0; i < ARRAY_SIZE(cs4234_core_supplies); i++) 760 cs4234->core_supplies[i].supply = cs4234_core_supplies[i]; 761 762 ret = devm_regulator_bulk_get(dev, cs4234->num_core_supplies, cs4234->core_supplies); 763 if (ret) { 764 dev_err(dev, "Failed to request core supplies %d\n", ret); 765 return ret; 766 } 767 768 cs4234->mclk = devm_clk_get(dev, "mclk"); 769 if (IS_ERR(cs4234->mclk)) { 770 ret = PTR_ERR(cs4234->mclk); 771 dev_err(dev, "Failed to get the mclk: %d\n", ret); 772 return ret; 773 } 774 cs4234->mclk_rate = clk_get_rate(cs4234->mclk); 775 776 if (cs4234->mclk_rate < 7680000 || cs4234->mclk_rate > 25600000) { 777 dev_err(dev, "Invalid Master Clock rate\n"); 778 return -EINVAL; 779 } 780 781 cs4234->regmap = devm_regmap_init_i2c(i2c_client, &cs4234_regmap); 782 if (IS_ERR(cs4234->regmap)) { 783 ret = PTR_ERR(cs4234->regmap); 784 dev_err(dev, "regmap_init() failed: %d\n", ret); 785 return ret; 786 } 787 788 ret = cs4234_powerup(cs4234); 789 if (ret) 790 return ret; 791 792 ret = regmap_bulk_read(cs4234->regmap, CS4234_DEVID_AB, ids, ARRAY_SIZE(ids)); 793 if (ret < 0) { 794 dev_err(dev, "Failed to read DEVID: %d\n", ret); 795 goto fail_shutdown; 796 } 797 798 devid = (ids[0] << 16) | (ids[1] << 8) | ids[2]; 799 if (devid != CS4234_SUPPORTED_ID) { 800 dev_err(dev, "Unknown device ID: %x\n", devid); 801 ret = -EINVAL; 802 goto fail_shutdown; 803 } 804 805 ret = regmap_read(cs4234->regmap, CS4234_REVID, &revid); 806 if (ret < 0) { 807 dev_err(dev, "Failed to read CS4234_REVID: %d\n", ret); 808 goto fail_shutdown; 809 } 810 811 dev_info(dev, "Cirrus Logic CS4234, Alpha Rev: %02X, Numeric Rev: %02X\n", 812 (revid & 0xF0) >> 4, revid & 0x0F); 813 814 ret = regulator_get_voltage(cs4234->core_supplies[CS4234_SUPPLY_VA].consumer); 815 switch (ret) { 816 case 3135000 ... 3650000: 817 regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1, 818 CS4234_VA_SEL_MASK, 819 CS4234_3V3 << CS4234_VA_SEL_SHIFT); 820 break; 821 case 4750000 ... 5250000: 822 regmap_update_bits(cs4234->regmap, CS4234_ADC_CTRL1, 823 CS4234_VA_SEL_MASK, 824 CS4234_5V << CS4234_VA_SEL_SHIFT); 825 break; 826 default: 827 dev_err(dev, "Invalid VA voltage\n"); 828 ret = -EINVAL; 829 goto fail_shutdown; 830 } 831 832 pm_runtime_set_active(&i2c_client->dev); 833 pm_runtime_enable(&i2c_client->dev); 834 835 memcpy(&cs4234->rate_dividers, &cs4234_dividers, sizeof(cs4234_dividers)); 836 cs4234->rate_constraint.rats = cs4234->rate_dividers; 837 838 ret = snd_soc_register_component(dev, &soc_component_cs4234, cs4234_dai, 839 ARRAY_SIZE(cs4234_dai)); 840 if (ret < 0) { 841 dev_err(dev, "Failed to register component:%d\n", ret); 842 pm_runtime_disable(&i2c_client->dev); 843 goto fail_shutdown; 844 } 845 846 return ret; 847 848 fail_shutdown: 849 cs4234_shutdown(cs4234); 850 851 return ret; 852 } 853 854 static void cs4234_i2c_remove(struct i2c_client *i2c_client) 855 { 856 struct cs4234 *cs4234 = i2c_get_clientdata(i2c_client); 857 struct device *dev = &i2c_client->dev; 858 859 snd_soc_unregister_component(dev); 860 pm_runtime_disable(dev); 861 cs4234_shutdown(cs4234); 862 } 863 864 static int cs4234_runtime_resume(struct device *dev) 865 { 866 struct cs4234 *cs4234 = dev_get_drvdata(dev); 867 int ret; 868 869 ret = cs4234_powerup(cs4234); 870 if (ret) 871 return ret; 872 873 regcache_mark_dirty(cs4234->regmap); 874 regcache_cache_only(cs4234->regmap, false); 875 ret = regcache_sync(cs4234->regmap); 876 if (ret) { 877 dev_err(dev, "Failed to sync regmap: %d\n", ret); 878 cs4234_shutdown(cs4234); 879 return ret; 880 } 881 882 return 0; 883 } 884 885 static int cs4234_runtime_suspend(struct device *dev) 886 { 887 struct cs4234 *cs4234 = dev_get_drvdata(dev); 888 889 cs4234_shutdown(cs4234); 890 891 return 0; 892 } 893 894 static const struct dev_pm_ops cs4234_pm = { 895 RUNTIME_PM_OPS(cs4234_runtime_suspend, cs4234_runtime_resume, NULL) 896 }; 897 898 static const struct of_device_id cs4234_of_match[] = { 899 { .compatible = "cirrus,cs4234", }, 900 { } 901 }; 902 MODULE_DEVICE_TABLE(of, cs4234_of_match); 903 904 static struct i2c_driver cs4234_i2c_driver = { 905 .driver = { 906 .name = "cs4234", 907 .pm = pm_ptr(&cs4234_pm), 908 .of_match_table = cs4234_of_match, 909 }, 910 .probe = cs4234_i2c_probe, 911 .remove = cs4234_i2c_remove, 912 }; 913 module_i2c_driver(cs4234_i2c_driver); 914 915 MODULE_DESCRIPTION("ASoC Cirrus Logic CS4234 driver"); 916 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>"); 917 MODULE_LICENSE("GPL v2"); 918