1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Driver for Cirrus Logic CS35L56 smart amp 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/acpi.h> 9 #include <linux/completion.h> 10 #include <linux/debugfs.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/interrupt.h> 15 #include <linux/math.h> 16 #include <linux/module.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <linux/soundwire/sdw.h> 23 #include <linux/types.h> 24 #include <linux/workqueue.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/tlv.h> 30 31 #include "wm_adsp.h" 32 #include "cs35l56.h" 33 34 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 35 struct snd_kcontrol *kcontrol, int event); 36 37 static void cs35l56_wait_dsp_ready(struct cs35l56_private *cs35l56) 38 { 39 /* Wait for patching to complete */ 40 flush_work(&cs35l56->dsp_work); 41 } 42 43 static int cs35l56_dspwait_get_volsw(struct snd_kcontrol *kcontrol, 44 struct snd_ctl_elem_value *ucontrol) 45 { 46 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 47 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 48 49 cs35l56_wait_dsp_ready(cs35l56); 50 return snd_soc_get_volsw(kcontrol, ucontrol); 51 } 52 53 static int cs35l56_dspwait_put_volsw(struct snd_kcontrol *kcontrol, 54 struct snd_ctl_elem_value *ucontrol) 55 { 56 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 57 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 58 59 cs35l56_wait_dsp_ready(cs35l56); 60 return snd_soc_put_volsw(kcontrol, ucontrol); 61 } 62 63 static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0); 64 65 static const struct snd_kcontrol_new cs35l56_controls[] = { 66 SOC_SINGLE_EXT("Speaker Switch", 67 CS35L56_MAIN_RENDER_USER_MUTE, 0, 1, 1, 68 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 69 SOC_SINGLE_S_EXT_TLV("Speaker Volume", 70 CS35L56_MAIN_RENDER_USER_VOLUME, 71 6, -400, 400, 9, 0, 72 cs35l56_dspwait_get_volsw, 73 cs35l56_dspwait_put_volsw, 74 vol_tlv), 75 SOC_SINGLE_EXT("Posture Number", CS35L56_MAIN_POSTURE_NUMBER, 76 0, 255, 0, 77 cs35l56_dspwait_get_volsw, cs35l56_dspwait_put_volsw), 78 }; 79 80 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum, 81 CS35L56_ASP1TX1_INPUT, 82 0, CS35L56_ASP_TXn_SRC_MASK, 83 cs35l56_tx_input_texts, 84 cs35l56_tx_input_values); 85 86 static const struct snd_kcontrol_new asp1_tx1_mux = 87 SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum); 88 89 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum, 90 CS35L56_ASP1TX2_INPUT, 91 0, CS35L56_ASP_TXn_SRC_MASK, 92 cs35l56_tx_input_texts, 93 cs35l56_tx_input_values); 94 95 static const struct snd_kcontrol_new asp1_tx2_mux = 96 SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum); 97 98 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum, 99 CS35L56_ASP1TX3_INPUT, 100 0, CS35L56_ASP_TXn_SRC_MASK, 101 cs35l56_tx_input_texts, 102 cs35l56_tx_input_values); 103 104 static const struct snd_kcontrol_new asp1_tx3_mux = 105 SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum); 106 107 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum, 108 CS35L56_ASP1TX4_INPUT, 109 0, CS35L56_ASP_TXn_SRC_MASK, 110 cs35l56_tx_input_texts, 111 cs35l56_tx_input_values); 112 113 static const struct snd_kcontrol_new asp1_tx4_mux = 114 SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum); 115 116 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum, 117 CS35L56_SWIRE_DP3_CH1_INPUT, 118 0, CS35L56_SWIRETXn_SRC_MASK, 119 cs35l56_tx_input_texts, 120 cs35l56_tx_input_values); 121 122 static const struct snd_kcontrol_new sdw1_tx1_mux = 123 SOC_DAPM_ENUM("SDW1TX1 SRC", cs35l56_sdw1tx1_enum); 124 125 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx2_enum, 126 CS35L56_SWIRE_DP3_CH2_INPUT, 127 0, CS35L56_SWIRETXn_SRC_MASK, 128 cs35l56_tx_input_texts, 129 cs35l56_tx_input_values); 130 131 static const struct snd_kcontrol_new sdw1_tx2_mux = 132 SOC_DAPM_ENUM("SDW1TX2 SRC", cs35l56_sdw1tx2_enum); 133 134 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx3_enum, 135 CS35L56_SWIRE_DP3_CH3_INPUT, 136 0, CS35L56_SWIRETXn_SRC_MASK, 137 cs35l56_tx_input_texts, 138 cs35l56_tx_input_values); 139 140 static const struct snd_kcontrol_new sdw1_tx3_mux = 141 SOC_DAPM_ENUM("SDW1TX3 SRC", cs35l56_sdw1tx3_enum); 142 143 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx4_enum, 144 CS35L56_SWIRE_DP3_CH4_INPUT, 145 0, CS35L56_SWIRETXn_SRC_MASK, 146 cs35l56_tx_input_texts, 147 cs35l56_tx_input_values); 148 149 static const struct snd_kcontrol_new sdw1_tx4_mux = 150 SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum); 151 152 static int cs35l56_play_event(struct snd_soc_dapm_widget *w, 153 struct snd_kcontrol *kcontrol, int event) 154 { 155 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 156 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 157 unsigned int val; 158 int ret; 159 160 dev_dbg(cs35l56->base.dev, "play: %d\n", event); 161 162 switch (event) { 163 case SND_SOC_DAPM_PRE_PMU: 164 /* Don't wait for ACK, we check in POST_PMU that it completed */ 165 return regmap_write(cs35l56->base.regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 166 CS35L56_MBOX_CMD_AUDIO_PLAY); 167 case SND_SOC_DAPM_POST_PMU: 168 /* Wait for firmware to enter PS0 power state */ 169 ret = regmap_read_poll_timeout(cs35l56->base.regmap, 170 CS35L56_TRANSDUCER_ACTUAL_PS, 171 val, (val == CS35L56_PS0), 172 CS35L56_PS0_POLL_US, 173 CS35L56_PS0_TIMEOUT_US); 174 if (ret) 175 dev_err(cs35l56->base.dev, "PS0 wait failed: %d\n", ret); 176 return ret; 177 case SND_SOC_DAPM_POST_PMD: 178 return cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_PAUSE); 179 default: 180 return 0; 181 } 182 } 183 184 static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = { 185 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0), 186 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0), 187 188 SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event, 189 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 190 191 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0), 192 SND_SOC_DAPM_OUTPUT("SPK"), 193 194 SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, cs35l56_dsp_event, 195 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 196 197 SND_SOC_DAPM_AIF_IN("ASP1RX1", NULL, 0, CS35L56_ASP1_ENABLES1, 198 CS35L56_ASP_RX1_EN_SHIFT, 0), 199 SND_SOC_DAPM_AIF_IN("ASP1RX2", NULL, 1, CS35L56_ASP1_ENABLES1, 200 CS35L56_ASP_RX2_EN_SHIFT, 0), 201 SND_SOC_DAPM_AIF_OUT("ASP1TX1", NULL, 0, CS35L56_ASP1_ENABLES1, 202 CS35L56_ASP_TX1_EN_SHIFT, 0), 203 SND_SOC_DAPM_AIF_OUT("ASP1TX2", NULL, 1, CS35L56_ASP1_ENABLES1, 204 CS35L56_ASP_TX2_EN_SHIFT, 0), 205 SND_SOC_DAPM_AIF_OUT("ASP1TX3", NULL, 2, CS35L56_ASP1_ENABLES1, 206 CS35L56_ASP_TX3_EN_SHIFT, 0), 207 SND_SOC_DAPM_AIF_OUT("ASP1TX4", NULL, 3, CS35L56_ASP1_ENABLES1, 208 CS35L56_ASP_TX4_EN_SHIFT, 0), 209 210 SND_SOC_DAPM_MUX("ASP1 TX1 Source", SND_SOC_NOPM, 0, 0, &asp1_tx1_mux), 211 SND_SOC_DAPM_MUX("ASP1 TX2 Source", SND_SOC_NOPM, 0, 0, &asp1_tx2_mux), 212 SND_SOC_DAPM_MUX("ASP1 TX3 Source", SND_SOC_NOPM, 0, 0, &asp1_tx3_mux), 213 SND_SOC_DAPM_MUX("ASP1 TX4 Source", SND_SOC_NOPM, 0, 0, &asp1_tx4_mux), 214 215 SND_SOC_DAPM_MUX("SDW1 TX1 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx1_mux), 216 SND_SOC_DAPM_MUX("SDW1 TX2 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx2_mux), 217 SND_SOC_DAPM_MUX("SDW1 TX3 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx3_mux), 218 SND_SOC_DAPM_MUX("SDW1 TX4 Source", SND_SOC_NOPM, 0, 0, &sdw1_tx4_mux), 219 220 SND_SOC_DAPM_SIGGEN("VMON ADC"), 221 SND_SOC_DAPM_SIGGEN("IMON ADC"), 222 SND_SOC_DAPM_SIGGEN("ERRVOL ADC"), 223 SND_SOC_DAPM_SIGGEN("CLASSH ADC"), 224 SND_SOC_DAPM_SIGGEN("VDDBMON ADC"), 225 SND_SOC_DAPM_SIGGEN("VBSTMON ADC"), 226 SND_SOC_DAPM_SIGGEN("TEMPMON ADC"), 227 }; 228 229 #define CS35L56_SRC_ROUTE(name) \ 230 { name" Source", "ASP1RX1", "ASP1RX1" }, \ 231 { name" Source", "ASP1RX2", "ASP1RX2" }, \ 232 { name" Source", "VMON", "VMON ADC" }, \ 233 { name" Source", "IMON", "IMON ADC" }, \ 234 { name" Source", "ERRVOL", "ERRVOL ADC" }, \ 235 { name" Source", "CLASSH", "CLASSH ADC" }, \ 236 { name" Source", "VDDBMON", "VDDBMON ADC" }, \ 237 { name" Source", "VBSTMON", "VBSTMON ADC" }, \ 238 { name" Source", "DSP1TX1", "DSP1" }, \ 239 { name" Source", "DSP1TX2", "DSP1" }, \ 240 { name" Source", "DSP1TX3", "DSP1" }, \ 241 { name" Source", "DSP1TX4", "DSP1" }, \ 242 { name" Source", "DSP1TX5", "DSP1" }, \ 243 { name" Source", "DSP1TX6", "DSP1" }, \ 244 { name" Source", "DSP1TX7", "DSP1" }, \ 245 { name" Source", "DSP1TX8", "DSP1" }, \ 246 { name" Source", "TEMPMON", "TEMPMON ADC" }, \ 247 { name" Source", "INTERPOLATOR", "AMP" }, \ 248 { name" Source", "SDW1RX1", "SDW1 Playback" }, \ 249 { name" Source", "SDW1RX2", "SDW1 Playback" }, 250 251 static const struct snd_soc_dapm_route cs35l56_audio_map[] = { 252 { "AMP", NULL, "VDD_B" }, 253 { "AMP", NULL, "VDD_AMP" }, 254 255 { "ASP1 Playback", NULL, "PLAY" }, 256 { "SDW1 Playback", NULL, "PLAY" }, 257 258 { "ASP1RX1", NULL, "ASP1 Playback" }, 259 { "ASP1RX2", NULL, "ASP1 Playback" }, 260 { "DSP1", NULL, "ASP1RX1" }, 261 { "DSP1", NULL, "ASP1RX2" }, 262 { "DSP1", NULL, "SDW1 Playback" }, 263 { "AMP", NULL, "DSP1" }, 264 { "SPK", NULL, "AMP" }, 265 266 CS35L56_SRC_ROUTE("ASP1 TX1") 267 CS35L56_SRC_ROUTE("ASP1 TX2") 268 CS35L56_SRC_ROUTE("ASP1 TX3") 269 CS35L56_SRC_ROUTE("ASP1 TX4") 270 271 { "ASP1TX1", NULL, "ASP1 TX1 Source" }, 272 { "ASP1TX2", NULL, "ASP1 TX2 Source" }, 273 { "ASP1TX3", NULL, "ASP1 TX3 Source" }, 274 { "ASP1TX4", NULL, "ASP1 TX4 Source" }, 275 { "ASP1 Capture", NULL, "ASP1TX1" }, 276 { "ASP1 Capture", NULL, "ASP1TX2" }, 277 { "ASP1 Capture", NULL, "ASP1TX3" }, 278 { "ASP1 Capture", NULL, "ASP1TX4" }, 279 280 CS35L56_SRC_ROUTE("SDW1 TX1") 281 CS35L56_SRC_ROUTE("SDW1 TX2") 282 CS35L56_SRC_ROUTE("SDW1 TX3") 283 CS35L56_SRC_ROUTE("SDW1 TX4") 284 { "SDW1 Capture", NULL, "SDW1 TX1 Source" }, 285 { "SDW1 Capture", NULL, "SDW1 TX2 Source" }, 286 { "SDW1 Capture", NULL, "SDW1 TX3 Source" }, 287 { "SDW1 Capture", NULL, "SDW1 TX4 Source" }, 288 }; 289 290 static int cs35l56_dsp_event(struct snd_soc_dapm_widget *w, 291 struct snd_kcontrol *kcontrol, int event) 292 { 293 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 294 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 295 296 dev_dbg(cs35l56->base.dev, "%s: %d\n", __func__, event); 297 298 return wm_adsp_event(w, kcontrol, event); 299 } 300 301 static int cs35l56_asp_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 302 { 303 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component); 304 unsigned int val; 305 306 dev_dbg(cs35l56->base.dev, "%s: %#x\n", __func__, fmt); 307 308 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 309 case SND_SOC_DAIFMT_CBC_CFC: 310 break; 311 default: 312 dev_err(cs35l56->base.dev, "Unsupported clock source mode\n"); 313 return -EINVAL; 314 } 315 316 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 317 case SND_SOC_DAIFMT_DSP_A: 318 val = CS35L56_ASP_FMT_DSP_A << CS35L56_ASP_FMT_SHIFT; 319 cs35l56->tdm_mode = true; 320 break; 321 case SND_SOC_DAIFMT_I2S: 322 val = CS35L56_ASP_FMT_I2S << CS35L56_ASP_FMT_SHIFT; 323 cs35l56->tdm_mode = false; 324 break; 325 default: 326 dev_err(cs35l56->base.dev, "Unsupported DAI format\n"); 327 return -EINVAL; 328 } 329 330 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 331 case SND_SOC_DAIFMT_NB_IF: 332 val |= CS35L56_ASP_FSYNC_INV_MASK; 333 break; 334 case SND_SOC_DAIFMT_IB_NF: 335 val |= CS35L56_ASP_BCLK_INV_MASK; 336 break; 337 case SND_SOC_DAIFMT_IB_IF: 338 val |= CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK; 339 break; 340 case SND_SOC_DAIFMT_NB_NF: 341 break; 342 default: 343 dev_err(cs35l56->base.dev, "Invalid clock invert\n"); 344 return -EINVAL; 345 } 346 347 regmap_update_bits(cs35l56->base.regmap, 348 CS35L56_ASP1_CONTROL2, 349 CS35L56_ASP_FMT_MASK | 350 CS35L56_ASP_BCLK_INV_MASK | CS35L56_ASP_FSYNC_INV_MASK, 351 val); 352 353 /* Hi-Z DOUT in unused slots and when all TX are disabled */ 354 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL3, 355 CS35L56_ASP1_DOUT_HIZ_CTRL_MASK, 356 CS35L56_ASP_UNUSED_HIZ_OFF_HIZ); 357 358 return 0; 359 } 360 361 static void cs35l56_set_asp_slot_positions(struct cs35l56_private *cs35l56, 362 unsigned int reg, unsigned long mask) 363 { 364 unsigned int reg_val, channel_shift; 365 int bit_num; 366 367 /* Init all slots to 63 */ 368 switch (reg) { 369 case CS35L56_ASP1_FRAME_CONTROL1: 370 reg_val = 0x3f3f3f3f; 371 break; 372 case CS35L56_ASP1_FRAME_CONTROL5: 373 reg_val = 0x3f3f3f; 374 break; 375 } 376 377 /* Enable consecutive TX1..TXn for each of the slots set in mask */ 378 channel_shift = 0; 379 for_each_set_bit(bit_num, &mask, 32) { 380 reg_val &= ~(0x3f << channel_shift); 381 reg_val |= bit_num << channel_shift; 382 channel_shift += 8; 383 } 384 385 regmap_write(cs35l56->base.regmap, reg, reg_val); 386 } 387 388 static int cs35l56_asp_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 389 unsigned int rx_mask, int slots, int slot_width) 390 { 391 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 392 393 if ((slots == 0) || (slot_width == 0)) { 394 dev_dbg(cs35l56->base.dev, "tdm config cleared\n"); 395 cs35l56->asp_slot_width = 0; 396 cs35l56->asp_slot_count = 0; 397 return 0; 398 } 399 400 if (slot_width > (CS35L56_ASP_RX_WIDTH_MASK >> CS35L56_ASP_RX_WIDTH_SHIFT)) { 401 dev_err(cs35l56->base.dev, "tdm invalid slot width %d\n", slot_width); 402 return -EINVAL; 403 } 404 405 /* More than 32 slots would give an unsupportable BCLK frequency */ 406 if (slots > 32) { 407 dev_err(cs35l56->base.dev, "tdm invalid slot count %d\n", slots); 408 return -EINVAL; 409 } 410 411 cs35l56->asp_slot_width = (u8)slot_width; 412 cs35l56->asp_slot_count = (u8)slots; 413 414 // Note: rx/tx is from point of view of the CPU end 415 if (tx_mask == 0) 416 tx_mask = 0x3; // ASPRX1/RX2 in slots 0 and 1 417 418 if (rx_mask == 0) 419 rx_mask = 0xf; // ASPTX1..TX4 in slots 0..3 420 421 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL1, rx_mask); 422 cs35l56_set_asp_slot_positions(cs35l56, CS35L56_ASP1_FRAME_CONTROL5, tx_mask); 423 424 dev_dbg(cs35l56->base.dev, "tdm slot width: %u count: %u tx_mask: %#x rx_mask: %#x\n", 425 cs35l56->asp_slot_width, cs35l56->asp_slot_count, tx_mask, rx_mask); 426 427 return 0; 428 } 429 430 static int cs35l56_asp_dai_hw_params(struct snd_pcm_substream *substream, 431 struct snd_pcm_hw_params *params, 432 struct snd_soc_dai *dai) 433 { 434 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 435 unsigned int rate = params_rate(params); 436 u8 asp_width, asp_wl; 437 438 asp_wl = params_width(params); 439 if (cs35l56->asp_slot_width) 440 asp_width = cs35l56->asp_slot_width; 441 else 442 asp_width = asp_wl; 443 444 dev_dbg(cs35l56->base.dev, "%s: wl=%d, width=%d, rate=%d", 445 __func__, asp_wl, asp_width, rate); 446 447 if (!cs35l56->sysclk_set) { 448 unsigned int slots = cs35l56->asp_slot_count; 449 unsigned int bclk_freq; 450 int freq_id; 451 452 if (slots == 0) { 453 slots = params_channels(params); 454 455 /* I2S always has an even number of slots */ 456 if (!cs35l56->tdm_mode) 457 slots = round_up(slots, 2); 458 } 459 460 bclk_freq = asp_width * slots * rate; 461 freq_id = cs35l56_get_bclk_freq_id(bclk_freq); 462 if (freq_id < 0) { 463 dev_err(cs35l56->base.dev, "%s: Invalid BCLK %u\n", __func__, bclk_freq); 464 return -EINVAL; 465 } 466 467 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1, 468 CS35L56_ASP_BCLK_FREQ_MASK, 469 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 470 } 471 472 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 473 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2, 474 CS35L56_ASP_RX_WIDTH_MASK, asp_width << 475 CS35L56_ASP_RX_WIDTH_SHIFT); 476 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL5, 477 CS35L56_ASP_RX_WL_MASK, asp_wl); 478 } else { 479 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL2, 480 CS35L56_ASP_TX_WIDTH_MASK, asp_width << 481 CS35L56_ASP_TX_WIDTH_SHIFT); 482 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_DATA_CONTROL1, 483 CS35L56_ASP_TX_WL_MASK, asp_wl); 484 } 485 486 return 0; 487 } 488 489 static int cs35l56_asp_dai_set_sysclk(struct snd_soc_dai *dai, 490 int clk_id, unsigned int freq, int dir) 491 { 492 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 493 int freq_id; 494 495 if (freq == 0) { 496 cs35l56->sysclk_set = false; 497 return 0; 498 } 499 500 freq_id = cs35l56_get_bclk_freq_id(freq); 501 if (freq_id < 0) 502 return freq_id; 503 504 regmap_update_bits(cs35l56->base.regmap, CS35L56_ASP1_CONTROL1, 505 CS35L56_ASP_BCLK_FREQ_MASK, 506 freq_id << CS35L56_ASP_BCLK_FREQ_SHIFT); 507 cs35l56->sysclk_set = true; 508 509 return 0; 510 } 511 512 static const struct snd_soc_dai_ops cs35l56_ops = { 513 .set_fmt = cs35l56_asp_dai_set_fmt, 514 .set_tdm_slot = cs35l56_asp_dai_set_tdm_slot, 515 .hw_params = cs35l56_asp_dai_hw_params, 516 .set_sysclk = cs35l56_asp_dai_set_sysclk, 517 }; 518 519 static void cs35l56_sdw_dai_shutdown(struct snd_pcm_substream *substream, 520 struct snd_soc_dai *dai) 521 { 522 snd_soc_dai_set_dma_data(dai, substream, NULL); 523 } 524 525 static int cs35l56_sdw_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 526 unsigned int rx_mask, int slots, int slot_width) 527 { 528 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 529 530 /* rx/tx are from point of view of the CPU end so opposite to our rx/tx */ 531 cs35l56->rx_mask = tx_mask; 532 cs35l56->tx_mask = rx_mask; 533 534 return 0; 535 } 536 537 static int cs35l56_sdw_dai_hw_params(struct snd_pcm_substream *substream, 538 struct snd_pcm_hw_params *params, 539 struct snd_soc_dai *dai) 540 { 541 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 542 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 543 struct sdw_stream_config sconfig; 544 struct sdw_port_config pconfig; 545 int ret; 546 547 dev_dbg(cs35l56->base.dev, "%s: rate %d\n", __func__, params_rate(params)); 548 549 if (!cs35l56->base.init_done) 550 return -ENODEV; 551 552 if (!sdw_stream) 553 return -EINVAL; 554 555 memset(&sconfig, 0, sizeof(sconfig)); 556 memset(&pconfig, 0, sizeof(pconfig)); 557 558 sconfig.frame_rate = params_rate(params); 559 sconfig.bps = snd_pcm_format_width(params_format(params)); 560 561 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 562 sconfig.direction = SDW_DATA_DIR_RX; 563 pconfig.num = CS35L56_SDW1_PLAYBACK_PORT; 564 pconfig.ch_mask = cs35l56->rx_mask; 565 } else { 566 sconfig.direction = SDW_DATA_DIR_TX; 567 pconfig.num = CS35L56_SDW1_CAPTURE_PORT; 568 pconfig.ch_mask = cs35l56->tx_mask; 569 } 570 571 if (pconfig.ch_mask == 0) { 572 sconfig.ch_count = params_channels(params); 573 pconfig.ch_mask = GENMASK(sconfig.ch_count - 1, 0); 574 } else { 575 sconfig.ch_count = hweight32(pconfig.ch_mask); 576 } 577 578 ret = sdw_stream_add_slave(cs35l56->sdw_peripheral, &sconfig, &pconfig, 579 1, sdw_stream); 580 if (ret) { 581 dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret); 582 return ret; 583 } 584 585 return 0; 586 } 587 588 static int cs35l56_sdw_dai_hw_free(struct snd_pcm_substream *substream, 589 struct snd_soc_dai *dai) 590 { 591 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component); 592 struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 593 594 if (!cs35l56->sdw_peripheral) 595 return -EINVAL; 596 597 sdw_stream_remove_slave(cs35l56->sdw_peripheral, sdw_stream); 598 599 return 0; 600 } 601 602 static int cs35l56_sdw_dai_set_stream(struct snd_soc_dai *dai, 603 void *sdw_stream, int direction) 604 { 605 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 606 607 return 0; 608 } 609 610 static const struct snd_soc_dai_ops cs35l56_sdw_dai_ops = { 611 .set_tdm_slot = cs35l56_sdw_dai_set_tdm_slot, 612 .shutdown = cs35l56_sdw_dai_shutdown, 613 .hw_params = cs35l56_sdw_dai_hw_params, 614 .hw_free = cs35l56_sdw_dai_hw_free, 615 .set_stream = cs35l56_sdw_dai_set_stream, 616 }; 617 618 static struct snd_soc_dai_driver cs35l56_dai[] = { 619 { 620 .name = "cs35l56-asp1", 621 .id = 0, 622 .playback = { 623 .stream_name = "ASP1 Playback", 624 .channels_min = 1, 625 .channels_max = 2, 626 .rates = CS35L56_RATES, 627 .formats = CS35L56_RX_FORMATS, 628 }, 629 .capture = { 630 .stream_name = "ASP1 Capture", 631 .channels_min = 1, 632 .channels_max = 4, 633 .rates = CS35L56_RATES, 634 .formats = CS35L56_TX_FORMATS, 635 }, 636 .ops = &cs35l56_ops, 637 .symmetric_rate = 1, 638 .symmetric_sample_bits = 1, 639 }, 640 { 641 .name = "cs35l56-sdw1", 642 .id = 1, 643 .playback = { 644 .stream_name = "SDW1 Playback", 645 .channels_min = 1, 646 .channels_max = 2, 647 .rates = CS35L56_RATES, 648 .formats = CS35L56_RX_FORMATS, 649 }, 650 .capture = { 651 .stream_name = "SDW1 Capture", 652 .channels_min = 1, 653 .channels_max = 4, 654 .rates = CS35L56_RATES, 655 .formats = CS35L56_TX_FORMATS, 656 }, 657 .symmetric_rate = 1, 658 .ops = &cs35l56_sdw_dai_ops, 659 } 660 }; 661 662 static void cs35l56_secure_patch(struct cs35l56_private *cs35l56) 663 { 664 int ret; 665 666 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 667 ret = wm_adsp_power_up(&cs35l56->dsp); 668 if (ret) 669 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 670 else 671 cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_AUDIO_REINIT); 672 } 673 674 static void cs35l56_patch(struct cs35l56_private *cs35l56) 675 { 676 int ret; 677 678 /* 679 * Disable SoundWire interrupts to prevent race with IRQ work. 680 * Setting sdw_irq_no_unmask prevents the handler re-enabling 681 * the SoundWire interrupt. 682 */ 683 if (cs35l56->sdw_peripheral) { 684 cs35l56->sdw_irq_no_unmask = true; 685 flush_work(&cs35l56->sdw_irq_work); 686 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 0); 687 sdw_read_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1); 688 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_STAT_1, 0xFF); 689 flush_work(&cs35l56->sdw_irq_work); 690 } 691 692 ret = cs35l56_firmware_shutdown(&cs35l56->base); 693 if (ret) 694 goto err; 695 696 /* Use wm_adsp to load and apply the firmware patch and coefficient files */ 697 ret = wm_adsp_power_up(&cs35l56->dsp); 698 if (ret) { 699 dev_dbg(cs35l56->base.dev, "%s: wm_adsp_power_up ret %d\n", __func__, ret); 700 goto err; 701 } 702 703 mutex_lock(&cs35l56->base.irq_lock); 704 705 init_completion(&cs35l56->init_completion); 706 707 cs35l56->soft_resetting = true; 708 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral); 709 710 if (cs35l56->sdw_peripheral) { 711 /* 712 * The system-reset causes the CS35L56 to detach from the bus. 713 * Wait for the manager to re-enumerate the CS35L56 and 714 * cs35l56_init() to run again. 715 */ 716 if (!wait_for_completion_timeout(&cs35l56->init_completion, 717 msecs_to_jiffies(5000))) { 718 dev_err(cs35l56->base.dev, "%s: init_completion timed out (SDW)\n", 719 __func__); 720 goto err_unlock; 721 } 722 } else if (cs35l56_init(cs35l56)) { 723 goto err_unlock; 724 } 725 726 regmap_clear_bits(cs35l56->base.regmap, CS35L56_PROTECTION_STATUS, 727 CS35L56_FIRMWARE_MISSING); 728 cs35l56->base.fw_patched = true; 729 730 err_unlock: 731 mutex_unlock(&cs35l56->base.irq_lock); 732 err: 733 /* Re-enable SoundWire interrupts */ 734 if (cs35l56->sdw_peripheral) { 735 cs35l56->sdw_irq_no_unmask = false; 736 sdw_write_no_pm(cs35l56->sdw_peripheral, CS35L56_SDW_GEN_INT_MASK_1, 737 CS35L56_SDW_INT_MASK_CODEC_IRQ); 738 } 739 } 740 741 static void cs35l56_dsp_work(struct work_struct *work) 742 { 743 struct cs35l56_private *cs35l56 = container_of(work, 744 struct cs35l56_private, 745 dsp_work); 746 747 if (!cs35l56->base.init_done) 748 return; 749 750 pm_runtime_get_sync(cs35l56->base.dev); 751 752 /* 753 * When the device is running in secure mode the firmware files can 754 * only contain insecure tunings and therefore we do not need to 755 * shutdown the firmware to apply them and can use the lower cost 756 * reinit sequence instead. 757 */ 758 if (cs35l56->base.secured) 759 cs35l56_secure_patch(cs35l56); 760 else 761 cs35l56_patch(cs35l56); 762 763 pm_runtime_mark_last_busy(cs35l56->base.dev); 764 pm_runtime_put_autosuspend(cs35l56->base.dev); 765 } 766 767 static int cs35l56_component_probe(struct snd_soc_component *component) 768 { 769 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 770 struct dentry *debugfs_root = component->debugfs_root; 771 772 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_tx_input_texts) != ARRAY_SIZE(cs35l56_tx_input_values)); 773 774 if (!wait_for_completion_timeout(&cs35l56->init_completion, 775 msecs_to_jiffies(5000))) { 776 dev_err(cs35l56->base.dev, "%s: init_completion timed out\n", __func__); 777 return -ENODEV; 778 } 779 780 cs35l56->component = component; 781 wm_adsp2_component_probe(&cs35l56->dsp, component); 782 783 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->base.init_done); 784 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->base.can_hibernate); 785 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->base.fw_patched); 786 787 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 788 789 return 0; 790 } 791 792 static void cs35l56_component_remove(struct snd_soc_component *component) 793 { 794 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 795 796 cancel_work_sync(&cs35l56->dsp_work); 797 } 798 799 static int cs35l56_set_bias_level(struct snd_soc_component *component, 800 enum snd_soc_bias_level level) 801 { 802 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component); 803 804 switch (level) { 805 case SND_SOC_BIAS_STANDBY: 806 /* 807 * Wait for patching to complete when transitioning from 808 * BIAS_OFF to BIAS_STANDBY 809 */ 810 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 811 cs35l56_wait_dsp_ready(cs35l56); 812 813 break; 814 default: 815 break; 816 } 817 818 return 0; 819 } 820 821 static const struct snd_soc_component_driver soc_component_dev_cs35l56 = { 822 .probe = cs35l56_component_probe, 823 .remove = cs35l56_component_remove, 824 825 .dapm_widgets = cs35l56_dapm_widgets, 826 .num_dapm_widgets = ARRAY_SIZE(cs35l56_dapm_widgets), 827 .dapm_routes = cs35l56_audio_map, 828 .num_dapm_routes = ARRAY_SIZE(cs35l56_audio_map), 829 .controls = cs35l56_controls, 830 .num_controls = ARRAY_SIZE(cs35l56_controls), 831 832 .set_bias_level = cs35l56_set_bias_level, 833 834 .suspend_bias_off = 1, /* see cs35l56_system_resume() */ 835 }; 836 837 static int __maybe_unused cs35l56_runtime_suspend_i2c_spi(struct device *dev) 838 { 839 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 840 841 return cs35l56_runtime_suspend_common(&cs35l56->base); 842 } 843 844 static int __maybe_unused cs35l56_runtime_resume_i2c_spi(struct device *dev) 845 { 846 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 847 848 return cs35l56_runtime_resume_common(&cs35l56->base, false); 849 } 850 851 int cs35l56_system_suspend(struct device *dev) 852 { 853 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 854 855 dev_dbg(dev, "system_suspend\n"); 856 857 if (cs35l56->component) 858 flush_work(&cs35l56->dsp_work); 859 860 /* 861 * The interrupt line is normally shared, but after we start suspending 862 * we can't check if our device is the source of an interrupt, and can't 863 * clear it. Prevent this race by temporarily disabling the parent irq 864 * until we reach _no_irq. 865 */ 866 if (cs35l56->base.irq) 867 disable_irq(cs35l56->base.irq); 868 869 return pm_runtime_force_suspend(dev); 870 } 871 EXPORT_SYMBOL_GPL(cs35l56_system_suspend); 872 873 int cs35l56_system_suspend_late(struct device *dev) 874 { 875 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 876 877 dev_dbg(dev, "system_suspend_late\n"); 878 879 /* 880 * Assert RESET before removing supplies. 881 * RESET is usually shared by all amps so it must not be asserted until 882 * all driver instances have done their suspend() stage. 883 */ 884 if (cs35l56->base.reset_gpio) { 885 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 886 cs35l56_wait_min_reset_pulse(); 887 } 888 889 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 890 891 return 0; 892 } 893 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_late); 894 895 int cs35l56_system_suspend_no_irq(struct device *dev) 896 { 897 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 898 899 dev_dbg(dev, "system_suspend_no_irq\n"); 900 901 /* Handlers are now disabled so the parent IRQ can safely be re-enabled. */ 902 if (cs35l56->base.irq) 903 enable_irq(cs35l56->base.irq); 904 905 return 0; 906 } 907 EXPORT_SYMBOL_GPL(cs35l56_system_suspend_no_irq); 908 909 int cs35l56_system_resume_no_irq(struct device *dev) 910 { 911 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 912 913 dev_dbg(dev, "system_resume_no_irq\n"); 914 915 /* 916 * WAKE interrupts unmask if the CS35L56 hibernates, which can cause 917 * spurious interrupts, and the interrupt line is normally shared. 918 * We can't check if our device is the source of an interrupt, and can't 919 * clear it, until it has fully resumed. Prevent this race by temporarily 920 * disabling the parent irq until we complete resume(). 921 */ 922 if (cs35l56->base.irq) 923 disable_irq(cs35l56->base.irq); 924 925 return 0; 926 } 927 EXPORT_SYMBOL_GPL(cs35l56_system_resume_no_irq); 928 929 int cs35l56_system_resume_early(struct device *dev) 930 { 931 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 932 int ret; 933 934 dev_dbg(dev, "system_resume_early\n"); 935 936 /* Ensure a spec-compliant RESET pulse. */ 937 if (cs35l56->base.reset_gpio) { 938 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 939 cs35l56_wait_min_reset_pulse(); 940 } 941 942 /* Enable supplies before releasing RESET. */ 943 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 944 if (ret) { 945 dev_err(dev, "system_resume_early failed to enable supplies: %d\n", ret); 946 return ret; 947 } 948 949 /* Release shared RESET before drivers start resume(). */ 950 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1); 951 952 return 0; 953 } 954 EXPORT_SYMBOL_GPL(cs35l56_system_resume_early); 955 956 int cs35l56_system_resume(struct device *dev) 957 { 958 struct cs35l56_private *cs35l56 = dev_get_drvdata(dev); 959 int ret; 960 961 dev_dbg(dev, "system_resume\n"); 962 963 /* Undo pm_runtime_force_suspend() before re-enabling the irq */ 964 ret = pm_runtime_force_resume(dev); 965 if (cs35l56->base.irq) 966 enable_irq(cs35l56->base.irq); 967 968 if (ret) 969 return ret; 970 971 /* Firmware won't have been loaded if the component hasn't probed */ 972 if (!cs35l56->component) 973 return 0; 974 975 ret = cs35l56_is_fw_reload_needed(&cs35l56->base); 976 dev_dbg(cs35l56->base.dev, "fw_reload_needed: %d\n", ret); 977 if (ret < 1) 978 return ret; 979 980 cs35l56->base.fw_patched = false; 981 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work); 982 983 /* 984 * suspend_bias_off ensures we are now in BIAS_OFF so there will be 985 * a BIAS_OFF->BIAS_STANDBY transition to complete dsp patching. 986 */ 987 988 return 0; 989 } 990 EXPORT_SYMBOL_GPL(cs35l56_system_resume); 991 992 static int cs35l56_dsp_init(struct cs35l56_private *cs35l56) 993 { 994 struct wm_adsp *dsp; 995 int ret; 996 997 cs35l56->dsp_wq = create_singlethread_workqueue("cs35l56-dsp"); 998 if (!cs35l56->dsp_wq) 999 return -ENOMEM; 1000 1001 INIT_WORK(&cs35l56->dsp_work, cs35l56_dsp_work); 1002 1003 dsp = &cs35l56->dsp; 1004 cs35l56_init_cs_dsp(&cs35l56->base, &dsp->cs_dsp); 1005 dsp->part = "cs35l56"; 1006 dsp->fw = 12; 1007 dsp->wmfw_optional = true; 1008 1009 dev_dbg(cs35l56->base.dev, "DSP system name: '%s'\n", dsp->system_name); 1010 1011 ret = wm_halo_init(dsp); 1012 if (ret != 0) { 1013 dev_err(cs35l56->base.dev, "wm_halo_init failed\n"); 1014 return ret; 1015 } 1016 1017 return 0; 1018 } 1019 1020 static int cs35l56_acpi_get_name(struct cs35l56_private *cs35l56) 1021 { 1022 acpi_handle handle = ACPI_HANDLE(cs35l56->base.dev); 1023 const char *sub; 1024 1025 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */ 1026 if (!handle) 1027 return 0; 1028 1029 sub = acpi_get_subsystem_id(handle); 1030 if (IS_ERR(sub)) { 1031 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */ 1032 if (PTR_ERR(sub) == -ENODATA) 1033 return 0; 1034 else 1035 return PTR_ERR(sub); 1036 } 1037 1038 cs35l56->dsp.system_name = sub; 1039 dev_dbg(cs35l56->base.dev, "Subsystem ID: %s\n", cs35l56->dsp.system_name); 1040 1041 return 0; 1042 } 1043 1044 int cs35l56_common_probe(struct cs35l56_private *cs35l56) 1045 { 1046 int ret; 1047 1048 init_completion(&cs35l56->init_completion); 1049 mutex_init(&cs35l56->base.irq_lock); 1050 1051 dev_set_drvdata(cs35l56->base.dev, cs35l56); 1052 1053 cs35l56_fill_supply_names(cs35l56->supplies); 1054 ret = devm_regulator_bulk_get(cs35l56->base.dev, ARRAY_SIZE(cs35l56->supplies), 1055 cs35l56->supplies); 1056 if (ret != 0) 1057 return dev_err_probe(cs35l56->base.dev, ret, "Failed to request supplies\n"); 1058 1059 /* Reset could be controlled by the BIOS or shared by multiple amps */ 1060 cs35l56->base.reset_gpio = devm_gpiod_get_optional(cs35l56->base.dev, "reset", 1061 GPIOD_OUT_LOW); 1062 if (IS_ERR(cs35l56->base.reset_gpio)) { 1063 ret = PTR_ERR(cs35l56->base.reset_gpio); 1064 /* 1065 * If RESET is shared the first amp to probe will grab the reset 1066 * line and reset all the amps 1067 */ 1068 if (ret != -EBUSY) 1069 return dev_err_probe(cs35l56->base.dev, ret, "Failed to get reset GPIO\n"); 1070 1071 dev_info(cs35l56->base.dev, "Reset GPIO busy, assume shared reset\n"); 1072 cs35l56->base.reset_gpio = NULL; 1073 } 1074 1075 ret = regulator_bulk_enable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1076 if (ret != 0) 1077 return dev_err_probe(cs35l56->base.dev, ret, "Failed to enable supplies\n"); 1078 1079 if (cs35l56->base.reset_gpio) { 1080 cs35l56_wait_min_reset_pulse(); 1081 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 1); 1082 } 1083 1084 ret = cs35l56_acpi_get_name(cs35l56); 1085 if (ret != 0) 1086 goto err; 1087 1088 ret = cs35l56_dsp_init(cs35l56); 1089 if (ret < 0) { 1090 dev_err_probe(cs35l56->base.dev, ret, "DSP init failed\n"); 1091 goto err; 1092 } 1093 1094 ret = devm_snd_soc_register_component(cs35l56->base.dev, 1095 &soc_component_dev_cs35l56, 1096 cs35l56_dai, ARRAY_SIZE(cs35l56_dai)); 1097 if (ret < 0) { 1098 dev_err_probe(cs35l56->base.dev, ret, "Register codec failed\n"); 1099 goto err; 1100 } 1101 1102 return 0; 1103 1104 err: 1105 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 1106 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1107 1108 return ret; 1109 } 1110 EXPORT_SYMBOL_NS_GPL(cs35l56_common_probe, SND_SOC_CS35L56_CORE); 1111 1112 int cs35l56_init(struct cs35l56_private *cs35l56) 1113 { 1114 int ret; 1115 1116 /* 1117 * Check whether the actions associated with soft reset or one time 1118 * init need to be performed. 1119 */ 1120 if (cs35l56->soft_resetting) 1121 goto post_soft_reset; 1122 1123 if (cs35l56->base.init_done) 1124 return 0; 1125 1126 pm_runtime_set_autosuspend_delay(cs35l56->base.dev, 100); 1127 pm_runtime_use_autosuspend(cs35l56->base.dev); 1128 pm_runtime_set_active(cs35l56->base.dev); 1129 pm_runtime_enable(cs35l56->base.dev); 1130 1131 ret = cs35l56_hw_init(&cs35l56->base); 1132 if (ret < 0) 1133 return ret; 1134 1135 /* Populate the DSP information with the revision and security state */ 1136 cs35l56->dsp.part = devm_kasprintf(cs35l56->base.dev, GFP_KERNEL, "cs35l56%s-%02x", 1137 cs35l56->base.secured ? "s" : "", cs35l56->base.rev); 1138 if (!cs35l56->dsp.part) 1139 return -ENOMEM; 1140 1141 if (!cs35l56->base.reset_gpio) { 1142 dev_dbg(cs35l56->base.dev, "No reset gpio: using soft reset\n"); 1143 cs35l56->soft_resetting = true; 1144 cs35l56_system_reset(&cs35l56->base, !!cs35l56->sdw_peripheral); 1145 if (cs35l56->sdw_peripheral) { 1146 /* Keep alive while we wait for re-enumeration */ 1147 pm_runtime_get_noresume(cs35l56->base.dev); 1148 return 0; 1149 } 1150 } 1151 1152 post_soft_reset: 1153 if (cs35l56->soft_resetting) { 1154 cs35l56->soft_resetting = false; 1155 1156 /* Done re-enumerating after one-time init so release the keep-alive */ 1157 if (cs35l56->sdw_peripheral && !cs35l56->base.init_done) 1158 pm_runtime_put_noidle(cs35l56->base.dev); 1159 1160 regcache_mark_dirty(cs35l56->base.regmap); 1161 ret = cs35l56_wait_for_firmware_boot(&cs35l56->base); 1162 if (ret) 1163 return ret; 1164 1165 dev_dbg(cs35l56->base.dev, "Firmware rebooted after soft reset\n"); 1166 } 1167 1168 /* Disable auto-hibernate so that runtime_pm has control */ 1169 ret = cs35l56_mbox_send(&cs35l56->base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 1170 if (ret) 1171 return ret; 1172 1173 ret = cs35l56_set_patch(&cs35l56->base); 1174 if (ret) 1175 return ret; 1176 1177 /* Registers could be dirty after soft reset or SoundWire enumeration */ 1178 regcache_sync(cs35l56->base.regmap); 1179 1180 cs35l56->base.init_done = true; 1181 complete(&cs35l56->init_completion); 1182 1183 return 0; 1184 } 1185 EXPORT_SYMBOL_NS_GPL(cs35l56_init, SND_SOC_CS35L56_CORE); 1186 1187 void cs35l56_remove(struct cs35l56_private *cs35l56) 1188 { 1189 cs35l56->base.init_done = false; 1190 1191 /* 1192 * WAKE IRQs unmask if CS35L56 hibernates so free the handler to 1193 * prevent it racing with remove(). 1194 */ 1195 if (cs35l56->base.irq) 1196 devm_free_irq(cs35l56->base.dev, cs35l56->base.irq, &cs35l56->base); 1197 1198 flush_workqueue(cs35l56->dsp_wq); 1199 destroy_workqueue(cs35l56->dsp_wq); 1200 1201 pm_runtime_suspend(cs35l56->base.dev); 1202 pm_runtime_disable(cs35l56->base.dev); 1203 1204 regcache_cache_only(cs35l56->base.regmap, true); 1205 1206 kfree(cs35l56->dsp.system_name); 1207 1208 gpiod_set_value_cansleep(cs35l56->base.reset_gpio, 0); 1209 regulator_bulk_disable(ARRAY_SIZE(cs35l56->supplies), cs35l56->supplies); 1210 } 1211 EXPORT_SYMBOL_NS_GPL(cs35l56_remove, SND_SOC_CS35L56_CORE); 1212 1213 const struct dev_pm_ops cs35l56_pm_ops_i2c_spi = { 1214 SET_RUNTIME_PM_OPS(cs35l56_runtime_suspend_i2c_spi, cs35l56_runtime_resume_i2c_spi, NULL) 1215 SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend, cs35l56_system_resume) 1216 LATE_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_late, cs35l56_system_resume_early) 1217 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l56_system_suspend_no_irq, cs35l56_system_resume_no_irq) 1218 }; 1219 EXPORT_SYMBOL_NS_GPL(cs35l56_pm_ops_i2c_spi, SND_SOC_CS35L56_CORE); 1220 1221 MODULE_DESCRIPTION("ASoC CS35L56 driver"); 1222 MODULE_IMPORT_NS(SND_SOC_CS35L56_SHARED); 1223 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1224 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1225 MODULE_LICENSE("GPL"); 1226