1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 47 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 48 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 49 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 50 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 51 }; 52 53 static const struct reg_sequence cs35l56_patch_fw[] = { 54 /* These are not reset by a soft-reset, so patch to defaults. */ 55 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 56 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 57 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 58 }; 59 60 static const struct reg_sequence cs35l63_patch_fw[] = { 61 /* These are not reset by a soft-reset, so patch to defaults. */ 62 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 63 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 64 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 65 }; 66 67 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 68 { 69 int ret; 70 71 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 72 ARRAY_SIZE(cs35l56_patch)); 73 if (ret) 74 return ret; 75 76 77 switch (cs35l56_base->type) { 78 case 0x54: 79 case 0x56: 80 case 0x57: 81 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 82 ARRAY_SIZE(cs35l56_patch_fw)); 83 break; 84 case 0x63: 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 86 ARRAY_SIZE(cs35l63_patch_fw)); 87 break; 88 default: 89 break; 90 } 91 92 return ret; 93 } 94 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 95 96 static const struct reg_default cs35l56_reg_defaults[] = { 97 /* no defaults for OTP_MEM - first read populates cache */ 98 99 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 100 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 101 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 102 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 103 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 104 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 105 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 106 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 107 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 108 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 109 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 110 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 111 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 112 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 113 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 114 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 115 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 116 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 117 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 118 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 119 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 120 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 121 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 122 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 123 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 124 }; 125 126 static const struct reg_default cs35l63_reg_defaults[] = { 127 /* no defaults for OTP_MEM - first read populates cache */ 128 129 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 130 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 131 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 132 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 133 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 134 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 135 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 136 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 137 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 138 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 139 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 140 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 141 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 142 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 143 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 144 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 145 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 146 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 147 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 148 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 149 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 150 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 151 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 152 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 153 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 154 }; 155 156 static bool cs35l56_is_dsp_memory(unsigned int reg) 157 { 158 switch (reg) { 159 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 160 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 161 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 162 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 163 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 164 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 165 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 173 { 174 switch (reg) { 175 case CS35L56_DEVID: 176 case CS35L56_REVID: 177 case CS35L56_RELID: 178 case CS35L56_OTPID: 179 case CS35L56_SFT_RESET: 180 case CS35L56_GLOBAL_ENABLES: 181 case CS35L56_BLOCK_ENABLES: 182 case CS35L56_BLOCK_ENABLES2: 183 case CS35L56_REFCLK_INPUT: 184 case CS35L56_GLOBAL_SAMPLE_RATE: 185 case CS35L56_OTP_MEM_53: 186 case CS35L56_OTP_MEM_54: 187 case CS35L56_OTP_MEM_55: 188 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 189 case CS35L56_UPDATE_REGS: 190 case CS35L56_ASP1_ENABLES1: 191 case CS35L56_ASP1_CONTROL1: 192 case CS35L56_ASP1_CONTROL2: 193 case CS35L56_ASP1_CONTROL3: 194 case CS35L56_ASP1_FRAME_CONTROL1: 195 case CS35L56_ASP1_FRAME_CONTROL5: 196 case CS35L56_ASP1_DATA_CONTROL1: 197 case CS35L56_ASP1_DATA_CONTROL5: 198 case CS35L56_DACPCM1_INPUT: 199 case CS35L56_DACPCM2_INPUT: 200 case CS35L56_ASP1TX1_INPUT: 201 case CS35L56_ASP1TX2_INPUT: 202 case CS35L56_ASP1TX3_INPUT: 203 case CS35L56_ASP1TX4_INPUT: 204 case CS35L56_DSP1RX1_INPUT: 205 case CS35L56_DSP1RX2_INPUT: 206 case CS35L56_SWIRE_DP3_CH1_INPUT: 207 case CS35L56_SWIRE_DP3_CH2_INPUT: 208 case CS35L56_SWIRE_DP3_CH3_INPUT: 209 case CS35L56_SWIRE_DP3_CH4_INPUT: 210 case CS35L56_IRQ1_CFG: 211 case CS35L56_IRQ1_STATUS: 212 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 213 case CS35L56_IRQ1_EINT_18: 214 case CS35L56_IRQ1_EINT_20: 215 case CS35L56_IRQ1_MASK_1: 216 case CS35L56_IRQ1_MASK_2: 217 case CS35L56_IRQ1_MASK_4: 218 case CS35L56_IRQ1_MASK_8: 219 case CS35L56_IRQ1_MASK_18: 220 case CS35L56_IRQ1_MASK_20: 221 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 222 case CS35L56_MIXER_NGATE_CH1_CFG: 223 case CS35L56_MIXER_NGATE_CH2_CFG: 224 case CS35L56_DSP_VIRTUAL1_MBOX_1: 225 case CS35L56_DSP_VIRTUAL1_MBOX_2: 226 case CS35L56_DSP_VIRTUAL1_MBOX_3: 227 case CS35L56_DSP_VIRTUAL1_MBOX_4: 228 case CS35L56_DSP_VIRTUAL1_MBOX_5: 229 case CS35L56_DSP_VIRTUAL1_MBOX_6: 230 case CS35L56_DSP_VIRTUAL1_MBOX_7: 231 case CS35L56_DSP_VIRTUAL1_MBOX_8: 232 case CS35L56_DIE_STS1: 233 case CS35L56_DIE_STS2: 234 case CS35L56_DSP_RESTRICT_STS1: 235 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 236 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 237 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 238 case CS35L56_DSP1_SCRATCH1: 239 case CS35L56_DSP1_SCRATCH2: 240 case CS35L56_DSP1_SCRATCH3: 241 case CS35L56_DSP1_SCRATCH4: 242 return true; 243 default: 244 return cs35l56_is_dsp_memory(reg); 245 } 246 } 247 248 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 249 { 250 switch (reg) { 251 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 252 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 253 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 254 return true; 255 default: 256 return false; 257 } 258 } 259 260 static bool cs35l56_common_volatile_reg(unsigned int reg) 261 { 262 switch (reg) { 263 case CS35L56_DEVID: 264 case CS35L56_REVID: 265 case CS35L56_RELID: 266 case CS35L56_OTPID: 267 case CS35L56_SFT_RESET: 268 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 269 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 270 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 271 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 272 case CS35L56_UPDATE_REGS: 273 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 274 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 275 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 276 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 277 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 278 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 279 case CS35L56_IRQ1_STATUS: 280 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 281 case CS35L56_IRQ1_EINT_18: 282 case CS35L56_IRQ1_EINT_20: 283 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 284 case CS35L56_MIXER_NGATE_CH1_CFG: 285 case CS35L56_MIXER_NGATE_CH2_CFG: 286 case CS35L56_DSP_VIRTUAL1_MBOX_1: 287 case CS35L56_DSP_VIRTUAL1_MBOX_2: 288 case CS35L56_DSP_VIRTUAL1_MBOX_3: 289 case CS35L56_DSP_VIRTUAL1_MBOX_4: 290 case CS35L56_DSP_VIRTUAL1_MBOX_5: 291 case CS35L56_DSP_VIRTUAL1_MBOX_6: 292 case CS35L56_DSP_VIRTUAL1_MBOX_7: 293 case CS35L56_DSP_VIRTUAL1_MBOX_8: 294 case CS35L56_DSP_RESTRICT_STS1: 295 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 296 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 297 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 298 case CS35L56_DSP1_SCRATCH1: 299 case CS35L56_DSP1_SCRATCH2: 300 case CS35L56_DSP1_SCRATCH3: 301 case CS35L56_DSP1_SCRATCH4: 302 return true; 303 default: 304 return cs35l56_is_dsp_memory(reg); 305 } 306 } 307 308 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 309 { 310 switch (reg) { 311 case CS35L56_MAIN_RENDER_USER_MUTE: 312 case CS35L56_MAIN_RENDER_USER_VOLUME: 313 case CS35L56_MAIN_POSTURE_NUMBER: 314 return false; 315 default: 316 return cs35l56_common_volatile_reg(reg); 317 } 318 } 319 320 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 321 { 322 switch (reg) { 323 case CS35L63_MAIN_RENDER_USER_MUTE: 324 case CS35L63_MAIN_RENDER_USER_VOLUME: 325 case CS35L63_MAIN_POSTURE_NUMBER: 326 return false; 327 default: 328 return cs35l56_common_volatile_reg(reg); 329 } 330 } 331 332 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 333 .fw_ver = CS35L56_DSP1_FW_VER, 334 .halo_state = CS35L56_DSP1_HALO_STATE, 335 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 336 .prot_sts = CS35L56_PROTECTION_STATUS, 337 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 338 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 339 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 340 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 341 }; 342 343 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 344 .fw_ver = CS35L56_DSP1_FW_VER, 345 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 346 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 347 .prot_sts = CS35L56_PROTECTION_STATUS, 348 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 349 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 350 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 351 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 352 }; 353 354 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 355 .fw_ver = CS35L63_DSP1_FW_VER, 356 .halo_state = CS35L63_DSP1_HALO_STATE, 357 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 358 .prot_sts = CS35L63_PROTECTION_STATUS, 359 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 360 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 361 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 362 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 363 }; 364 365 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 366 { 367 switch (cs35l56_base->type) { 368 default: 369 switch (cs35l56_base->rev) { 370 case 0xb0: 371 cs35l56_base->fw_reg = &cs35l56_fw_reg; 372 break; 373 default: 374 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 375 break; 376 } 377 break; 378 case 0x63: 379 cs35l56_base->fw_reg = &cs35l63_fw_reg; 380 break; 381 } 382 } 383 384 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 385 { 386 unsigned int val; 387 int ret; 388 389 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 390 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 391 val, (val == 0), 392 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 393 if (ret) { 394 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 395 return ret; 396 } 397 398 return 0; 399 } 400 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 401 402 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 403 { 404 int ret; 405 unsigned int val; 406 407 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 408 if (ret) 409 return ret; 410 411 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 412 cs35l56_base->fw_reg->pm_cur_stat, 413 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 414 CS35L56_HALO_STATE_POLL_US, 415 CS35L56_HALO_STATE_TIMEOUT_US); 416 if (ret < 0) 417 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 418 val, ret); 419 return ret; 420 } 421 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 422 423 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 424 { 425 unsigned int val = 0; 426 int read_ret, poll_ret; 427 428 /* 429 * The regmap must remain in cache-only until the chip has 430 * booted, so use a bypassed read of the status register. 431 */ 432 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 433 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 434 CS35L56_HALO_STATE_POLL_US, 435 CS35L56_HALO_STATE_TIMEOUT_US, 436 false, 437 cs35l56_base->regmap, 438 cs35l56_base->fw_reg->halo_state, 439 &val); 440 441 if (poll_ret) { 442 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 443 read_ret, val); 444 return -EIO; 445 } 446 447 return 0; 448 } 449 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 450 451 void cs35l56_wait_control_port_ready(void) 452 { 453 /* Wait for control port to be ready (datasheet tIRS). */ 454 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 455 } 456 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 457 458 void cs35l56_wait_min_reset_pulse(void) 459 { 460 /* Satisfy minimum reset pulse width spec */ 461 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 462 } 463 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 464 465 static const struct { 466 u32 addr; 467 u32 value; 468 } cs35l56_spi_system_reset_stages[] = { 469 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 470 /* The next write is necessary to delimit the soft reset */ 471 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 472 }; 473 474 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 475 struct spi_device *spi) 476 { 477 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 478 struct spi_transfer t = { 479 .tx_buf = buf, 480 .len = sizeof(*buf), 481 }; 482 struct spi_message m; 483 int i, ret; 484 485 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 486 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 487 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 488 spi_message_init_with_transfers(&m, &t, 1); 489 ret = spi_sync_locked(spi, &m); 490 if (ret) 491 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 492 493 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 494 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 495 } 496 } 497 498 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 499 { 500 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 501 unsigned int val; 502 int read_ret, ret; 503 504 /* 505 * There must not be any other SPI bus activity while the amp is 506 * soft-resetting. 507 */ 508 ret = spi_bus_lock(spi->controller); 509 if (ret) { 510 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 511 return; 512 } 513 514 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 515 spi_bus_unlock(spi->controller); 516 517 /* 518 * Check firmware boot by testing for a response in MBOX_2. 519 * HALO_STATE cannot be trusted yet because the reset sequence 520 * can leave it with stale state. But MBOX is reset. 521 * The regmap must remain in cache-only until the chip has 522 * booted, so use a bypassed read. 523 */ 524 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 525 (val > 0) && (val < 0xffffffff), 526 CS35L56_HALO_STATE_POLL_US, 527 CS35L56_HALO_STATE_TIMEOUT_US, 528 false, 529 cs35l56_base->regmap, 530 CS35L56_DSP_VIRTUAL1_MBOX_2, 531 &val); 532 if (ret) { 533 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 534 read_ret, val); 535 } 536 } 537 538 static const struct reg_sequence cs35l56_system_reset_seq[] = { 539 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 540 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 541 }; 542 543 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 544 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 545 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 546 }; 547 548 static const struct reg_sequence cs35l63_system_reset_seq[] = { 549 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 550 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 551 }; 552 553 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 554 { 555 /* 556 * Must enter cache-only first so there can't be any more register 557 * accesses other than the controlled system reset sequence below. 558 */ 559 regcache_cache_only(cs35l56_base->regmap, true); 560 561 if (cs35l56_is_spi(cs35l56_base)) { 562 cs35l56_spi_system_reset(cs35l56_base); 563 return; 564 } 565 566 switch (cs35l56_base->type) { 567 case 0x54: 568 case 0x56: 569 case 0x57: 570 switch (cs35l56_base->rev) { 571 case 0xb0: 572 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 573 cs35l56_system_reset_seq, 574 ARRAY_SIZE(cs35l56_system_reset_seq)); 575 break; 576 default: 577 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 578 cs35l56_b2_system_reset_seq, 579 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 580 break; 581 } 582 break; 583 case 0x63: 584 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 585 cs35l63_system_reset_seq, 586 ARRAY_SIZE(cs35l63_system_reset_seq)); 587 break; 588 default: 589 break; 590 } 591 592 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 593 if (is_soundwire) 594 return; 595 596 cs35l56_wait_control_port_ready(); 597 598 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 599 } 600 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 601 602 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 603 { 604 int ret; 605 606 if (irq < 1) 607 return 0; 608 609 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 610 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 611 "cs35l56", cs35l56_base); 612 if (!ret) 613 cs35l56_base->irq = irq; 614 else 615 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 616 617 return ret; 618 } 619 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 620 621 irqreturn_t cs35l56_irq(int irq, void *data) 622 { 623 struct cs35l56_base *cs35l56_base = data; 624 unsigned int status1 = 0, status8 = 0, status20 = 0; 625 unsigned int mask1, mask8, mask20; 626 unsigned int val; 627 int rv; 628 629 irqreturn_t ret = IRQ_NONE; 630 631 if (!cs35l56_base->init_done) 632 return IRQ_NONE; 633 634 mutex_lock(&cs35l56_base->irq_lock); 635 636 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 637 if (rv < 0) { 638 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 639 goto err_unlock; 640 } 641 642 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 643 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 644 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 645 goto err; 646 } 647 648 /* Ack interrupts */ 649 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 650 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 651 status1 &= ~mask1; 652 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 653 654 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 655 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 656 status8 &= ~mask8; 657 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 658 659 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 660 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 661 status20 &= ~mask20; 662 /* We don't want EINT20 but they default to unmasked: force mask */ 663 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 664 665 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 666 667 /* Check to see if unmasked bits are active */ 668 if (!status1 && !status8 && !status20) 669 goto err; 670 671 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 672 dev_crit(cs35l56_base->dev, "Amp short error\n"); 673 674 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 675 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 676 677 ret = IRQ_HANDLED; 678 679 err: 680 pm_runtime_put(cs35l56_base->dev); 681 err_unlock: 682 mutex_unlock(&cs35l56_base->irq_lock); 683 684 return ret; 685 } 686 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 687 688 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 689 { 690 unsigned int val; 691 int ret; 692 693 /* 694 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 695 * can't be used here to test for memory retention. 696 * Assume that tuning must be re-loaded. 697 */ 698 if (cs35l56_base->secured) 699 return true; 700 701 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 702 if (ret) { 703 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 704 return ret; 705 } 706 707 ret = regmap_read(cs35l56_base->regmap, 708 cs35l56_base->fw_reg->prot_sts, 709 &val); 710 if (ret) 711 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 712 else 713 ret = !!(val & CS35L56_FIRMWARE_MISSING); 714 715 pm_runtime_put_autosuspend(cs35l56_base->dev); 716 717 return ret; 718 } 719 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 720 721 static const struct reg_sequence cs35l56_hibernate_seq[] = { 722 /* This must be the last register access */ 723 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 724 }; 725 726 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 727 { 728 unsigned int val; 729 730 /* 731 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 732 * transactions to meet the minimum required time from the rising edge 733 * to the last falling edge of wake. 734 * 735 * It uses bypassed read because we must wake the chip before 736 * disabling regmap cache-only. 737 */ 738 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 739 740 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 741 742 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 743 744 cs35l56_wait_control_port_ready(); 745 } 746 747 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 748 { 749 unsigned int val; 750 int ret; 751 752 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 753 cs35l56_base->fw_reg->transducer_actual_ps, 754 val, (val >= CS35L56_PS3), 755 CS35L56_PS3_POLL_US, 756 CS35L56_PS3_TIMEOUT_US); 757 if (ret) 758 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 759 760 return ret; 761 } 762 763 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 764 { 765 if (!cs35l56_base->init_done) 766 return 0; 767 768 /* Firmware must have entered a power-save state */ 769 cs35l56_wait_for_ps3(cs35l56_base); 770 771 /* Clear BOOT_DONE so it can be used to detect a reboot */ 772 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 773 774 if (!cs35l56_base->can_hibernate) { 775 regcache_cache_only(cs35l56_base->regmap, true); 776 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 777 778 return 0; 779 } 780 781 /* 782 * Must enter cache-only first so there can't be any more register 783 * accesses other than the controlled hibernate sequence below. 784 */ 785 regcache_cache_only(cs35l56_base->regmap, true); 786 787 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 788 cs35l56_hibernate_seq, 789 ARRAY_SIZE(cs35l56_hibernate_seq)); 790 791 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 792 793 return 0; 794 } 795 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 796 797 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 798 { 799 unsigned int val; 800 int ret; 801 802 if (!cs35l56_base->init_done) 803 return 0; 804 805 if (!cs35l56_base->can_hibernate) 806 goto out_sync; 807 808 /* Must be done before releasing cache-only */ 809 if (!is_soundwire) 810 cs35l56_issue_wake_event(cs35l56_base); 811 812 out_sync: 813 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 814 if (ret) { 815 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 816 goto err; 817 } 818 819 regcache_cache_only(cs35l56_base->regmap, false); 820 821 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 822 if (ret) 823 goto err; 824 825 /* BOOT_DONE will be 1 if the amp reset */ 826 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 827 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 828 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 829 regcache_mark_dirty(cs35l56_base->regmap); 830 } 831 832 regcache_sync(cs35l56_base->regmap); 833 834 dev_dbg(cs35l56_base->dev, "Resumed"); 835 836 return 0; 837 838 err: 839 regcache_cache_only(cs35l56_base->regmap, true); 840 841 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 842 cs35l56_hibernate_seq, 843 ARRAY_SIZE(cs35l56_hibernate_seq)); 844 845 return ret; 846 } 847 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 848 849 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 850 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 851 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 852 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 853 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 854 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 855 }; 856 857 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 858 { 859 cs_dsp->num = 1; 860 cs_dsp->type = WMFW_HALO; 861 cs_dsp->rev = 0; 862 cs_dsp->dev = cs35l56_base->dev; 863 cs_dsp->regmap = cs35l56_base->regmap; 864 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 865 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 866 cs_dsp->mem = cs35l56_dsp1_regions; 867 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 868 cs_dsp->no_core_startstop = true; 869 870 cs35l56_base->dsp = cs_dsp; 871 } 872 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 873 874 struct cs35l56_pte { 875 u8 x; 876 u8 wafer_id; 877 u8 pte[2]; 878 u8 lot[3]; 879 u8 y; 880 u8 unused[3]; 881 u8 dvs; 882 } __packed; 883 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 884 885 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 886 { 887 struct cs35l56_pte pte; 888 u64 unique_id; 889 int ret; 890 891 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 892 if (ret) { 893 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 894 return ret; 895 } 896 897 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 898 unique_id <<= 32; 899 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 900 ((u32)pte.dvs << 24); 901 902 cs35l56_base->silicon_uid = unique_id; 903 904 return 0; 905 } 906 907 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 908 { 909 u32 tmp[2]; 910 u64 unique_id; 911 int ret; 912 913 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 914 if (ret) { 915 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 916 return ret; 917 } 918 919 unique_id = tmp[1]; 920 unique_id <<= 32; 921 unique_id |= tmp[0]; 922 923 cs35l56_base->silicon_uid = unique_id; 924 925 return 0; 926 } 927 928 /* Firmware calibration controls */ 929 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 930 .alg_id = 0x9f210, 931 .mem_region = WMFW_ADSP2_YM, 932 .ambient = "CAL_AMBIENT", 933 .calr = "CAL_R", 934 .status = "CAL_STATUS", 935 .checksum = "CAL_CHECKSUM", 936 }; 937 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 938 939 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 940 .alg_id = 0xbf210, 941 .mem_region = WMFW_ADSP2_YM, 942 .ambient = "CAL_AMBIENT", 943 .calr = "CAL_R", 944 .status = "CAL_STATUS", 945 .checksum = "CAL_CHECKSUM", 946 }; 947 948 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 949 { 950 int ret; 951 952 /* Driver can't apply calibration to a secured part, so skip */ 953 if (cs35l56_base->secured) 954 return 0; 955 956 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 957 cs35l56_base->silicon_uid, 958 cs35l56_base->cal_index, 959 &cs35l56_base->cal_data); 960 961 /* Only return an error status if probe should be aborted */ 962 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 963 return 0; 964 965 if (ret < 0) 966 return ret; 967 968 cs35l56_base->cal_data_valid = true; 969 970 return 0; 971 } 972 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 973 974 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 975 const struct cirrus_amp_cal_data *data) 976 { 977 978 /* Ignore if it is empty */ 979 if (!data->calTime[0] && !data->calTime[1]) 980 return -ENODATA; 981 982 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 983 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 984 return -EINVAL; 985 } 986 987 cs35l56_base->cal_data = *data; 988 cs35l56_base->cal_data_valid = true; 989 990 return 0; 991 } 992 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 993 994 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 995 { 996 const struct cirrus_amp_cal_controls *calibration_controls = 997 cs35l56_base->calibration_controls; 998 struct cs_dsp *dsp = cs35l56_base->dsp; 999 struct cirrus_amp_cal_data cal_data; 1000 struct cs_dsp_coeff_ctl *ctl; 1001 bool ngate_ch1_was_enabled = false; 1002 bool ngate_ch2_was_enabled = false; 1003 int cali_norm_en_alg_id, cali_norm_en_mem; 1004 int ret; 1005 __be32 val; 1006 1007 if (cs35l56_base->silicon_uid == 0) { 1008 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1009 return -ENXIO; 1010 } 1011 1012 switch (cs35l56_base->type) { 1013 case 0x54: 1014 case 0x56: 1015 case 0x57: 1016 if (cs35l56_base->rev < 0xb2) { 1017 cali_norm_en_alg_id = 0x9f22f; 1018 cali_norm_en_mem = WMFW_ADSP2_YM; 1019 } else { 1020 cali_norm_en_alg_id = 0x9f210; 1021 cali_norm_en_mem = WMFW_ADSP2_XM; 1022 } 1023 break; 1024 default: 1025 cali_norm_en_alg_id = 0xbf210; 1026 cali_norm_en_mem = WMFW_ADSP2_XM; 1027 break; 1028 } 1029 1030 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1031 if (ret) 1032 return ret; 1033 1034 ret = cs35l56_wait_for_ps3(cs35l56_base); 1035 if (ret) { 1036 ret = -EBUSY; 1037 goto err_pm_put; 1038 } 1039 1040 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1041 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1042 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1043 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1044 1045 scoped_guard(mutex, &dsp->pwr_lock) { 1046 ctl = cs_dsp_get_ctl(dsp, 1047 calibration_controls->status, 1048 calibration_controls->mem_region, 1049 calibration_controls->alg_id); 1050 if (!ctl) { 1051 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1052 calibration_controls->status); 1053 ret = -EIO; 1054 goto err; 1055 } 1056 1057 val = cpu_to_be32(0); 1058 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1059 "CALI_NORM_EN", 1060 cali_norm_en_mem, 1061 cali_norm_en_alg_id), 1062 0, &val, sizeof(val)); 1063 if (ret < 0) { 1064 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1065 ret = -EIO; 1066 goto err; 1067 } 1068 1069 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1070 if (ret) { 1071 ret = -EIO; 1072 goto err; 1073 } 1074 1075 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1076 (val == cpu_to_be32(1)), 1077 CS35L56_CALIBRATION_POLL_US, 1078 CS35L56_CALIBRATION_TIMEOUT_US, 1079 true, 1080 ctl, 0, &val, sizeof(val))) { 1081 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1082 be32_to_cpu(val)); 1083 switch (be32_to_cpu(val)) { 1084 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1085 ret = -ERANGE; 1086 goto err; 1087 default: 1088 ret = -ETIMEDOUT; 1089 goto err; 1090 } 1091 } 1092 } 1093 1094 cs35l56_base->cal_data_valid = false; 1095 memset(&cal_data, 0, sizeof(cal_data)); 1096 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1097 if (ret) { 1098 ret = -EIO; 1099 goto err; 1100 } 1101 1102 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1103 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1104 1105 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1106 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1107 cs35l56_base->cal_data = cal_data; 1108 cs35l56_base->cal_data_valid = true; 1109 1110 ret = 0; 1111 1112 err: 1113 if (ngate_ch1_was_enabled) { 1114 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1115 CS35L56_AUX_NGATE_CHn_EN); 1116 } 1117 if (ngate_ch2_was_enabled) { 1118 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1119 CS35L56_AUX_NGATE_CHn_EN); 1120 } 1121 err_pm_put: 1122 pm_runtime_put(cs35l56_base->dev); 1123 1124 return ret; 1125 } 1126 1127 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1128 const char __user *from, size_t count, 1129 loff_t *ppos) 1130 { 1131 static const char * const options[] = { "factory", "store_uefi" }; 1132 char buf[11] = { 0 }; 1133 int num_amps, ret; 1134 1135 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1136 return -ENXIO; 1137 1138 if (*ppos) 1139 return -EINVAL; 1140 1141 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1142 if (ret < 0) 1143 return ret; 1144 1145 switch (sysfs_match_string(options, buf)) { 1146 case 0: 1147 ret = cs35l56_perform_calibration(cs35l56_base); 1148 if (ret < 0) 1149 return ret; 1150 break; 1151 case 1: 1152 if (!cs35l56_base->cal_data_valid) 1153 return -ENODATA; 1154 1155 num_amps = cs35l56_base->num_amps; 1156 if (num_amps == 0) 1157 num_amps = -1; 1158 1159 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1160 cs35l56_base->cal_index, 1161 num_amps, 1162 &cs35l56_base->cal_data); 1163 if (ret < 0) 1164 return ret; 1165 break; 1166 default: 1167 return -EOPNOTSUPP; 1168 } 1169 1170 return count; 1171 } 1172 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1173 1174 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1175 const char __user *from, size_t count, 1176 loff_t *ppos) 1177 { 1178 unsigned long val; 1179 int ret; 1180 1181 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1182 return -ENXIO; 1183 1184 if (*ppos) 1185 return -EINVAL; 1186 1187 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1188 if (ret) 1189 return ret; 1190 1191 ret = kstrtoul_from_user(from, count, 10, &val); 1192 if (ret < 0) 1193 goto out; 1194 1195 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1196 if (ret) 1197 ret = -EIO; 1198 out: 1199 pm_runtime_put(cs35l56_base->dev); 1200 1201 if (ret < 0) 1202 return ret; 1203 1204 return count; 1205 } 1206 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1207 1208 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1209 char __user *to, size_t count, 1210 loff_t *ppos) 1211 { 1212 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1213 return -ENXIO; 1214 1215 if (!cs35l56_base->cal_data_valid) 1216 return 0; 1217 1218 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1219 sizeof(cs35l56_base->cal_data)); 1220 } 1221 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1222 1223 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1224 const char __user *from, size_t count, 1225 loff_t *ppos) 1226 { 1227 struct cirrus_amp_cal_data cal_data; 1228 int ret; 1229 1230 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1231 return -ENXIO; 1232 1233 /* Only allow a full blob to be written */ 1234 if (*ppos || (count != sizeof(cal_data))) 1235 return -EMSGSIZE; 1236 1237 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1238 if (ret) 1239 return ret; 1240 1241 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1242 if (ret) 1243 return ret; 1244 1245 return count; 1246 } 1247 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1248 1249 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1250 const struct cs35l56_cal_debugfs_fops *fops) 1251 { 1252 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1253 return; 1254 1255 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1256 1257 debugfs_create_file("calibrate", 1258 0200, cs35l56_base->debugfs, cs35l56_base, 1259 &fops->calibrate); 1260 debugfs_create_file("cal_temperature", 1261 0200, cs35l56_base->debugfs, cs35l56_base, 1262 &fops->cal_temperature); 1263 debugfs_create_file("cal_data", 1264 0644, cs35l56_base->debugfs, cs35l56_base, 1265 &fops->cal_data); 1266 } 1267 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1268 1269 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1270 { 1271 debugfs_remove_recursive(cs35l56_base->debugfs); 1272 } 1273 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1274 1275 const char * const cs35l56_cal_set_status_text[] = { 1276 "Unknown", "Default", "Set", 1277 }; 1278 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1279 1280 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1281 struct snd_ctl_elem_value *uvalue) 1282 { 1283 struct cs_dsp *dsp = cs35l56_base->dsp; 1284 __be32 cal_set_status_be; 1285 int alg_id; 1286 int ret; 1287 1288 switch (cs35l56_base->type) { 1289 case 0x54: 1290 case 0x56: 1291 case 0x57: 1292 alg_id = 0x9f210; 1293 break; 1294 default: 1295 alg_id = 0xbf210; 1296 break; 1297 } 1298 1299 scoped_guard(mutex, &dsp->pwr_lock) { 1300 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1301 "CAL_SET_STATUS", 1302 WMFW_ADSP2_YM, alg_id), 1303 0, &cal_set_status_be, 1304 sizeof(cal_set_status_be)); 1305 } 1306 if (ret) { 1307 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1308 return 0; 1309 } 1310 1311 switch (be32_to_cpu(cal_set_status_be)) { 1312 case CS35L56_CAL_SET_STATUS_DEFAULT: 1313 case CS35L56_CAL_SET_STATUS_SET: 1314 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1315 return 0; 1316 default: 1317 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1318 return 0; 1319 } 1320 } 1321 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1322 1323 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1324 bool *fw_missing, unsigned int *fw_version) 1325 { 1326 unsigned int prot_status; 1327 int ret; 1328 1329 ret = regmap_read(cs35l56_base->regmap, 1330 cs35l56_base->fw_reg->prot_sts, &prot_status); 1331 if (ret) { 1332 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1333 return ret; 1334 } 1335 1336 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1337 1338 ret = regmap_read(cs35l56_base->regmap, 1339 cs35l56_base->fw_reg->fw_ver, fw_version); 1340 if (ret) { 1341 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1342 return ret; 1343 } 1344 1345 return 0; 1346 } 1347 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1348 1349 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1350 { 1351 unsigned int firmware_version; 1352 bool firmware_missing; 1353 int ret; 1354 1355 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1356 if (ret) 1357 return; 1358 1359 if (!firmware_missing) 1360 return; 1361 1362 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1363 } 1364 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1365 1366 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1367 { 1368 __be32 pid, sid, tid; 1369 unsigned int alg_id; 1370 int ret; 1371 1372 switch (cs35l56_base->type) { 1373 case 0x54: 1374 case 0x56: 1375 case 0x57: 1376 alg_id = 0x9f212; 1377 break; 1378 default: 1379 alg_id = 0xbf212; 1380 break; 1381 } 1382 1383 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1384 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1385 WMFW_ADSP2_XM, alg_id), 1386 0, &pid, sizeof(pid)); 1387 if (!ret) 1388 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1389 WMFW_ADSP2_XM, alg_id), 1390 0, &sid, sizeof(sid)); 1391 if (!ret) 1392 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1393 WMFW_ADSP2_XM, alg_id), 1394 0, &tid, sizeof(tid)); 1395 } 1396 1397 if (ret) 1398 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1399 else 1400 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1401 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1402 } 1403 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1404 1405 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1406 { 1407 int ret; 1408 unsigned int devid, revid, otpid, secured, fw_ver; 1409 bool fw_missing; 1410 1411 /* 1412 * When the system is not using a reset_gpio ensure the device is 1413 * awake, otherwise the device has just been released from reset and 1414 * the driver must wait for the control port to become usable. 1415 */ 1416 if (!cs35l56_base->reset_gpio) 1417 cs35l56_issue_wake_event(cs35l56_base); 1418 else 1419 cs35l56_wait_control_port_ready(); 1420 1421 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1422 if (ret < 0) { 1423 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1424 return ret; 1425 } 1426 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1427 cs35l56_set_fw_reg_table(cs35l56_base); 1428 1429 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1430 if (ret) 1431 return ret; 1432 1433 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1434 if (ret < 0) { 1435 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1436 return ret; 1437 } 1438 devid &= CS35L56_DEVID_MASK; 1439 1440 switch (devid) { 1441 case 0x35A54: 1442 case 0x35A56: 1443 case 0x35A57: 1444 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1445 break; 1446 case 0x35A630: 1447 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1448 devid = devid >> 4; 1449 break; 1450 default: 1451 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1452 return -ENODEV; 1453 } 1454 1455 cs35l56_base->type = devid & 0xFF; 1456 1457 /* Silicon is now identified and booted so exit cache-only */ 1458 regcache_cache_only(cs35l56_base->regmap, false); 1459 1460 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1461 if (ret) { 1462 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1463 return ret; 1464 } 1465 1466 /* When any bus is restricted treat the device as secured */ 1467 if (secured & CS35L56_RESTRICTED_MASK) 1468 cs35l56_base->secured = true; 1469 1470 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1471 if (ret < 0) { 1472 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1473 return ret; 1474 } 1475 1476 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1477 if (ret) 1478 return ret; 1479 1480 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1481 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1482 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1483 1484 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1485 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1486 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1487 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1488 0); 1489 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1490 CS35L56_TEMP_ERR_EINT1_MASK, 1491 0); 1492 1493 switch (cs35l56_base->type) { 1494 case 0x54: 1495 case 0x56: 1496 case 0x57: 1497 ret = cs35l56_read_silicon_uid(cs35l56_base); 1498 break; 1499 default: 1500 ret = cs35l63_read_silicon_uid(cs35l56_base); 1501 break; 1502 } 1503 if (ret) 1504 return ret; 1505 1506 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1507 1508 return 0; 1509 } 1510 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1511 1512 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1513 { 1514 struct gpio_descs *descs; 1515 u32 speaker_id; 1516 int i, ret; 1517 1518 /* Check for vendor-specific speaker ID method */ 1519 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1520 if (ret >= 0) { 1521 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1522 return ret; 1523 } else if (ret != -ENOENT) { 1524 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1525 return ret; 1526 } 1527 1528 /* Attempt to read the speaker type from a device property */ 1529 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1530 if (!ret) { 1531 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1532 return speaker_id; 1533 } 1534 1535 /* Read the speaker type qualifier from the motherboard GPIOs */ 1536 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1537 if (!descs) { 1538 return -ENOENT; 1539 } else if (IS_ERR(descs)) { 1540 ret = PTR_ERR(descs); 1541 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1542 } 1543 1544 speaker_id = 0; 1545 for (i = 0; i < descs->ndescs; i++) { 1546 ret = gpiod_get_value_cansleep(descs->desc[i]); 1547 if (ret < 0) { 1548 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1549 goto err; 1550 } 1551 1552 speaker_id |= (ret << i); 1553 } 1554 1555 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1556 ret = speaker_id; 1557 err: 1558 gpiod_put_array(descs); 1559 1560 return ret; 1561 } 1562 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1563 1564 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1565 const u32 *gpios, int num_gpios, 1566 const u32 *pulls, int num_pulls) 1567 { 1568 int max_gpio; 1569 int ret = 0; 1570 int i; 1571 1572 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1573 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1574 return -EOVERFLOW; 1575 1576 switch (cs35l56_base->type) { 1577 case 0x54: 1578 case 0x56: 1579 case 0x57: 1580 max_gpio = CS35L56_MAX_GPIO; 1581 break; 1582 default: 1583 max_gpio = CS35L63_MAX_GPIO; 1584 break; 1585 } 1586 1587 for (i = 0; i < num_gpios; i++) { 1588 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1589 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1590 /* Keep going so we log all bad values */ 1591 ret = -EINVAL; 1592 } 1593 1594 /* Change to zero-based */ 1595 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1596 } 1597 1598 for (i = 0; i < num_pulls; i++) { 1599 switch (pulls[i]) { 1600 case 0: 1601 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1602 break; 1603 case 1: 1604 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1605 break; 1606 case 2: 1607 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1608 break; 1609 default: 1610 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1611 /* Keep going so we log all bad values */ 1612 ret = -EINVAL; 1613 break; 1614 } 1615 } 1616 if (ret) 1617 return ret; 1618 1619 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1620 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1621 1622 return 0; 1623 } 1624 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1625 1626 /* Caller must pm_runtime resume before calling this function */ 1627 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1628 { 1629 struct regmap *regmap = cs35l56_base->regmap; 1630 unsigned int addr_offset, val; 1631 int num_gpios, num_pulls; 1632 int i, ret; 1633 1634 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1635 1636 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1637 return 0; 1638 1639 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1640 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1641 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1642 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1643 1644 for (i = 0; i < num_gpios; i++) { 1645 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1646 1647 /* Set unspecified pulls to NONE */ 1648 if (i < num_pulls) { 1649 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1650 cs35l56_base->onchip_spkid_pulls[i]); 1651 } else { 1652 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1653 } 1654 1655 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1656 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1657 val | CS35L56_PAD_GPIO_IE); 1658 if (ret) { 1659 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1660 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1661 return ret; 1662 } 1663 } 1664 1665 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1666 if (ret) { 1667 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1668 return ret; 1669 } 1670 1671 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1672 1673 return 0; 1674 } 1675 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1676 1677 /* Caller must pm_runtime resume before calling this function */ 1678 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1679 { 1680 struct regmap *regmap = cs35l56_base->regmap; 1681 unsigned int addr_offset, val; 1682 int num_gpios; 1683 int speaker_id = 0; 1684 int i, ret; 1685 1686 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1687 1688 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1689 return -ENOENT; 1690 1691 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1692 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1693 1694 for (i = 0; i < num_gpios; i++) { 1695 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1696 1697 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1698 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1699 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1700 if (ret) { 1701 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1702 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1703 return ret; 1704 } 1705 } 1706 1707 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1708 if (ret) { 1709 dev_err(cs35l56_base->dev, "GPIO%d status read failed: %d\n", 1710 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1711 return ret; 1712 } 1713 1714 for (i = 0; i < num_gpios; i++) { 1715 speaker_id <<= 1; 1716 1717 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1718 speaker_id |= 1; 1719 } 1720 1721 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1722 1723 return speaker_id; 1724 } 1725 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1726 1727 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1728 [0x0C] = 128000, 1729 [0x0F] = 256000, 1730 [0x11] = 384000, 1731 [0x12] = 512000, 1732 [0x15] = 768000, 1733 [0x17] = 1024000, 1734 [0x1A] = 1500000, 1735 [0x1B] = 1536000, 1736 [0x1C] = 2000000, 1737 [0x1D] = 2048000, 1738 [0x1E] = 2400000, 1739 [0x20] = 3000000, 1740 [0x21] = 3072000, 1741 [0x23] = 4000000, 1742 [0x24] = 4096000, 1743 [0x25] = 4800000, 1744 [0x27] = 6000000, 1745 [0x28] = 6144000, 1746 [0x29] = 6250000, 1747 [0x2A] = 6400000, 1748 [0x2E] = 8000000, 1749 [0x2F] = 8192000, 1750 [0x30] = 9600000, 1751 [0x32] = 12000000, 1752 [0x33] = 12288000, 1753 [0x37] = 13500000, 1754 [0x38] = 19200000, 1755 [0x39] = 22579200, 1756 [0x3B] = 24576000, 1757 }; 1758 1759 int cs35l56_get_bclk_freq_id(unsigned int freq) 1760 { 1761 int i; 1762 1763 if (freq == 0) 1764 return -EINVAL; 1765 1766 /* The BCLK frequency must be a valid PLL REFCLK */ 1767 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1768 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1769 return i; 1770 } 1771 1772 return -EINVAL; 1773 } 1774 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1775 1776 static const char * const cs35l56_supplies[/* auto-sized */] = { 1777 "VDD_P", 1778 "VDD_IO", 1779 "VDD_A", 1780 }; 1781 1782 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1783 { 1784 int i; 1785 1786 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1787 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1788 data[i].supply = cs35l56_supplies[i]; 1789 } 1790 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1791 1792 const char * const cs35l56_tx_input_texts[] = { 1793 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1794 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1795 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1796 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1797 }; 1798 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1799 1800 const unsigned int cs35l56_tx_input_values[] = { 1801 CS35L56_INPUT_SRC_NONE, 1802 CS35L56_INPUT_SRC_ASP1RX1, 1803 CS35L56_INPUT_SRC_ASP1RX2, 1804 CS35L56_INPUT_SRC_VMON, 1805 CS35L56_INPUT_SRC_IMON, 1806 CS35L56_INPUT_SRC_ERR_VOL, 1807 CS35L56_INPUT_SRC_CLASSH, 1808 CS35L56_INPUT_SRC_VDDBMON, 1809 CS35L56_INPUT_SRC_VBSTMON, 1810 CS35L56_INPUT_SRC_DSP1TX1, 1811 CS35L56_INPUT_SRC_DSP1TX2, 1812 CS35L56_INPUT_SRC_DSP1TX3, 1813 CS35L56_INPUT_SRC_DSP1TX4, 1814 CS35L56_INPUT_SRC_DSP1TX5, 1815 CS35L56_INPUT_SRC_DSP1TX6, 1816 CS35L56_INPUT_SRC_DSP1TX7, 1817 CS35L56_INPUT_SRC_DSP1TX8, 1818 CS35L56_INPUT_SRC_TEMPMON, 1819 CS35L56_INPUT_SRC_INTERPOLATOR, 1820 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1821 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1822 }; 1823 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1824 1825 const struct regmap_config cs35l56_regmap_i2c = { 1826 .reg_bits = 32, 1827 .val_bits = 32, 1828 .reg_stride = 4, 1829 .reg_format_endian = REGMAP_ENDIAN_BIG, 1830 .val_format_endian = REGMAP_ENDIAN_BIG, 1831 .max_register = CS35L56_DSP1_PMEM_5114, 1832 .reg_defaults = cs35l56_reg_defaults, 1833 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1834 .volatile_reg = cs35l56_volatile_reg, 1835 .readable_reg = cs35l56_readable_reg, 1836 .precious_reg = cs35l56_precious_reg, 1837 .cache_type = REGCACHE_MAPLE, 1838 }; 1839 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1840 1841 const struct regmap_config cs35l56_regmap_spi = { 1842 .reg_bits = 32, 1843 .val_bits = 32, 1844 .pad_bits = 16, 1845 .reg_stride = 4, 1846 .reg_format_endian = REGMAP_ENDIAN_BIG, 1847 .val_format_endian = REGMAP_ENDIAN_BIG, 1848 .max_register = CS35L56_DSP1_PMEM_5114, 1849 .reg_defaults = cs35l56_reg_defaults, 1850 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1851 .volatile_reg = cs35l56_volatile_reg, 1852 .readable_reg = cs35l56_readable_reg, 1853 .precious_reg = cs35l56_precious_reg, 1854 .cache_type = REGCACHE_MAPLE, 1855 }; 1856 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1857 1858 const struct regmap_config cs35l56_regmap_sdw = { 1859 .reg_bits = 32, 1860 .val_bits = 32, 1861 .reg_stride = 4, 1862 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1863 .val_format_endian = REGMAP_ENDIAN_BIG, 1864 .max_register = CS35L56_DSP1_PMEM_5114, 1865 .reg_defaults = cs35l56_reg_defaults, 1866 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1867 .volatile_reg = cs35l56_volatile_reg, 1868 .readable_reg = cs35l56_readable_reg, 1869 .precious_reg = cs35l56_precious_reg, 1870 .cache_type = REGCACHE_MAPLE, 1871 }; 1872 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1873 1874 const struct regmap_config cs35l63_regmap_i2c = { 1875 .reg_bits = 32, 1876 .val_bits = 32, 1877 .reg_stride = 4, 1878 .reg_base = 0x8000, 1879 .reg_format_endian = REGMAP_ENDIAN_BIG, 1880 .val_format_endian = REGMAP_ENDIAN_BIG, 1881 .max_register = CS35L56_DSP1_PMEM_5114, 1882 .reg_defaults = cs35l63_reg_defaults, 1883 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1884 .volatile_reg = cs35l63_volatile_reg, 1885 .readable_reg = cs35l56_readable_reg, 1886 .precious_reg = cs35l56_precious_reg, 1887 .cache_type = REGCACHE_MAPLE, 1888 }; 1889 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1890 1891 const struct regmap_config cs35l63_regmap_sdw = { 1892 .reg_bits = 32, 1893 .val_bits = 32, 1894 .reg_stride = 4, 1895 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1896 .val_format_endian = REGMAP_ENDIAN_BIG, 1897 .max_register = CS35L56_DSP1_PMEM_5114, 1898 .reg_defaults = cs35l63_reg_defaults, 1899 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1900 .volatile_reg = cs35l63_volatile_reg, 1901 .readable_reg = cs35l56_readable_reg, 1902 .precious_reg = cs35l56_precious_reg, 1903 .cache_type = REGCACHE_MAPLE, 1904 }; 1905 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1906 1907 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1908 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1909 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1910 MODULE_LICENSE("GPL"); 1911 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1912 MODULE_IMPORT_NS("FW_CS_DSP"); 1913