1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/cleanup.h> 10 #include <linux/debugfs.h> 11 #include <linux/firmware/cirrus/wmfw.h> 12 #include <linux/fs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/kstrtox.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/spi/spi.h> 18 #include <linux/stddef.h> 19 #include <linux/string.h> 20 #include <linux/string_choices.h> 21 #include <linux/types.h> 22 #include <sound/cs-amp-lib.h> 23 24 #include "cs35l56.h" 25 26 static const struct reg_sequence cs35l56_patch[] = { 27 /* 28 * Firmware can change these to non-defaults to satisfy SDCA. 29 * Ensure that they are at known defaults. 30 */ 31 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 32 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 33 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 34 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 35 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 36 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 37 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 38 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 39 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 40 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 41 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 42 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 43 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 44 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 45 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 46 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 47 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 48 }; 49 50 static const struct reg_sequence cs35l56_patch_fw[] = { 51 /* These are not reset by a soft-reset, so patch to defaults. */ 52 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 53 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 54 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 55 }; 56 57 static const struct reg_sequence cs35l63_patch_fw[] = { 58 /* These are not reset by a soft-reset, so patch to defaults. */ 59 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 60 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 61 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 62 }; 63 64 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 65 { 66 int ret; 67 68 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 69 ARRAY_SIZE(cs35l56_patch)); 70 if (ret) 71 return ret; 72 73 74 switch (cs35l56_base->type) { 75 case 0x54: 76 case 0x56: 77 case 0x57: 78 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 79 ARRAY_SIZE(cs35l56_patch_fw)); 80 break; 81 case 0x63: 82 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 83 ARRAY_SIZE(cs35l63_patch_fw)); 84 break; 85 default: 86 break; 87 } 88 89 return ret; 90 } 91 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 92 93 static const struct reg_default cs35l56_reg_defaults[] = { 94 /* no defaults for OTP_MEM - first read populates cache */ 95 96 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 97 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 98 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 99 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 100 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 101 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 102 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 103 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 104 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 105 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 106 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 107 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 108 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 109 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 110 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 111 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 112 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 113 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 114 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 115 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 116 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 117 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 118 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 119 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 120 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 121 }; 122 123 static const struct reg_default cs35l63_reg_defaults[] = { 124 /* no defaults for OTP_MEM - first read populates cache */ 125 126 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 127 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 128 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 129 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 130 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 131 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 132 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 133 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 134 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 135 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 136 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 137 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 138 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 139 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 140 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 141 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 142 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 143 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 144 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 145 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 146 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 147 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 148 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 149 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 150 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 151 }; 152 153 static bool cs35l56_is_dsp_memory(unsigned int reg) 154 { 155 switch (reg) { 156 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 157 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 158 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 159 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 160 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 161 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 162 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 163 return true; 164 default: 165 return false; 166 } 167 } 168 169 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 170 { 171 switch (reg) { 172 case CS35L56_DEVID: 173 case CS35L56_REVID: 174 case CS35L56_RELID: 175 case CS35L56_OTPID: 176 case CS35L56_SFT_RESET: 177 case CS35L56_GLOBAL_ENABLES: 178 case CS35L56_BLOCK_ENABLES: 179 case CS35L56_BLOCK_ENABLES2: 180 case CS35L56_REFCLK_INPUT: 181 case CS35L56_GLOBAL_SAMPLE_RATE: 182 case CS35L56_OTP_MEM_53: 183 case CS35L56_OTP_MEM_54: 184 case CS35L56_OTP_MEM_55: 185 case CS35L56_ASP1_ENABLES1: 186 case CS35L56_ASP1_CONTROL1: 187 case CS35L56_ASP1_CONTROL2: 188 case CS35L56_ASP1_CONTROL3: 189 case CS35L56_ASP1_FRAME_CONTROL1: 190 case CS35L56_ASP1_FRAME_CONTROL5: 191 case CS35L56_ASP1_DATA_CONTROL1: 192 case CS35L56_ASP1_DATA_CONTROL5: 193 case CS35L56_DACPCM1_INPUT: 194 case CS35L56_DACPCM2_INPUT: 195 case CS35L56_ASP1TX1_INPUT: 196 case CS35L56_ASP1TX2_INPUT: 197 case CS35L56_ASP1TX3_INPUT: 198 case CS35L56_ASP1TX4_INPUT: 199 case CS35L56_DSP1RX1_INPUT: 200 case CS35L56_DSP1RX2_INPUT: 201 case CS35L56_SWIRE_DP3_CH1_INPUT: 202 case CS35L56_SWIRE_DP3_CH2_INPUT: 203 case CS35L56_SWIRE_DP3_CH3_INPUT: 204 case CS35L56_SWIRE_DP3_CH4_INPUT: 205 case CS35L56_IRQ1_CFG: 206 case CS35L56_IRQ1_STATUS: 207 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 208 case CS35L56_IRQ1_EINT_18: 209 case CS35L56_IRQ1_EINT_20: 210 case CS35L56_IRQ1_MASK_1: 211 case CS35L56_IRQ1_MASK_2: 212 case CS35L56_IRQ1_MASK_4: 213 case CS35L56_IRQ1_MASK_8: 214 case CS35L56_IRQ1_MASK_18: 215 case CS35L56_IRQ1_MASK_20: 216 case CS35L56_MIXER_NGATE_CH1_CFG: 217 case CS35L56_MIXER_NGATE_CH2_CFG: 218 case CS35L56_DSP_VIRTUAL1_MBOX_1: 219 case CS35L56_DSP_VIRTUAL1_MBOX_2: 220 case CS35L56_DSP_VIRTUAL1_MBOX_3: 221 case CS35L56_DSP_VIRTUAL1_MBOX_4: 222 case CS35L56_DSP_VIRTUAL1_MBOX_5: 223 case CS35L56_DSP_VIRTUAL1_MBOX_6: 224 case CS35L56_DSP_VIRTUAL1_MBOX_7: 225 case CS35L56_DSP_VIRTUAL1_MBOX_8: 226 case CS35L56_DIE_STS1: 227 case CS35L56_DIE_STS2: 228 case CS35L56_DSP_RESTRICT_STS1: 229 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 230 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 231 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 232 case CS35L56_DSP1_SCRATCH1: 233 case CS35L56_DSP1_SCRATCH2: 234 case CS35L56_DSP1_SCRATCH3: 235 case CS35L56_DSP1_SCRATCH4: 236 return true; 237 default: 238 return cs35l56_is_dsp_memory(reg); 239 } 240 } 241 242 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 243 { 244 switch (reg) { 245 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 246 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 247 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 248 return true; 249 default: 250 return false; 251 } 252 } 253 254 static bool cs35l56_common_volatile_reg(unsigned int reg) 255 { 256 switch (reg) { 257 case CS35L56_DEVID: 258 case CS35L56_REVID: 259 case CS35L56_RELID: 260 case CS35L56_OTPID: 261 case CS35L56_SFT_RESET: 262 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 263 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 264 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 265 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 266 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 267 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 268 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 269 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 270 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 271 case CS35L56_IRQ1_STATUS: 272 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 273 case CS35L56_IRQ1_EINT_18: 274 case CS35L56_IRQ1_EINT_20: 275 case CS35L56_MIXER_NGATE_CH1_CFG: 276 case CS35L56_MIXER_NGATE_CH2_CFG: 277 case CS35L56_DSP_VIRTUAL1_MBOX_1: 278 case CS35L56_DSP_VIRTUAL1_MBOX_2: 279 case CS35L56_DSP_VIRTUAL1_MBOX_3: 280 case CS35L56_DSP_VIRTUAL1_MBOX_4: 281 case CS35L56_DSP_VIRTUAL1_MBOX_5: 282 case CS35L56_DSP_VIRTUAL1_MBOX_6: 283 case CS35L56_DSP_VIRTUAL1_MBOX_7: 284 case CS35L56_DSP_VIRTUAL1_MBOX_8: 285 case CS35L56_DSP_RESTRICT_STS1: 286 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 287 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 288 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 289 case CS35L56_DSP1_SCRATCH1: 290 case CS35L56_DSP1_SCRATCH2: 291 case CS35L56_DSP1_SCRATCH3: 292 case CS35L56_DSP1_SCRATCH4: 293 return true; 294 default: 295 return cs35l56_is_dsp_memory(reg); 296 } 297 } 298 299 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 300 { 301 switch (reg) { 302 case CS35L56_MAIN_RENDER_USER_MUTE: 303 case CS35L56_MAIN_RENDER_USER_VOLUME: 304 case CS35L56_MAIN_POSTURE_NUMBER: 305 return false; 306 default: 307 return cs35l56_common_volatile_reg(reg); 308 } 309 } 310 311 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 312 { 313 switch (reg) { 314 case CS35L63_MAIN_RENDER_USER_MUTE: 315 case CS35L63_MAIN_RENDER_USER_VOLUME: 316 case CS35L63_MAIN_POSTURE_NUMBER: 317 return false; 318 default: 319 return cs35l56_common_volatile_reg(reg); 320 } 321 } 322 323 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 324 .fw_ver = CS35L56_DSP1_FW_VER, 325 .halo_state = CS35L56_DSP1_HALO_STATE, 326 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 327 .prot_sts = CS35L56_PROTECTION_STATUS, 328 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 329 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 330 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 331 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 332 }; 333 334 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 335 .fw_ver = CS35L56_DSP1_FW_VER, 336 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 337 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 338 .prot_sts = CS35L56_PROTECTION_STATUS, 339 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 340 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 341 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 342 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 343 }; 344 345 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 346 .fw_ver = CS35L63_DSP1_FW_VER, 347 .halo_state = CS35L63_DSP1_HALO_STATE, 348 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 349 .prot_sts = CS35L63_PROTECTION_STATUS, 350 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 351 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 352 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 353 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 354 }; 355 356 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 357 { 358 switch (cs35l56_base->type) { 359 default: 360 switch (cs35l56_base->rev) { 361 case 0xb0: 362 cs35l56_base->fw_reg = &cs35l56_fw_reg; 363 break; 364 default: 365 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 366 break; 367 } 368 break; 369 case 0x63: 370 cs35l56_base->fw_reg = &cs35l63_fw_reg; 371 break; 372 } 373 } 374 375 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 376 { 377 unsigned int val; 378 int ret; 379 380 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 381 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 382 val, (val == 0), 383 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 384 if (ret) { 385 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 386 return ret; 387 } 388 389 return 0; 390 } 391 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 392 393 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 394 { 395 int ret; 396 unsigned int val; 397 398 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 399 if (ret) 400 return ret; 401 402 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 403 cs35l56_base->fw_reg->pm_cur_stat, 404 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 405 CS35L56_HALO_STATE_POLL_US, 406 CS35L56_HALO_STATE_TIMEOUT_US); 407 if (ret < 0) 408 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 409 val, ret); 410 return ret; 411 } 412 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 413 414 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 415 { 416 unsigned int val = 0; 417 int read_ret, poll_ret; 418 419 /* 420 * The regmap must remain in cache-only until the chip has 421 * booted, so use a bypassed read of the status register. 422 */ 423 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 424 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 425 CS35L56_HALO_STATE_POLL_US, 426 CS35L56_HALO_STATE_TIMEOUT_US, 427 false, 428 cs35l56_base->regmap, 429 cs35l56_base->fw_reg->halo_state, 430 &val); 431 432 if (poll_ret) { 433 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 434 read_ret, val); 435 return -EIO; 436 } 437 438 return 0; 439 } 440 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 441 442 void cs35l56_wait_control_port_ready(void) 443 { 444 /* Wait for control port to be ready (datasheet tIRS). */ 445 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 446 } 447 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 448 449 void cs35l56_wait_min_reset_pulse(void) 450 { 451 /* Satisfy minimum reset pulse width spec */ 452 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 453 } 454 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 455 456 static const struct { 457 u32 addr; 458 u32 value; 459 } cs35l56_spi_system_reset_stages[] = { 460 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 461 /* The next write is necessary to delimit the soft reset */ 462 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 463 }; 464 465 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 466 struct spi_device *spi) 467 { 468 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 469 struct spi_transfer t = { 470 .tx_buf = buf, 471 .len = sizeof(*buf), 472 }; 473 struct spi_message m; 474 int i, ret; 475 476 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 477 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 478 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 479 spi_message_init_with_transfers(&m, &t, 1); 480 ret = spi_sync_locked(spi, &m); 481 if (ret) 482 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 483 484 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 485 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 486 } 487 } 488 489 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 490 { 491 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 492 unsigned int val; 493 int read_ret, ret; 494 495 /* 496 * There must not be any other SPI bus activity while the amp is 497 * soft-resetting. 498 */ 499 ret = spi_bus_lock(spi->controller); 500 if (ret) { 501 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 502 return; 503 } 504 505 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 506 spi_bus_unlock(spi->controller); 507 508 /* 509 * Check firmware boot by testing for a response in MBOX_2. 510 * HALO_STATE cannot be trusted yet because the reset sequence 511 * can leave it with stale state. But MBOX is reset. 512 * The regmap must remain in cache-only until the chip has 513 * booted, so use a bypassed read. 514 */ 515 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 516 (val > 0) && (val < 0xffffffff), 517 CS35L56_HALO_STATE_POLL_US, 518 CS35L56_HALO_STATE_TIMEOUT_US, 519 false, 520 cs35l56_base->regmap, 521 CS35L56_DSP_VIRTUAL1_MBOX_2, 522 &val); 523 if (ret) { 524 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 525 read_ret, val); 526 } 527 } 528 529 static const struct reg_sequence cs35l56_system_reset_seq[] = { 530 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 531 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 532 }; 533 534 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 535 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 536 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 537 }; 538 539 static const struct reg_sequence cs35l63_system_reset_seq[] = { 540 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 541 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 542 }; 543 544 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 545 { 546 /* 547 * Must enter cache-only first so there can't be any more register 548 * accesses other than the controlled system reset sequence below. 549 */ 550 regcache_cache_only(cs35l56_base->regmap, true); 551 552 if (cs35l56_is_spi(cs35l56_base)) { 553 cs35l56_spi_system_reset(cs35l56_base); 554 return; 555 } 556 557 switch (cs35l56_base->type) { 558 case 0x54: 559 case 0x56: 560 case 0x57: 561 switch (cs35l56_base->rev) { 562 case 0xb0: 563 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 564 cs35l56_system_reset_seq, 565 ARRAY_SIZE(cs35l56_system_reset_seq)); 566 break; 567 default: 568 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 569 cs35l56_b2_system_reset_seq, 570 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 571 break; 572 } 573 break; 574 case 0x63: 575 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 576 cs35l63_system_reset_seq, 577 ARRAY_SIZE(cs35l63_system_reset_seq)); 578 break; 579 default: 580 break; 581 } 582 583 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 584 if (is_soundwire) 585 return; 586 587 cs35l56_wait_control_port_ready(); 588 589 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 590 } 591 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 592 593 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 594 { 595 int ret; 596 597 if (irq < 1) 598 return 0; 599 600 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 601 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 602 "cs35l56", cs35l56_base); 603 if (!ret) 604 cs35l56_base->irq = irq; 605 else 606 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 607 608 return ret; 609 } 610 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 611 612 irqreturn_t cs35l56_irq(int irq, void *data) 613 { 614 struct cs35l56_base *cs35l56_base = data; 615 unsigned int status1 = 0, status8 = 0, status20 = 0; 616 unsigned int mask1, mask8, mask20; 617 unsigned int val; 618 int rv; 619 620 irqreturn_t ret = IRQ_NONE; 621 622 if (!cs35l56_base->init_done) 623 return IRQ_NONE; 624 625 mutex_lock(&cs35l56_base->irq_lock); 626 627 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 628 if (rv < 0) { 629 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 630 goto err_unlock; 631 } 632 633 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 634 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 635 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 636 goto err; 637 } 638 639 /* Ack interrupts */ 640 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 641 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 642 status1 &= ~mask1; 643 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 644 645 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 646 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 647 status8 &= ~mask8; 648 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 649 650 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 651 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 652 status20 &= ~mask20; 653 /* We don't want EINT20 but they default to unmasked: force mask */ 654 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 655 656 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 657 658 /* Check to see if unmasked bits are active */ 659 if (!status1 && !status8 && !status20) 660 goto err; 661 662 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 663 dev_crit(cs35l56_base->dev, "Amp short error\n"); 664 665 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 666 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 667 668 ret = IRQ_HANDLED; 669 670 err: 671 pm_runtime_put(cs35l56_base->dev); 672 err_unlock: 673 mutex_unlock(&cs35l56_base->irq_lock); 674 675 return ret; 676 } 677 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 678 679 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 680 { 681 unsigned int val; 682 int ret; 683 684 /* 685 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 686 * can't be used here to test for memory retention. 687 * Assume that tuning must be re-loaded. 688 */ 689 if (cs35l56_base->secured) 690 return true; 691 692 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 693 if (ret) { 694 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 695 return ret; 696 } 697 698 ret = regmap_read(cs35l56_base->regmap, 699 cs35l56_base->fw_reg->prot_sts, 700 &val); 701 if (ret) 702 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 703 else 704 ret = !!(val & CS35L56_FIRMWARE_MISSING); 705 706 pm_runtime_put_autosuspend(cs35l56_base->dev); 707 708 return ret; 709 } 710 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 711 712 static const struct reg_sequence cs35l56_hibernate_seq[] = { 713 /* This must be the last register access */ 714 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 715 }; 716 717 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 718 { 719 unsigned int val; 720 721 /* 722 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 723 * transactions to meet the minimum required time from the rising edge 724 * to the last falling edge of wake. 725 * 726 * It uses bypassed read because we must wake the chip before 727 * disabling regmap cache-only. 728 */ 729 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 730 731 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 732 733 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 734 735 cs35l56_wait_control_port_ready(); 736 } 737 738 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 739 { 740 unsigned int val; 741 int ret; 742 743 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 744 cs35l56_base->fw_reg->transducer_actual_ps, 745 val, (val >= CS35L56_PS3), 746 CS35L56_PS3_POLL_US, 747 CS35L56_PS3_TIMEOUT_US); 748 if (ret) 749 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 750 751 return ret; 752 } 753 754 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 755 { 756 if (!cs35l56_base->init_done) 757 return 0; 758 759 /* Firmware must have entered a power-save state */ 760 cs35l56_wait_for_ps3(cs35l56_base); 761 762 /* Clear BOOT_DONE so it can be used to detect a reboot */ 763 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 764 765 if (!cs35l56_base->can_hibernate) { 766 regcache_cache_only(cs35l56_base->regmap, true); 767 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 768 769 return 0; 770 } 771 772 /* 773 * Must enter cache-only first so there can't be any more register 774 * accesses other than the controlled hibernate sequence below. 775 */ 776 regcache_cache_only(cs35l56_base->regmap, true); 777 778 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 779 cs35l56_hibernate_seq, 780 ARRAY_SIZE(cs35l56_hibernate_seq)); 781 782 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 783 784 return 0; 785 } 786 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 787 788 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 789 { 790 unsigned int val; 791 int ret; 792 793 if (!cs35l56_base->init_done) 794 return 0; 795 796 if (!cs35l56_base->can_hibernate) 797 goto out_sync; 798 799 /* Must be done before releasing cache-only */ 800 if (!is_soundwire) 801 cs35l56_issue_wake_event(cs35l56_base); 802 803 out_sync: 804 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 805 if (ret) { 806 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 807 goto err; 808 } 809 810 regcache_cache_only(cs35l56_base->regmap, false); 811 812 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 813 if (ret) 814 goto err; 815 816 /* BOOT_DONE will be 1 if the amp reset */ 817 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 818 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 819 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 820 regcache_mark_dirty(cs35l56_base->regmap); 821 } 822 823 regcache_sync(cs35l56_base->regmap); 824 825 dev_dbg(cs35l56_base->dev, "Resumed"); 826 827 return 0; 828 829 err: 830 regcache_cache_only(cs35l56_base->regmap, true); 831 832 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 833 cs35l56_hibernate_seq, 834 ARRAY_SIZE(cs35l56_hibernate_seq)); 835 836 return ret; 837 } 838 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 839 840 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 841 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 842 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 843 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 844 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 845 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 846 }; 847 848 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 849 { 850 cs_dsp->num = 1; 851 cs_dsp->type = WMFW_HALO; 852 cs_dsp->rev = 0; 853 cs_dsp->dev = cs35l56_base->dev; 854 cs_dsp->regmap = cs35l56_base->regmap; 855 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 856 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 857 cs_dsp->mem = cs35l56_dsp1_regions; 858 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 859 cs_dsp->no_core_startstop = true; 860 861 cs35l56_base->dsp = cs_dsp; 862 } 863 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 864 865 struct cs35l56_pte { 866 u8 x; 867 u8 wafer_id; 868 u8 pte[2]; 869 u8 lot[3]; 870 u8 y; 871 u8 unused[3]; 872 u8 dvs; 873 } __packed; 874 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 875 876 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 877 { 878 struct cs35l56_pte pte; 879 u64 unique_id; 880 int ret; 881 882 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 883 if (ret) { 884 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 885 return ret; 886 } 887 888 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 889 unique_id <<= 32; 890 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 891 ((u32)pte.dvs << 24); 892 893 cs35l56_base->silicon_uid = unique_id; 894 895 return 0; 896 } 897 898 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 899 { 900 u32 tmp[2]; 901 u64 unique_id; 902 int ret; 903 904 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 905 if (ret) { 906 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 907 return ret; 908 } 909 910 unique_id = tmp[1]; 911 unique_id <<= 32; 912 unique_id |= tmp[0]; 913 914 cs35l56_base->silicon_uid = unique_id; 915 916 return 0; 917 } 918 919 /* Firmware calibration controls */ 920 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 921 .alg_id = 0x9f210, 922 .mem_region = WMFW_ADSP2_YM, 923 .ambient = "CAL_AMBIENT", 924 .calr = "CAL_R", 925 .status = "CAL_STATUS", 926 .checksum = "CAL_CHECKSUM", 927 }; 928 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 929 930 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 931 .alg_id = 0xbf210, 932 .mem_region = WMFW_ADSP2_YM, 933 .ambient = "CAL_AMBIENT", 934 .calr = "CAL_R", 935 .status = "CAL_STATUS", 936 .checksum = "CAL_CHECKSUM", 937 }; 938 939 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 940 { 941 int ret; 942 943 /* Driver can't apply calibration to a secured part, so skip */ 944 if (cs35l56_base->secured) 945 return 0; 946 947 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 948 cs35l56_base->silicon_uid, 949 cs35l56_base->cal_index, 950 &cs35l56_base->cal_data); 951 952 /* Only return an error status if probe should be aborted */ 953 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 954 return 0; 955 956 if (ret < 0) 957 return ret; 958 959 cs35l56_base->cal_data_valid = true; 960 961 return 0; 962 } 963 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 964 965 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 966 const struct cirrus_amp_cal_data *data) 967 { 968 969 /* Ignore if it is empty */ 970 if (!data->calTime[0] && !data->calTime[1]) 971 return -ENODATA; 972 973 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 974 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 975 return -EINVAL; 976 } 977 978 cs35l56_base->cal_data = *data; 979 cs35l56_base->cal_data_valid = true; 980 981 return 0; 982 } 983 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 984 985 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 986 { 987 const struct cirrus_amp_cal_controls *calibration_controls = 988 cs35l56_base->calibration_controls; 989 struct cs_dsp *dsp = cs35l56_base->dsp; 990 struct cirrus_amp_cal_data cal_data; 991 struct cs_dsp_coeff_ctl *ctl; 992 bool ngate_ch1_was_enabled = false; 993 bool ngate_ch2_was_enabled = false; 994 int cali_norm_en_alg_id, cali_norm_en_mem; 995 int ret; 996 __be32 val; 997 998 if (cs35l56_base->silicon_uid == 0) { 999 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1000 return -ENXIO; 1001 } 1002 1003 switch (cs35l56_base->type) { 1004 case 0x54: 1005 case 0x56: 1006 case 0x57: 1007 if (cs35l56_base->rev < 0xb2) { 1008 cali_norm_en_alg_id = 0x9f22f; 1009 cali_norm_en_mem = WMFW_ADSP2_YM; 1010 } else { 1011 cali_norm_en_alg_id = 0x9f210; 1012 cali_norm_en_mem = WMFW_ADSP2_XM; 1013 } 1014 break; 1015 default: 1016 cali_norm_en_alg_id = 0xbf210; 1017 cali_norm_en_mem = WMFW_ADSP2_XM; 1018 break; 1019 } 1020 1021 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1022 if (ret) 1023 return ret; 1024 1025 ret = cs35l56_wait_for_ps3(cs35l56_base); 1026 if (ret) { 1027 ret = -EBUSY; 1028 goto err_pm_put; 1029 } 1030 1031 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1032 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1033 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1034 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1035 1036 scoped_guard(mutex, &dsp->pwr_lock) { 1037 ctl = cs_dsp_get_ctl(dsp, 1038 calibration_controls->status, 1039 calibration_controls->mem_region, 1040 calibration_controls->alg_id); 1041 if (!ctl) { 1042 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1043 calibration_controls->status); 1044 ret = -EIO; 1045 goto err; 1046 } 1047 1048 val = cpu_to_be32(0); 1049 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1050 "CALI_NORM_EN", 1051 cali_norm_en_mem, 1052 cali_norm_en_alg_id), 1053 0, &val, sizeof(val)); 1054 if (ret < 0) { 1055 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1056 ret = -EIO; 1057 goto err; 1058 } 1059 1060 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1061 if (ret) { 1062 ret = -EIO; 1063 goto err; 1064 } 1065 1066 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1067 (val == cpu_to_be32(1)), 1068 CS35L56_CALIBRATION_POLL_US, 1069 CS35L56_CALIBRATION_TIMEOUT_US, 1070 true, 1071 ctl, 0, &val, sizeof(val))) { 1072 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1073 be32_to_cpu(val)); 1074 switch (be32_to_cpu(val)) { 1075 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1076 ret = -ERANGE; 1077 goto err; 1078 default: 1079 ret = -ETIMEDOUT; 1080 goto err; 1081 } 1082 } 1083 } 1084 1085 cs35l56_base->cal_data_valid = false; 1086 memset(&cal_data, 0, sizeof(cal_data)); 1087 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1088 if (ret) { 1089 ret = -EIO; 1090 goto err; 1091 } 1092 1093 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1094 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1095 1096 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1097 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1098 cs35l56_base->cal_data = cal_data; 1099 cs35l56_base->cal_data_valid = true; 1100 1101 ret = 0; 1102 1103 err: 1104 if (ngate_ch1_was_enabled) { 1105 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1106 CS35L56_AUX_NGATE_CHn_EN); 1107 } 1108 if (ngate_ch2_was_enabled) { 1109 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1110 CS35L56_AUX_NGATE_CHn_EN); 1111 } 1112 err_pm_put: 1113 pm_runtime_put(cs35l56_base->dev); 1114 1115 return ret; 1116 } 1117 1118 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1119 const char __user *from, size_t count, 1120 loff_t *ppos) 1121 { 1122 static const char * const options[] = { "factory", "store_uefi" }; 1123 char buf[11] = { 0 }; 1124 int num_amps, ret; 1125 1126 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1127 return -ENXIO; 1128 1129 if (*ppos) 1130 return -EINVAL; 1131 1132 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1133 if (ret < 0) 1134 return ret; 1135 1136 switch (sysfs_match_string(options, buf)) { 1137 case 0: 1138 ret = cs35l56_perform_calibration(cs35l56_base); 1139 if (ret < 0) 1140 return ret; 1141 break; 1142 case 1: 1143 if (!cs35l56_base->cal_data_valid) 1144 return -ENODATA; 1145 1146 num_amps = cs35l56_base->num_amps; 1147 if (num_amps == 0) 1148 num_amps = -1; 1149 1150 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1151 cs35l56_base->cal_index, 1152 num_amps, 1153 &cs35l56_base->cal_data); 1154 if (ret < 0) 1155 return ret; 1156 break; 1157 default: 1158 return -EOPNOTSUPP; 1159 } 1160 1161 return count; 1162 } 1163 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1164 1165 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1166 const char __user *from, size_t count, 1167 loff_t *ppos) 1168 { 1169 unsigned long val; 1170 int ret; 1171 1172 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1173 return -ENXIO; 1174 1175 if (*ppos) 1176 return -EINVAL; 1177 1178 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1179 if (ret) 1180 return ret; 1181 1182 ret = kstrtoul_from_user(from, count, 10, &val); 1183 if (ret < 0) 1184 goto out; 1185 1186 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1187 if (ret) 1188 ret = -EIO; 1189 out: 1190 pm_runtime_put(cs35l56_base->dev); 1191 1192 if (ret < 0) 1193 return ret; 1194 1195 return count; 1196 } 1197 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1198 1199 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1200 char __user *to, size_t count, 1201 loff_t *ppos) 1202 { 1203 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1204 return -ENXIO; 1205 1206 if (!cs35l56_base->cal_data_valid) 1207 return 0; 1208 1209 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1210 sizeof(cs35l56_base->cal_data)); 1211 } 1212 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1213 1214 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1215 const char __user *from, size_t count, 1216 loff_t *ppos) 1217 { 1218 struct cirrus_amp_cal_data cal_data; 1219 int ret; 1220 1221 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1222 return -ENXIO; 1223 1224 /* Only allow a full blob to be written */ 1225 if (*ppos || (count != sizeof(cal_data))) 1226 return -EMSGSIZE; 1227 1228 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1229 if (ret) 1230 return ret; 1231 1232 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1233 if (ret) 1234 return ret; 1235 1236 return count; 1237 } 1238 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1239 1240 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1241 const struct cs35l56_cal_debugfs_fops *fops) 1242 { 1243 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1244 return; 1245 1246 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1247 1248 debugfs_create_file("calibrate", 1249 0200, cs35l56_base->debugfs, cs35l56_base, 1250 &fops->calibrate); 1251 debugfs_create_file("cal_temperature", 1252 0200, cs35l56_base->debugfs, cs35l56_base, 1253 &fops->cal_temperature); 1254 debugfs_create_file("cal_data", 1255 0644, cs35l56_base->debugfs, cs35l56_base, 1256 &fops->cal_data); 1257 } 1258 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1259 1260 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1261 { 1262 debugfs_remove_recursive(cs35l56_base->debugfs); 1263 } 1264 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1265 1266 const char * const cs35l56_cal_set_status_text[] = { 1267 "Unknown", "Default", "Set", 1268 }; 1269 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1270 1271 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1272 struct snd_ctl_elem_value *uvalue) 1273 { 1274 struct cs_dsp *dsp = cs35l56_base->dsp; 1275 __be32 cal_set_status_be; 1276 int alg_id; 1277 int ret; 1278 1279 switch (cs35l56_base->type) { 1280 case 0x54: 1281 case 0x56: 1282 case 0x57: 1283 alg_id = 0x9f210; 1284 break; 1285 default: 1286 alg_id = 0xbf210; 1287 break; 1288 } 1289 1290 scoped_guard(mutex, &dsp->pwr_lock) { 1291 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1292 "CAL_SET_STATUS", 1293 WMFW_ADSP2_YM, alg_id), 1294 0, &cal_set_status_be, 1295 sizeof(cal_set_status_be)); 1296 } 1297 if (ret) { 1298 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1299 return 0; 1300 } 1301 1302 switch (be32_to_cpu(cal_set_status_be)) { 1303 case CS35L56_CAL_SET_STATUS_DEFAULT: 1304 case CS35L56_CAL_SET_STATUS_SET: 1305 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1306 return 0; 1307 default: 1308 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1309 return 0; 1310 } 1311 } 1312 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1313 1314 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1315 bool *fw_missing, unsigned int *fw_version) 1316 { 1317 unsigned int prot_status; 1318 int ret; 1319 1320 ret = regmap_read(cs35l56_base->regmap, 1321 cs35l56_base->fw_reg->prot_sts, &prot_status); 1322 if (ret) { 1323 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1324 return ret; 1325 } 1326 1327 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1328 1329 ret = regmap_read(cs35l56_base->regmap, 1330 cs35l56_base->fw_reg->fw_ver, fw_version); 1331 if (ret) { 1332 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1333 return ret; 1334 } 1335 1336 return 0; 1337 } 1338 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1339 1340 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1341 { 1342 unsigned int firmware_version; 1343 bool firmware_missing; 1344 int ret; 1345 1346 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1347 if (ret) 1348 return; 1349 1350 if (!firmware_missing) 1351 return; 1352 1353 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1354 } 1355 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1356 1357 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1358 { 1359 __be32 pid, sid, tid; 1360 unsigned int alg_id; 1361 int ret; 1362 1363 switch (cs35l56_base->type) { 1364 case 0x54: 1365 case 0x56: 1366 case 0x57: 1367 alg_id = 0x9f212; 1368 break; 1369 default: 1370 alg_id = 0xbf212; 1371 break; 1372 } 1373 1374 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1375 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1376 WMFW_ADSP2_XM, alg_id), 1377 0, &pid, sizeof(pid)); 1378 if (!ret) 1379 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1380 WMFW_ADSP2_XM, alg_id), 1381 0, &sid, sizeof(sid)); 1382 if (!ret) 1383 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1384 WMFW_ADSP2_XM, alg_id), 1385 0, &tid, sizeof(tid)); 1386 } 1387 1388 if (ret) 1389 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1390 else 1391 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1392 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1393 } 1394 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1395 1396 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1397 { 1398 int ret; 1399 unsigned int devid, revid, otpid, secured, fw_ver; 1400 bool fw_missing; 1401 1402 /* 1403 * When the system is not using a reset_gpio ensure the device is 1404 * awake, otherwise the device has just been released from reset and 1405 * the driver must wait for the control port to become usable. 1406 */ 1407 if (!cs35l56_base->reset_gpio) 1408 cs35l56_issue_wake_event(cs35l56_base); 1409 else 1410 cs35l56_wait_control_port_ready(); 1411 1412 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1413 if (ret < 0) { 1414 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1415 return ret; 1416 } 1417 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1418 cs35l56_set_fw_reg_table(cs35l56_base); 1419 1420 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1421 if (ret) 1422 return ret; 1423 1424 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1425 if (ret < 0) { 1426 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1427 return ret; 1428 } 1429 devid &= CS35L56_DEVID_MASK; 1430 1431 switch (devid) { 1432 case 0x35A54: 1433 case 0x35A56: 1434 case 0x35A57: 1435 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1436 break; 1437 case 0x35A630: 1438 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1439 devid = devid >> 4; 1440 break; 1441 default: 1442 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1443 return -ENODEV; 1444 } 1445 1446 cs35l56_base->type = devid & 0xFF; 1447 1448 /* Silicon is now identified and booted so exit cache-only */ 1449 regcache_cache_only(cs35l56_base->regmap, false); 1450 1451 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1452 if (ret) { 1453 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1454 return ret; 1455 } 1456 1457 /* When any bus is restricted treat the device as secured */ 1458 if (secured & CS35L56_RESTRICTED_MASK) 1459 cs35l56_base->secured = true; 1460 1461 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1462 if (ret < 0) { 1463 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1464 return ret; 1465 } 1466 1467 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1468 if (ret) 1469 return ret; 1470 1471 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1472 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1473 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1474 1475 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1476 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1477 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1478 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1479 0); 1480 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1481 CS35L56_TEMP_ERR_EINT1_MASK, 1482 0); 1483 1484 switch (cs35l56_base->type) { 1485 case 0x54: 1486 case 0x56: 1487 case 0x57: 1488 ret = cs35l56_read_silicon_uid(cs35l56_base); 1489 break; 1490 default: 1491 ret = cs35l63_read_silicon_uid(cs35l56_base); 1492 break; 1493 } 1494 if (ret) 1495 return ret; 1496 1497 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1498 1499 return 0; 1500 } 1501 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1502 1503 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1504 { 1505 struct gpio_descs *descs; 1506 u32 speaker_id; 1507 int i, ret; 1508 1509 /* Check for vendor-specific speaker ID method */ 1510 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1511 if (ret >= 0) { 1512 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1513 return ret; 1514 } else if (ret != -ENOENT) { 1515 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1516 return ret; 1517 } 1518 1519 /* Attempt to read the speaker type from a device property */ 1520 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1521 if (!ret) { 1522 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1523 return speaker_id; 1524 } 1525 1526 /* Read the speaker type qualifier from the motherboard GPIOs */ 1527 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1528 if (!descs) { 1529 return -ENOENT; 1530 } else if (IS_ERR(descs)) { 1531 ret = PTR_ERR(descs); 1532 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1533 } 1534 1535 speaker_id = 0; 1536 for (i = 0; i < descs->ndescs; i++) { 1537 ret = gpiod_get_value_cansleep(descs->desc[i]); 1538 if (ret < 0) { 1539 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1540 goto err; 1541 } 1542 1543 speaker_id |= (ret << i); 1544 } 1545 1546 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1547 ret = speaker_id; 1548 err: 1549 gpiod_put_array(descs); 1550 1551 return ret; 1552 } 1553 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1554 1555 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1556 [0x0C] = 128000, 1557 [0x0F] = 256000, 1558 [0x11] = 384000, 1559 [0x12] = 512000, 1560 [0x15] = 768000, 1561 [0x17] = 1024000, 1562 [0x1A] = 1500000, 1563 [0x1B] = 1536000, 1564 [0x1C] = 2000000, 1565 [0x1D] = 2048000, 1566 [0x1E] = 2400000, 1567 [0x20] = 3000000, 1568 [0x21] = 3072000, 1569 [0x23] = 4000000, 1570 [0x24] = 4096000, 1571 [0x25] = 4800000, 1572 [0x27] = 6000000, 1573 [0x28] = 6144000, 1574 [0x29] = 6250000, 1575 [0x2A] = 6400000, 1576 [0x2E] = 8000000, 1577 [0x2F] = 8192000, 1578 [0x30] = 9600000, 1579 [0x32] = 12000000, 1580 [0x33] = 12288000, 1581 [0x37] = 13500000, 1582 [0x38] = 19200000, 1583 [0x39] = 22579200, 1584 [0x3B] = 24576000, 1585 }; 1586 1587 int cs35l56_get_bclk_freq_id(unsigned int freq) 1588 { 1589 int i; 1590 1591 if (freq == 0) 1592 return -EINVAL; 1593 1594 /* The BCLK frequency must be a valid PLL REFCLK */ 1595 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1596 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1597 return i; 1598 } 1599 1600 return -EINVAL; 1601 } 1602 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1603 1604 static const char * const cs35l56_supplies[/* auto-sized */] = { 1605 "VDD_P", 1606 "VDD_IO", 1607 "VDD_A", 1608 }; 1609 1610 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1611 { 1612 int i; 1613 1614 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1615 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1616 data[i].supply = cs35l56_supplies[i]; 1617 } 1618 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1619 1620 const char * const cs35l56_tx_input_texts[] = { 1621 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1622 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1623 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1624 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1625 }; 1626 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1627 1628 const unsigned int cs35l56_tx_input_values[] = { 1629 CS35L56_INPUT_SRC_NONE, 1630 CS35L56_INPUT_SRC_ASP1RX1, 1631 CS35L56_INPUT_SRC_ASP1RX2, 1632 CS35L56_INPUT_SRC_VMON, 1633 CS35L56_INPUT_SRC_IMON, 1634 CS35L56_INPUT_SRC_ERR_VOL, 1635 CS35L56_INPUT_SRC_CLASSH, 1636 CS35L56_INPUT_SRC_VDDBMON, 1637 CS35L56_INPUT_SRC_VBSTMON, 1638 CS35L56_INPUT_SRC_DSP1TX1, 1639 CS35L56_INPUT_SRC_DSP1TX2, 1640 CS35L56_INPUT_SRC_DSP1TX3, 1641 CS35L56_INPUT_SRC_DSP1TX4, 1642 CS35L56_INPUT_SRC_DSP1TX5, 1643 CS35L56_INPUT_SRC_DSP1TX6, 1644 CS35L56_INPUT_SRC_DSP1TX7, 1645 CS35L56_INPUT_SRC_DSP1TX8, 1646 CS35L56_INPUT_SRC_TEMPMON, 1647 CS35L56_INPUT_SRC_INTERPOLATOR, 1648 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1649 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1650 }; 1651 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1652 1653 const struct regmap_config cs35l56_regmap_i2c = { 1654 .reg_bits = 32, 1655 .val_bits = 32, 1656 .reg_stride = 4, 1657 .reg_format_endian = REGMAP_ENDIAN_BIG, 1658 .val_format_endian = REGMAP_ENDIAN_BIG, 1659 .max_register = CS35L56_DSP1_PMEM_5114, 1660 .reg_defaults = cs35l56_reg_defaults, 1661 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1662 .volatile_reg = cs35l56_volatile_reg, 1663 .readable_reg = cs35l56_readable_reg, 1664 .precious_reg = cs35l56_precious_reg, 1665 .cache_type = REGCACHE_MAPLE, 1666 }; 1667 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1668 1669 const struct regmap_config cs35l56_regmap_spi = { 1670 .reg_bits = 32, 1671 .val_bits = 32, 1672 .pad_bits = 16, 1673 .reg_stride = 4, 1674 .reg_format_endian = REGMAP_ENDIAN_BIG, 1675 .val_format_endian = REGMAP_ENDIAN_BIG, 1676 .max_register = CS35L56_DSP1_PMEM_5114, 1677 .reg_defaults = cs35l56_reg_defaults, 1678 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1679 .volatile_reg = cs35l56_volatile_reg, 1680 .readable_reg = cs35l56_readable_reg, 1681 .precious_reg = cs35l56_precious_reg, 1682 .cache_type = REGCACHE_MAPLE, 1683 }; 1684 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1685 1686 const struct regmap_config cs35l56_regmap_sdw = { 1687 .reg_bits = 32, 1688 .val_bits = 32, 1689 .reg_stride = 4, 1690 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1691 .val_format_endian = REGMAP_ENDIAN_BIG, 1692 .max_register = CS35L56_DSP1_PMEM_5114, 1693 .reg_defaults = cs35l56_reg_defaults, 1694 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1695 .volatile_reg = cs35l56_volatile_reg, 1696 .readable_reg = cs35l56_readable_reg, 1697 .precious_reg = cs35l56_precious_reg, 1698 .cache_type = REGCACHE_MAPLE, 1699 }; 1700 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1701 1702 const struct regmap_config cs35l63_regmap_i2c = { 1703 .reg_bits = 32, 1704 .val_bits = 32, 1705 .reg_stride = 4, 1706 .reg_base = 0x8000, 1707 .reg_format_endian = REGMAP_ENDIAN_BIG, 1708 .val_format_endian = REGMAP_ENDIAN_BIG, 1709 .max_register = CS35L56_DSP1_PMEM_5114, 1710 .reg_defaults = cs35l63_reg_defaults, 1711 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1712 .volatile_reg = cs35l63_volatile_reg, 1713 .readable_reg = cs35l56_readable_reg, 1714 .precious_reg = cs35l56_precious_reg, 1715 .cache_type = REGCACHE_MAPLE, 1716 }; 1717 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1718 1719 const struct regmap_config cs35l63_regmap_sdw = { 1720 .reg_bits = 32, 1721 .val_bits = 32, 1722 .reg_stride = 4, 1723 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1724 .val_format_endian = REGMAP_ENDIAN_BIG, 1725 .max_register = CS35L56_DSP1_PMEM_5114, 1726 .reg_defaults = cs35l63_reg_defaults, 1727 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1728 .volatile_reg = cs35l63_volatile_reg, 1729 .readable_reg = cs35l56_readable_reg, 1730 .precious_reg = cs35l56_precious_reg, 1731 .cache_type = REGCACHE_MAPLE, 1732 }; 1733 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1734 1735 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1736 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1737 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1738 MODULE_LICENSE("GPL"); 1739 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1740 MODULE_IMPORT_NS("FW_CS_DSP"); 1741