1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/firmware/cirrus/wmfw.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/types.h> 14 #include <sound/cs-amp-lib.h> 15 16 #include "cs35l56.h" 17 18 static const struct reg_sequence cs35l56_patch[] = { 19 /* 20 * Firmware can change these to non-defaults to satisfy SDCA. 21 * Ensure that they are at known defaults. 22 */ 23 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 24 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 25 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 26 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 27 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 28 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 29 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 30 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 31 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 32 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 33 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 34 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 35 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 36 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 37 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 38 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 39 40 /* These are not reset by a soft-reset, so patch to defaults. */ 41 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 42 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 43 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 44 }; 45 46 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 47 { 48 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 49 ARRAY_SIZE(cs35l56_patch)); 50 } 51 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 52 53 static const struct reg_default cs35l56_reg_defaults[] = { 54 /* no defaults for OTP_MEM - first read populates cache */ 55 56 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 57 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 58 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 59 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 60 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 61 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 62 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 63 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 64 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 65 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 66 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 67 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 68 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 69 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 70 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 71 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 72 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 73 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 74 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 75 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 76 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 77 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 78 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 79 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 80 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 81 }; 82 83 static bool cs35l56_is_dsp_memory(unsigned int reg) 84 { 85 switch (reg) { 86 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 87 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 88 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 89 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 90 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 91 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 92 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 93 return true; 94 default: 95 return false; 96 } 97 } 98 99 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 100 { 101 switch (reg) { 102 case CS35L56_DEVID: 103 case CS35L56_REVID: 104 case CS35L56_RELID: 105 case CS35L56_OTPID: 106 case CS35L56_SFT_RESET: 107 case CS35L56_GLOBAL_ENABLES: 108 case CS35L56_BLOCK_ENABLES: 109 case CS35L56_BLOCK_ENABLES2: 110 case CS35L56_REFCLK_INPUT: 111 case CS35L56_GLOBAL_SAMPLE_RATE: 112 case CS35L56_OTP_MEM_53: 113 case CS35L56_OTP_MEM_54: 114 case CS35L56_OTP_MEM_55: 115 case CS35L56_ASP1_ENABLES1: 116 case CS35L56_ASP1_CONTROL1: 117 case CS35L56_ASP1_CONTROL2: 118 case CS35L56_ASP1_CONTROL3: 119 case CS35L56_ASP1_FRAME_CONTROL1: 120 case CS35L56_ASP1_FRAME_CONTROL5: 121 case CS35L56_ASP1_DATA_CONTROL1: 122 case CS35L56_ASP1_DATA_CONTROL5: 123 case CS35L56_DACPCM1_INPUT: 124 case CS35L56_DACPCM2_INPUT: 125 case CS35L56_ASP1TX1_INPUT: 126 case CS35L56_ASP1TX2_INPUT: 127 case CS35L56_ASP1TX3_INPUT: 128 case CS35L56_ASP1TX4_INPUT: 129 case CS35L56_DSP1RX1_INPUT: 130 case CS35L56_DSP1RX2_INPUT: 131 case CS35L56_SWIRE_DP3_CH1_INPUT: 132 case CS35L56_SWIRE_DP3_CH2_INPUT: 133 case CS35L56_SWIRE_DP3_CH3_INPUT: 134 case CS35L56_SWIRE_DP3_CH4_INPUT: 135 case CS35L56_IRQ1_CFG: 136 case CS35L56_IRQ1_STATUS: 137 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 138 case CS35L56_IRQ1_EINT_18: 139 case CS35L56_IRQ1_EINT_20: 140 case CS35L56_IRQ1_MASK_1: 141 case CS35L56_IRQ1_MASK_2: 142 case CS35L56_IRQ1_MASK_4: 143 case CS35L56_IRQ1_MASK_8: 144 case CS35L56_IRQ1_MASK_18: 145 case CS35L56_IRQ1_MASK_20: 146 case CS35L56_DSP_VIRTUAL1_MBOX_1: 147 case CS35L56_DSP_VIRTUAL1_MBOX_2: 148 case CS35L56_DSP_VIRTUAL1_MBOX_3: 149 case CS35L56_DSP_VIRTUAL1_MBOX_4: 150 case CS35L56_DSP_VIRTUAL1_MBOX_5: 151 case CS35L56_DSP_VIRTUAL1_MBOX_6: 152 case CS35L56_DSP_VIRTUAL1_MBOX_7: 153 case CS35L56_DSP_VIRTUAL1_MBOX_8: 154 case CS35L56_DSP_RESTRICT_STS1: 155 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 156 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 157 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 158 case CS35L56_DSP1_SCRATCH1: 159 case CS35L56_DSP1_SCRATCH2: 160 case CS35L56_DSP1_SCRATCH3: 161 case CS35L56_DSP1_SCRATCH4: 162 return true; 163 default: 164 return cs35l56_is_dsp_memory(reg); 165 } 166 } 167 168 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 169 { 170 switch (reg) { 171 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 172 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 173 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 174 return true; 175 default: 176 return false; 177 } 178 } 179 180 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 181 { 182 switch (reg) { 183 case CS35L56_DEVID: 184 case CS35L56_REVID: 185 case CS35L56_RELID: 186 case CS35L56_OTPID: 187 case CS35L56_SFT_RESET: 188 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 189 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 190 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 191 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 192 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 193 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 194 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 195 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 196 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 197 case CS35L56_IRQ1_STATUS: 198 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 199 case CS35L56_IRQ1_EINT_18: 200 case CS35L56_IRQ1_EINT_20: 201 case CS35L56_DSP_VIRTUAL1_MBOX_1: 202 case CS35L56_DSP_VIRTUAL1_MBOX_2: 203 case CS35L56_DSP_VIRTUAL1_MBOX_3: 204 case CS35L56_DSP_VIRTUAL1_MBOX_4: 205 case CS35L56_DSP_VIRTUAL1_MBOX_5: 206 case CS35L56_DSP_VIRTUAL1_MBOX_6: 207 case CS35L56_DSP_VIRTUAL1_MBOX_7: 208 case CS35L56_DSP_VIRTUAL1_MBOX_8: 209 case CS35L56_DSP_RESTRICT_STS1: 210 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 211 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 212 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 213 case CS35L56_DSP1_SCRATCH1: 214 case CS35L56_DSP1_SCRATCH2: 215 case CS35L56_DSP1_SCRATCH3: 216 case CS35L56_DSP1_SCRATCH4: 217 return true; 218 case CS35L56_MAIN_RENDER_USER_MUTE: 219 case CS35L56_MAIN_RENDER_USER_VOLUME: 220 case CS35L56_MAIN_POSTURE_NUMBER: 221 return false; 222 default: 223 return cs35l56_is_dsp_memory(reg); 224 } 225 } 226 227 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 228 { 229 unsigned int val; 230 int ret; 231 232 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 233 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 234 val, (val == 0), 235 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 236 if (ret) { 237 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 238 return ret; 239 } 240 241 return 0; 242 } 243 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 244 245 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 246 { 247 int ret; 248 unsigned int val; 249 250 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 251 if (ret) 252 return ret; 253 254 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP1_PM_CUR_STATE, 255 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 256 CS35L56_HALO_STATE_POLL_US, 257 CS35L56_HALO_STATE_TIMEOUT_US); 258 if (ret < 0) 259 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 260 val, ret); 261 return ret; 262 } 263 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 264 265 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 266 { 267 unsigned int val = 0; 268 int read_ret, poll_ret; 269 270 /* 271 * The regmap must remain in cache-only until the chip has 272 * booted, so use a bypassed read of the status register. 273 */ 274 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 275 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 276 CS35L56_HALO_STATE_POLL_US, 277 CS35L56_HALO_STATE_TIMEOUT_US, 278 false, 279 cs35l56_base->regmap, CS35L56_DSP1_HALO_STATE, &val); 280 281 if (poll_ret) { 282 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 283 read_ret, val); 284 return -EIO; 285 } 286 287 return 0; 288 } 289 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 290 291 void cs35l56_wait_control_port_ready(void) 292 { 293 /* Wait for control port to be ready (datasheet tIRS). */ 294 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 295 } 296 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 297 298 void cs35l56_wait_min_reset_pulse(void) 299 { 300 /* Satisfy minimum reset pulse width spec */ 301 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 302 } 303 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 304 305 static const struct reg_sequence cs35l56_system_reset_seq[] = { 306 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 307 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 308 }; 309 310 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 311 { 312 /* 313 * Must enter cache-only first so there can't be any more register 314 * accesses other than the controlled system reset sequence below. 315 */ 316 regcache_cache_only(cs35l56_base->regmap, true); 317 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 318 cs35l56_system_reset_seq, 319 ARRAY_SIZE(cs35l56_system_reset_seq)); 320 321 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 322 if (is_soundwire) 323 return; 324 325 cs35l56_wait_control_port_ready(); 326 327 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 328 } 329 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 330 331 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 332 { 333 int ret; 334 335 if (irq < 1) 336 return 0; 337 338 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 339 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 340 "cs35l56", cs35l56_base); 341 if (!ret) 342 cs35l56_base->irq = irq; 343 else 344 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 345 346 return ret; 347 } 348 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 349 350 irqreturn_t cs35l56_irq(int irq, void *data) 351 { 352 struct cs35l56_base *cs35l56_base = data; 353 unsigned int status1 = 0, status8 = 0, status20 = 0; 354 unsigned int mask1, mask8, mask20; 355 unsigned int val; 356 int rv; 357 358 irqreturn_t ret = IRQ_NONE; 359 360 if (!cs35l56_base->init_done) 361 return IRQ_NONE; 362 363 mutex_lock(&cs35l56_base->irq_lock); 364 365 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 366 if (rv < 0) { 367 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 368 goto err_unlock; 369 } 370 371 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 372 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 373 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 374 goto err; 375 } 376 377 /* Ack interrupts */ 378 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 379 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 380 status1 &= ~mask1; 381 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 382 383 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 384 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 385 status8 &= ~mask8; 386 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 387 388 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 389 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 390 status20 &= ~mask20; 391 /* We don't want EINT20 but they default to unmasked: force mask */ 392 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 393 394 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 395 396 /* Check to see if unmasked bits are active */ 397 if (!status1 && !status8 && !status20) 398 goto err; 399 400 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 401 dev_crit(cs35l56_base->dev, "Amp short error\n"); 402 403 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 404 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 405 406 ret = IRQ_HANDLED; 407 408 err: 409 pm_runtime_put(cs35l56_base->dev); 410 err_unlock: 411 mutex_unlock(&cs35l56_base->irq_lock); 412 413 return ret; 414 } 415 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 416 417 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 418 { 419 unsigned int val; 420 int ret; 421 422 /* 423 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 424 * can't be used here to test for memory retention. 425 * Assume that tuning must be re-loaded. 426 */ 427 if (cs35l56_base->secured) 428 return true; 429 430 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 431 if (ret) { 432 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 433 return ret; 434 } 435 436 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 437 if (ret) 438 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 439 else 440 ret = !!(val & CS35L56_FIRMWARE_MISSING); 441 442 pm_runtime_put_autosuspend(cs35l56_base->dev); 443 444 return ret; 445 } 446 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 447 448 static const struct reg_sequence cs35l56_hibernate_seq[] = { 449 /* This must be the last register access */ 450 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 451 }; 452 453 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 454 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 455 }; 456 457 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 458 { 459 /* 460 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 461 * transactions to meet the minimum required time from the rising edge 462 * to the last falling edge of wake. 463 * 464 * It uses bypassed write because we must wake the chip before 465 * disabling regmap cache-only. 466 * 467 * This can NAK on I2C which will terminate the write sequence so the 468 * single-write sequence is issued twice. 469 */ 470 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 471 cs35l56_hibernate_wake_seq, 472 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 473 474 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 475 476 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 477 cs35l56_hibernate_wake_seq, 478 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 479 480 cs35l56_wait_control_port_ready(); 481 } 482 483 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 484 { 485 unsigned int val; 486 int ret; 487 488 if (!cs35l56_base->init_done) 489 return 0; 490 491 /* Firmware must have entered a power-save state */ 492 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 493 CS35L56_TRANSDUCER_ACTUAL_PS, 494 val, (val >= CS35L56_PS3), 495 CS35L56_PS3_POLL_US, 496 CS35L56_PS3_TIMEOUT_US); 497 if (ret) 498 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 499 500 /* Clear BOOT_DONE so it can be used to detect a reboot */ 501 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 502 503 if (!cs35l56_base->can_hibernate) { 504 regcache_cache_only(cs35l56_base->regmap, true); 505 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 506 507 return 0; 508 } 509 510 /* 511 * Must enter cache-only first so there can't be any more register 512 * accesses other than the controlled hibernate sequence below. 513 */ 514 regcache_cache_only(cs35l56_base->regmap, true); 515 516 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 517 cs35l56_hibernate_seq, 518 ARRAY_SIZE(cs35l56_hibernate_seq)); 519 520 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 521 522 return 0; 523 } 524 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 525 526 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 527 { 528 unsigned int val; 529 int ret; 530 531 if (!cs35l56_base->init_done) 532 return 0; 533 534 if (!cs35l56_base->can_hibernate) 535 goto out_sync; 536 537 /* Must be done before releasing cache-only */ 538 if (!is_soundwire) 539 cs35l56_issue_wake_event(cs35l56_base); 540 541 out_sync: 542 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 543 if (ret) { 544 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 545 goto err; 546 } 547 548 regcache_cache_only(cs35l56_base->regmap, false); 549 550 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 551 if (ret) 552 goto err; 553 554 /* BOOT_DONE will be 1 if the amp reset */ 555 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 556 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 557 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 558 regcache_mark_dirty(cs35l56_base->regmap); 559 } 560 561 regcache_sync(cs35l56_base->regmap); 562 563 dev_dbg(cs35l56_base->dev, "Resumed"); 564 565 return 0; 566 567 err: 568 regcache_cache_only(cs35l56_base->regmap, true); 569 570 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 571 cs35l56_hibernate_seq, 572 ARRAY_SIZE(cs35l56_hibernate_seq)); 573 574 return ret; 575 } 576 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 577 578 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 579 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 580 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 581 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 582 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 583 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 584 }; 585 586 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 587 { 588 cs_dsp->num = 1; 589 cs_dsp->type = WMFW_HALO; 590 cs_dsp->rev = 0; 591 cs_dsp->dev = cs35l56_base->dev; 592 cs_dsp->regmap = cs35l56_base->regmap; 593 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 594 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 595 cs_dsp->mem = cs35l56_dsp1_regions; 596 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 597 cs_dsp->no_core_startstop = true; 598 } 599 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 600 601 struct cs35l56_pte { 602 u8 x; 603 u8 wafer_id; 604 u8 pte[2]; 605 u8 lot[3]; 606 u8 y; 607 u8 unused[3]; 608 u8 dvs; 609 } __packed; 610 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 611 612 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 613 { 614 struct cs35l56_pte pte; 615 u64 unique_id; 616 int ret; 617 618 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 619 if (ret) { 620 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 621 return ret; 622 } 623 624 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 625 unique_id <<= 32; 626 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 627 ((u32)pte.dvs << 24); 628 629 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id); 630 631 *uid = unique_id; 632 633 return 0; 634 } 635 636 /* Firmware calibration controls */ 637 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 638 .alg_id = 0x9f210, 639 .mem_region = WMFW_ADSP2_YM, 640 .ambient = "CAL_AMBIENT", 641 .calr = "CAL_R", 642 .status = "CAL_STATUS", 643 .checksum = "CAL_CHECKSUM", 644 }; 645 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED); 646 647 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 648 { 649 u64 silicon_uid = 0; 650 int ret; 651 652 /* Driver can't apply calibration to a secured part, so skip */ 653 if (cs35l56_base->secured) 654 return 0; 655 656 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 657 if (ret < 0) 658 return ret; 659 660 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 661 cs35l56_base->cal_index, 662 &cs35l56_base->cal_data); 663 664 /* Only return an error status if probe should be aborted */ 665 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 666 return 0; 667 668 if (ret < 0) 669 return ret; 670 671 cs35l56_base->cal_data_valid = true; 672 673 return 0; 674 } 675 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED); 676 677 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 678 bool *fw_missing, unsigned int *fw_version) 679 { 680 unsigned int prot_status; 681 int ret; 682 683 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 684 if (ret) { 685 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 686 return ret; 687 } 688 689 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 690 691 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 692 if (ret) { 693 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 694 return ret; 695 } 696 697 return 0; 698 } 699 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 700 701 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 702 { 703 int ret; 704 unsigned int devid, revid, otpid, secured, fw_ver; 705 bool fw_missing; 706 707 /* 708 * When the system is not using a reset_gpio ensure the device is 709 * awake, otherwise the device has just been released from reset and 710 * the driver must wait for the control port to become usable. 711 */ 712 if (!cs35l56_base->reset_gpio) 713 cs35l56_issue_wake_event(cs35l56_base); 714 else 715 cs35l56_wait_control_port_ready(); 716 717 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 718 if (ret < 0) { 719 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 720 return ret; 721 } 722 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 723 724 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 725 if (ret) 726 return ret; 727 728 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 729 if (ret < 0) { 730 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 731 return ret; 732 } 733 devid &= CS35L56_DEVID_MASK; 734 735 switch (devid) { 736 case 0x35A54: 737 case 0x35A56: 738 case 0x35A57: 739 break; 740 default: 741 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 742 return ret; 743 } 744 745 cs35l56_base->type = devid & 0xFF; 746 747 /* Silicon is now identified and booted so exit cache-only */ 748 regcache_cache_only(cs35l56_base->regmap, false); 749 750 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 751 if (ret) { 752 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 753 return ret; 754 } 755 756 /* When any bus is restricted treat the device as secured */ 757 if (secured & CS35L56_RESTRICTED_MASK) 758 cs35l56_base->secured = true; 759 760 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 761 if (ret < 0) { 762 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 763 return ret; 764 } 765 766 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 767 if (ret) 768 return ret; 769 770 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 771 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 772 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 773 774 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 775 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 776 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 777 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 778 0); 779 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 780 CS35L56_TEMP_ERR_EINT1_MASK, 781 0); 782 783 return 0; 784 } 785 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 786 787 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 788 { 789 struct gpio_descs *descs; 790 u32 speaker_id; 791 int i, ret; 792 793 /* Attempt to read the speaker type from a device property first */ 794 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 795 if (!ret) { 796 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 797 return speaker_id; 798 } 799 800 /* Read the speaker type qualifier from the motherboard GPIOs */ 801 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 802 if (!descs) { 803 return -ENOENT; 804 } else if (IS_ERR(descs)) { 805 ret = PTR_ERR(descs); 806 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 807 } 808 809 speaker_id = 0; 810 for (i = 0; i < descs->ndescs; i++) { 811 ret = gpiod_get_value_cansleep(descs->desc[i]); 812 if (ret < 0) { 813 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 814 goto err; 815 } 816 817 speaker_id |= (ret << i); 818 } 819 820 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 821 ret = speaker_id; 822 err: 823 gpiod_put_array(descs); 824 825 return ret; 826 } 827 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 828 829 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 830 [0x0C] = 128000, 831 [0x0F] = 256000, 832 [0x11] = 384000, 833 [0x12] = 512000, 834 [0x15] = 768000, 835 [0x17] = 1024000, 836 [0x1A] = 1500000, 837 [0x1B] = 1536000, 838 [0x1C] = 2000000, 839 [0x1D] = 2048000, 840 [0x1E] = 2400000, 841 [0x20] = 3000000, 842 [0x21] = 3072000, 843 [0x23] = 4000000, 844 [0x24] = 4096000, 845 [0x25] = 4800000, 846 [0x27] = 6000000, 847 [0x28] = 6144000, 848 [0x29] = 6250000, 849 [0x2A] = 6400000, 850 [0x2E] = 8000000, 851 [0x2F] = 8192000, 852 [0x30] = 9600000, 853 [0x32] = 12000000, 854 [0x33] = 12288000, 855 [0x37] = 13500000, 856 [0x38] = 19200000, 857 [0x39] = 22579200, 858 [0x3B] = 24576000, 859 }; 860 861 int cs35l56_get_bclk_freq_id(unsigned int freq) 862 { 863 int i; 864 865 if (freq == 0) 866 return -EINVAL; 867 868 /* The BCLK frequency must be a valid PLL REFCLK */ 869 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 870 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 871 return i; 872 } 873 874 return -EINVAL; 875 } 876 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 877 878 static const char * const cs35l56_supplies[/* auto-sized */] = { 879 "VDD_P", 880 "VDD_IO", 881 "VDD_A", 882 }; 883 884 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 885 { 886 int i; 887 888 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 889 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 890 data[i].supply = cs35l56_supplies[i]; 891 } 892 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 893 894 const char * const cs35l56_tx_input_texts[] = { 895 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 896 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 897 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 898 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 899 }; 900 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 901 902 const unsigned int cs35l56_tx_input_values[] = { 903 CS35L56_INPUT_SRC_NONE, 904 CS35L56_INPUT_SRC_ASP1RX1, 905 CS35L56_INPUT_SRC_ASP1RX2, 906 CS35L56_INPUT_SRC_VMON, 907 CS35L56_INPUT_SRC_IMON, 908 CS35L56_INPUT_SRC_ERR_VOL, 909 CS35L56_INPUT_SRC_CLASSH, 910 CS35L56_INPUT_SRC_VDDBMON, 911 CS35L56_INPUT_SRC_VBSTMON, 912 CS35L56_INPUT_SRC_DSP1TX1, 913 CS35L56_INPUT_SRC_DSP1TX2, 914 CS35L56_INPUT_SRC_DSP1TX3, 915 CS35L56_INPUT_SRC_DSP1TX4, 916 CS35L56_INPUT_SRC_DSP1TX5, 917 CS35L56_INPUT_SRC_DSP1TX6, 918 CS35L56_INPUT_SRC_DSP1TX7, 919 CS35L56_INPUT_SRC_DSP1TX8, 920 CS35L56_INPUT_SRC_TEMPMON, 921 CS35L56_INPUT_SRC_INTERPOLATOR, 922 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 923 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 924 }; 925 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 926 927 struct regmap_config cs35l56_regmap_i2c = { 928 .reg_bits = 32, 929 .val_bits = 32, 930 .reg_stride = 4, 931 .reg_format_endian = REGMAP_ENDIAN_BIG, 932 .val_format_endian = REGMAP_ENDIAN_BIG, 933 .max_register = CS35L56_DSP1_PMEM_5114, 934 .reg_defaults = cs35l56_reg_defaults, 935 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 936 .volatile_reg = cs35l56_volatile_reg, 937 .readable_reg = cs35l56_readable_reg, 938 .precious_reg = cs35l56_precious_reg, 939 .cache_type = REGCACHE_MAPLE, 940 }; 941 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 942 943 struct regmap_config cs35l56_regmap_spi = { 944 .reg_bits = 32, 945 .val_bits = 32, 946 .pad_bits = 16, 947 .reg_stride = 4, 948 .reg_format_endian = REGMAP_ENDIAN_BIG, 949 .val_format_endian = REGMAP_ENDIAN_BIG, 950 .max_register = CS35L56_DSP1_PMEM_5114, 951 .reg_defaults = cs35l56_reg_defaults, 952 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 953 .volatile_reg = cs35l56_volatile_reg, 954 .readable_reg = cs35l56_readable_reg, 955 .precious_reg = cs35l56_precious_reg, 956 .cache_type = REGCACHE_MAPLE, 957 }; 958 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 959 960 struct regmap_config cs35l56_regmap_sdw = { 961 .reg_bits = 32, 962 .val_bits = 32, 963 .reg_stride = 4, 964 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 965 .val_format_endian = REGMAP_ENDIAN_BIG, 966 .max_register = CS35L56_DSP1_PMEM_5114, 967 .reg_defaults = cs35l56_reg_defaults, 968 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 969 .volatile_reg = cs35l56_volatile_reg, 970 .readable_reg = cs35l56_readable_reg, 971 .precious_reg = cs35l56_precious_reg, 972 .cache_type = REGCACHE_MAPLE, 973 }; 974 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 975 976 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 977 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 978 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 979 MODULE_LICENSE("GPL"); 980 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 981