1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/firmware/cirrus/wmfw.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/types.h> 14 #include <sound/cs-amp-lib.h> 15 16 #include "cs35l56.h" 17 18 static const struct reg_sequence cs35l56_patch[] = { 19 /* 20 * Firmware can change these to non-defaults to satisfy SDCA. 21 * Ensure that they are at known defaults. 22 */ 23 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 24 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 25 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 26 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 27 28 /* These are not reset by a soft-reset, so patch to defaults. */ 29 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 30 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 31 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 32 }; 33 34 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 35 { 36 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 37 ARRAY_SIZE(cs35l56_patch)); 38 } 39 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 40 41 static const struct reg_default cs35l56_reg_defaults[] = { 42 /* no defaults for OTP_MEM - first read populates cache */ 43 44 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 45 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 46 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 47 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 48 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 49 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 50 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 51 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 52 53 /* no defaults for ASP1TX mixer */ 54 55 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 56 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 57 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 58 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 59 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 60 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 61 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 62 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 63 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 64 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 65 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 66 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 67 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 68 }; 69 70 static bool cs35l56_is_dsp_memory(unsigned int reg) 71 { 72 switch (reg) { 73 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 74 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 75 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 76 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 77 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 78 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 79 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 80 return true; 81 default: 82 return false; 83 } 84 } 85 86 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 87 { 88 switch (reg) { 89 case CS35L56_DEVID: 90 case CS35L56_REVID: 91 case CS35L56_RELID: 92 case CS35L56_OTPID: 93 case CS35L56_SFT_RESET: 94 case CS35L56_GLOBAL_ENABLES: 95 case CS35L56_BLOCK_ENABLES: 96 case CS35L56_BLOCK_ENABLES2: 97 case CS35L56_REFCLK_INPUT: 98 case CS35L56_GLOBAL_SAMPLE_RATE: 99 case CS35L56_OTP_MEM_53: 100 case CS35L56_OTP_MEM_54: 101 case CS35L56_OTP_MEM_55: 102 case CS35L56_ASP1_ENABLES1: 103 case CS35L56_ASP1_CONTROL1: 104 case CS35L56_ASP1_CONTROL2: 105 case CS35L56_ASP1_CONTROL3: 106 case CS35L56_ASP1_FRAME_CONTROL1: 107 case CS35L56_ASP1_FRAME_CONTROL5: 108 case CS35L56_ASP1_DATA_CONTROL1: 109 case CS35L56_ASP1_DATA_CONTROL5: 110 case CS35L56_DACPCM1_INPUT: 111 case CS35L56_DACPCM2_INPUT: 112 case CS35L56_ASP1TX1_INPUT: 113 case CS35L56_ASP1TX2_INPUT: 114 case CS35L56_ASP1TX3_INPUT: 115 case CS35L56_ASP1TX4_INPUT: 116 case CS35L56_DSP1RX1_INPUT: 117 case CS35L56_DSP1RX2_INPUT: 118 case CS35L56_SWIRE_DP3_CH1_INPUT: 119 case CS35L56_SWIRE_DP3_CH2_INPUT: 120 case CS35L56_SWIRE_DP3_CH3_INPUT: 121 case CS35L56_SWIRE_DP3_CH4_INPUT: 122 case CS35L56_IRQ1_CFG: 123 case CS35L56_IRQ1_STATUS: 124 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 125 case CS35L56_IRQ1_EINT_18: 126 case CS35L56_IRQ1_EINT_20: 127 case CS35L56_IRQ1_MASK_1: 128 case CS35L56_IRQ1_MASK_2: 129 case CS35L56_IRQ1_MASK_4: 130 case CS35L56_IRQ1_MASK_8: 131 case CS35L56_IRQ1_MASK_18: 132 case CS35L56_IRQ1_MASK_20: 133 case CS35L56_DSP_VIRTUAL1_MBOX_1: 134 case CS35L56_DSP_VIRTUAL1_MBOX_2: 135 case CS35L56_DSP_VIRTUAL1_MBOX_3: 136 case CS35L56_DSP_VIRTUAL1_MBOX_4: 137 case CS35L56_DSP_VIRTUAL1_MBOX_5: 138 case CS35L56_DSP_VIRTUAL1_MBOX_6: 139 case CS35L56_DSP_VIRTUAL1_MBOX_7: 140 case CS35L56_DSP_VIRTUAL1_MBOX_8: 141 case CS35L56_DSP_RESTRICT_STS1: 142 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 143 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 144 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 145 case CS35L56_DSP1_SCRATCH1: 146 case CS35L56_DSP1_SCRATCH2: 147 case CS35L56_DSP1_SCRATCH3: 148 case CS35L56_DSP1_SCRATCH4: 149 return true; 150 default: 151 return cs35l56_is_dsp_memory(reg); 152 } 153 } 154 155 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 156 { 157 switch (reg) { 158 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 159 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 160 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 161 return true; 162 default: 163 return false; 164 } 165 } 166 167 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 168 { 169 switch (reg) { 170 case CS35L56_DEVID: 171 case CS35L56_REVID: 172 case CS35L56_RELID: 173 case CS35L56_OTPID: 174 case CS35L56_SFT_RESET: 175 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 176 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 177 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 178 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 179 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 180 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 181 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 182 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 183 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 184 case CS35L56_IRQ1_STATUS: 185 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 186 case CS35L56_IRQ1_EINT_18: 187 case CS35L56_IRQ1_EINT_20: 188 case CS35L56_DSP_VIRTUAL1_MBOX_1: 189 case CS35L56_DSP_VIRTUAL1_MBOX_2: 190 case CS35L56_DSP_VIRTUAL1_MBOX_3: 191 case CS35L56_DSP_VIRTUAL1_MBOX_4: 192 case CS35L56_DSP_VIRTUAL1_MBOX_5: 193 case CS35L56_DSP_VIRTUAL1_MBOX_6: 194 case CS35L56_DSP_VIRTUAL1_MBOX_7: 195 case CS35L56_DSP_VIRTUAL1_MBOX_8: 196 case CS35L56_DSP_RESTRICT_STS1: 197 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 198 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 199 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 200 case CS35L56_DSP1_SCRATCH1: 201 case CS35L56_DSP1_SCRATCH2: 202 case CS35L56_DSP1_SCRATCH3: 203 case CS35L56_DSP1_SCRATCH4: 204 return true; 205 case CS35L56_MAIN_RENDER_USER_MUTE: 206 case CS35L56_MAIN_RENDER_USER_VOLUME: 207 case CS35L56_MAIN_POSTURE_NUMBER: 208 return false; 209 default: 210 return cs35l56_is_dsp_memory(reg); 211 } 212 } 213 214 /* 215 * The firmware boot sequence can overwrite the ASP1 config registers so that 216 * they don't match regmap's view of their values. Rewrite the values from the 217 * regmap cache into the hardware registers. 218 */ 219 int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base) 220 { 221 struct reg_sequence asp1_regs[] = { 222 { .reg = CS35L56_ASP1_ENABLES1 }, 223 { .reg = CS35L56_ASP1_CONTROL1 }, 224 { .reg = CS35L56_ASP1_CONTROL2 }, 225 { .reg = CS35L56_ASP1_CONTROL3 }, 226 { .reg = CS35L56_ASP1_FRAME_CONTROL1 }, 227 { .reg = CS35L56_ASP1_FRAME_CONTROL5 }, 228 { .reg = CS35L56_ASP1_DATA_CONTROL1 }, 229 { .reg = CS35L56_ASP1_DATA_CONTROL5 }, 230 }; 231 int i, ret; 232 233 /* Read values from regmap cache into a write sequence */ 234 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) { 235 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); 236 if (ret) 237 goto err; 238 } 239 240 /* Write the values cache-bypassed so that they will be written to silicon */ 241 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, 242 ARRAY_SIZE(asp1_regs)); 243 if (ret) 244 goto err; 245 246 return 0; 247 248 err: 249 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); 250 251 return ret; 252 } 253 EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED); 254 255 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 256 { 257 unsigned int val; 258 int ret; 259 260 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 261 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 262 val, (val == 0), 263 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 264 if (ret) { 265 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 266 return ret; 267 } 268 269 return 0; 270 } 271 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 272 273 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 274 { 275 int ret; 276 unsigned int reg; 277 unsigned int val; 278 279 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 280 if (ret) 281 return ret; 282 283 if (cs35l56_base->rev < CS35L56_REVID_B0) 284 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 285 else 286 reg = CS35L56_DSP1_PM_CUR_STATE; 287 288 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 289 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 290 CS35L56_HALO_STATE_POLL_US, 291 CS35L56_HALO_STATE_TIMEOUT_US); 292 if (ret < 0) 293 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 294 val, ret); 295 return ret; 296 } 297 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 298 299 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 300 { 301 unsigned int reg; 302 unsigned int val = 0; 303 int read_ret, poll_ret; 304 305 if (cs35l56_base->rev < CS35L56_REVID_B0) 306 reg = CS35L56_DSP1_HALO_STATE_A1; 307 else 308 reg = CS35L56_DSP1_HALO_STATE; 309 310 /* 311 * This can't be a regmap_read_poll_timeout() because cs35l56 will NAK 312 * I2C until it has booted which would terminate the poll 313 */ 314 poll_ret = read_poll_timeout(regmap_read, read_ret, 315 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 316 CS35L56_HALO_STATE_POLL_US, 317 CS35L56_HALO_STATE_TIMEOUT_US, 318 false, 319 cs35l56_base->regmap, reg, &val); 320 321 if (poll_ret) { 322 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 323 read_ret, val); 324 return -EIO; 325 } 326 327 return 0; 328 } 329 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 330 331 void cs35l56_wait_control_port_ready(void) 332 { 333 /* Wait for control port to be ready (datasheet tIRS). */ 334 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 335 } 336 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 337 338 void cs35l56_wait_min_reset_pulse(void) 339 { 340 /* Satisfy minimum reset pulse width spec */ 341 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 342 } 343 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 344 345 static const struct reg_sequence cs35l56_system_reset_seq[] = { 346 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 347 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 348 }; 349 350 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 351 { 352 /* 353 * Must enter cache-only first so there can't be any more register 354 * accesses other than the controlled system reset sequence below. 355 */ 356 regcache_cache_only(cs35l56_base->regmap, true); 357 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 358 cs35l56_system_reset_seq, 359 ARRAY_SIZE(cs35l56_system_reset_seq)); 360 361 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 362 if (is_soundwire) 363 return; 364 365 cs35l56_wait_control_port_ready(); 366 regcache_cache_only(cs35l56_base->regmap, false); 367 } 368 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 369 370 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 371 { 372 int ret; 373 374 if (!irq) 375 return 0; 376 377 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 378 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 379 "cs35l56", cs35l56_base); 380 if (!ret) 381 cs35l56_base->irq = irq; 382 else 383 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 384 385 return ret; 386 } 387 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 388 389 irqreturn_t cs35l56_irq(int irq, void *data) 390 { 391 struct cs35l56_base *cs35l56_base = data; 392 unsigned int status1 = 0, status8 = 0, status20 = 0; 393 unsigned int mask1, mask8, mask20; 394 unsigned int val; 395 int rv; 396 397 irqreturn_t ret = IRQ_NONE; 398 399 if (!cs35l56_base->init_done) 400 return IRQ_NONE; 401 402 mutex_lock(&cs35l56_base->irq_lock); 403 404 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 405 if (rv < 0) { 406 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 407 goto err_unlock; 408 } 409 410 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 411 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 412 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 413 goto err; 414 } 415 416 /* Ack interrupts */ 417 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 418 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 419 status1 &= ~mask1; 420 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 421 422 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 423 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 424 status8 &= ~mask8; 425 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 426 427 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 428 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 429 status20 &= ~mask20; 430 /* We don't want EINT20 but they default to unmasked: force mask */ 431 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 432 433 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 434 435 /* Check to see if unmasked bits are active */ 436 if (!status1 && !status8 && !status20) 437 goto err; 438 439 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 440 dev_crit(cs35l56_base->dev, "Amp short error\n"); 441 442 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 443 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 444 445 ret = IRQ_HANDLED; 446 447 err: 448 pm_runtime_put(cs35l56_base->dev); 449 err_unlock: 450 mutex_unlock(&cs35l56_base->irq_lock); 451 452 return ret; 453 } 454 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 455 456 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 457 { 458 unsigned int val; 459 int ret; 460 461 /* 462 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 463 * can't be used here to test for memory retention. 464 * Assume that tuning must be re-loaded. 465 */ 466 if (cs35l56_base->secured) 467 return true; 468 469 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 470 if (ret) { 471 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 472 return ret; 473 } 474 475 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 476 if (ret) 477 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 478 else 479 ret = !!(val & CS35L56_FIRMWARE_MISSING); 480 481 pm_runtime_put_autosuspend(cs35l56_base->dev); 482 483 return ret; 484 } 485 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 486 487 static const struct reg_sequence cs35l56_hibernate_seq[] = { 488 /* This must be the last register access */ 489 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 490 }; 491 492 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 493 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 494 }; 495 496 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 497 { 498 /* 499 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 500 * transactions to meet the minimum required time from the rising edge 501 * to the last falling edge of wake. 502 * 503 * It uses bypassed write because we must wake the chip before 504 * disabling regmap cache-only. 505 * 506 * This can NAK on I2C which will terminate the write sequence so the 507 * single-write sequence is issued twice. 508 */ 509 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 510 cs35l56_hibernate_wake_seq, 511 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 512 513 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 514 515 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 516 cs35l56_hibernate_wake_seq, 517 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 518 519 cs35l56_wait_control_port_ready(); 520 } 521 522 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 523 { 524 unsigned int val; 525 int ret; 526 527 if (!cs35l56_base->init_done) 528 return 0; 529 530 /* Firmware must have entered a power-save state */ 531 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 532 CS35L56_TRANSDUCER_ACTUAL_PS, 533 val, (val >= CS35L56_PS3), 534 CS35L56_PS3_POLL_US, 535 CS35L56_PS3_TIMEOUT_US); 536 if (ret) 537 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 538 539 /* Clear BOOT_DONE so it can be used to detect a reboot */ 540 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 541 542 if (!cs35l56_base->can_hibernate) { 543 regcache_cache_only(cs35l56_base->regmap, true); 544 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 545 546 return 0; 547 } 548 549 /* 550 * Must enter cache-only first so there can't be any more register 551 * accesses other than the controlled hibernate sequence below. 552 */ 553 regcache_cache_only(cs35l56_base->regmap, true); 554 555 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 556 cs35l56_hibernate_seq, 557 ARRAY_SIZE(cs35l56_hibernate_seq)); 558 559 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 560 561 return 0; 562 } 563 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 564 565 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 566 { 567 unsigned int val; 568 int ret; 569 570 if (!cs35l56_base->init_done) 571 return 0; 572 573 if (!cs35l56_base->can_hibernate) 574 goto out_sync; 575 576 /* Must be done before releasing cache-only */ 577 if (!is_soundwire) 578 cs35l56_issue_wake_event(cs35l56_base); 579 580 out_sync: 581 regcache_cache_only(cs35l56_base->regmap, false); 582 583 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 584 if (ret) { 585 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 586 goto err; 587 } 588 589 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 590 if (ret) 591 goto err; 592 593 /* BOOT_DONE will be 1 if the amp reset */ 594 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 595 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 596 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 597 regcache_mark_dirty(cs35l56_base->regmap); 598 } 599 600 regcache_sync(cs35l56_base->regmap); 601 602 dev_dbg(cs35l56_base->dev, "Resumed"); 603 604 return 0; 605 606 err: 607 regcache_cache_only(cs35l56_base->regmap, true); 608 609 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 610 cs35l56_hibernate_seq, 611 ARRAY_SIZE(cs35l56_hibernate_seq)); 612 613 return ret; 614 } 615 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 616 617 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 618 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 619 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 620 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 621 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 622 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 623 }; 624 625 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 626 { 627 cs_dsp->num = 1; 628 cs_dsp->type = WMFW_HALO; 629 cs_dsp->rev = 0; 630 cs_dsp->dev = cs35l56_base->dev; 631 cs_dsp->regmap = cs35l56_base->regmap; 632 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 633 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 634 cs_dsp->mem = cs35l56_dsp1_regions; 635 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 636 cs_dsp->no_core_startstop = true; 637 } 638 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 639 640 struct cs35l56_pte { 641 u8 x; 642 u8 wafer_id; 643 u8 pte[2]; 644 u8 lot[3]; 645 u8 y; 646 u8 unused[3]; 647 u8 dvs; 648 } __packed; 649 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 650 651 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 652 { 653 struct cs35l56_pte pte; 654 u64 unique_id; 655 int ret; 656 657 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 658 if (ret) { 659 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 660 return ret; 661 } 662 663 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 664 unique_id <<= 32; 665 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 666 ((u32)pte.dvs << 24); 667 668 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id); 669 670 *uid = unique_id; 671 672 return 0; 673 } 674 675 /* Firmware calibration controls */ 676 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 677 .alg_id = 0x9f210, 678 .mem_region = WMFW_ADSP2_YM, 679 .ambient = "CAL_AMBIENT", 680 .calr = "CAL_R", 681 .status = "CAL_STATUS", 682 .checksum = "CAL_CHECKSUM", 683 }; 684 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED); 685 686 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 687 { 688 u64 silicon_uid; 689 int ret; 690 691 /* Driver can't apply calibration to a secured part, so skip */ 692 if (cs35l56_base->secured) 693 return 0; 694 695 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 696 if (ret < 0) 697 return ret; 698 699 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 700 cs35l56_base->cal_index, 701 &cs35l56_base->cal_data); 702 703 /* Only return an error status if probe should be aborted */ 704 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 705 return 0; 706 707 if (ret < 0) 708 return ret; 709 710 cs35l56_base->cal_data_valid = true; 711 712 return 0; 713 } 714 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED); 715 716 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 717 bool *fw_missing, unsigned int *fw_version) 718 { 719 unsigned int prot_status; 720 int ret; 721 722 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 723 if (ret) { 724 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 725 return ret; 726 } 727 728 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 729 730 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 731 if (ret) { 732 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 733 return ret; 734 } 735 736 return 0; 737 } 738 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 739 740 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 741 { 742 int ret; 743 unsigned int devid, revid, otpid, secured, fw_ver; 744 bool fw_missing; 745 746 /* 747 * When the system is not using a reset_gpio ensure the device is 748 * awake, otherwise the device has just been released from reset and 749 * the driver must wait for the control port to become usable. 750 */ 751 if (!cs35l56_base->reset_gpio) 752 cs35l56_issue_wake_event(cs35l56_base); 753 else 754 cs35l56_wait_control_port_ready(); 755 756 /* 757 * The HALO_STATE register is in different locations on Ax and B0 758 * devices so the REVID needs to be determined before waiting for the 759 * firmware to boot. 760 */ 761 ret = regmap_read(cs35l56_base->regmap, CS35L56_REVID, &revid); 762 if (ret < 0) { 763 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 764 return ret; 765 } 766 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 767 768 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 769 if (ret) 770 return ret; 771 772 ret = regmap_read(cs35l56_base->regmap, CS35L56_DEVID, &devid); 773 if (ret < 0) { 774 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 775 return ret; 776 } 777 devid &= CS35L56_DEVID_MASK; 778 779 switch (devid) { 780 case 0x35A54: 781 case 0x35A56: 782 case 0x35A57: 783 break; 784 default: 785 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 786 return ret; 787 } 788 789 cs35l56_base->type = devid & 0xFF; 790 791 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 792 if (ret) { 793 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 794 return ret; 795 } 796 797 /* When any bus is restricted treat the device as secured */ 798 if (secured & CS35L56_RESTRICTED_MASK) 799 cs35l56_base->secured = true; 800 801 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 802 if (ret < 0) { 803 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 804 return ret; 805 } 806 807 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 808 if (ret) 809 return ret; 810 811 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 812 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 813 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 814 815 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 816 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 817 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 818 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 819 0); 820 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 821 CS35L56_TEMP_ERR_EINT1_MASK, 822 0); 823 824 return 0; 825 } 826 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 827 828 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 829 { 830 struct gpio_descs *descs; 831 int speaker_id; 832 int i, ret; 833 834 /* Read the speaker type qualifier from the motherboard GPIOs */ 835 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 836 if (!descs) { 837 return -ENOENT; 838 } else if (IS_ERR(descs)) { 839 ret = PTR_ERR(descs); 840 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 841 } 842 843 speaker_id = 0; 844 for (i = 0; i < descs->ndescs; i++) { 845 ret = gpiod_get_value_cansleep(descs->desc[i]); 846 if (ret < 0) { 847 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 848 goto err; 849 } 850 851 speaker_id |= (ret << i); 852 } 853 854 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 855 ret = speaker_id; 856 err: 857 gpiod_put_array(descs); 858 859 return ret; 860 } 861 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 862 863 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 864 [0x0C] = 128000, 865 [0x0F] = 256000, 866 [0x11] = 384000, 867 [0x12] = 512000, 868 [0x15] = 768000, 869 [0x17] = 1024000, 870 [0x1A] = 1500000, 871 [0x1B] = 1536000, 872 [0x1C] = 2000000, 873 [0x1D] = 2048000, 874 [0x1E] = 2400000, 875 [0x20] = 3000000, 876 [0x21] = 3072000, 877 [0x23] = 4000000, 878 [0x24] = 4096000, 879 [0x25] = 4800000, 880 [0x27] = 6000000, 881 [0x28] = 6144000, 882 [0x29] = 6250000, 883 [0x2A] = 6400000, 884 [0x2E] = 8000000, 885 [0x2F] = 8192000, 886 [0x30] = 9600000, 887 [0x32] = 12000000, 888 [0x33] = 12288000, 889 [0x37] = 13500000, 890 [0x38] = 19200000, 891 [0x39] = 22579200, 892 [0x3B] = 24576000, 893 }; 894 895 int cs35l56_get_bclk_freq_id(unsigned int freq) 896 { 897 int i; 898 899 if (freq == 0) 900 return -EINVAL; 901 902 /* The BCLK frequency must be a valid PLL REFCLK */ 903 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 904 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 905 return i; 906 } 907 908 return -EINVAL; 909 } 910 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 911 912 static const char * const cs35l56_supplies[/* auto-sized */] = { 913 "VDD_P", 914 "VDD_IO", 915 "VDD_A", 916 }; 917 918 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 919 { 920 int i; 921 922 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 923 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 924 data[i].supply = cs35l56_supplies[i]; 925 } 926 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 927 928 const char * const cs35l56_tx_input_texts[] = { 929 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 930 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 931 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 932 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 933 }; 934 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 935 936 const unsigned int cs35l56_tx_input_values[] = { 937 CS35L56_INPUT_SRC_NONE, 938 CS35L56_INPUT_SRC_ASP1RX1, 939 CS35L56_INPUT_SRC_ASP1RX2, 940 CS35L56_INPUT_SRC_VMON, 941 CS35L56_INPUT_SRC_IMON, 942 CS35L56_INPUT_SRC_ERR_VOL, 943 CS35L56_INPUT_SRC_CLASSH, 944 CS35L56_INPUT_SRC_VDDBMON, 945 CS35L56_INPUT_SRC_VBSTMON, 946 CS35L56_INPUT_SRC_DSP1TX1, 947 CS35L56_INPUT_SRC_DSP1TX2, 948 CS35L56_INPUT_SRC_DSP1TX3, 949 CS35L56_INPUT_SRC_DSP1TX4, 950 CS35L56_INPUT_SRC_DSP1TX5, 951 CS35L56_INPUT_SRC_DSP1TX6, 952 CS35L56_INPUT_SRC_DSP1TX7, 953 CS35L56_INPUT_SRC_DSP1TX8, 954 CS35L56_INPUT_SRC_TEMPMON, 955 CS35L56_INPUT_SRC_INTERPOLATOR, 956 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 957 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 958 }; 959 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 960 961 struct regmap_config cs35l56_regmap_i2c = { 962 .reg_bits = 32, 963 .val_bits = 32, 964 .reg_stride = 4, 965 .reg_format_endian = REGMAP_ENDIAN_BIG, 966 .val_format_endian = REGMAP_ENDIAN_BIG, 967 .max_register = CS35L56_DSP1_PMEM_5114, 968 .reg_defaults = cs35l56_reg_defaults, 969 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 970 .volatile_reg = cs35l56_volatile_reg, 971 .readable_reg = cs35l56_readable_reg, 972 .precious_reg = cs35l56_precious_reg, 973 .cache_type = REGCACHE_MAPLE, 974 }; 975 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 976 977 struct regmap_config cs35l56_regmap_spi = { 978 .reg_bits = 32, 979 .val_bits = 32, 980 .pad_bits = 16, 981 .reg_stride = 4, 982 .reg_format_endian = REGMAP_ENDIAN_BIG, 983 .val_format_endian = REGMAP_ENDIAN_BIG, 984 .max_register = CS35L56_DSP1_PMEM_5114, 985 .reg_defaults = cs35l56_reg_defaults, 986 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 987 .volatile_reg = cs35l56_volatile_reg, 988 .readable_reg = cs35l56_readable_reg, 989 .precious_reg = cs35l56_precious_reg, 990 .cache_type = REGCACHE_MAPLE, 991 }; 992 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 993 994 struct regmap_config cs35l56_regmap_sdw = { 995 .reg_bits = 32, 996 .val_bits = 32, 997 .reg_stride = 4, 998 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 999 .val_format_endian = REGMAP_ENDIAN_BIG, 1000 .max_register = CS35L56_DSP1_PMEM_5114, 1001 .reg_defaults = cs35l56_reg_defaults, 1002 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1003 .volatile_reg = cs35l56_volatile_reg, 1004 .readable_reg = cs35l56_readable_reg, 1005 .precious_reg = cs35l56_precious_reg, 1006 .cache_type = REGCACHE_MAPLE, 1007 }; 1008 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 1009 1010 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1011 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1012 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1013 MODULE_LICENSE("GPL"); 1014 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 1015