1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/firmware/cirrus/wmfw.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/types.h> 14 #include <sound/cs-amp-lib.h> 15 16 #include "cs35l56.h" 17 18 static const struct reg_sequence cs35l56_patch[] = { 19 /* 20 * Firmware can change these to non-defaults to satisfy SDCA. 21 * Ensure that they are at known defaults. 22 */ 23 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 24 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 25 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 26 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 27 28 /* These are not reset by a soft-reset, so patch to defaults. */ 29 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 30 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 31 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 32 }; 33 34 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 35 { 36 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 37 ARRAY_SIZE(cs35l56_patch)); 38 } 39 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 40 41 static const struct reg_default cs35l56_reg_defaults[] = { 42 /* no defaults for OTP_MEM - first read populates cache */ 43 44 /* 45 * No defaults for ASP1 control or ASP1TX mixer. See 46 * cs35l56_populate_asp1_register_defaults() and 47 * cs35l56_sync_asp1_mixer_widgets_with_firmware(). 48 */ 49 50 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 51 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 52 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 53 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 54 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 55 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 56 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 57 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 58 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 59 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 60 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 61 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 62 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 63 }; 64 65 static bool cs35l56_is_dsp_memory(unsigned int reg) 66 { 67 switch (reg) { 68 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 69 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 70 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 71 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 72 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 73 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 74 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 75 return true; 76 default: 77 return false; 78 } 79 } 80 81 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 82 { 83 switch (reg) { 84 case CS35L56_DEVID: 85 case CS35L56_REVID: 86 case CS35L56_RELID: 87 case CS35L56_OTPID: 88 case CS35L56_SFT_RESET: 89 case CS35L56_GLOBAL_ENABLES: 90 case CS35L56_BLOCK_ENABLES: 91 case CS35L56_BLOCK_ENABLES2: 92 case CS35L56_REFCLK_INPUT: 93 case CS35L56_GLOBAL_SAMPLE_RATE: 94 case CS35L56_OTP_MEM_53: 95 case CS35L56_OTP_MEM_54: 96 case CS35L56_OTP_MEM_55: 97 case CS35L56_ASP1_ENABLES1: 98 case CS35L56_ASP1_CONTROL1: 99 case CS35L56_ASP1_CONTROL2: 100 case CS35L56_ASP1_CONTROL3: 101 case CS35L56_ASP1_FRAME_CONTROL1: 102 case CS35L56_ASP1_FRAME_CONTROL5: 103 case CS35L56_ASP1_DATA_CONTROL1: 104 case CS35L56_ASP1_DATA_CONTROL5: 105 case CS35L56_DACPCM1_INPUT: 106 case CS35L56_DACPCM2_INPUT: 107 case CS35L56_ASP1TX1_INPUT: 108 case CS35L56_ASP1TX2_INPUT: 109 case CS35L56_ASP1TX3_INPUT: 110 case CS35L56_ASP1TX4_INPUT: 111 case CS35L56_DSP1RX1_INPUT: 112 case CS35L56_DSP1RX2_INPUT: 113 case CS35L56_SWIRE_DP3_CH1_INPUT: 114 case CS35L56_SWIRE_DP3_CH2_INPUT: 115 case CS35L56_SWIRE_DP3_CH3_INPUT: 116 case CS35L56_SWIRE_DP3_CH4_INPUT: 117 case CS35L56_IRQ1_CFG: 118 case CS35L56_IRQ1_STATUS: 119 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 120 case CS35L56_IRQ1_EINT_18: 121 case CS35L56_IRQ1_EINT_20: 122 case CS35L56_IRQ1_MASK_1: 123 case CS35L56_IRQ1_MASK_2: 124 case CS35L56_IRQ1_MASK_4: 125 case CS35L56_IRQ1_MASK_8: 126 case CS35L56_IRQ1_MASK_18: 127 case CS35L56_IRQ1_MASK_20: 128 case CS35L56_DSP_VIRTUAL1_MBOX_1: 129 case CS35L56_DSP_VIRTUAL1_MBOX_2: 130 case CS35L56_DSP_VIRTUAL1_MBOX_3: 131 case CS35L56_DSP_VIRTUAL1_MBOX_4: 132 case CS35L56_DSP_VIRTUAL1_MBOX_5: 133 case CS35L56_DSP_VIRTUAL1_MBOX_6: 134 case CS35L56_DSP_VIRTUAL1_MBOX_7: 135 case CS35L56_DSP_VIRTUAL1_MBOX_8: 136 case CS35L56_DSP_RESTRICT_STS1: 137 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 138 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 139 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 140 case CS35L56_DSP1_SCRATCH1: 141 case CS35L56_DSP1_SCRATCH2: 142 case CS35L56_DSP1_SCRATCH3: 143 case CS35L56_DSP1_SCRATCH4: 144 return true; 145 default: 146 return cs35l56_is_dsp_memory(reg); 147 } 148 } 149 150 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 154 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 155 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case CS35L56_DEVID: 166 case CS35L56_REVID: 167 case CS35L56_RELID: 168 case CS35L56_OTPID: 169 case CS35L56_SFT_RESET: 170 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 171 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 172 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 173 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 174 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 175 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 176 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 177 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 178 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 179 case CS35L56_IRQ1_STATUS: 180 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 181 case CS35L56_IRQ1_EINT_18: 182 case CS35L56_IRQ1_EINT_20: 183 case CS35L56_DSP_VIRTUAL1_MBOX_1: 184 case CS35L56_DSP_VIRTUAL1_MBOX_2: 185 case CS35L56_DSP_VIRTUAL1_MBOX_3: 186 case CS35L56_DSP_VIRTUAL1_MBOX_4: 187 case CS35L56_DSP_VIRTUAL1_MBOX_5: 188 case CS35L56_DSP_VIRTUAL1_MBOX_6: 189 case CS35L56_DSP_VIRTUAL1_MBOX_7: 190 case CS35L56_DSP_VIRTUAL1_MBOX_8: 191 case CS35L56_DSP_RESTRICT_STS1: 192 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 193 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 194 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 195 case CS35L56_DSP1_SCRATCH1: 196 case CS35L56_DSP1_SCRATCH2: 197 case CS35L56_DSP1_SCRATCH3: 198 case CS35L56_DSP1_SCRATCH4: 199 return true; 200 case CS35L56_MAIN_RENDER_USER_MUTE: 201 case CS35L56_MAIN_RENDER_USER_VOLUME: 202 case CS35L56_MAIN_POSTURE_NUMBER: 203 return false; 204 default: 205 return cs35l56_is_dsp_memory(reg); 206 } 207 } 208 209 static const struct reg_sequence cs35l56_asp1_defaults[] = { 210 REG_SEQ0(CS35L56_ASP1_ENABLES1, 0x00000000), 211 REG_SEQ0(CS35L56_ASP1_CONTROL1, 0x00000028), 212 REG_SEQ0(CS35L56_ASP1_CONTROL2, 0x18180200), 213 REG_SEQ0(CS35L56_ASP1_CONTROL3, 0x00000002), 214 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL1, 0x03020100), 215 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL5, 0x00020100), 216 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL1, 0x00000018), 217 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL5, 0x00000018), 218 }; 219 220 /* 221 * The firmware can have control of the ASP so we don't provide regmap 222 * with defaults for these registers, to prevent a regcache_sync() from 223 * overwriting the firmware settings. But if the machine driver hooks up 224 * the ASP it means the driver is taking control of the ASP, so then the 225 * registers are populated with the defaults. 226 */ 227 int cs35l56_init_asp1_regs_for_driver_control(struct cs35l56_base *cs35l56_base) 228 { 229 if (!cs35l56_base->fw_owns_asp1) 230 return 0; 231 232 cs35l56_base->fw_owns_asp1 = false; 233 234 return regmap_multi_reg_write(cs35l56_base->regmap, cs35l56_asp1_defaults, 235 ARRAY_SIZE(cs35l56_asp1_defaults)); 236 } 237 EXPORT_SYMBOL_NS_GPL(cs35l56_init_asp1_regs_for_driver_control, SND_SOC_CS35L56_SHARED); 238 239 /* 240 * The firmware boot sequence can overwrite the ASP1 config registers so that 241 * they don't match regmap's view of their values. Rewrite the values from the 242 * regmap cache into the hardware registers. 243 */ 244 int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base) 245 { 246 struct reg_sequence asp1_regs[ARRAY_SIZE(cs35l56_asp1_defaults)]; 247 int i, ret; 248 249 if (cs35l56_base->fw_owns_asp1) 250 return 0; 251 252 memcpy(asp1_regs, cs35l56_asp1_defaults, sizeof(asp1_regs)); 253 254 /* Read current values from regmap cache into the write sequence */ 255 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) { 256 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); 257 if (ret) 258 goto err; 259 } 260 261 /* Write the values cache-bypassed so that they will be written to silicon */ 262 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, 263 ARRAY_SIZE(asp1_regs)); 264 if (ret) 265 goto err; 266 267 return 0; 268 269 err: 270 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); 271 272 return ret; 273 } 274 EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED); 275 276 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 277 { 278 unsigned int val; 279 int ret; 280 281 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 282 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 283 val, (val == 0), 284 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 285 if (ret) { 286 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 287 return ret; 288 } 289 290 return 0; 291 } 292 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 293 294 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 295 { 296 int ret; 297 unsigned int reg; 298 unsigned int val; 299 300 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 301 if (ret) 302 return ret; 303 304 if (cs35l56_base->rev < CS35L56_REVID_B0) 305 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 306 else 307 reg = CS35L56_DSP1_PM_CUR_STATE; 308 309 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 310 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 311 CS35L56_HALO_STATE_POLL_US, 312 CS35L56_HALO_STATE_TIMEOUT_US); 313 if (ret < 0) 314 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 315 val, ret); 316 return ret; 317 } 318 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 319 320 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 321 { 322 unsigned int reg; 323 unsigned int val = 0; 324 int read_ret, poll_ret; 325 326 if (cs35l56_base->rev < CS35L56_REVID_B0) 327 reg = CS35L56_DSP1_HALO_STATE_A1; 328 else 329 reg = CS35L56_DSP1_HALO_STATE; 330 331 /* 332 * The regmap must remain in cache-only until the chip has 333 * booted, so use a bypassed read of the status register. 334 */ 335 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 336 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 337 CS35L56_HALO_STATE_POLL_US, 338 CS35L56_HALO_STATE_TIMEOUT_US, 339 false, 340 cs35l56_base->regmap, reg, &val); 341 342 if (poll_ret) { 343 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 344 read_ret, val); 345 return -EIO; 346 } 347 348 return 0; 349 } 350 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 351 352 void cs35l56_wait_control_port_ready(void) 353 { 354 /* Wait for control port to be ready (datasheet tIRS). */ 355 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 356 } 357 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 358 359 void cs35l56_wait_min_reset_pulse(void) 360 { 361 /* Satisfy minimum reset pulse width spec */ 362 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 363 } 364 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 365 366 static const struct reg_sequence cs35l56_system_reset_seq[] = { 367 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 368 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 369 }; 370 371 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 372 { 373 /* 374 * Must enter cache-only first so there can't be any more register 375 * accesses other than the controlled system reset sequence below. 376 */ 377 regcache_cache_only(cs35l56_base->regmap, true); 378 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 379 cs35l56_system_reset_seq, 380 ARRAY_SIZE(cs35l56_system_reset_seq)); 381 382 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 383 if (is_soundwire) 384 return; 385 386 cs35l56_wait_control_port_ready(); 387 388 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 389 } 390 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 391 392 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 393 { 394 int ret; 395 396 if (!irq) 397 return 0; 398 399 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 400 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 401 "cs35l56", cs35l56_base); 402 if (!ret) 403 cs35l56_base->irq = irq; 404 else 405 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 406 407 return ret; 408 } 409 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 410 411 irqreturn_t cs35l56_irq(int irq, void *data) 412 { 413 struct cs35l56_base *cs35l56_base = data; 414 unsigned int status1 = 0, status8 = 0, status20 = 0; 415 unsigned int mask1, mask8, mask20; 416 unsigned int val; 417 int rv; 418 419 irqreturn_t ret = IRQ_NONE; 420 421 if (!cs35l56_base->init_done) 422 return IRQ_NONE; 423 424 mutex_lock(&cs35l56_base->irq_lock); 425 426 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 427 if (rv < 0) { 428 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 429 goto err_unlock; 430 } 431 432 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 433 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 434 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 435 goto err; 436 } 437 438 /* Ack interrupts */ 439 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 440 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 441 status1 &= ~mask1; 442 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 443 444 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 445 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 446 status8 &= ~mask8; 447 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 448 449 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 450 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 451 status20 &= ~mask20; 452 /* We don't want EINT20 but they default to unmasked: force mask */ 453 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 454 455 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 456 457 /* Check to see if unmasked bits are active */ 458 if (!status1 && !status8 && !status20) 459 goto err; 460 461 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 462 dev_crit(cs35l56_base->dev, "Amp short error\n"); 463 464 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 465 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 466 467 ret = IRQ_HANDLED; 468 469 err: 470 pm_runtime_put(cs35l56_base->dev); 471 err_unlock: 472 mutex_unlock(&cs35l56_base->irq_lock); 473 474 return ret; 475 } 476 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 477 478 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 479 { 480 unsigned int val; 481 int ret; 482 483 /* 484 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 485 * can't be used here to test for memory retention. 486 * Assume that tuning must be re-loaded. 487 */ 488 if (cs35l56_base->secured) 489 return true; 490 491 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 492 if (ret) { 493 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 494 return ret; 495 } 496 497 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 498 if (ret) 499 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 500 else 501 ret = !!(val & CS35L56_FIRMWARE_MISSING); 502 503 pm_runtime_put_autosuspend(cs35l56_base->dev); 504 505 return ret; 506 } 507 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 508 509 static const struct reg_sequence cs35l56_hibernate_seq[] = { 510 /* This must be the last register access */ 511 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 512 }; 513 514 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 515 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 516 }; 517 518 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 519 { 520 /* 521 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 522 * transactions to meet the minimum required time from the rising edge 523 * to the last falling edge of wake. 524 * 525 * It uses bypassed write because we must wake the chip before 526 * disabling regmap cache-only. 527 * 528 * This can NAK on I2C which will terminate the write sequence so the 529 * single-write sequence is issued twice. 530 */ 531 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 532 cs35l56_hibernate_wake_seq, 533 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 534 535 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 536 537 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 538 cs35l56_hibernate_wake_seq, 539 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 540 541 cs35l56_wait_control_port_ready(); 542 } 543 544 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 545 { 546 unsigned int val; 547 int ret; 548 549 if (!cs35l56_base->init_done) 550 return 0; 551 552 /* Firmware must have entered a power-save state */ 553 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 554 CS35L56_TRANSDUCER_ACTUAL_PS, 555 val, (val >= CS35L56_PS3), 556 CS35L56_PS3_POLL_US, 557 CS35L56_PS3_TIMEOUT_US); 558 if (ret) 559 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 560 561 /* Clear BOOT_DONE so it can be used to detect a reboot */ 562 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 563 564 if (!cs35l56_base->can_hibernate) { 565 regcache_cache_only(cs35l56_base->regmap, true); 566 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 567 568 return 0; 569 } 570 571 /* 572 * Must enter cache-only first so there can't be any more register 573 * accesses other than the controlled hibernate sequence below. 574 */ 575 regcache_cache_only(cs35l56_base->regmap, true); 576 577 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 578 cs35l56_hibernate_seq, 579 ARRAY_SIZE(cs35l56_hibernate_seq)); 580 581 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 582 583 return 0; 584 } 585 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 586 587 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 588 { 589 unsigned int val; 590 int ret; 591 592 if (!cs35l56_base->init_done) 593 return 0; 594 595 if (!cs35l56_base->can_hibernate) 596 goto out_sync; 597 598 /* Must be done before releasing cache-only */ 599 if (!is_soundwire) 600 cs35l56_issue_wake_event(cs35l56_base); 601 602 out_sync: 603 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 604 if (ret) { 605 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 606 goto err; 607 } 608 609 regcache_cache_only(cs35l56_base->regmap, false); 610 611 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 612 if (ret) 613 goto err; 614 615 /* BOOT_DONE will be 1 if the amp reset */ 616 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 617 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 618 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 619 regcache_mark_dirty(cs35l56_base->regmap); 620 } 621 622 regcache_sync(cs35l56_base->regmap); 623 624 dev_dbg(cs35l56_base->dev, "Resumed"); 625 626 return 0; 627 628 err: 629 regcache_cache_only(cs35l56_base->regmap, true); 630 631 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 632 cs35l56_hibernate_seq, 633 ARRAY_SIZE(cs35l56_hibernate_seq)); 634 635 return ret; 636 } 637 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 638 639 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 640 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 641 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 642 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 643 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 644 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 645 }; 646 647 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 648 { 649 cs_dsp->num = 1; 650 cs_dsp->type = WMFW_HALO; 651 cs_dsp->rev = 0; 652 cs_dsp->dev = cs35l56_base->dev; 653 cs_dsp->regmap = cs35l56_base->regmap; 654 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 655 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 656 cs_dsp->mem = cs35l56_dsp1_regions; 657 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 658 cs_dsp->no_core_startstop = true; 659 } 660 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 661 662 struct cs35l56_pte { 663 u8 x; 664 u8 wafer_id; 665 u8 pte[2]; 666 u8 lot[3]; 667 u8 y; 668 u8 unused[3]; 669 u8 dvs; 670 } __packed; 671 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 672 673 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 674 { 675 struct cs35l56_pte pte; 676 u64 unique_id; 677 int ret; 678 679 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 680 if (ret) { 681 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 682 return ret; 683 } 684 685 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 686 unique_id <<= 32; 687 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 688 ((u32)pte.dvs << 24); 689 690 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id); 691 692 *uid = unique_id; 693 694 return 0; 695 } 696 697 /* Firmware calibration controls */ 698 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 699 .alg_id = 0x9f210, 700 .mem_region = WMFW_ADSP2_YM, 701 .ambient = "CAL_AMBIENT", 702 .calr = "CAL_R", 703 .status = "CAL_STATUS", 704 .checksum = "CAL_CHECKSUM", 705 }; 706 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED); 707 708 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 709 { 710 u64 silicon_uid = 0; 711 int ret; 712 713 /* Driver can't apply calibration to a secured part, so skip */ 714 if (cs35l56_base->secured) 715 return 0; 716 717 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 718 if (ret < 0) 719 return ret; 720 721 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 722 cs35l56_base->cal_index, 723 &cs35l56_base->cal_data); 724 725 /* Only return an error status if probe should be aborted */ 726 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 727 return 0; 728 729 if (ret < 0) 730 return ret; 731 732 cs35l56_base->cal_data_valid = true; 733 734 return 0; 735 } 736 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED); 737 738 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 739 bool *fw_missing, unsigned int *fw_version) 740 { 741 unsigned int prot_status; 742 int ret; 743 744 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 745 if (ret) { 746 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 747 return ret; 748 } 749 750 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 751 752 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 753 if (ret) { 754 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 755 return ret; 756 } 757 758 return 0; 759 } 760 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 761 762 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 763 { 764 int ret; 765 unsigned int devid, revid, otpid, secured, fw_ver; 766 bool fw_missing; 767 768 /* 769 * When the system is not using a reset_gpio ensure the device is 770 * awake, otherwise the device has just been released from reset and 771 * the driver must wait for the control port to become usable. 772 */ 773 if (!cs35l56_base->reset_gpio) 774 cs35l56_issue_wake_event(cs35l56_base); 775 else 776 cs35l56_wait_control_port_ready(); 777 778 /* 779 * The HALO_STATE register is in different locations on Ax and B0 780 * devices so the REVID needs to be determined before waiting for the 781 * firmware to boot. 782 */ 783 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 784 if (ret < 0) { 785 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 786 return ret; 787 } 788 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 789 790 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 791 if (ret) 792 return ret; 793 794 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 795 if (ret < 0) { 796 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 797 return ret; 798 } 799 devid &= CS35L56_DEVID_MASK; 800 801 switch (devid) { 802 case 0x35A54: 803 case 0x35A56: 804 case 0x35A57: 805 break; 806 default: 807 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 808 return ret; 809 } 810 811 cs35l56_base->type = devid & 0xFF; 812 813 /* Silicon is now identified and booted so exit cache-only */ 814 regcache_cache_only(cs35l56_base->regmap, false); 815 816 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 817 if (ret) { 818 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 819 return ret; 820 } 821 822 /* When any bus is restricted treat the device as secured */ 823 if (secured & CS35L56_RESTRICTED_MASK) 824 cs35l56_base->secured = true; 825 826 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 827 if (ret < 0) { 828 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 829 return ret; 830 } 831 832 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 833 if (ret) 834 return ret; 835 836 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 837 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 838 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 839 840 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 841 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 842 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 843 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 844 0); 845 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 846 CS35L56_TEMP_ERR_EINT1_MASK, 847 0); 848 849 return 0; 850 } 851 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 852 853 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 854 { 855 struct gpio_descs *descs; 856 int speaker_id; 857 int i, ret; 858 859 /* Read the speaker type qualifier from the motherboard GPIOs */ 860 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 861 if (!descs) { 862 return -ENOENT; 863 } else if (IS_ERR(descs)) { 864 ret = PTR_ERR(descs); 865 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 866 } 867 868 speaker_id = 0; 869 for (i = 0; i < descs->ndescs; i++) { 870 ret = gpiod_get_value_cansleep(descs->desc[i]); 871 if (ret < 0) { 872 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 873 goto err; 874 } 875 876 speaker_id |= (ret << i); 877 } 878 879 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 880 ret = speaker_id; 881 err: 882 gpiod_put_array(descs); 883 884 return ret; 885 } 886 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 887 888 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 889 [0x0C] = 128000, 890 [0x0F] = 256000, 891 [0x11] = 384000, 892 [0x12] = 512000, 893 [0x15] = 768000, 894 [0x17] = 1024000, 895 [0x1A] = 1500000, 896 [0x1B] = 1536000, 897 [0x1C] = 2000000, 898 [0x1D] = 2048000, 899 [0x1E] = 2400000, 900 [0x20] = 3000000, 901 [0x21] = 3072000, 902 [0x23] = 4000000, 903 [0x24] = 4096000, 904 [0x25] = 4800000, 905 [0x27] = 6000000, 906 [0x28] = 6144000, 907 [0x29] = 6250000, 908 [0x2A] = 6400000, 909 [0x2E] = 8000000, 910 [0x2F] = 8192000, 911 [0x30] = 9600000, 912 [0x32] = 12000000, 913 [0x33] = 12288000, 914 [0x37] = 13500000, 915 [0x38] = 19200000, 916 [0x39] = 22579200, 917 [0x3B] = 24576000, 918 }; 919 920 int cs35l56_get_bclk_freq_id(unsigned int freq) 921 { 922 int i; 923 924 if (freq == 0) 925 return -EINVAL; 926 927 /* The BCLK frequency must be a valid PLL REFCLK */ 928 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 929 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 930 return i; 931 } 932 933 return -EINVAL; 934 } 935 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 936 937 static const char * const cs35l56_supplies[/* auto-sized */] = { 938 "VDD_P", 939 "VDD_IO", 940 "VDD_A", 941 }; 942 943 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 944 { 945 int i; 946 947 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 948 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 949 data[i].supply = cs35l56_supplies[i]; 950 } 951 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 952 953 const char * const cs35l56_tx_input_texts[] = { 954 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 955 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 956 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 957 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 958 }; 959 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 960 961 const unsigned int cs35l56_tx_input_values[] = { 962 CS35L56_INPUT_SRC_NONE, 963 CS35L56_INPUT_SRC_ASP1RX1, 964 CS35L56_INPUT_SRC_ASP1RX2, 965 CS35L56_INPUT_SRC_VMON, 966 CS35L56_INPUT_SRC_IMON, 967 CS35L56_INPUT_SRC_ERR_VOL, 968 CS35L56_INPUT_SRC_CLASSH, 969 CS35L56_INPUT_SRC_VDDBMON, 970 CS35L56_INPUT_SRC_VBSTMON, 971 CS35L56_INPUT_SRC_DSP1TX1, 972 CS35L56_INPUT_SRC_DSP1TX2, 973 CS35L56_INPUT_SRC_DSP1TX3, 974 CS35L56_INPUT_SRC_DSP1TX4, 975 CS35L56_INPUT_SRC_DSP1TX5, 976 CS35L56_INPUT_SRC_DSP1TX6, 977 CS35L56_INPUT_SRC_DSP1TX7, 978 CS35L56_INPUT_SRC_DSP1TX8, 979 CS35L56_INPUT_SRC_TEMPMON, 980 CS35L56_INPUT_SRC_INTERPOLATOR, 981 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 982 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 983 }; 984 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 985 986 struct regmap_config cs35l56_regmap_i2c = { 987 .reg_bits = 32, 988 .val_bits = 32, 989 .reg_stride = 4, 990 .reg_format_endian = REGMAP_ENDIAN_BIG, 991 .val_format_endian = REGMAP_ENDIAN_BIG, 992 .max_register = CS35L56_DSP1_PMEM_5114, 993 .reg_defaults = cs35l56_reg_defaults, 994 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 995 .volatile_reg = cs35l56_volatile_reg, 996 .readable_reg = cs35l56_readable_reg, 997 .precious_reg = cs35l56_precious_reg, 998 .cache_type = REGCACHE_MAPLE, 999 }; 1000 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 1001 1002 struct regmap_config cs35l56_regmap_spi = { 1003 .reg_bits = 32, 1004 .val_bits = 32, 1005 .pad_bits = 16, 1006 .reg_stride = 4, 1007 .reg_format_endian = REGMAP_ENDIAN_BIG, 1008 .val_format_endian = REGMAP_ENDIAN_BIG, 1009 .max_register = CS35L56_DSP1_PMEM_5114, 1010 .reg_defaults = cs35l56_reg_defaults, 1011 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1012 .volatile_reg = cs35l56_volatile_reg, 1013 .readable_reg = cs35l56_readable_reg, 1014 .precious_reg = cs35l56_precious_reg, 1015 .cache_type = REGCACHE_MAPLE, 1016 }; 1017 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 1018 1019 struct regmap_config cs35l56_regmap_sdw = { 1020 .reg_bits = 32, 1021 .val_bits = 32, 1022 .reg_stride = 4, 1023 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1024 .val_format_endian = REGMAP_ENDIAN_BIG, 1025 .max_register = CS35L56_DSP1_PMEM_5114, 1026 .reg_defaults = cs35l56_reg_defaults, 1027 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1028 .volatile_reg = cs35l56_volatile_reg, 1029 .readable_reg = cs35l56_readable_reg, 1030 .precious_reg = cs35l56_precious_reg, 1031 .cache_type = REGCACHE_MAPLE, 1032 }; 1033 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 1034 1035 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1036 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1037 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1038 MODULE_LICENSE("GPL"); 1039 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 1040