1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/array_size.h> 9 #include <linux/firmware/cirrus/wmfw.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/regmap.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/types.h> 14 #include <sound/cs-amp-lib.h> 15 16 #include "cs35l56.h" 17 18 static const struct reg_sequence cs35l56_patch[] = { 19 /* 20 * Firmware can change these to non-defaults to satisfy SDCA. 21 * Ensure that they are at known defaults. 22 */ 23 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 24 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 25 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 26 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 27 28 /* These are not reset by a soft-reset, so patch to defaults. */ 29 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 30 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 31 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 32 }; 33 34 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 35 { 36 return regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 37 ARRAY_SIZE(cs35l56_patch)); 38 } 39 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, SND_SOC_CS35L56_SHARED); 40 41 static const struct reg_default cs35l56_reg_defaults[] = { 42 /* no defaults for OTP_MEM - first read populates cache */ 43 44 /* 45 * No defaults for ASP1 control or ASP1TX mixer. See 46 * cs35l56_populate_asp1_register_defaults() and 47 * cs35l56_sync_asp1_mixer_widgets_with_firmware(). 48 */ 49 50 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 51 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 52 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 53 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 54 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 55 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 56 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 57 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 58 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 59 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 60 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 61 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 62 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 63 }; 64 65 static bool cs35l56_is_dsp_memory(unsigned int reg) 66 { 67 switch (reg) { 68 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 69 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 70 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 71 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 72 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 73 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 74 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 75 return true; 76 default: 77 return false; 78 } 79 } 80 81 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 82 { 83 switch (reg) { 84 case CS35L56_DEVID: 85 case CS35L56_REVID: 86 case CS35L56_RELID: 87 case CS35L56_OTPID: 88 case CS35L56_SFT_RESET: 89 case CS35L56_GLOBAL_ENABLES: 90 case CS35L56_BLOCK_ENABLES: 91 case CS35L56_BLOCK_ENABLES2: 92 case CS35L56_REFCLK_INPUT: 93 case CS35L56_GLOBAL_SAMPLE_RATE: 94 case CS35L56_OTP_MEM_53: 95 case CS35L56_OTP_MEM_54: 96 case CS35L56_OTP_MEM_55: 97 case CS35L56_ASP1_ENABLES1: 98 case CS35L56_ASP1_CONTROL1: 99 case CS35L56_ASP1_CONTROL2: 100 case CS35L56_ASP1_CONTROL3: 101 case CS35L56_ASP1_FRAME_CONTROL1: 102 case CS35L56_ASP1_FRAME_CONTROL5: 103 case CS35L56_ASP1_DATA_CONTROL1: 104 case CS35L56_ASP1_DATA_CONTROL5: 105 case CS35L56_DACPCM1_INPUT: 106 case CS35L56_DACPCM2_INPUT: 107 case CS35L56_ASP1TX1_INPUT: 108 case CS35L56_ASP1TX2_INPUT: 109 case CS35L56_ASP1TX3_INPUT: 110 case CS35L56_ASP1TX4_INPUT: 111 case CS35L56_DSP1RX1_INPUT: 112 case CS35L56_DSP1RX2_INPUT: 113 case CS35L56_SWIRE_DP3_CH1_INPUT: 114 case CS35L56_SWIRE_DP3_CH2_INPUT: 115 case CS35L56_SWIRE_DP3_CH3_INPUT: 116 case CS35L56_SWIRE_DP3_CH4_INPUT: 117 case CS35L56_IRQ1_CFG: 118 case CS35L56_IRQ1_STATUS: 119 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 120 case CS35L56_IRQ1_EINT_18: 121 case CS35L56_IRQ1_EINT_20: 122 case CS35L56_IRQ1_MASK_1: 123 case CS35L56_IRQ1_MASK_2: 124 case CS35L56_IRQ1_MASK_4: 125 case CS35L56_IRQ1_MASK_8: 126 case CS35L56_IRQ1_MASK_18: 127 case CS35L56_IRQ1_MASK_20: 128 case CS35L56_DSP_VIRTUAL1_MBOX_1: 129 case CS35L56_DSP_VIRTUAL1_MBOX_2: 130 case CS35L56_DSP_VIRTUAL1_MBOX_3: 131 case CS35L56_DSP_VIRTUAL1_MBOX_4: 132 case CS35L56_DSP_VIRTUAL1_MBOX_5: 133 case CS35L56_DSP_VIRTUAL1_MBOX_6: 134 case CS35L56_DSP_VIRTUAL1_MBOX_7: 135 case CS35L56_DSP_VIRTUAL1_MBOX_8: 136 case CS35L56_DSP_RESTRICT_STS1: 137 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 138 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 139 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 140 case CS35L56_DSP1_SCRATCH1: 141 case CS35L56_DSP1_SCRATCH2: 142 case CS35L56_DSP1_SCRATCH3: 143 case CS35L56_DSP1_SCRATCH4: 144 return true; 145 default: 146 return cs35l56_is_dsp_memory(reg); 147 } 148 } 149 150 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 154 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 155 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case CS35L56_DEVID: 166 case CS35L56_REVID: 167 case CS35L56_RELID: 168 case CS35L56_OTPID: 169 case CS35L56_SFT_RESET: 170 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 171 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 172 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 173 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 174 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 175 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 176 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 177 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 178 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 179 case CS35L56_IRQ1_STATUS: 180 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 181 case CS35L56_IRQ1_EINT_18: 182 case CS35L56_IRQ1_EINT_20: 183 case CS35L56_DSP_VIRTUAL1_MBOX_1: 184 case CS35L56_DSP_VIRTUAL1_MBOX_2: 185 case CS35L56_DSP_VIRTUAL1_MBOX_3: 186 case CS35L56_DSP_VIRTUAL1_MBOX_4: 187 case CS35L56_DSP_VIRTUAL1_MBOX_5: 188 case CS35L56_DSP_VIRTUAL1_MBOX_6: 189 case CS35L56_DSP_VIRTUAL1_MBOX_7: 190 case CS35L56_DSP_VIRTUAL1_MBOX_8: 191 case CS35L56_DSP_RESTRICT_STS1: 192 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 193 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 194 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 195 case CS35L56_DSP1_SCRATCH1: 196 case CS35L56_DSP1_SCRATCH2: 197 case CS35L56_DSP1_SCRATCH3: 198 case CS35L56_DSP1_SCRATCH4: 199 return true; 200 case CS35L56_MAIN_RENDER_USER_MUTE: 201 case CS35L56_MAIN_RENDER_USER_VOLUME: 202 case CS35L56_MAIN_POSTURE_NUMBER: 203 return false; 204 default: 205 return cs35l56_is_dsp_memory(reg); 206 } 207 } 208 209 static const struct reg_sequence cs35l56_asp1_defaults[] = { 210 REG_SEQ0(CS35L56_ASP1_ENABLES1, 0x00000000), 211 REG_SEQ0(CS35L56_ASP1_CONTROL1, 0x00000028), 212 REG_SEQ0(CS35L56_ASP1_CONTROL2, 0x18180200), 213 REG_SEQ0(CS35L56_ASP1_CONTROL3, 0x00000002), 214 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL1, 0x03020100), 215 REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL5, 0x00020100), 216 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL1, 0x00000018), 217 REG_SEQ0(CS35L56_ASP1_DATA_CONTROL5, 0x00000018), 218 REG_SEQ0(CS35L56_ASP1TX1_INPUT, 0x00000000), 219 REG_SEQ0(CS35L56_ASP1TX2_INPUT, 0x00000000), 220 REG_SEQ0(CS35L56_ASP1TX3_INPUT, 0x00000000), 221 REG_SEQ0(CS35L56_ASP1TX4_INPUT, 0x00000000), 222 }; 223 224 /* 225 * The firmware can have control of the ASP so we don't provide regmap 226 * with defaults for these registers, to prevent a regcache_sync() from 227 * overwriting the firmware settings. But if the machine driver hooks up 228 * the ASP it means the driver is taking control of the ASP, so then the 229 * registers are populated with the defaults. 230 */ 231 int cs35l56_init_asp1_regs_for_driver_control(struct cs35l56_base *cs35l56_base) 232 { 233 if (!cs35l56_base->fw_owns_asp1) 234 return 0; 235 236 cs35l56_base->fw_owns_asp1 = false; 237 238 return regmap_multi_reg_write(cs35l56_base->regmap, cs35l56_asp1_defaults, 239 ARRAY_SIZE(cs35l56_asp1_defaults)); 240 } 241 EXPORT_SYMBOL_NS_GPL(cs35l56_init_asp1_regs_for_driver_control, SND_SOC_CS35L56_SHARED); 242 243 /* 244 * The firmware boot sequence can overwrite the ASP1 config registers so that 245 * they don't match regmap's view of their values. Rewrite the values from the 246 * regmap cache into the hardware registers. 247 */ 248 int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base) 249 { 250 struct reg_sequence asp1_regs[ARRAY_SIZE(cs35l56_asp1_defaults)]; 251 int i, ret; 252 253 if (cs35l56_base->fw_owns_asp1) 254 return 0; 255 256 memcpy(asp1_regs, cs35l56_asp1_defaults, sizeof(asp1_regs)); 257 258 /* Read current values from regmap cache into the write sequence */ 259 for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) { 260 ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def); 261 if (ret) 262 goto err; 263 } 264 265 /* Write the values cache-bypassed so that they will be written to silicon */ 266 ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs, 267 ARRAY_SIZE(asp1_regs)); 268 if (ret) 269 goto err; 270 271 return 0; 272 273 err: 274 dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret); 275 276 return ret; 277 } 278 EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED); 279 280 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 281 { 282 unsigned int val; 283 int ret; 284 285 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 286 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 287 val, (val == 0), 288 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 289 if (ret) { 290 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 291 return ret; 292 } 293 294 return 0; 295 } 296 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, SND_SOC_CS35L56_SHARED); 297 298 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 299 { 300 int ret; 301 unsigned int reg; 302 unsigned int val; 303 304 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 305 if (ret) 306 return ret; 307 308 if (cs35l56_base->rev < CS35L56_REVID_B0) 309 reg = CS35L56_DSP1_PM_CUR_STATE_A1; 310 else 311 reg = CS35L56_DSP1_PM_CUR_STATE; 312 313 ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg, 314 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 315 CS35L56_HALO_STATE_POLL_US, 316 CS35L56_HALO_STATE_TIMEOUT_US); 317 if (ret < 0) 318 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 319 val, ret); 320 return ret; 321 } 322 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, SND_SOC_CS35L56_SHARED); 323 324 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 325 { 326 unsigned int reg; 327 unsigned int val = 0; 328 int read_ret, poll_ret; 329 330 if (cs35l56_base->rev < CS35L56_REVID_B0) 331 reg = CS35L56_DSP1_HALO_STATE_A1; 332 else 333 reg = CS35L56_DSP1_HALO_STATE; 334 335 /* 336 * The regmap must remain in cache-only until the chip has 337 * booted, so use a bypassed read of the status register. 338 */ 339 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 340 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 341 CS35L56_HALO_STATE_POLL_US, 342 CS35L56_HALO_STATE_TIMEOUT_US, 343 false, 344 cs35l56_base->regmap, reg, &val); 345 346 if (poll_ret) { 347 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 348 read_ret, val); 349 return -EIO; 350 } 351 352 return 0; 353 } 354 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, SND_SOC_CS35L56_SHARED); 355 356 void cs35l56_wait_control_port_ready(void) 357 { 358 /* Wait for control port to be ready (datasheet tIRS). */ 359 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 360 } 361 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, SND_SOC_CS35L56_SHARED); 362 363 void cs35l56_wait_min_reset_pulse(void) 364 { 365 /* Satisfy minimum reset pulse width spec */ 366 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 367 } 368 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, SND_SOC_CS35L56_SHARED); 369 370 static const struct reg_sequence cs35l56_system_reset_seq[] = { 371 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 372 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 373 }; 374 375 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 376 { 377 /* 378 * Must enter cache-only first so there can't be any more register 379 * accesses other than the controlled system reset sequence below. 380 */ 381 regcache_cache_only(cs35l56_base->regmap, true); 382 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 383 cs35l56_system_reset_seq, 384 ARRAY_SIZE(cs35l56_system_reset_seq)); 385 386 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 387 if (is_soundwire) 388 return; 389 390 cs35l56_wait_control_port_ready(); 391 392 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 393 } 394 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, SND_SOC_CS35L56_SHARED); 395 396 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 397 { 398 int ret; 399 400 if (!irq) 401 return 0; 402 403 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 404 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 405 "cs35l56", cs35l56_base); 406 if (!ret) 407 cs35l56_base->irq = irq; 408 else 409 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 410 411 return ret; 412 } 413 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, SND_SOC_CS35L56_SHARED); 414 415 irqreturn_t cs35l56_irq(int irq, void *data) 416 { 417 struct cs35l56_base *cs35l56_base = data; 418 unsigned int status1 = 0, status8 = 0, status20 = 0; 419 unsigned int mask1, mask8, mask20; 420 unsigned int val; 421 int rv; 422 423 irqreturn_t ret = IRQ_NONE; 424 425 if (!cs35l56_base->init_done) 426 return IRQ_NONE; 427 428 mutex_lock(&cs35l56_base->irq_lock); 429 430 rv = pm_runtime_resume_and_get(cs35l56_base->dev); 431 if (rv < 0) { 432 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 433 goto err_unlock; 434 } 435 436 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 437 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 438 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 439 goto err; 440 } 441 442 /* Ack interrupts */ 443 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 444 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 445 status1 &= ~mask1; 446 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 447 448 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 449 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 450 status8 &= ~mask8; 451 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 452 453 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 454 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 455 status20 &= ~mask20; 456 /* We don't want EINT20 but they default to unmasked: force mask */ 457 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 458 459 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 460 461 /* Check to see if unmasked bits are active */ 462 if (!status1 && !status8 && !status20) 463 goto err; 464 465 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 466 dev_crit(cs35l56_base->dev, "Amp short error\n"); 467 468 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 469 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 470 471 ret = IRQ_HANDLED; 472 473 err: 474 pm_runtime_put(cs35l56_base->dev); 475 err_unlock: 476 mutex_unlock(&cs35l56_base->irq_lock); 477 478 return ret; 479 } 480 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, SND_SOC_CS35L56_SHARED); 481 482 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 483 { 484 unsigned int val; 485 int ret; 486 487 /* 488 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 489 * can't be used here to test for memory retention. 490 * Assume that tuning must be re-loaded. 491 */ 492 if (cs35l56_base->secured) 493 return true; 494 495 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 496 if (ret) { 497 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 498 return ret; 499 } 500 501 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &val); 502 if (ret) 503 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 504 else 505 ret = !!(val & CS35L56_FIRMWARE_MISSING); 506 507 pm_runtime_put_autosuspend(cs35l56_base->dev); 508 509 return ret; 510 } 511 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, SND_SOC_CS35L56_SHARED); 512 513 static const struct reg_sequence cs35l56_hibernate_seq[] = { 514 /* This must be the last register access */ 515 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 516 }; 517 518 static const struct reg_sequence cs35l56_hibernate_wake_seq[] = { 519 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_WAKEUP), 520 }; 521 522 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 523 { 524 /* 525 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 526 * transactions to meet the minimum required time from the rising edge 527 * to the last falling edge of wake. 528 * 529 * It uses bypassed write because we must wake the chip before 530 * disabling regmap cache-only. 531 * 532 * This can NAK on I2C which will terminate the write sequence so the 533 * single-write sequence is issued twice. 534 */ 535 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 536 cs35l56_hibernate_wake_seq, 537 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 538 539 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 540 541 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 542 cs35l56_hibernate_wake_seq, 543 ARRAY_SIZE(cs35l56_hibernate_wake_seq)); 544 545 cs35l56_wait_control_port_ready(); 546 } 547 548 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 549 { 550 unsigned int val; 551 int ret; 552 553 if (!cs35l56_base->init_done) 554 return 0; 555 556 /* Firmware must have entered a power-save state */ 557 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 558 CS35L56_TRANSDUCER_ACTUAL_PS, 559 val, (val >= CS35L56_PS3), 560 CS35L56_PS3_POLL_US, 561 CS35L56_PS3_TIMEOUT_US); 562 if (ret) 563 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 564 565 /* Clear BOOT_DONE so it can be used to detect a reboot */ 566 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 567 568 if (!cs35l56_base->can_hibernate) { 569 regcache_cache_only(cs35l56_base->regmap, true); 570 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 571 572 return 0; 573 } 574 575 /* 576 * Must enter cache-only first so there can't be any more register 577 * accesses other than the controlled hibernate sequence below. 578 */ 579 regcache_cache_only(cs35l56_base->regmap, true); 580 581 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 582 cs35l56_hibernate_seq, 583 ARRAY_SIZE(cs35l56_hibernate_seq)); 584 585 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 586 587 return 0; 588 } 589 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, SND_SOC_CS35L56_SHARED); 590 591 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 592 { 593 unsigned int val; 594 int ret; 595 596 if (!cs35l56_base->init_done) 597 return 0; 598 599 if (!cs35l56_base->can_hibernate) 600 goto out_sync; 601 602 /* Must be done before releasing cache-only */ 603 if (!is_soundwire) 604 cs35l56_issue_wake_event(cs35l56_base); 605 606 out_sync: 607 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 608 if (ret) { 609 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 610 goto err; 611 } 612 613 regcache_cache_only(cs35l56_base->regmap, false); 614 615 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 616 if (ret) 617 goto err; 618 619 /* BOOT_DONE will be 1 if the amp reset */ 620 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 621 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 622 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 623 regcache_mark_dirty(cs35l56_base->regmap); 624 } 625 626 regcache_sync(cs35l56_base->regmap); 627 628 dev_dbg(cs35l56_base->dev, "Resumed"); 629 630 return 0; 631 632 err: 633 regcache_cache_only(cs35l56_base->regmap, true); 634 635 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 636 cs35l56_hibernate_seq, 637 ARRAY_SIZE(cs35l56_hibernate_seq)); 638 639 return ret; 640 } 641 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, SND_SOC_CS35L56_SHARED); 642 643 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 644 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 645 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 646 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 647 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 648 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 649 }; 650 651 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 652 { 653 cs_dsp->num = 1; 654 cs_dsp->type = WMFW_HALO; 655 cs_dsp->rev = 0; 656 cs_dsp->dev = cs35l56_base->dev; 657 cs_dsp->regmap = cs35l56_base->regmap; 658 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 659 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 660 cs_dsp->mem = cs35l56_dsp1_regions; 661 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 662 cs_dsp->no_core_startstop = true; 663 } 664 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, SND_SOC_CS35L56_SHARED); 665 666 struct cs35l56_pte { 667 u8 x; 668 u8 wafer_id; 669 u8 pte[2]; 670 u8 lot[3]; 671 u8 y; 672 u8 unused[3]; 673 u8 dvs; 674 } __packed; 675 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 676 677 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base, u64 *uid) 678 { 679 struct cs35l56_pte pte; 680 u64 unique_id; 681 int ret; 682 683 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 684 if (ret) { 685 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 686 return ret; 687 } 688 689 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 690 unique_id <<= 32; 691 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 692 ((u32)pte.dvs << 24); 693 694 dev_dbg(cs35l56_base->dev, "UniqueID = %#llx\n", unique_id); 695 696 *uid = unique_id; 697 698 return 0; 699 } 700 701 /* Firmware calibration controls */ 702 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 703 .alg_id = 0x9f210, 704 .mem_region = WMFW_ADSP2_YM, 705 .ambient = "CAL_AMBIENT", 706 .calr = "CAL_R", 707 .status = "CAL_STATUS", 708 .checksum = "CAL_CHECKSUM", 709 }; 710 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, SND_SOC_CS35L56_SHARED); 711 712 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 713 { 714 u64 silicon_uid = 0; 715 int ret; 716 717 /* Driver can't apply calibration to a secured part, so skip */ 718 if (cs35l56_base->secured) 719 return 0; 720 721 ret = cs35l56_read_silicon_uid(cs35l56_base, &silicon_uid); 722 if (ret < 0) 723 return ret; 724 725 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, silicon_uid, 726 cs35l56_base->cal_index, 727 &cs35l56_base->cal_data); 728 729 /* Only return an error status if probe should be aborted */ 730 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 731 return 0; 732 733 if (ret < 0) 734 return ret; 735 736 cs35l56_base->cal_data_valid = true; 737 738 return 0; 739 } 740 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, SND_SOC_CS35L56_SHARED); 741 742 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 743 bool *fw_missing, unsigned int *fw_version) 744 { 745 unsigned int prot_status; 746 int ret; 747 748 ret = regmap_read(cs35l56_base->regmap, CS35L56_PROTECTION_STATUS, &prot_status); 749 if (ret) { 750 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 751 return ret; 752 } 753 754 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 755 756 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP1_FW_VER, fw_version); 757 if (ret) { 758 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 759 return ret; 760 } 761 762 return 0; 763 } 764 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, SND_SOC_CS35L56_SHARED); 765 766 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 767 { 768 int ret; 769 unsigned int devid, revid, otpid, secured, fw_ver; 770 bool fw_missing; 771 772 /* 773 * When the system is not using a reset_gpio ensure the device is 774 * awake, otherwise the device has just been released from reset and 775 * the driver must wait for the control port to become usable. 776 */ 777 if (!cs35l56_base->reset_gpio) 778 cs35l56_issue_wake_event(cs35l56_base); 779 else 780 cs35l56_wait_control_port_ready(); 781 782 /* 783 * The HALO_STATE register is in different locations on Ax and B0 784 * devices so the REVID needs to be determined before waiting for the 785 * firmware to boot. 786 */ 787 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 788 if (ret < 0) { 789 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 790 return ret; 791 } 792 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 793 794 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 795 if (ret) 796 return ret; 797 798 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 799 if (ret < 0) { 800 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 801 return ret; 802 } 803 devid &= CS35L56_DEVID_MASK; 804 805 switch (devid) { 806 case 0x35A54: 807 case 0x35A56: 808 case 0x35A57: 809 break; 810 default: 811 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 812 return ret; 813 } 814 815 cs35l56_base->type = devid & 0xFF; 816 817 /* Silicon is now identified and booted so exit cache-only */ 818 regcache_cache_only(cs35l56_base->regmap, false); 819 820 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 821 if (ret) { 822 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 823 return ret; 824 } 825 826 /* When any bus is restricted treat the device as secured */ 827 if (secured & CS35L56_RESTRICTED_MASK) 828 cs35l56_base->secured = true; 829 830 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 831 if (ret < 0) { 832 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 833 return ret; 834 } 835 836 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 837 if (ret) 838 return ret; 839 840 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 841 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 842 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 843 844 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 845 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 846 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 847 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 848 0); 849 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 850 CS35L56_TEMP_ERR_EINT1_MASK, 851 0); 852 853 return 0; 854 } 855 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, SND_SOC_CS35L56_SHARED); 856 857 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 858 { 859 struct gpio_descs *descs; 860 int speaker_id; 861 int i, ret; 862 863 /* Read the speaker type qualifier from the motherboard GPIOs */ 864 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 865 if (!descs) { 866 return -ENOENT; 867 } else if (IS_ERR(descs)) { 868 ret = PTR_ERR(descs); 869 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 870 } 871 872 speaker_id = 0; 873 for (i = 0; i < descs->ndescs; i++) { 874 ret = gpiod_get_value_cansleep(descs->desc[i]); 875 if (ret < 0) { 876 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 877 goto err; 878 } 879 880 speaker_id |= (ret << i); 881 } 882 883 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 884 ret = speaker_id; 885 err: 886 gpiod_put_array(descs); 887 888 return ret; 889 } 890 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, SND_SOC_CS35L56_SHARED); 891 892 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 893 [0x0C] = 128000, 894 [0x0F] = 256000, 895 [0x11] = 384000, 896 [0x12] = 512000, 897 [0x15] = 768000, 898 [0x17] = 1024000, 899 [0x1A] = 1500000, 900 [0x1B] = 1536000, 901 [0x1C] = 2000000, 902 [0x1D] = 2048000, 903 [0x1E] = 2400000, 904 [0x20] = 3000000, 905 [0x21] = 3072000, 906 [0x23] = 4000000, 907 [0x24] = 4096000, 908 [0x25] = 4800000, 909 [0x27] = 6000000, 910 [0x28] = 6144000, 911 [0x29] = 6250000, 912 [0x2A] = 6400000, 913 [0x2E] = 8000000, 914 [0x2F] = 8192000, 915 [0x30] = 9600000, 916 [0x32] = 12000000, 917 [0x33] = 12288000, 918 [0x37] = 13500000, 919 [0x38] = 19200000, 920 [0x39] = 22579200, 921 [0x3B] = 24576000, 922 }; 923 924 int cs35l56_get_bclk_freq_id(unsigned int freq) 925 { 926 int i; 927 928 if (freq == 0) 929 return -EINVAL; 930 931 /* The BCLK frequency must be a valid PLL REFCLK */ 932 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 933 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 934 return i; 935 } 936 937 return -EINVAL; 938 } 939 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, SND_SOC_CS35L56_SHARED); 940 941 static const char * const cs35l56_supplies[/* auto-sized */] = { 942 "VDD_P", 943 "VDD_IO", 944 "VDD_A", 945 }; 946 947 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 948 { 949 int i; 950 951 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 952 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 953 data[i].supply = cs35l56_supplies[i]; 954 } 955 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, SND_SOC_CS35L56_SHARED); 956 957 const char * const cs35l56_tx_input_texts[] = { 958 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 959 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 960 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 961 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 962 }; 963 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, SND_SOC_CS35L56_SHARED); 964 965 const unsigned int cs35l56_tx_input_values[] = { 966 CS35L56_INPUT_SRC_NONE, 967 CS35L56_INPUT_SRC_ASP1RX1, 968 CS35L56_INPUT_SRC_ASP1RX2, 969 CS35L56_INPUT_SRC_VMON, 970 CS35L56_INPUT_SRC_IMON, 971 CS35L56_INPUT_SRC_ERR_VOL, 972 CS35L56_INPUT_SRC_CLASSH, 973 CS35L56_INPUT_SRC_VDDBMON, 974 CS35L56_INPUT_SRC_VBSTMON, 975 CS35L56_INPUT_SRC_DSP1TX1, 976 CS35L56_INPUT_SRC_DSP1TX2, 977 CS35L56_INPUT_SRC_DSP1TX3, 978 CS35L56_INPUT_SRC_DSP1TX4, 979 CS35L56_INPUT_SRC_DSP1TX5, 980 CS35L56_INPUT_SRC_DSP1TX6, 981 CS35L56_INPUT_SRC_DSP1TX7, 982 CS35L56_INPUT_SRC_DSP1TX8, 983 CS35L56_INPUT_SRC_TEMPMON, 984 CS35L56_INPUT_SRC_INTERPOLATOR, 985 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 986 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 987 }; 988 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, SND_SOC_CS35L56_SHARED); 989 990 struct regmap_config cs35l56_regmap_i2c = { 991 .reg_bits = 32, 992 .val_bits = 32, 993 .reg_stride = 4, 994 .reg_format_endian = REGMAP_ENDIAN_BIG, 995 .val_format_endian = REGMAP_ENDIAN_BIG, 996 .max_register = CS35L56_DSP1_PMEM_5114, 997 .reg_defaults = cs35l56_reg_defaults, 998 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 999 .volatile_reg = cs35l56_volatile_reg, 1000 .readable_reg = cs35l56_readable_reg, 1001 .precious_reg = cs35l56_precious_reg, 1002 .cache_type = REGCACHE_MAPLE, 1003 }; 1004 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, SND_SOC_CS35L56_SHARED); 1005 1006 struct regmap_config cs35l56_regmap_spi = { 1007 .reg_bits = 32, 1008 .val_bits = 32, 1009 .pad_bits = 16, 1010 .reg_stride = 4, 1011 .reg_format_endian = REGMAP_ENDIAN_BIG, 1012 .val_format_endian = REGMAP_ENDIAN_BIG, 1013 .max_register = CS35L56_DSP1_PMEM_5114, 1014 .reg_defaults = cs35l56_reg_defaults, 1015 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1016 .volatile_reg = cs35l56_volatile_reg, 1017 .readable_reg = cs35l56_readable_reg, 1018 .precious_reg = cs35l56_precious_reg, 1019 .cache_type = REGCACHE_MAPLE, 1020 }; 1021 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, SND_SOC_CS35L56_SHARED); 1022 1023 struct regmap_config cs35l56_regmap_sdw = { 1024 .reg_bits = 32, 1025 .val_bits = 32, 1026 .reg_stride = 4, 1027 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1028 .val_format_endian = REGMAP_ENDIAN_BIG, 1029 .max_register = CS35L56_DSP1_PMEM_5114, 1030 .reg_defaults = cs35l56_reg_defaults, 1031 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1032 .volatile_reg = cs35l56_volatile_reg, 1033 .readable_reg = cs35l56_readable_reg, 1034 .precious_reg = cs35l56_precious_reg, 1035 .cache_type = REGCACHE_MAPLE, 1036 }; 1037 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, SND_SOC_CS35L56_SHARED); 1038 1039 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1040 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1041 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1042 MODULE_LICENSE("GPL"); 1043 MODULE_IMPORT_NS(SND_SOC_CS_AMP_LIB); 1044