1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Components shared between ASoC and HDA CS35L56 drivers 4 // 5 // Copyright (C) 2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <kunit/static_stub.h> 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/cleanup.h> 12 #include <linux/debugfs.h> 13 #include <linux/firmware/cirrus/wmfw.h> 14 #include <linux/fs.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/kstrtox.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 #include <linux/stddef.h> 22 #include <linux/string.h> 23 #include <linux/string_choices.h> 24 #include <linux/types.h> 25 #include <sound/cs-amp-lib.h> 26 27 #include "cs35l56.h" 28 29 static const struct reg_sequence cs35l56_asp_patch[] = { 30 /* 31 * Firmware can change these to non-defaults to satisfy SDCA. 32 * Ensure that they are at known defaults. 33 */ 34 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 35 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 36 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 37 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 38 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 39 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 40 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 41 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 42 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 43 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 44 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 45 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 46 }; 47 48 int cs35l56_set_asp_patch(struct cs35l56_base *cs35l56_base) 49 { 50 return regmap_register_patch(cs35l56_base->regmap, cs35l56_asp_patch, 51 ARRAY_SIZE(cs35l56_asp_patch)); 52 } 53 EXPORT_SYMBOL_NS_GPL(cs35l56_set_asp_patch, "SND_SOC_CS35L56_SHARED"); 54 55 static const struct reg_sequence cs35l56_patch[] = { 56 /* 57 * Firmware can change these to non-defaults to satisfy SDCA. 58 * Ensure that they are at known defaults. 59 */ 60 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 61 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 62 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 63 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 64 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 65 }; 66 67 static const struct reg_sequence cs35l56_patch_fw[] = { 68 /* These are not reset by a soft-reset, so patch to defaults. */ 69 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 70 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 71 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 72 }; 73 74 static const struct reg_sequence cs35l63_patch_fw[] = { 75 /* These are not reset by a soft-reset, so patch to defaults. */ 76 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 77 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 78 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 79 }; 80 81 int cs35l56_set_patch(struct cs35l56_base *cs35l56_base) 82 { 83 int ret; 84 85 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch, 86 ARRAY_SIZE(cs35l56_patch)); 87 if (ret) 88 return ret; 89 90 91 switch (cs35l56_base->type) { 92 case 0x54: 93 case 0x56: 94 case 0x57: 95 ret = regmap_register_patch(cs35l56_base->regmap, cs35l56_patch_fw, 96 ARRAY_SIZE(cs35l56_patch_fw)); 97 break; 98 case 0x63: 99 case 0x62: 100 ret = regmap_register_patch(cs35l56_base->regmap, cs35l63_patch_fw, 101 ARRAY_SIZE(cs35l63_patch_fw)); 102 break; 103 default: 104 break; 105 } 106 107 return ret; 108 } 109 EXPORT_SYMBOL_NS_GPL(cs35l56_set_patch, "SND_SOC_CS35L56_SHARED"); 110 111 static const struct reg_default cs35l56_reg_defaults[] = { 112 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 113 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 114 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 115 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 116 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 117 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 118 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 119 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 120 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 121 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 122 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 123 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 124 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 125 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 126 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 127 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 128 { CS35L56_IRQ1_MASK_1, 0x83ffffff }, 129 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 130 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 131 { CS35L56_IRQ1_MASK_8, 0xfc000fff }, 132 { CS35L56_IRQ1_MASK_18, 0x1f7df0ff }, 133 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 134 { CS35L56_MAIN_RENDER_USER_MUTE, 0x00000000 }, 135 { CS35L56_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 136 { CS35L56_MAIN_POSTURE_NUMBER, 0x00000000 }, 137 }; 138 139 static const struct reg_default cs35l63_reg_defaults[] = { 140 { CS35L56_ASP1_ENABLES1, 0x00000000 }, 141 { CS35L56_ASP1_CONTROL1, 0x00000028 }, 142 { CS35L56_ASP1_CONTROL2, 0x18180200 }, 143 { CS35L56_ASP1_CONTROL3, 0x00000002 }, 144 { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 }, 145 { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 }, 146 { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 }, 147 { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 }, 148 { CS35L56_ASP1TX1_INPUT, 0x00000000 }, 149 { CS35L56_ASP1TX2_INPUT, 0x00000000 }, 150 { CS35L56_ASP1TX3_INPUT, 0x00000000 }, 151 { CS35L56_ASP1TX4_INPUT, 0x00000000 }, 152 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 }, 153 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 }, 154 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 }, 155 { CS35L56_SWIRE_DP3_CH4_INPUT, 0x00000028 }, 156 { CS35L56_IRQ1_MASK_1, 0x8003ffff }, 157 { CS35L56_IRQ1_MASK_2, 0xffff7fff }, 158 { CS35L56_IRQ1_MASK_4, 0xe0ffffff }, 159 { CS35L56_IRQ1_MASK_8, 0x8c000fff }, 160 { CS35L56_IRQ1_MASK_18, 0x0760f000 }, 161 { CS35L56_IRQ1_MASK_20, 0x15c00000 }, 162 { CS35L63_MAIN_RENDER_USER_MUTE, 0x00000000 }, 163 { CS35L63_MAIN_RENDER_USER_VOLUME, 0x00000000 }, 164 { CS35L63_MAIN_POSTURE_NUMBER, 0x00000000 }, 165 }; 166 167 static bool cs35l56_is_dsp_memory(unsigned int reg) 168 { 169 switch (reg) { 170 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 171 case CS35L56_DSP1_XMEM_UNPACKED32_0 ... CS35L56_DSP1_XMEM_UNPACKED32_4095: 172 case CS35L56_DSP1_XMEM_UNPACKED24_0 ... CS35L56_DSP1_XMEM_UNPACKED24_8191: 173 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 174 case CS35L56_DSP1_YMEM_UNPACKED32_0 ... CS35L56_DSP1_YMEM_UNPACKED32_3070: 175 case CS35L56_DSP1_YMEM_UNPACKED24_0 ... CS35L56_DSP1_YMEM_UNPACKED24_6141: 176 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static bool cs35l56_readable_reg(struct device *dev, unsigned int reg) 184 { 185 switch (reg) { 186 case CS35L56_DEVID: 187 case CS35L56_REVID: 188 case CS35L56_RELID: 189 case CS35L56_OTPID: 190 case CS35L56_SFT_RESET: 191 case CS35L56_GLOBAL_ENABLES: 192 case CS35L56_BLOCK_ENABLES: 193 case CS35L56_BLOCK_ENABLES2: 194 case CS35L56_REFCLK_INPUT: 195 case CS35L56_GLOBAL_SAMPLE_RATE: 196 case CS35L56_OTP_MEM_53: 197 case CS35L56_OTP_MEM_54: 198 case CS35L56_OTP_MEM_55: 199 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 200 case CS35L56_UPDATE_REGS: 201 case CS35L56_ASP1_ENABLES1: 202 case CS35L56_ASP1_CONTROL1: 203 case CS35L56_ASP1_CONTROL2: 204 case CS35L56_ASP1_CONTROL3: 205 case CS35L56_ASP1_FRAME_CONTROL1: 206 case CS35L56_ASP1_FRAME_CONTROL5: 207 case CS35L56_ASP1_DATA_CONTROL1: 208 case CS35L56_ASP1_DATA_CONTROL5: 209 case CS35L56_DACPCM1_INPUT: 210 case CS35L56_DACPCM2_INPUT: 211 case CS35L56_ASP1TX1_INPUT: 212 case CS35L56_ASP1TX2_INPUT: 213 case CS35L56_ASP1TX3_INPUT: 214 case CS35L56_ASP1TX4_INPUT: 215 case CS35L56_DSP1RX1_INPUT: 216 case CS35L56_DSP1RX2_INPUT: 217 case CS35L56_SWIRE_DP3_CH1_INPUT: 218 case CS35L56_SWIRE_DP3_CH2_INPUT: 219 case CS35L56_SWIRE_DP3_CH3_INPUT: 220 case CS35L56_SWIRE_DP3_CH4_INPUT: 221 case CS35L56_IRQ1_CFG: 222 case CS35L56_IRQ1_STATUS: 223 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 224 case CS35L56_IRQ1_EINT_18: 225 case CS35L56_IRQ1_EINT_20: 226 case CS35L56_IRQ1_MASK_1: 227 case CS35L56_IRQ1_MASK_2: 228 case CS35L56_IRQ1_MASK_4: 229 case CS35L56_IRQ1_MASK_8: 230 case CS35L56_IRQ1_MASK_18: 231 case CS35L56_IRQ1_MASK_20: 232 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 233 case CS35L56_MIXER_NGATE_CH1_CFG: 234 case CS35L56_MIXER_NGATE_CH2_CFG: 235 case CS35L56_DSP_VIRTUAL1_MBOX_1: 236 case CS35L56_DSP_VIRTUAL1_MBOX_2: 237 case CS35L56_DSP_VIRTUAL1_MBOX_3: 238 case CS35L56_DSP_VIRTUAL1_MBOX_4: 239 case CS35L56_DSP_VIRTUAL1_MBOX_5: 240 case CS35L56_DSP_VIRTUAL1_MBOX_6: 241 case CS35L56_DSP_VIRTUAL1_MBOX_7: 242 case CS35L56_DSP_VIRTUAL1_MBOX_8: 243 case CS35L56_DIE_STS1: 244 case CS35L56_DIE_STS2: 245 case CS35L56_DSP_RESTRICT_STS1: 246 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 247 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 248 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 249 case CS35L56_DSP1_SCRATCH1: 250 case CS35L56_DSP1_SCRATCH2: 251 case CS35L56_DSP1_SCRATCH3: 252 case CS35L56_DSP1_SCRATCH4: 253 return true; 254 default: 255 return cs35l56_is_dsp_memory(reg); 256 } 257 } 258 259 static bool cs35l56_precious_reg(struct device *dev, unsigned int reg) 260 { 261 switch (reg) { 262 case CS35L56_DSP1_XMEM_PACKED_0 ... CS35L56_DSP1_XMEM_PACKED_6143: 263 case CS35L56_DSP1_YMEM_PACKED_0 ... CS35L56_DSP1_YMEM_PACKED_4604: 264 case CS35L56_DSP1_PMEM_0 ... CS35L56_DSP1_PMEM_5114: 265 return true; 266 default: 267 return false; 268 } 269 } 270 271 static bool cs35l56_common_volatile_reg(unsigned int reg) 272 { 273 switch (reg) { 274 case CS35L56_DEVID: 275 case CS35L56_REVID: 276 case CS35L56_RELID: 277 case CS35L56_OTPID: 278 case CS35L56_SFT_RESET: 279 case CS35L56_GLOBAL_ENABLES: /* owned by firmware */ 280 case CS35L56_BLOCK_ENABLES: /* owned by firmware */ 281 case CS35L56_BLOCK_ENABLES2: /* owned by firmware */ 282 case CS35L56_OTP_MEM_53: 283 case CS35L56_OTP_MEM_54: 284 case CS35L56_OTP_MEM_55: 285 case CS35L56_SYNC_GPIO1_CFG ... CS35L56_ASP2_DIO_GPIO13_CFG: 286 case CS35L56_UPDATE_REGS: 287 case CS35L56_REFCLK_INPUT: /* owned by firmware */ 288 case CS35L56_GLOBAL_SAMPLE_RATE: /* owned by firmware */ 289 case CS35L56_DACPCM1_INPUT: /* owned by firmware */ 290 case CS35L56_DACPCM2_INPUT: /* owned by firmware */ 291 case CS35L56_DSP1RX1_INPUT: /* owned by firmware */ 292 case CS35L56_DSP1RX2_INPUT: /* owned by firmware */ 293 case CS35L56_IRQ1_STATUS: 294 case CS35L56_IRQ1_EINT_1 ... CS35L56_IRQ1_EINT_8: 295 case CS35L56_IRQ1_EINT_18: 296 case CS35L56_IRQ1_EINT_20: 297 case CS35L56_GPIO_STATUS1 ... CS35L56_GPIO13_CTRL1: 298 case CS35L56_MIXER_NGATE_CH1_CFG: 299 case CS35L56_MIXER_NGATE_CH2_CFG: 300 case CS35L56_DSP_VIRTUAL1_MBOX_1: 301 case CS35L56_DSP_VIRTUAL1_MBOX_2: 302 case CS35L56_DSP_VIRTUAL1_MBOX_3: 303 case CS35L56_DSP_VIRTUAL1_MBOX_4: 304 case CS35L56_DSP_VIRTUAL1_MBOX_5: 305 case CS35L56_DSP_VIRTUAL1_MBOX_6: 306 case CS35L56_DSP_VIRTUAL1_MBOX_7: 307 case CS35L56_DSP_VIRTUAL1_MBOX_8: 308 case CS35L56_DSP_RESTRICT_STS1: 309 case CS35L56_DSP1_SYS_INFO_ID ... CS35L56_DSP1_SYS_INFO_END: 310 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_0: 311 case CS35L56_DSP1_AHBM_WINDOW_DEBUG_1: 312 case CS35L56_DSP1_SCRATCH1: 313 case CS35L56_DSP1_SCRATCH2: 314 case CS35L56_DSP1_SCRATCH3: 315 case CS35L56_DSP1_SCRATCH4: 316 return true; 317 default: 318 return cs35l56_is_dsp_memory(reg); 319 } 320 } 321 322 static bool cs35l56_volatile_reg(struct device *dev, unsigned int reg) 323 { 324 switch (reg) { 325 case CS35L56_MAIN_RENDER_USER_MUTE: 326 case CS35L56_MAIN_RENDER_USER_VOLUME: 327 case CS35L56_MAIN_POSTURE_NUMBER: 328 return false; 329 default: 330 return cs35l56_common_volatile_reg(reg); 331 } 332 } 333 334 static bool cs35l63_volatile_reg(struct device *dev, unsigned int reg) 335 { 336 switch (reg) { 337 case CS35L63_MAIN_RENDER_USER_MUTE: 338 case CS35L63_MAIN_RENDER_USER_VOLUME: 339 case CS35L63_MAIN_POSTURE_NUMBER: 340 return false; 341 default: 342 return cs35l56_common_volatile_reg(reg); 343 } 344 } 345 346 static const struct cs35l56_fw_reg cs35l56_fw_reg = { 347 .fw_ver = CS35L56_DSP1_FW_VER, 348 .halo_state = CS35L56_DSP1_HALO_STATE, 349 .pm_cur_stat = CS35L56_DSP1_PM_CUR_STATE, 350 .prot_sts = CS35L56_PROTECTION_STATUS, 351 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 352 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 353 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 354 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 355 }; 356 357 static const struct cs35l56_fw_reg cs35l56_b2_fw_reg = { 358 .fw_ver = CS35L56_DSP1_FW_VER, 359 .halo_state = CS35L56_B2_DSP1_HALO_STATE, 360 .pm_cur_stat = CS35L56_B2_DSP1_PM_CUR_STATE, 361 .prot_sts = CS35L56_PROTECTION_STATUS, 362 .transducer_actual_ps = CS35L56_TRANSDUCER_ACTUAL_PS, 363 .user_mute = CS35L56_MAIN_RENDER_USER_MUTE, 364 .user_volume = CS35L56_MAIN_RENDER_USER_VOLUME, 365 .posture_number = CS35L56_MAIN_POSTURE_NUMBER, 366 }; 367 368 static const struct cs35l56_fw_reg cs35l63_fw_reg = { 369 .fw_ver = CS35L63_DSP1_FW_VER, 370 .halo_state = CS35L63_DSP1_HALO_STATE, 371 .pm_cur_stat = CS35L63_DSP1_PM_CUR_STATE, 372 .prot_sts = CS35L63_PROTECTION_STATUS, 373 .transducer_actual_ps = CS35L63_TRANSDUCER_ACTUAL_PS, 374 .user_mute = CS35L63_MAIN_RENDER_USER_MUTE, 375 .user_volume = CS35L63_MAIN_RENDER_USER_VOLUME, 376 .posture_number = CS35L63_MAIN_POSTURE_NUMBER, 377 }; 378 379 static void cs35l56_set_fw_reg_table(struct cs35l56_base *cs35l56_base) 380 { 381 switch (cs35l56_base->type) { 382 default: 383 switch (cs35l56_base->rev) { 384 case 0xb0: 385 cs35l56_base->fw_reg = &cs35l56_fw_reg; 386 break; 387 default: 388 cs35l56_base->fw_reg = &cs35l56_b2_fw_reg; 389 break; 390 } 391 break; 392 case 0x63: 393 case 0x62: 394 cs35l56_base->fw_reg = &cs35l63_fw_reg; 395 break; 396 } 397 } 398 399 int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command) 400 { 401 unsigned int val; 402 int ret; 403 404 regmap_write(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, command); 405 ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP_VIRTUAL1_MBOX_1, 406 val, (val == 0), 407 CS35L56_MBOX_POLL_US, CS35L56_MBOX_TIMEOUT_US); 408 if (ret) { 409 dev_warn(cs35l56_base->dev, "MBOX command %#x failed: %d\n", command, ret); 410 return ret; 411 } 412 413 return 0; 414 } 415 EXPORT_SYMBOL_NS_GPL(cs35l56_mbox_send, "SND_SOC_CS35L56_SHARED"); 416 417 int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base) 418 { 419 int ret; 420 unsigned int val; 421 422 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN); 423 if (ret) 424 return ret; 425 426 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 427 cs35l56_base->fw_reg->pm_cur_stat, 428 val, (val == CS35L56_HALO_STATE_SHUTDOWN), 429 CS35L56_HALO_STATE_POLL_US, 430 CS35L56_HALO_STATE_TIMEOUT_US); 431 if (ret < 0) 432 dev_err(cs35l56_base->dev, "Failed to poll PM_CUR_STATE to 1 is %d (ret %d)\n", 433 val, ret); 434 return ret; 435 } 436 EXPORT_SYMBOL_NS_GPL(cs35l56_firmware_shutdown, "SND_SOC_CS35L56_SHARED"); 437 438 int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base) 439 { 440 unsigned int val = 0; 441 int read_ret, poll_ret; 442 443 /* 444 * The regmap must remain in cache-only until the chip has 445 * booted, so use a bypassed read of the status register. 446 */ 447 poll_ret = read_poll_timeout(regmap_read_bypassed, read_ret, 448 (val < 0xFFFF) && (val >= CS35L56_HALO_STATE_BOOT_DONE), 449 CS35L56_HALO_STATE_POLL_US, 450 CS35L56_HALO_STATE_TIMEOUT_US, 451 false, 452 cs35l56_base->regmap, 453 cs35l56_base->fw_reg->halo_state, 454 &val); 455 456 if (poll_ret) { 457 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n", 458 read_ret, val); 459 return -EIO; 460 } 461 462 return 0; 463 } 464 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_for_firmware_boot, "SND_SOC_CS35L56_SHARED"); 465 466 void cs35l56_wait_control_port_ready(void) 467 { 468 /* Wait for control port to be ready (datasheet tIRS). */ 469 usleep_range(CS35L56_CONTROL_PORT_READY_US, 2 * CS35L56_CONTROL_PORT_READY_US); 470 } 471 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_control_port_ready, "SND_SOC_CS35L56_SHARED"); 472 473 void cs35l56_wait_min_reset_pulse(void) 474 { 475 /* Satisfy minimum reset pulse width spec */ 476 usleep_range(CS35L56_RESET_PULSE_MIN_US, 2 * CS35L56_RESET_PULSE_MIN_US); 477 } 478 EXPORT_SYMBOL_NS_GPL(cs35l56_wait_min_reset_pulse, "SND_SOC_CS35L56_SHARED"); 479 480 static const struct { 481 u32 addr; 482 u32 value; 483 } cs35l56_spi_system_reset_stages[] = { 484 { .addr = CS35L56_DSP_VIRTUAL1_MBOX_1, .value = CS35L56_MBOX_CMD_SYSTEM_RESET }, 485 /* The next write is necessary to delimit the soft reset */ 486 { .addr = CS35L56_DSP_MBOX_1_RAW, .value = CS35L56_MBOX_CMD_PING }, 487 }; 488 489 static void cs35l56_spi_issue_bus_locked_reset(struct cs35l56_base *cs35l56_base, 490 struct spi_device *spi) 491 { 492 struct cs35l56_spi_payload *buf = cs35l56_base->spi_payload_buf; 493 struct spi_transfer t = { 494 .tx_buf = buf, 495 .len = sizeof(*buf), 496 }; 497 struct spi_message m; 498 int i, ret; 499 500 for (i = 0; i < ARRAY_SIZE(cs35l56_spi_system_reset_stages); i++) { 501 buf->addr = cpu_to_be32(cs35l56_spi_system_reset_stages[i].addr); 502 buf->value = cpu_to_be32(cs35l56_spi_system_reset_stages[i].value); 503 spi_message_init_with_transfers(&m, &t, 1); 504 ret = spi_sync_locked(spi, &m); 505 if (ret) 506 dev_warn(cs35l56_base->dev, "spi_sync failed: %d\n", ret); 507 508 usleep_range(CS35L56_SPI_RESET_TO_PORT_READY_US, 509 2 * CS35L56_SPI_RESET_TO_PORT_READY_US); 510 } 511 } 512 513 static void cs35l56_spi_system_reset(struct cs35l56_base *cs35l56_base) 514 { 515 struct spi_device *spi = to_spi_device(cs35l56_base->dev); 516 unsigned int val; 517 int read_ret, ret; 518 519 /* 520 * There must not be any other SPI bus activity while the amp is 521 * soft-resetting. 522 */ 523 ret = spi_bus_lock(spi->controller); 524 if (ret) { 525 dev_warn(cs35l56_base->dev, "spi_bus_lock failed: %d\n", ret); 526 return; 527 } 528 529 cs35l56_spi_issue_bus_locked_reset(cs35l56_base, spi); 530 spi_bus_unlock(spi->controller); 531 532 /* 533 * Check firmware boot by testing for a response in MBOX_2. 534 * HALO_STATE cannot be trusted yet because the reset sequence 535 * can leave it with stale state. But MBOX is reset. 536 * The regmap must remain in cache-only until the chip has 537 * booted, so use a bypassed read. 538 */ 539 val = 0; 540 ret = read_poll_timeout(regmap_read_bypassed, read_ret, 541 (val > 0) && (val < 0xffffffff), 542 CS35L56_HALO_STATE_POLL_US, 543 CS35L56_HALO_STATE_TIMEOUT_US, 544 false, 545 cs35l56_base->regmap, 546 CS35L56_DSP_VIRTUAL1_MBOX_2, 547 &val); 548 if (ret) { 549 dev_err(cs35l56_base->dev, "SPI reboot timed out(%d): MBOX2=%#x\n", 550 read_ret, val); 551 } 552 } 553 554 static const struct reg_sequence cs35l56_system_reset_seq[] = { 555 REG_SEQ0(CS35L56_DSP1_HALO_STATE, 0), 556 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 557 }; 558 559 static const struct reg_sequence cs35l56_b2_system_reset_seq[] = { 560 REG_SEQ0(CS35L56_B2_DSP1_HALO_STATE, 0), 561 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 562 }; 563 564 static const struct reg_sequence cs35l63_system_reset_seq[] = { 565 REG_SEQ0(CS35L63_DSP1_HALO_STATE, 0), 566 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_SYSTEM_RESET), 567 }; 568 569 void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire) 570 { 571 /* 572 * Must enter cache-only first so there can't be any more register 573 * accesses other than the controlled system reset sequence below. 574 */ 575 regcache_cache_only(cs35l56_base->regmap, true); 576 577 if (cs35l56_is_spi(cs35l56_base)) { 578 cs35l56_spi_system_reset(cs35l56_base); 579 return; 580 } 581 582 switch (cs35l56_base->type) { 583 case 0x54: 584 case 0x56: 585 case 0x57: 586 switch (cs35l56_base->rev) { 587 case 0xb0: 588 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 589 cs35l56_system_reset_seq, 590 ARRAY_SIZE(cs35l56_system_reset_seq)); 591 break; 592 default: 593 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 594 cs35l56_b2_system_reset_seq, 595 ARRAY_SIZE(cs35l56_b2_system_reset_seq)); 596 break; 597 } 598 break; 599 case 0x63: 600 case 0x62: 601 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 602 cs35l63_system_reset_seq, 603 ARRAY_SIZE(cs35l63_system_reset_seq)); 604 break; 605 default: 606 break; 607 } 608 609 /* On SoundWire the registers won't be accessible until it re-enumerates. */ 610 if (is_soundwire) 611 return; 612 613 cs35l56_wait_control_port_ready(); 614 615 /* Leave in cache-only. This will be revoked when the chip has rebooted. */ 616 } 617 EXPORT_SYMBOL_NS_GPL(cs35l56_system_reset, "SND_SOC_CS35L56_SHARED"); 618 619 int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq) 620 { 621 int ret; 622 623 if (irq < 1) 624 return 0; 625 626 ret = devm_request_threaded_irq(cs35l56_base->dev, irq, NULL, cs35l56_irq, 627 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW, 628 "cs35l56", cs35l56_base); 629 if (!ret) 630 cs35l56_base->irq = irq; 631 else 632 dev_err(cs35l56_base->dev, "Failed to get IRQ: %d\n", ret); 633 634 return ret; 635 } 636 EXPORT_SYMBOL_NS_GPL(cs35l56_irq_request, "SND_SOC_CS35L56_SHARED"); 637 638 irqreturn_t cs35l56_irq(int irq, void *data) 639 { 640 struct cs35l56_base *cs35l56_base = data; 641 unsigned int status1 = 0, status8 = 0, status20 = 0; 642 unsigned int mask1, mask8, mask20; 643 unsigned int val; 644 int rv; 645 646 if (!cs35l56_base->init_done) 647 return IRQ_NONE; 648 649 guard(mutex)(&cs35l56_base->irq_lock); 650 651 PM_RUNTIME_ACQUIRE_IF_ENABLED(cs35l56_base->dev, pm); 652 rv = PM_RUNTIME_ACQUIRE_ERR(&pm); 653 if (rv < 0) { 654 dev_err(cs35l56_base->dev, "irq: failed to get pm_runtime: %d\n", rv); 655 return IRQ_NONE; 656 } 657 658 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 659 if ((val & CS35L56_IRQ1_STS_MASK) == 0) { 660 dev_dbg(cs35l56_base->dev, "Spurious IRQ: no pending interrupt\n"); 661 return IRQ_NONE; 662 } 663 664 /* Ack interrupts */ 665 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, &status1); 666 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, &mask1); 667 status1 &= ~mask1; 668 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_1, status1); 669 670 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, &status8); 671 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, &mask8); 672 status8 &= ~mask8; 673 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_8, status8); 674 675 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_20, &status20); 676 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, &mask20); 677 status20 &= ~mask20; 678 /* We don't want EINT20 but they default to unmasked: force mask */ 679 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 680 681 dev_dbg(cs35l56_base->dev, "%s: %#x %#x\n", __func__, status1, status8); 682 683 /* Check to see if unmasked bits are active */ 684 if (!status1 && !status8 && !status20) 685 return IRQ_NONE; 686 687 if (status1 & CS35L56_AMP_SHORT_ERR_EINT1_MASK) 688 dev_crit(cs35l56_base->dev, "Amp short error\n"); 689 690 if (status8 & CS35L56_TEMP_ERR_EINT1_MASK) 691 dev_crit(cs35l56_base->dev, "Overtemp error\n"); 692 693 return IRQ_HANDLED; 694 } 695 EXPORT_SYMBOL_NS_GPL(cs35l56_irq, "SND_SOC_CS35L56_SHARED"); 696 697 int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base) 698 { 699 unsigned int val; 700 int ret; 701 702 /* 703 * In secure mode FIRMWARE_MISSING is cleared by the BIOS loader so 704 * can't be used here to test for memory retention. 705 * Assume that tuning must be re-loaded. 706 */ 707 if (cs35l56_base->secured) 708 return true; 709 710 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 711 if (ret) { 712 dev_err(cs35l56_base->dev, "Failed to runtime_get: %d\n", ret); 713 return ret; 714 } 715 716 ret = regmap_read(cs35l56_base->regmap, 717 cs35l56_base->fw_reg->prot_sts, 718 &val); 719 if (ret) 720 dev_err(cs35l56_base->dev, "Failed to read PROTECTION_STATUS: %d\n", ret); 721 else 722 ret = !!(val & CS35L56_FIRMWARE_MISSING); 723 724 pm_runtime_put_autosuspend(cs35l56_base->dev); 725 726 return ret; 727 } 728 EXPORT_SYMBOL_NS_GPL(cs35l56_is_fw_reload_needed, "SND_SOC_CS35L56_SHARED"); 729 730 static const struct reg_sequence cs35l56_hibernate_seq[] = { 731 /* This must be the last register access */ 732 REG_SEQ0(CS35L56_DSP_VIRTUAL1_MBOX_1, CS35L56_MBOX_CMD_ALLOW_AUTO_HIBERNATE), 733 }; 734 735 static void cs35l56_issue_wake_event(struct cs35l56_base *cs35l56_base) 736 { 737 unsigned int val; 738 739 /* 740 * Dummy transactions to trigger I2C/SPI auto-wake. Issue two 741 * transactions to meet the minimum required time from the rising edge 742 * to the last falling edge of wake. 743 * 744 * It uses bypassed read because we must wake the chip before 745 * disabling regmap cache-only. 746 */ 747 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 748 749 usleep_range(CS35L56_WAKE_HOLD_TIME_US, 2 * CS35L56_WAKE_HOLD_TIME_US); 750 751 regmap_read_bypassed(cs35l56_base->regmap, CS35L56_IRQ1_STATUS, &val); 752 753 cs35l56_wait_control_port_ready(); 754 } 755 756 static int cs35l56_wait_for_ps3(struct cs35l56_base *cs35l56_base) 757 { 758 unsigned int val; 759 int ret; 760 761 ret = regmap_read_poll_timeout(cs35l56_base->regmap, 762 cs35l56_base->fw_reg->transducer_actual_ps, 763 val, (val >= CS35L56_PS3), 764 CS35L56_PS3_POLL_US, 765 CS35L56_PS3_TIMEOUT_US); 766 if (ret) 767 dev_warn(cs35l56_base->dev, "PS3 wait failed: %d\n", ret); 768 769 return ret; 770 } 771 772 int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base) 773 { 774 if (!cs35l56_base->init_done) 775 return 0; 776 777 /* Firmware must have entered a power-save state */ 778 cs35l56_wait_for_ps3(cs35l56_base); 779 780 /* Clear BOOT_DONE so it can be used to detect a reboot */ 781 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, CS35L56_OTP_BOOT_DONE_MASK); 782 783 if (!cs35l56_base->can_hibernate) { 784 regcache_cache_only(cs35l56_base->regmap, true); 785 dev_dbg(cs35l56_base->dev, "Suspended: no hibernate"); 786 787 return 0; 788 } 789 790 /* 791 * Must enter cache-only first so there can't be any more register 792 * accesses other than the controlled hibernate sequence below. 793 */ 794 regcache_cache_only(cs35l56_base->regmap, true); 795 796 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 797 cs35l56_hibernate_seq, 798 ARRAY_SIZE(cs35l56_hibernate_seq)); 799 800 dev_dbg(cs35l56_base->dev, "Suspended: hibernate"); 801 802 return 0; 803 } 804 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_suspend_common, "SND_SOC_CS35L56_SHARED"); 805 806 int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire) 807 { 808 unsigned int val; 809 int ret; 810 811 if (!cs35l56_base->init_done) 812 return 0; 813 814 /* Hibernate wake must be done before releasing cache-only */ 815 if (cs35l56_base->can_hibernate && !is_soundwire) 816 cs35l56_issue_wake_event(cs35l56_base); 817 818 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 819 if (ret) { 820 dev_err(cs35l56_base->dev, "Hibernate wake failed: %d\n", ret); 821 goto err; 822 } 823 824 regcache_cache_only(cs35l56_base->regmap, false); 825 826 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_PREVENT_AUTO_HIBERNATE); 827 if (ret) 828 goto err; 829 830 /* BOOT_DONE will be 1 if the amp reset */ 831 regmap_read(cs35l56_base->regmap, CS35L56_IRQ1_EINT_4, &val); 832 if (val & CS35L56_OTP_BOOT_DONE_MASK) { 833 dev_dbg(cs35l56_base->dev, "Registers reset in suspend\n"); 834 regcache_mark_dirty(cs35l56_base->regmap); 835 } 836 837 regcache_sync(cs35l56_base->regmap); 838 839 dev_dbg(cs35l56_base->dev, "Resumed"); 840 841 return 0; 842 843 err: 844 regcache_cache_only(cs35l56_base->regmap, true); 845 846 if (cs35l56_base->can_hibernate) { 847 regmap_multi_reg_write_bypassed(cs35l56_base->regmap, 848 cs35l56_hibernate_seq, 849 ARRAY_SIZE(cs35l56_hibernate_seq)); 850 } 851 852 return ret; 853 } 854 EXPORT_SYMBOL_NS_GPL(cs35l56_runtime_resume_common, "SND_SOC_CS35L56_SHARED"); 855 856 static const struct cs_dsp_region cs35l56_dsp1_regions[] = { 857 { .type = WMFW_HALO_PM_PACKED, .base = CS35L56_DSP1_PMEM_0 }, 858 { .type = WMFW_HALO_XM_PACKED, .base = CS35L56_DSP1_XMEM_PACKED_0 }, 859 { .type = WMFW_HALO_YM_PACKED, .base = CS35L56_DSP1_YMEM_PACKED_0 }, 860 { .type = WMFW_ADSP2_XM, .base = CS35L56_DSP1_XMEM_UNPACKED24_0 }, 861 { .type = WMFW_ADSP2_YM, .base = CS35L56_DSP1_YMEM_UNPACKED24_0 }, 862 }; 863 864 void cs35l56_init_cs_dsp(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 865 { 866 cs_dsp->num = 1; 867 cs_dsp->type = WMFW_HALO; 868 cs_dsp->rev = 0; 869 cs_dsp->dev = cs35l56_base->dev; 870 cs_dsp->regmap = cs35l56_base->regmap; 871 cs_dsp->base = CS35L56_DSP1_CORE_BASE; 872 cs_dsp->base_sysinfo = CS35L56_DSP1_SYS_INFO_ID; 873 cs_dsp->mem = cs35l56_dsp1_regions; 874 cs_dsp->num_mems = ARRAY_SIZE(cs35l56_dsp1_regions); 875 cs_dsp->no_core_startstop = true; 876 877 cs35l56_base->dsp = cs_dsp; 878 } 879 EXPORT_SYMBOL_NS_GPL(cs35l56_init_cs_dsp, "SND_SOC_CS35L56_SHARED"); 880 881 struct cs35l56_pte { 882 u8 x; 883 u8 wafer_id; 884 u8 pte[2]; 885 u8 lot[3]; 886 u8 y; 887 u8 unused[3]; 888 u8 dvs; 889 } __packed; 890 static_assert((sizeof(struct cs35l56_pte) % sizeof(u32)) == 0); 891 892 static int cs35l56_read_silicon_uid(struct cs35l56_base *cs35l56_base) 893 { 894 struct cs35l56_pte pte; 895 u64 unique_id; 896 int ret; 897 898 ret = regmap_raw_read(cs35l56_base->regmap, CS35L56_OTP_MEM_53, &pte, sizeof(pte)); 899 if (ret) { 900 dev_err(cs35l56_base->dev, "Failed to read OTP: %d\n", ret); 901 return ret; 902 } 903 904 unique_id = (u32)pte.lot[2] | ((u32)pte.lot[1] << 8) | ((u32)pte.lot[0] << 16); 905 unique_id <<= 32; 906 unique_id |= (u32)pte.x | ((u32)pte.y << 8) | ((u32)pte.wafer_id << 16) | 907 ((u32)pte.dvs << 24); 908 909 cs35l56_base->silicon_uid = unique_id; 910 911 return 0; 912 } 913 914 static int cs35l63_read_silicon_uid(struct cs35l56_base *cs35l56_base) 915 { 916 u32 tmp[2]; 917 u64 unique_id; 918 int ret; 919 920 ret = regmap_bulk_read(cs35l56_base->regmap, CS35L56_DIE_STS1, tmp, ARRAY_SIZE(tmp)); 921 if (ret) { 922 dev_err(cs35l56_base->dev, "Cannot obtain CS35L56_DIE_STS: %d\n", ret); 923 return ret; 924 } 925 926 unique_id = tmp[1]; 927 unique_id <<= 32; 928 unique_id |= tmp[0]; 929 930 cs35l56_base->silicon_uid = unique_id; 931 932 return 0; 933 } 934 935 /* Firmware calibration controls */ 936 const struct cirrus_amp_cal_controls cs35l56_calibration_controls = { 937 .alg_id = 0x9f210, 938 .mem_region = WMFW_ADSP2_YM, 939 .ambient = "CAL_AMBIENT", 940 .calr = "CAL_R", 941 .status = "CAL_STATUS", 942 .checksum = "CAL_CHECKSUM", 943 }; 944 EXPORT_SYMBOL_NS_GPL(cs35l56_calibration_controls, "SND_SOC_CS35L56_SHARED"); 945 946 static const struct cirrus_amp_cal_controls cs35l63_calibration_controls = { 947 .alg_id = 0xbf210, 948 .mem_region = WMFW_ADSP2_YM, 949 .ambient = "CAL_AMBIENT", 950 .calr = "CAL_R", 951 .status = "CAL_STATUS", 952 .checksum = "CAL_CHECKSUM", 953 }; 954 955 int cs35l56_get_calibration(struct cs35l56_base *cs35l56_base) 956 { 957 int ret; 958 959 /* Driver can't apply calibration to a secured part, so skip */ 960 if (cs35l56_base->secured) 961 return 0; 962 963 ret = cs_amp_get_efi_calibration_data(cs35l56_base->dev, 964 cs35l56_base->silicon_uid, 965 cs35l56_base->cal_index, 966 &cs35l56_base->cal_data); 967 968 /* Only return an error status if probe should be aborted */ 969 if ((ret == -ENOENT) || (ret == -EOVERFLOW)) 970 return 0; 971 972 if (ret < 0) 973 return ret; 974 975 cs35l56_base->cal_data_valid = true; 976 977 return 0; 978 } 979 EXPORT_SYMBOL_NS_GPL(cs35l56_get_calibration, "SND_SOC_CS35L56_SHARED"); 980 981 int cs35l56_stash_calibration(struct cs35l56_base *cs35l56_base, 982 const struct cirrus_amp_cal_data *data) 983 { 984 985 /* Ignore if it is empty */ 986 if (!data->calTime[0] && !data->calTime[1]) 987 return -ENODATA; 988 989 if (cs_amp_cal_target_u64(data) != cs35l56_base->silicon_uid) { 990 dev_err(cs35l56_base->dev, "cal_data not for this silicon ID\n"); 991 return -EINVAL; 992 } 993 994 cs35l56_base->cal_data = *data; 995 cs35l56_base->cal_data_valid = true; 996 997 return 0; 998 } 999 EXPORT_SYMBOL_NS_GPL(cs35l56_stash_calibration, "SND_SOC_CS35L56_SHARED"); 1000 1001 static int cs35l56_perform_calibration(struct cs35l56_base *cs35l56_base) 1002 { 1003 const struct cirrus_amp_cal_controls *calibration_controls = 1004 cs35l56_base->calibration_controls; 1005 struct cs_dsp *dsp = cs35l56_base->dsp; 1006 struct cirrus_amp_cal_data cal_data; 1007 struct cs_dsp_coeff_ctl *ctl; 1008 bool ngate_ch1_was_enabled = false; 1009 bool ngate_ch2_was_enabled = false; 1010 int cali_norm_en_alg_id, cali_norm_en_mem; 1011 int ret; 1012 __be32 val; 1013 1014 if (cs35l56_base->silicon_uid == 0) { 1015 dev_err(cs35l56_base->dev, "Cannot calibrate: no silicon UID\n"); 1016 return -ENXIO; 1017 } 1018 1019 switch (cs35l56_base->type) { 1020 case 0x54: 1021 case 0x56: 1022 case 0x57: 1023 if (cs35l56_base->rev < 0xb2) { 1024 cali_norm_en_alg_id = 0x9f22f; 1025 cali_norm_en_mem = WMFW_ADSP2_YM; 1026 } else { 1027 cali_norm_en_alg_id = 0x9f210; 1028 cali_norm_en_mem = WMFW_ADSP2_XM; 1029 } 1030 break; 1031 default: 1032 cali_norm_en_alg_id = 0xbf210; 1033 cali_norm_en_mem = WMFW_ADSP2_XM; 1034 break; 1035 } 1036 1037 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1038 if (ret) 1039 return ret; 1040 1041 ret = cs35l56_wait_for_ps3(cs35l56_base); 1042 if (ret) { 1043 ret = -EBUSY; 1044 goto err_pm_put; 1045 } 1046 1047 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1048 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch1_was_enabled); 1049 regmap_update_bits_check(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1050 CS35L56_AUX_NGATE_CHn_EN, 0, &ngate_ch2_was_enabled); 1051 1052 scoped_guard(mutex, &dsp->pwr_lock) { 1053 ctl = cs_dsp_get_ctl(dsp, 1054 calibration_controls->status, 1055 calibration_controls->mem_region, 1056 calibration_controls->alg_id); 1057 if (!ctl) { 1058 dev_err(cs35l56_base->dev, "Could not get %s control\n", 1059 calibration_controls->status); 1060 ret = -EIO; 1061 goto err; 1062 } 1063 1064 val = cpu_to_be32(0); 1065 ret = cs_dsp_coeff_write_ctrl(cs_dsp_get_ctl(dsp, 1066 "CALI_NORM_EN", 1067 cali_norm_en_mem, 1068 cali_norm_en_alg_id), 1069 0, &val, sizeof(val)); 1070 if (ret < 0) { 1071 dev_err(cs35l56_base->dev, "Could not write %s: %d\n", "CALI_NORM_EN", ret); 1072 ret = -EIO; 1073 goto err; 1074 } 1075 1076 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_AUDIO_CALIBRATION); 1077 if (ret) { 1078 ret = -EIO; 1079 goto err; 1080 } 1081 1082 if (read_poll_timeout(cs_dsp_coeff_read_ctrl, ret, 1083 (val == cpu_to_be32(1)), 1084 CS35L56_CALIBRATION_POLL_US, 1085 CS35L56_CALIBRATION_TIMEOUT_US, 1086 true, 1087 ctl, 0, &val, sizeof(val))) { 1088 dev_err(cs35l56_base->dev, "Calibration timed out (CAL_STATUS: %u)\n", 1089 be32_to_cpu(val)); 1090 switch (be32_to_cpu(val)) { 1091 case CS35L56_CAL_STATUS_OUT_OF_RANGE: 1092 ret = -ERANGE; 1093 goto err; 1094 default: 1095 ret = -ETIMEDOUT; 1096 goto err; 1097 } 1098 } 1099 } 1100 1101 cs35l56_base->cal_data_valid = false; 1102 memset(&cal_data, 0, sizeof(cal_data)); 1103 ret = cs_amp_read_cal_coeffs(dsp, calibration_controls, &cal_data); 1104 if (ret) { 1105 ret = -EIO; 1106 goto err; 1107 } 1108 1109 dev_info(cs35l56_base->dev, "Cal status:%d calR:%d ambient:%d\n", 1110 cal_data.calStatus, cal_data.calR, cal_data.calAmbient); 1111 1112 cal_data.calTarget[0] = (u32)cs35l56_base->silicon_uid; 1113 cal_data.calTarget[1] = (u32)(cs35l56_base->silicon_uid >> 32); 1114 cs35l56_base->cal_data = cal_data; 1115 cs35l56_base->cal_data_valid = true; 1116 1117 ret = 0; 1118 1119 err: 1120 if (ngate_ch1_was_enabled) { 1121 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH1_CFG, 1122 CS35L56_AUX_NGATE_CHn_EN); 1123 } 1124 if (ngate_ch2_was_enabled) { 1125 regmap_set_bits(cs35l56_base->regmap, CS35L56_MIXER_NGATE_CH2_CFG, 1126 CS35L56_AUX_NGATE_CHn_EN); 1127 } 1128 err_pm_put: 1129 pm_runtime_put(cs35l56_base->dev); 1130 1131 return ret; 1132 } 1133 1134 ssize_t cs35l56_calibrate_debugfs_write(struct cs35l56_base *cs35l56_base, 1135 const char __user *from, size_t count, 1136 loff_t *ppos) 1137 { 1138 static const char * const options[] = { "factory", "store_uefi" }; 1139 char buf[11] = { 0 }; 1140 int num_amps, ret; 1141 1142 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1143 return -ENXIO; 1144 1145 if (*ppos) 1146 return -EINVAL; 1147 1148 ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); 1149 if (ret < 0) 1150 return ret; 1151 1152 switch (sysfs_match_string(options, buf)) { 1153 case 0: 1154 ret = cs35l56_perform_calibration(cs35l56_base); 1155 if (ret < 0) 1156 return ret; 1157 break; 1158 case 1: 1159 if (!cs35l56_base->cal_data_valid) 1160 return -ENODATA; 1161 1162 num_amps = cs35l56_base->num_amps; 1163 if (num_amps == 0) 1164 num_amps = -1; 1165 1166 ret = cs_amp_set_efi_calibration_data(cs35l56_base->dev, 1167 cs35l56_base->cal_index, 1168 num_amps, 1169 &cs35l56_base->cal_data); 1170 if (ret < 0) 1171 return ret; 1172 break; 1173 default: 1174 return -EOPNOTSUPP; 1175 } 1176 1177 return count; 1178 } 1179 EXPORT_SYMBOL_NS_GPL(cs35l56_calibrate_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1180 1181 int cs35l56_factory_calibrate(struct cs35l56_base *cs35l56_base) 1182 { 1183 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_PERFORM_CTRL)) 1184 return -ENXIO; 1185 1186 return cs35l56_perform_calibration(cs35l56_base); 1187 } 1188 EXPORT_SYMBOL_NS_GPL(cs35l56_factory_calibrate, "SND_SOC_CS35L56_SHARED"); 1189 1190 ssize_t cs35l56_cal_ambient_debugfs_write(struct cs35l56_base *cs35l56_base, 1191 const char __user *from, size_t count, 1192 loff_t *ppos) 1193 { 1194 unsigned long val; 1195 int ret; 1196 1197 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1198 return -ENXIO; 1199 1200 if (*ppos) 1201 return -EINVAL; 1202 1203 ret = pm_runtime_resume_and_get(cs35l56_base->dev); 1204 if (ret) 1205 return ret; 1206 1207 ret = kstrtoul_from_user(from, count, 10, &val); 1208 if (ret < 0) 1209 goto out; 1210 1211 ret = cs_amp_write_ambient_temp(cs35l56_base->dsp, cs35l56_base->calibration_controls, val); 1212 if (ret) 1213 ret = -EIO; 1214 out: 1215 pm_runtime_put(cs35l56_base->dev); 1216 1217 if (ret < 0) 1218 return ret; 1219 1220 return count; 1221 } 1222 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_ambient_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1223 1224 ssize_t cs35l56_cal_data_debugfs_read(struct cs35l56_base *cs35l56_base, 1225 char __user *to, size_t count, 1226 loff_t *ppos) 1227 { 1228 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1229 return -ENXIO; 1230 1231 if (!cs35l56_base->cal_data_valid) 1232 return 0; 1233 1234 return simple_read_from_buffer(to, count, ppos, &cs35l56_base->cal_data, 1235 sizeof(cs35l56_base->cal_data)); 1236 } 1237 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_read, "SND_SOC_CS35L56_SHARED"); 1238 1239 ssize_t cs35l56_cal_data_debugfs_write(struct cs35l56_base *cs35l56_base, 1240 const char __user *from, size_t count, 1241 loff_t *ppos) 1242 { 1243 struct cirrus_amp_cal_data cal_data; 1244 int ret; 1245 1246 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1247 return -ENXIO; 1248 1249 /* Only allow a full blob to be written */ 1250 if (*ppos || (count != sizeof(cal_data))) 1251 return -EMSGSIZE; 1252 1253 ret = simple_write_to_buffer(&cal_data, sizeof(cal_data), ppos, from, count); 1254 if (ret < 0) 1255 return ret; 1256 1257 ret = cs35l56_stash_calibration(cs35l56_base, &cal_data); 1258 if (ret) 1259 return ret; 1260 1261 return count; 1262 } 1263 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_data_debugfs_write, "SND_SOC_CS35L56_SHARED"); 1264 1265 void cs35l56_create_cal_debugfs(struct cs35l56_base *cs35l56_base, 1266 const struct cs35l56_cal_debugfs_fops *fops) 1267 { 1268 if (!IS_ENABLED(CONFIG_SND_SOC_CS35L56_CAL_DEBUGFS_COMMON)) 1269 return; 1270 1271 cs35l56_base->debugfs = cs_amp_create_debugfs(cs35l56_base->dev); 1272 1273 debugfs_create_file("calibrate", 1274 0200, cs35l56_base->debugfs, cs35l56_base, 1275 &fops->calibrate); 1276 debugfs_create_file("cal_temperature", 1277 0200, cs35l56_base->debugfs, cs35l56_base, 1278 &fops->cal_temperature); 1279 debugfs_create_file("cal_data", 1280 0644, cs35l56_base->debugfs, cs35l56_base, 1281 &fops->cal_data); 1282 } 1283 EXPORT_SYMBOL_NS_GPL(cs35l56_create_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1284 1285 void cs35l56_remove_cal_debugfs(struct cs35l56_base *cs35l56_base) 1286 { 1287 debugfs_remove_recursive(cs35l56_base->debugfs); 1288 cs35l56_base->debugfs = ERR_PTR(-ENOENT); 1289 } 1290 EXPORT_SYMBOL_NS_GPL(cs35l56_remove_cal_debugfs, "SND_SOC_CS35L56_SHARED"); 1291 1292 const char * const cs35l56_cal_set_status_text[] = { 1293 "Unknown", "Default", "Set", 1294 }; 1295 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_text, "SND_SOC_CS35L56_SHARED"); 1296 1297 int cs35l56_cal_set_status_get(struct cs35l56_base *cs35l56_base, 1298 struct snd_ctl_elem_value *uvalue) 1299 { 1300 struct cs_dsp *dsp = cs35l56_base->dsp; 1301 __be32 cal_set_status_be; 1302 int alg_id; 1303 int ret; 1304 1305 switch (cs35l56_base->type) { 1306 case 0x54: 1307 case 0x56: 1308 case 0x57: 1309 alg_id = 0x9f210; 1310 break; 1311 default: 1312 alg_id = 0xbf210; 1313 break; 1314 } 1315 1316 scoped_guard(mutex, &dsp->pwr_lock) { 1317 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(dsp, 1318 "CAL_SET_STATUS", 1319 WMFW_ADSP2_YM, alg_id), 1320 0, &cal_set_status_be, 1321 sizeof(cal_set_status_be)); 1322 } 1323 if (ret) { 1324 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1325 return 0; 1326 } 1327 1328 switch (be32_to_cpu(cal_set_status_be)) { 1329 case CS35L56_CAL_SET_STATUS_DEFAULT: 1330 case CS35L56_CAL_SET_STATUS_SET: 1331 uvalue->value.enumerated.item[0] = be32_to_cpu(cal_set_status_be); 1332 return 0; 1333 default: 1334 uvalue->value.enumerated.item[0] = CS35L56_CAL_SET_STATUS_UNKNOWN; 1335 return 0; 1336 } 1337 } 1338 EXPORT_SYMBOL_NS_GPL(cs35l56_cal_set_status_get, "SND_SOC_CS35L56_SHARED"); 1339 1340 int cs35l56_read_prot_status(struct cs35l56_base *cs35l56_base, 1341 bool *fw_missing, unsigned int *fw_version) 1342 { 1343 unsigned int prot_status; 1344 int ret; 1345 1346 ret = regmap_read(cs35l56_base->regmap, 1347 cs35l56_base->fw_reg->prot_sts, &prot_status); 1348 if (ret) { 1349 dev_err(cs35l56_base->dev, "Get PROTECTION_STATUS failed: %d\n", ret); 1350 return ret; 1351 } 1352 1353 *fw_missing = !!(prot_status & CS35L56_FIRMWARE_MISSING); 1354 1355 ret = regmap_read(cs35l56_base->regmap, 1356 cs35l56_base->fw_reg->fw_ver, fw_version); 1357 if (ret) { 1358 dev_err(cs35l56_base->dev, "Get FW VER failed: %d\n", ret); 1359 return ret; 1360 } 1361 1362 return 0; 1363 } 1364 EXPORT_SYMBOL_NS_GPL(cs35l56_read_prot_status, "SND_SOC_CS35L56_SHARED"); 1365 1366 void cs35l56_warn_if_firmware_missing(struct cs35l56_base *cs35l56_base) 1367 { 1368 unsigned int firmware_version; 1369 bool firmware_missing; 1370 int ret; 1371 1372 ret = cs35l56_read_prot_status(cs35l56_base, &firmware_missing, &firmware_version); 1373 if (ret) 1374 return; 1375 1376 if (!firmware_missing) 1377 return; 1378 1379 dev_warn(cs35l56_base->dev, "FIRMWARE_MISSING\n"); 1380 } 1381 EXPORT_SYMBOL_NS_GPL(cs35l56_warn_if_firmware_missing, "SND_SOC_CS35L56_SHARED"); 1382 1383 void cs35l56_log_tuning(struct cs35l56_base *cs35l56_base, struct cs_dsp *cs_dsp) 1384 { 1385 __be32 pid, sid, tid; 1386 unsigned int alg_id; 1387 int ret; 1388 1389 switch (cs35l56_base->type) { 1390 case 0x54: 1391 case 0x56: 1392 case 0x57: 1393 alg_id = 0x9f212; 1394 break; 1395 default: 1396 alg_id = 0xbf212; 1397 break; 1398 } 1399 1400 scoped_guard(mutex, &cs_dsp->pwr_lock) { 1401 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_PRJCT_ID", 1402 WMFW_ADSP2_XM, alg_id), 1403 0, &pid, sizeof(pid)); 1404 if (!ret) 1405 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_CHNNL_ID", 1406 WMFW_ADSP2_XM, alg_id), 1407 0, &sid, sizeof(sid)); 1408 if (!ret) 1409 ret = cs_dsp_coeff_read_ctrl(cs_dsp_get_ctl(cs_dsp, "AS_SNPSHT_ID", 1410 WMFW_ADSP2_XM, alg_id), 1411 0, &tid, sizeof(tid)); 1412 } 1413 1414 if (ret) 1415 dev_warn(cs35l56_base->dev, "Can't read tuning IDs"); 1416 else 1417 dev_info(cs35l56_base->dev, "Tuning PID: %#x, SID: %#x, TID: %#x\n", 1418 be32_to_cpu(pid), be32_to_cpu(sid), be32_to_cpu(tid)); 1419 } 1420 EXPORT_SYMBOL_NS_GPL(cs35l56_log_tuning, "SND_SOC_CS35L56_SHARED"); 1421 1422 int cs35l56_hw_init(struct cs35l56_base *cs35l56_base) 1423 { 1424 int ret; 1425 unsigned int devid, revid, otpid, secured, fw_ver; 1426 bool fw_missing; 1427 1428 /* 1429 * When the system is not using a reset_gpio ensure the device is 1430 * awake, otherwise the device has just been released from reset and 1431 * the driver must wait for the control port to become usable. 1432 */ 1433 if (!cs35l56_base->reset_gpio) 1434 cs35l56_issue_wake_event(cs35l56_base); 1435 else 1436 cs35l56_wait_control_port_ready(); 1437 1438 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid); 1439 if (ret < 0) { 1440 dev_err(cs35l56_base->dev, "Get Revision ID failed\n"); 1441 return ret; 1442 } 1443 cs35l56_base->rev = revid & (CS35L56_AREVID_MASK | CS35L56_MTLREVID_MASK); 1444 cs35l56_set_fw_reg_table(cs35l56_base); 1445 1446 ret = cs35l56_wait_for_firmware_boot(cs35l56_base); 1447 if (ret) 1448 return ret; 1449 1450 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_DEVID, &devid); 1451 if (ret < 0) { 1452 dev_err(cs35l56_base->dev, "Get Device ID failed\n"); 1453 return ret; 1454 } 1455 devid &= CS35L56_DEVID_MASK; 1456 1457 switch (devid) { 1458 case 0x35A54: 1459 case 0x35A56: 1460 case 0x35A57: 1461 cs35l56_base->calibration_controls = &cs35l56_calibration_controls; 1462 break; 1463 case 0x35A630: 1464 case 0x35A620: 1465 cs35l56_base->calibration_controls = &cs35l63_calibration_controls; 1466 devid = devid >> 4; 1467 break; 1468 default: 1469 dev_err(cs35l56_base->dev, "Unknown device %x\n", devid); 1470 return -ENODEV; 1471 } 1472 1473 cs35l56_base->type = devid & 0xFF; 1474 1475 /* Silicon is now identified and booted so exit cache-only */ 1476 regcache_cache_only(cs35l56_base->regmap, false); 1477 1478 ret = regmap_read(cs35l56_base->regmap, CS35L56_DSP_RESTRICT_STS1, &secured); 1479 if (ret) { 1480 dev_err(cs35l56_base->dev, "Get Secure status failed\n"); 1481 return ret; 1482 } 1483 1484 /* When any bus is restricted treat the device as secured */ 1485 if (secured & CS35L56_RESTRICTED_MASK) 1486 cs35l56_base->secured = true; 1487 1488 ret = regmap_read(cs35l56_base->regmap, CS35L56_OTPID, &otpid); 1489 if (ret < 0) { 1490 dev_err(cs35l56_base->dev, "Get OTP ID failed\n"); 1491 return ret; 1492 } 1493 1494 ret = cs35l56_read_prot_status(cs35l56_base, &fw_missing, &fw_ver); 1495 if (ret) 1496 return ret; 1497 1498 dev_info(cs35l56_base->dev, "Cirrus Logic CS35L%02X%s Rev %02X OTP%d fw:%d.%d.%d (patched=%u)\n", 1499 cs35l56_base->type, cs35l56_base->secured ? "s" : "", cs35l56_base->rev, otpid, 1500 fw_ver >> 16, (fw_ver >> 8) & 0xff, fw_ver & 0xff, !fw_missing); 1501 1502 /* Wake source and *_BLOCKED interrupts default to unmasked, so mask them */ 1503 regmap_write(cs35l56_base->regmap, CS35L56_IRQ1_MASK_20, 0xffffffff); 1504 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_1, 1505 CS35L56_AMP_SHORT_ERR_EINT1_MASK, 1506 0); 1507 regmap_update_bits(cs35l56_base->regmap, CS35L56_IRQ1_MASK_8, 1508 CS35L56_TEMP_ERR_EINT1_MASK, 1509 0); 1510 1511 switch (cs35l56_base->type) { 1512 case 0x54: 1513 case 0x56: 1514 case 0x57: 1515 ret = cs35l56_read_silicon_uid(cs35l56_base); 1516 break; 1517 default: 1518 ret = cs35l63_read_silicon_uid(cs35l56_base); 1519 break; 1520 } 1521 if (ret) 1522 return ret; 1523 1524 dev_dbg(cs35l56_base->dev, "SiliconID = %#llx\n", cs35l56_base->silicon_uid); 1525 1526 return 0; 1527 } 1528 EXPORT_SYMBOL_NS_GPL(cs35l56_hw_init, "SND_SOC_CS35L56_SHARED"); 1529 1530 int cs35l56_get_speaker_id(struct cs35l56_base *cs35l56_base) 1531 { 1532 struct gpio_descs *descs; 1533 u32 speaker_id; 1534 int i, ret; 1535 1536 /* Check for vendor-specific speaker ID method */ 1537 ret = cs_amp_get_vendor_spkid(cs35l56_base->dev); 1538 if (ret >= 0) { 1539 dev_dbg(cs35l56_base->dev, "Vendor Speaker ID = %d\n", ret); 1540 return ret; 1541 } else if (ret != -ENOENT) { 1542 dev_err(cs35l56_base->dev, "Error getting vendor Speaker ID: %d\n", ret); 1543 return ret; 1544 } 1545 1546 /* Attempt to read the speaker type from a device property */ 1547 ret = device_property_read_u32(cs35l56_base->dev, "cirrus,speaker-id", &speaker_id); 1548 if (!ret) { 1549 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1550 return speaker_id; 1551 } 1552 1553 /* Read the speaker type qualifier from the motherboard GPIOs */ 1554 descs = gpiod_get_array_optional(cs35l56_base->dev, "spk-id", GPIOD_IN); 1555 if (!descs) { 1556 return -ENOENT; 1557 } else if (IS_ERR(descs)) { 1558 ret = PTR_ERR(descs); 1559 return dev_err_probe(cs35l56_base->dev, ret, "Failed to get spk-id-gpios\n"); 1560 } 1561 1562 speaker_id = 0; 1563 for (i = 0; i < descs->ndescs; i++) { 1564 ret = gpiod_get_value_cansleep(descs->desc[i]); 1565 if (ret < 0) { 1566 dev_err_probe(cs35l56_base->dev, ret, "Failed to read spk-id[%d]\n", i); 1567 goto err; 1568 } 1569 1570 speaker_id |= (ret << i); 1571 } 1572 1573 dev_dbg(cs35l56_base->dev, "Speaker ID = %d\n", speaker_id); 1574 ret = speaker_id; 1575 err: 1576 gpiod_put_array(descs); 1577 1578 return ret; 1579 } 1580 EXPORT_SYMBOL_NS_GPL(cs35l56_get_speaker_id, "SND_SOC_CS35L56_SHARED"); 1581 1582 int cs35l56_check_and_save_onchip_spkid_gpios(struct cs35l56_base *cs35l56_base, 1583 const u32 *gpios, int num_gpios, 1584 const u32 *pulls, int num_pulls) 1585 { 1586 int max_gpio; 1587 int ret = 0; 1588 int i; 1589 1590 if ((num_gpios > ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)) || 1591 (num_pulls > ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls))) 1592 return -EOVERFLOW; 1593 1594 switch (cs35l56_base->type) { 1595 case 0x54: 1596 case 0x56: 1597 case 0x57: 1598 max_gpio = CS35L56_MAX_GPIO; 1599 break; 1600 default: 1601 max_gpio = CS35L63_MAX_GPIO; 1602 break; 1603 } 1604 1605 for (i = 0; i < num_gpios; i++) { 1606 if (gpios[i] < 1 || gpios[i] > max_gpio) { 1607 dev_err(cs35l56_base->dev, "Invalid spkid GPIO %d\n", gpios[i]); 1608 /* Keep going so we log all bad values */ 1609 ret = -EINVAL; 1610 } 1611 1612 /* Change to zero-based */ 1613 cs35l56_base->onchip_spkid_gpios[i] = gpios[i] - 1; 1614 } 1615 1616 for (i = 0; i < num_pulls; i++) { 1617 switch (pulls[i]) { 1618 case 0: 1619 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_NONE; 1620 break; 1621 case 1: 1622 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_UP; 1623 break; 1624 case 2: 1625 cs35l56_base->onchip_spkid_pulls[i] = CS35L56_PAD_PULL_DOWN; 1626 break; 1627 default: 1628 dev_err(cs35l56_base->dev, "Invalid spkid pull %d\n", pulls[i]); 1629 /* Keep going so we log all bad values */ 1630 ret = -EINVAL; 1631 break; 1632 } 1633 } 1634 if (ret) 1635 return ret; 1636 1637 cs35l56_base->num_onchip_spkid_gpios = num_gpios; 1638 cs35l56_base->num_onchip_spkid_pulls = num_pulls; 1639 1640 return 0; 1641 } 1642 EXPORT_SYMBOL_NS_GPL(cs35l56_check_and_save_onchip_spkid_gpios, "SND_SOC_CS35L56_SHARED"); 1643 1644 /* Caller must pm_runtime resume before calling this function */ 1645 int cs35l56_configure_onchip_spkid_pads(struct cs35l56_base *cs35l56_base) 1646 { 1647 struct regmap *regmap = cs35l56_base->regmap; 1648 unsigned int addr_offset, val; 1649 int num_gpios, num_pulls; 1650 int i, ret; 1651 1652 KUNIT_STATIC_STUB_REDIRECT(cs35l56_configure_onchip_spkid_pads, cs35l56_base); 1653 1654 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1655 return 0; 1656 1657 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1658 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1659 num_pulls = min(cs35l56_base->num_onchip_spkid_pulls, 1660 ARRAY_SIZE(cs35l56_base->onchip_spkid_pulls)); 1661 1662 for (i = 0; i < num_gpios; i++) { 1663 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1664 1665 /* Set unspecified pulls to NONE */ 1666 if (i < num_pulls) { 1667 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, 1668 cs35l56_base->onchip_spkid_pulls[i]); 1669 } else { 1670 val = FIELD_PREP(CS35L56_PAD_GPIO_PULL_MASK, CS35L56_PAD_PULL_NONE); 1671 } 1672 1673 ret = regmap_update_bits(regmap, CS35L56_SYNC_GPIO1_CFG + addr_offset, 1674 CS35L56_PAD_GPIO_PULL_MASK | CS35L56_PAD_GPIO_IE, 1675 val | CS35L56_PAD_GPIO_IE); 1676 if (ret) { 1677 dev_err(cs35l56_base->dev, "GPIO%d set pad fail: %d\n", 1678 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1679 return ret; 1680 } 1681 } 1682 1683 ret = regmap_write(regmap, CS35L56_UPDATE_REGS, CS35L56_UPDT_GPIO_PRES); 1684 if (ret) { 1685 dev_err(cs35l56_base->dev, "UPDT_GPIO_PRES failed:%d\n", ret); 1686 return ret; 1687 } 1688 1689 usleep_range(CS35L56_PAD_PULL_SETTLE_US, CS35L56_PAD_PULL_SETTLE_US * 2); 1690 1691 return 0; 1692 } 1693 EXPORT_SYMBOL_NS_GPL(cs35l56_configure_onchip_spkid_pads, "SND_SOC_CS35L56_SHARED"); 1694 1695 /* Caller must pm_runtime resume before calling this function */ 1696 int cs35l56_read_onchip_spkid(struct cs35l56_base *cs35l56_base) 1697 { 1698 struct regmap *regmap = cs35l56_base->regmap; 1699 unsigned int addr_offset, val; 1700 int num_gpios; 1701 int speaker_id = 0; 1702 int i, ret; 1703 1704 KUNIT_STATIC_STUB_REDIRECT(cs35l56_read_onchip_spkid, cs35l56_base); 1705 1706 if (cs35l56_base->num_onchip_spkid_gpios == 0) 1707 return -ENOENT; 1708 1709 num_gpios = min(cs35l56_base->num_onchip_spkid_gpios, 1710 ARRAY_SIZE(cs35l56_base->onchip_spkid_gpios)); 1711 1712 for (i = 0; i < num_gpios; i++) { 1713 addr_offset = cs35l56_base->onchip_spkid_gpios[i] * sizeof(u32); 1714 1715 ret = regmap_update_bits(regmap, CS35L56_GPIO1_CTRL1 + addr_offset, 1716 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_MASK, 1717 CS35L56_GPIO_DIR_MASK | CS35L56_GPIO_FN_GPIO); 1718 if (ret) { 1719 dev_err(cs35l56_base->dev, "GPIO%u set func fail: %d\n", 1720 cs35l56_base->onchip_spkid_gpios[i] + 1, ret); 1721 return ret; 1722 } 1723 } 1724 1725 ret = regmap_read(regmap, CS35L56_GPIO_STATUS1, &val); 1726 if (ret) { 1727 dev_err(cs35l56_base->dev, "GPIO status read failed: %d\n", ret); 1728 return ret; 1729 } 1730 1731 for (i = 0; i < num_gpios; i++) { 1732 speaker_id <<= 1; 1733 1734 if (val & BIT(cs35l56_base->onchip_spkid_gpios[i])) 1735 speaker_id |= 1; 1736 } 1737 1738 dev_dbg(cs35l56_base->dev, "Onchip GPIO Speaker ID = %d\n", speaker_id); 1739 1740 return speaker_id; 1741 } 1742 EXPORT_SYMBOL_NS_GPL(cs35l56_read_onchip_spkid, "SND_SOC_CS35L56_SHARED"); 1743 1744 static const u32 cs35l56_bclk_valid_for_pll_freq_table[] = { 1745 [0x0C] = 128000, 1746 [0x0F] = 256000, 1747 [0x11] = 384000, 1748 [0x12] = 512000, 1749 [0x15] = 768000, 1750 [0x17] = 1024000, 1751 [0x1A] = 1500000, 1752 [0x1B] = 1536000, 1753 [0x1C] = 2000000, 1754 [0x1D] = 2048000, 1755 [0x1E] = 2400000, 1756 [0x20] = 3000000, 1757 [0x21] = 3072000, 1758 [0x23] = 4000000, 1759 [0x24] = 4096000, 1760 [0x25] = 4800000, 1761 [0x27] = 6000000, 1762 [0x28] = 6144000, 1763 [0x29] = 6250000, 1764 [0x2A] = 6400000, 1765 [0x2E] = 8000000, 1766 [0x2F] = 8192000, 1767 [0x30] = 9600000, 1768 [0x32] = 12000000, 1769 [0x33] = 12288000, 1770 [0x37] = 13500000, 1771 [0x38] = 19200000, 1772 [0x39] = 22579200, 1773 [0x3B] = 24576000, 1774 }; 1775 1776 int cs35l56_get_bclk_freq_id(unsigned int freq) 1777 { 1778 int i; 1779 1780 if (freq == 0) 1781 return -EINVAL; 1782 1783 /* The BCLK frequency must be a valid PLL REFCLK */ 1784 for (i = 0; i < ARRAY_SIZE(cs35l56_bclk_valid_for_pll_freq_table); ++i) { 1785 if (cs35l56_bclk_valid_for_pll_freq_table[i] == freq) 1786 return i; 1787 } 1788 1789 return -EINVAL; 1790 } 1791 EXPORT_SYMBOL_NS_GPL(cs35l56_get_bclk_freq_id, "SND_SOC_CS35L56_SHARED"); 1792 1793 static const char * const cs35l56_supplies[/* auto-sized */] = { 1794 "VDD_P", 1795 "VDD_IO", 1796 "VDD_A", 1797 }; 1798 1799 void cs35l56_fill_supply_names(struct regulator_bulk_data *data) 1800 { 1801 int i; 1802 1803 BUILD_BUG_ON(ARRAY_SIZE(cs35l56_supplies) != CS35L56_NUM_BULK_SUPPLIES); 1804 for (i = 0; i < ARRAY_SIZE(cs35l56_supplies); i++) 1805 data[i].supply = cs35l56_supplies[i]; 1806 } 1807 EXPORT_SYMBOL_NS_GPL(cs35l56_fill_supply_names, "SND_SOC_CS35L56_SHARED"); 1808 1809 const char * const cs35l56_tx_input_texts[] = { 1810 "None", "ASP1RX1", "ASP1RX2", "VMON", "IMON", "ERRVOL", "CLASSH", 1811 "VDDBMON", "VBSTMON", "DSP1TX1", "DSP1TX2", "DSP1TX3", "DSP1TX4", 1812 "DSP1TX5", "DSP1TX6", "DSP1TX7", "DSP1TX8", "TEMPMON", 1813 "INTERPOLATOR", "SDW1RX1", "SDW1RX2", 1814 }; 1815 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_texts, "SND_SOC_CS35L56_SHARED"); 1816 1817 const unsigned int cs35l56_tx_input_values[] = { 1818 CS35L56_INPUT_SRC_NONE, 1819 CS35L56_INPUT_SRC_ASP1RX1, 1820 CS35L56_INPUT_SRC_ASP1RX2, 1821 CS35L56_INPUT_SRC_VMON, 1822 CS35L56_INPUT_SRC_IMON, 1823 CS35L56_INPUT_SRC_ERR_VOL, 1824 CS35L56_INPUT_SRC_CLASSH, 1825 CS35L56_INPUT_SRC_VDDBMON, 1826 CS35L56_INPUT_SRC_VBSTMON, 1827 CS35L56_INPUT_SRC_DSP1TX1, 1828 CS35L56_INPUT_SRC_DSP1TX2, 1829 CS35L56_INPUT_SRC_DSP1TX3, 1830 CS35L56_INPUT_SRC_DSP1TX4, 1831 CS35L56_INPUT_SRC_DSP1TX5, 1832 CS35L56_INPUT_SRC_DSP1TX6, 1833 CS35L56_INPUT_SRC_DSP1TX7, 1834 CS35L56_INPUT_SRC_DSP1TX8, 1835 CS35L56_INPUT_SRC_TEMPMON, 1836 CS35L56_INPUT_SRC_INTERPOLATOR, 1837 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL1, 1838 CS35L56_INPUT_SRC_SWIRE_DP1_CHANNEL2, 1839 }; 1840 EXPORT_SYMBOL_NS_GPL(cs35l56_tx_input_values, "SND_SOC_CS35L56_SHARED"); 1841 1842 const struct regmap_config cs35l56_regmap_i2c = { 1843 .reg_bits = 32, 1844 .val_bits = 32, 1845 .reg_stride = 4, 1846 .reg_format_endian = REGMAP_ENDIAN_BIG, 1847 .val_format_endian = REGMAP_ENDIAN_BIG, 1848 .max_register = CS35L56_DSP1_PMEM_5114, 1849 .reg_defaults = cs35l56_reg_defaults, 1850 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1851 .volatile_reg = cs35l56_volatile_reg, 1852 .readable_reg = cs35l56_readable_reg, 1853 .precious_reg = cs35l56_precious_reg, 1854 .cache_type = REGCACHE_MAPLE, 1855 }; 1856 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1857 1858 const struct regmap_config cs35l56_regmap_spi = { 1859 .reg_bits = 32, 1860 .val_bits = 32, 1861 .pad_bits = 16, 1862 .reg_stride = 4, 1863 .reg_format_endian = REGMAP_ENDIAN_BIG, 1864 .val_format_endian = REGMAP_ENDIAN_BIG, 1865 .max_register = CS35L56_DSP1_PMEM_5114, 1866 .reg_defaults = cs35l56_reg_defaults, 1867 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1868 .volatile_reg = cs35l56_volatile_reg, 1869 .readable_reg = cs35l56_readable_reg, 1870 .precious_reg = cs35l56_precious_reg, 1871 .cache_type = REGCACHE_MAPLE, 1872 }; 1873 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_spi, "SND_SOC_CS35L56_SHARED"); 1874 1875 const struct regmap_config cs35l56_regmap_sdw = { 1876 .reg_bits = 32, 1877 .reg_base = 0x8000, 1878 .val_bits = 32, 1879 .reg_stride = 4, 1880 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1881 .val_format_endian = REGMAP_ENDIAN_BIG, 1882 .max_register = CS35L56_DSP1_PMEM_5114, 1883 .reg_defaults = cs35l56_reg_defaults, 1884 .num_reg_defaults = ARRAY_SIZE(cs35l56_reg_defaults), 1885 .volatile_reg = cs35l56_volatile_reg, 1886 .readable_reg = cs35l56_readable_reg, 1887 .precious_reg = cs35l56_precious_reg, 1888 .cache_type = REGCACHE_MAPLE, 1889 }; 1890 EXPORT_SYMBOL_NS_GPL(cs35l56_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1891 1892 const struct regmap_config cs35l63_regmap_i2c = { 1893 .reg_bits = 32, 1894 .val_bits = 32, 1895 .reg_stride = 4, 1896 .reg_base = 0x8000, 1897 .reg_format_endian = REGMAP_ENDIAN_BIG, 1898 .val_format_endian = REGMAP_ENDIAN_BIG, 1899 .max_register = CS35L56_DSP1_PMEM_5114, 1900 .reg_defaults = cs35l63_reg_defaults, 1901 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1902 .volatile_reg = cs35l63_volatile_reg, 1903 .readable_reg = cs35l56_readable_reg, 1904 .precious_reg = cs35l56_precious_reg, 1905 .cache_type = REGCACHE_MAPLE, 1906 }; 1907 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_i2c, "SND_SOC_CS35L56_SHARED"); 1908 1909 const struct regmap_config cs35l63_regmap_sdw = { 1910 .reg_bits = 32, 1911 .val_bits = 32, 1912 .reg_stride = 4, 1913 .reg_base = 0x8000, 1914 .reg_format_endian = REGMAP_ENDIAN_LITTLE, 1915 .val_format_endian = REGMAP_ENDIAN_BIG, 1916 .max_register = CS35L56_DSP1_PMEM_5114, 1917 .reg_defaults = cs35l63_reg_defaults, 1918 .num_reg_defaults = ARRAY_SIZE(cs35l63_reg_defaults), 1919 .volatile_reg = cs35l63_volatile_reg, 1920 .readable_reg = cs35l56_readable_reg, 1921 .precious_reg = cs35l56_precious_reg, 1922 .cache_type = REGCACHE_MAPLE, 1923 }; 1924 EXPORT_SYMBOL_NS_GPL(cs35l63_regmap_sdw, "SND_SOC_CS35L56_SHARED"); 1925 1926 MODULE_DESCRIPTION("ASoC CS35L56 Shared"); 1927 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>"); 1928 MODULE_AUTHOR("Simon Trimmer <simont@opensource.cirrus.com>"); 1929 MODULE_LICENSE("GPL"); 1930 MODULE_IMPORT_NS("SND_SOC_CS_AMP_LIB"); 1931 MODULE_IMPORT_NS("FW_CS_DSP"); 1932