1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4 // 5 // Copyright 2019-2022 Cirrus Logic, Inc. 6 // 7 // Author: James Schulman <james.schulman@cirrus.com> 8 9 #include <linux/module.h> 10 #include <linux/regmap.h> 11 12 #include "cs35l45.h" 13 14 static const struct reg_sequence cs35l45_patch[] = { 15 { 0x00000040, 0x00000055 }, 16 { 0x00000040, 0x000000AA }, 17 { 0x00000044, 0x00000055 }, 18 { 0x00000044, 0x000000AA }, 19 { 0x00006480, 0x0830500A }, 20 { 0x00007C60, 0x1000850B }, 21 { CS35L45_BOOST_OV_CFG, 0x007000D0 }, 22 { CS35L45_LDPM_CONFIG, 0x0001B636 }, 23 { 0x00002C08, 0x00000009 }, 24 { 0x00006850, 0x0A30FFC4 }, 25 { 0x00003820, 0x00040100 }, 26 { 0x00003824, 0x00000000 }, 27 { 0x00007CFC, 0x62870004 }, 28 { 0x00007C60, 0x1001850B }, 29 { 0x00000040, 0x00000000 }, 30 { 0x00000044, 0x00000000 }, 31 { CS35L45_BOOST_CCM_CFG, 0xF0000003 }, 32 { CS35L45_BOOST_DCM_CFG, 0x08710220 }, 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34 }; 35 36 int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37 { 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40 } 41 EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45); 42 43 static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_SYNC_GPIO1, 0x00000007 }, 47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 }, 48 { CS35L45_GPIO3, 0x00000005 }, 49 { CS35L45_PWRMGT_CTL, 0x00000000 }, 50 { CS35L45_WAKESRC_CTL, 0x00000008 }, 51 { CS35L45_WKI2C_CTL, 0x00000030 }, 52 { CS35L45_REFCLK_INPUT, 0x00000510 }, 53 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 54 { CS35L45_ASP_ENABLES1, 0x00000000 }, 55 { CS35L45_ASP_CONTROL1, 0x00000028 }, 56 { CS35L45_ASP_CONTROL2, 0x18180200 }, 57 { CS35L45_ASP_CONTROL3, 0x00000002 }, 58 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 }, 59 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 }, 60 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 }, 61 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 }, 62 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 }, 63 { CS35L45_DACPCM1_INPUT, 0x00000008 }, 64 { CS35L45_ASPTX1_INPUT, 0x00000018 }, 65 { CS35L45_ASPTX2_INPUT, 0x00000019 }, 66 { CS35L45_ASPTX3_INPUT, 0x00000020 }, 67 { CS35L45_ASPTX4_INPUT, 0x00000028 }, 68 { CS35L45_ASPTX5_INPUT, 0x00000048 }, 69 { CS35L45_DSP1_RX1_RATE, 0x00000001 }, 70 { CS35L45_DSP1_RX2_RATE, 0x00000001 }, 71 { CS35L45_DSP1_RX3_RATE, 0x00000001 }, 72 { CS35L45_DSP1_RX4_RATE, 0x00000001 }, 73 { CS35L45_DSP1_RX5_RATE, 0x00000001 }, 74 { CS35L45_DSP1_RX6_RATE, 0x00000001 }, 75 { CS35L45_DSP1_RX7_RATE, 0x00000001 }, 76 { CS35L45_DSP1_RX8_RATE, 0x00000001 }, 77 { CS35L45_DSP1_TX1_RATE, 0x00000001 }, 78 { CS35L45_DSP1_TX2_RATE, 0x00000001 }, 79 { CS35L45_DSP1_TX3_RATE, 0x00000001 }, 80 { CS35L45_DSP1_TX4_RATE, 0x00000001 }, 81 { CS35L45_DSP1_TX5_RATE, 0x00000001 }, 82 { CS35L45_DSP1_TX6_RATE, 0x00000001 }, 83 { CS35L45_DSP1_TX7_RATE, 0x00000001 }, 84 { CS35L45_DSP1_TX8_RATE, 0x00000001 }, 85 { CS35L45_DSP1RX1_INPUT, 0x00000008 }, 86 { CS35L45_DSP1RX2_INPUT, 0x00000009 }, 87 { CS35L45_DSP1RX3_INPUT, 0x00000018 }, 88 { CS35L45_DSP1RX4_INPUT, 0x00000019 }, 89 { CS35L45_DSP1RX5_INPUT, 0x00000020 }, 90 { CS35L45_DSP1RX6_INPUT, 0x00000028 }, 91 { CS35L45_DSP1RX7_INPUT, 0x0000003A }, 92 { CS35L45_DSP1RX8_INPUT, 0x00000028 }, 93 { CS35L45_AMP_PCM_CONTROL, 0x00100000 }, 94 { CS35L45_AMP_GAIN, 0x00002300 }, 95 { CS35L45_IRQ1_CFG, 0x00000000 }, 96 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF }, 97 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF }, 98 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF }, 99 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF }, 100 { CS35L45_IRQ1_MASK_5, 0x0EF80000 }, 101 { CS35L45_IRQ1_MASK_6, 0x00000000 }, 102 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 }, 103 { CS35L45_IRQ1_MASK_8, 0x00003FFF }, 104 { CS35L45_IRQ1_MASK_9, 0x00000000 }, 105 { CS35L45_IRQ1_MASK_10, 0x00000000 }, 106 { CS35L45_IRQ1_MASK_11, 0x00000000 }, 107 { CS35L45_IRQ1_MASK_12, 0x00000000 }, 108 { CS35L45_IRQ1_MASK_13, 0x00000000 }, 109 { CS35L45_IRQ1_MASK_14, 0x00000001 }, 110 { CS35L45_IRQ1_MASK_15, 0x00000000 }, 111 { CS35L45_IRQ1_MASK_16, 0x00000000 }, 112 { CS35L45_IRQ1_MASK_17, 0x00000000 }, 113 { CS35L45_IRQ1_MASK_18, 0x3FE5D0FF }, 114 { CS35L45_GPIO1_CTRL1, 0x81000001 }, 115 { CS35L45_GPIO2_CTRL1, 0x81000001 }, 116 { CS35L45_GPIO3_CTRL1, 0x81000001 }, 117 }; 118 119 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg) 120 { 121 switch (reg) { 122 case CS35L45_DEVID ... CS35L45_OTPID: 123 case CS35L45_SFT_RESET: 124 case CS35L45_GLOBAL_ENABLES: 125 case CS35L45_BLOCK_ENABLES: 126 case CS35L45_BLOCK_ENABLES2: 127 case CS35L45_ERROR_RELEASE: 128 case CS35L45_SYNC_GPIO1: 129 case CS35L45_INTB_GPIO2_MCLK_REF: 130 case CS35L45_GPIO3: 131 case CS35L45_PWRMGT_CTL: 132 case CS35L45_WAKESRC_CTL: 133 case CS35L45_WKI2C_CTL: 134 case CS35L45_PWRMGT_STS: 135 case CS35L45_REFCLK_INPUT: 136 case CS35L45_GLOBAL_SAMPLE_RATE: 137 case CS35L45_ASP_ENABLES1: 138 case CS35L45_ASP_CONTROL1: 139 case CS35L45_ASP_CONTROL2: 140 case CS35L45_ASP_CONTROL3: 141 case CS35L45_ASP_FRAME_CONTROL1: 142 case CS35L45_ASP_FRAME_CONTROL2: 143 case CS35L45_ASP_FRAME_CONTROL5: 144 case CS35L45_ASP_DATA_CONTROL1: 145 case CS35L45_ASP_DATA_CONTROL5: 146 case CS35L45_DACPCM1_INPUT: 147 case CS35L45_ASPTX1_INPUT: 148 case CS35L45_ASPTX2_INPUT: 149 case CS35L45_ASPTX3_INPUT: 150 case CS35L45_ASPTX4_INPUT: 151 case CS35L45_ASPTX5_INPUT: 152 case CS35L45_DSP1RX1_INPUT: 153 case CS35L45_DSP1RX2_INPUT: 154 case CS35L45_DSP1RX3_INPUT: 155 case CS35L45_DSP1RX4_INPUT: 156 case CS35L45_DSP1RX5_INPUT: 157 case CS35L45_DSP1RX6_INPUT: 158 case CS35L45_DSP1RX7_INPUT: 159 case CS35L45_DSP1RX8_INPUT: 160 case CS35L45_HVLV_CONFIG: 161 case CS35L45_AMP_PCM_CONTROL: 162 case CS35L45_AMP_GAIN: 163 case CS35L45_AMP_PCM_HPF_TST: 164 case CS35L45_IRQ1_CFG: 165 case CS35L45_IRQ1_STATUS: 166 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 167 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 168 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18: 169 case CS35L45_GPIO_STATUS1: 170 case CS35L45_GPIO1_CTRL1: 171 case CS35L45_GPIO2_CTRL1: 172 case CS35L45_GPIO3_CTRL1: 173 case CS35L45_DSP_MBOX_1: 174 case CS35L45_DSP_MBOX_2: 175 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4: 176 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4: 177 case CS35L45_DSP1_SYS_ID: 178 case CS35L45_DSP1_CLOCK_FREQ: 179 case CS35L45_DSP1_RX1_RATE: 180 case CS35L45_DSP1_RX2_RATE: 181 case CS35L45_DSP1_RX3_RATE: 182 case CS35L45_DSP1_RX4_RATE: 183 case CS35L45_DSP1_RX5_RATE: 184 case CS35L45_DSP1_RX6_RATE: 185 case CS35L45_DSP1_RX7_RATE: 186 case CS35L45_DSP1_RX8_RATE: 187 case CS35L45_DSP1_TX1_RATE: 188 case CS35L45_DSP1_TX2_RATE: 189 case CS35L45_DSP1_TX3_RATE: 190 case CS35L45_DSP1_TX4_RATE: 191 case CS35L45_DSP1_TX5_RATE: 192 case CS35L45_DSP1_TX6_RATE: 193 case CS35L45_DSP1_TX7_RATE: 194 case CS35L45_DSP1_TX8_RATE: 195 case CS35L45_DSP1_SCRATCH1: 196 case CS35L45_DSP1_SCRATCH2: 197 case CS35L45_DSP1_SCRATCH3: 198 case CS35L45_DSP1_SCRATCH4: 199 case CS35L45_DSP1_CCM_CORE_CONTROL: 200 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: 201 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: 202 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: 203 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: 204 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: 205 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: 206 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: 207 return true; 208 default: 209 return false; 210 } 211 } 212 213 static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg) 214 { 215 switch (reg) { 216 case CS35L45_DEVID ... CS35L45_OTPID: 217 case CS35L45_SFT_RESET: 218 case CS35L45_GLOBAL_ENABLES: 219 case CS35L45_ERROR_RELEASE: 220 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */ 221 case CS35L45_PWRMGT_STS: 222 case CS35L45_IRQ1_STATUS: 223 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18: 224 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18: 225 case CS35L45_GPIO_STATUS1: 226 case CS35L45_DSP_MBOX_1: 227 case CS35L45_DSP_MBOX_2: 228 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4: 229 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4: 230 case CS35L45_DSP1_SYS_ID: 231 case CS35L45_DSP1_CLOCK_FREQ: 232 case CS35L45_DSP1_SCRATCH1: 233 case CS35L45_DSP1_SCRATCH2: 234 case CS35L45_DSP1_SCRATCH3: 235 case CS35L45_DSP1_SCRATCH4: 236 case CS35L45_DSP1_CCM_CORE_CONTROL: 237 case CS35L45_DSP1_XMEM_PACK_0 ... CS35L45_DSP1_XMEM_PACK_4607: 238 case CS35L45_DSP1_XMEM_UNPACK32_0 ... CS35L45_DSP1_XMEM_UNPACK32_3071: 239 case CS35L45_DSP1_XMEM_UNPACK24_0 ... CS35L45_DSP1_XMEM_UNPACK24_6143: 240 case CS35L45_DSP1_YMEM_PACK_0 ... CS35L45_DSP1_YMEM_PACK_1532: 241 case CS35L45_DSP1_YMEM_UNPACK32_0 ... CS35L45_DSP1_YMEM_UNPACK32_1022: 242 case CS35L45_DSP1_YMEM_UNPACK24_0 ... CS35L45_DSP1_YMEM_UNPACK24_2043: 243 case CS35L45_DSP1_PMEM_0 ... CS35L45_DSP1_PMEM_3834: 244 return true; 245 default: 246 return false; 247 } 248 } 249 250 const struct regmap_config cs35l45_i2c_regmap = { 251 .reg_bits = 32, 252 .val_bits = 32, 253 .reg_stride = 4, 254 .reg_format_endian = REGMAP_ENDIAN_BIG, 255 .val_format_endian = REGMAP_ENDIAN_BIG, 256 .max_register = CS35L45_LASTREG, 257 .reg_defaults = cs35l45_defaults, 258 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 259 .volatile_reg = cs35l45_volatile_reg, 260 .readable_reg = cs35l45_readable_reg, 261 .cache_type = REGCACHE_MAPLE, 262 }; 263 EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45); 264 265 const struct regmap_config cs35l45_spi_regmap = { 266 .reg_bits = 32, 267 .val_bits = 32, 268 .pad_bits = 16, 269 .reg_stride = 4, 270 .reg_format_endian = REGMAP_ENDIAN_BIG, 271 .val_format_endian = REGMAP_ENDIAN_BIG, 272 .max_register = CS35L45_LASTREG, 273 .reg_defaults = cs35l45_defaults, 274 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 275 .volatile_reg = cs35l45_volatile_reg, 276 .readable_reg = cs35l45_readable_reg, 277 .cache_type = REGCACHE_MAPLE, 278 }; 279 EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45); 280 281 static const struct { 282 u8 cfg_id; 283 u32 freq; 284 } cs35l45_pll_refclk_freq[] = { 285 { 0x0C, 128000 }, 286 { 0x0F, 256000 }, 287 { 0x11, 384000 }, 288 { 0x12, 512000 }, 289 { 0x15, 768000 }, 290 { 0x17, 1024000 }, 291 { 0x19, 1411200 }, 292 { 0x1B, 1536000 }, 293 { 0x1C, 2116800 }, 294 { 0x1D, 2048000 }, 295 { 0x1E, 2304000 }, 296 { 0x1F, 2822400 }, 297 { 0x21, 3072000 }, 298 { 0x23, 4233600 }, 299 { 0x24, 4096000 }, 300 { 0x25, 4608000 }, 301 { 0x26, 5644800 }, 302 { 0x27, 6000000 }, 303 { 0x28, 6144000 }, 304 { 0x29, 6350400 }, 305 { 0x2A, 6912000 }, 306 { 0x2D, 7526400 }, 307 { 0x2E, 8467200 }, 308 { 0x2F, 8192000 }, 309 { 0x30, 9216000 }, 310 { 0x31, 11289600 }, 311 { 0x33, 12288000 }, 312 { 0x37, 16934400 }, 313 { 0x38, 18432000 }, 314 { 0x39, 22579200 }, 315 { 0x3B, 24576000 }, 316 }; 317 318 unsigned int cs35l45_get_clk_freq_id(unsigned int freq) 319 { 320 int i; 321 322 if (freq == 0) 323 return -EINVAL; 324 325 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 326 if (cs35l45_pll_refclk_freq[i].freq == freq) 327 return cs35l45_pll_refclk_freq[i].cfg_id; 328 } 329 330 return -EINVAL; 331 } 332 EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45); 333