1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // cs35l41.c -- CS35l41 ALSA SoC audio driver 4 // 5 // Copyright 2017-2021 Cirrus Logic, Inc. 6 // 7 // Author: David Rhodes <david.rhodes@cirrus.com> 8 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/of_device.h> 16 #include <linux/property.h> 17 #include <linux/slab.h> 18 #include <sound/initval.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/tlv.h> 24 25 #include "cs35l41.h" 26 27 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = { 28 "VA", 29 "VP", 30 }; 31 32 struct cs35l41_pll_sysclk_config { 33 int freq; 34 int clk_cfg; 35 }; 36 37 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = { 38 { 32768, 0x00 }, 39 { 8000, 0x01 }, 40 { 11025, 0x02 }, 41 { 12000, 0x03 }, 42 { 16000, 0x04 }, 43 { 22050, 0x05 }, 44 { 24000, 0x06 }, 45 { 32000, 0x07 }, 46 { 44100, 0x08 }, 47 { 48000, 0x09 }, 48 { 88200, 0x0A }, 49 { 96000, 0x0B }, 50 { 128000, 0x0C }, 51 { 176400, 0x0D }, 52 { 192000, 0x0E }, 53 { 256000, 0x0F }, 54 { 352800, 0x10 }, 55 { 384000, 0x11 }, 56 { 512000, 0x12 }, 57 { 705600, 0x13 }, 58 { 750000, 0x14 }, 59 { 768000, 0x15 }, 60 { 1000000, 0x16 }, 61 { 1024000, 0x17 }, 62 { 1200000, 0x18 }, 63 { 1411200, 0x19 }, 64 { 1500000, 0x1A }, 65 { 1536000, 0x1B }, 66 { 2000000, 0x1C }, 67 { 2048000, 0x1D }, 68 { 2400000, 0x1E }, 69 { 2822400, 0x1F }, 70 { 3000000, 0x20 }, 71 { 3072000, 0x21 }, 72 { 3200000, 0x22 }, 73 { 4000000, 0x23 }, 74 { 4096000, 0x24 }, 75 { 4800000, 0x25 }, 76 { 5644800, 0x26 }, 77 { 6000000, 0x27 }, 78 { 6144000, 0x28 }, 79 { 6250000, 0x29 }, 80 { 6400000, 0x2A }, 81 { 6500000, 0x2B }, 82 { 6750000, 0x2C }, 83 { 7526400, 0x2D }, 84 { 8000000, 0x2E }, 85 { 8192000, 0x2F }, 86 { 9600000, 0x30 }, 87 { 11289600, 0x31 }, 88 { 12000000, 0x32 }, 89 { 12288000, 0x33 }, 90 { 12500000, 0x34 }, 91 { 12800000, 0x35 }, 92 { 13000000, 0x36 }, 93 { 13500000, 0x37 }, 94 { 19200000, 0x38 }, 95 { 22579200, 0x39 }, 96 { 24000000, 0x3A }, 97 { 24576000, 0x3B }, 98 { 25000000, 0x3C }, 99 { 25600000, 0x3D }, 100 { 26000000, 0x3E }, 101 { 27000000, 0x3F }, 102 }; 103 104 struct cs35l41_fs_mon_config { 105 int freq; 106 unsigned int fs1; 107 unsigned int fs2; 108 }; 109 110 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = { 111 { 32768, 2254, 3754 }, 112 { 8000, 9220, 15364 }, 113 { 11025, 6148, 10244 }, 114 { 12000, 6148, 10244 }, 115 { 16000, 4612, 7684 }, 116 { 22050, 3076, 5124 }, 117 { 24000, 3076, 5124 }, 118 { 32000, 2308, 3844 }, 119 { 44100, 1540, 2564 }, 120 { 48000, 1540, 2564 }, 121 { 88200, 772, 1284 }, 122 { 96000, 772, 1284 }, 123 { 128000, 580, 964 }, 124 { 176400, 388, 644 }, 125 { 192000, 388, 644 }, 126 { 256000, 292, 484 }, 127 { 352800, 196, 324 }, 128 { 384000, 196, 324 }, 129 { 512000, 148, 244 }, 130 { 705600, 100, 164 }, 131 { 750000, 100, 164 }, 132 { 768000, 100, 164 }, 133 { 1000000, 76, 124 }, 134 { 1024000, 76, 124 }, 135 { 1200000, 64, 104 }, 136 { 1411200, 52, 84 }, 137 { 1500000, 52, 84 }, 138 { 1536000, 52, 84 }, 139 { 2000000, 40, 64 }, 140 { 2048000, 40, 64 }, 141 { 2400000, 34, 54 }, 142 { 2822400, 28, 44 }, 143 { 3000000, 28, 44 }, 144 { 3072000, 28, 44 }, 145 { 3200000, 27, 42 }, 146 { 4000000, 22, 34 }, 147 { 4096000, 22, 34 }, 148 { 4800000, 19, 29 }, 149 { 5644800, 16, 24 }, 150 { 6000000, 16, 24 }, 151 { 6144000, 16, 24 }, 152 }; 153 154 static const unsigned char cs35l41_bst_k1_table[4][5] = { 155 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 156 { 0x24, 0x32, 0x32, 0x4F, 0x57 }, 157 { 0x40, 0x32, 0x32, 0x4F, 0x57 }, 158 { 0x40, 0x32, 0x32, 0x4F, 0x57 } 159 }; 160 161 static const unsigned char cs35l41_bst_k2_table[4][5] = { 162 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 163 { 0x24, 0x49, 0x66, 0xA3, 0xEA }, 164 { 0x48, 0x49, 0x66, 0xA3, 0xEA }, 165 { 0x48, 0x49, 0x66, 0xA3, 0xEA } 166 }; 167 168 static const unsigned char cs35l41_bst_slope_table[4] = { 169 0x75, 0x6B, 0x3B, 0x28 170 }; 171 172 static int cs35l41_get_fs_mon_config_index(int freq) 173 { 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) { 177 if (cs35l41_fs_mon[i].freq == freq) 178 return i; 179 } 180 181 return -EINVAL; 182 } 183 184 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 185 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 186 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200)); 187 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 188 189 static const struct snd_kcontrol_new dre_ctrl = 190 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0); 191 192 static const char * const cs35l41_pcm_sftramp_text[] = { 193 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms" 194 }; 195 196 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, 197 CS35L41_AMP_DIG_VOL_CTRL, 0, 198 cs35l41_pcm_sftramp_text); 199 200 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w, 201 struct snd_kcontrol *kcontrol, int event) 202 { 203 int ret; 204 205 switch (event) { 206 case SND_SOC_DAPM_PRE_PMU: 207 return wm_adsp_early_event(w, kcontrol, event); 208 case SND_SOC_DAPM_PRE_PMD: 209 ret = wm_adsp_early_event(w, kcontrol, event); 210 if (ret) 211 return ret; 212 213 return wm_adsp_event(w, kcontrol, event); 214 default: 215 return 0; 216 } 217 } 218 219 static bool cs35l41_check_cspl_mbox_sts(enum cs35l41_cspl_mbox_cmd cmd, 220 enum cs35l41_cspl_mbox_status sts) 221 { 222 switch (cmd) { 223 case CSPL_MBOX_CMD_NONE: 224 case CSPL_MBOX_CMD_UNKNOWN_CMD: 225 return true; 226 case CSPL_MBOX_CMD_PAUSE: 227 return (sts == CSPL_MBOX_STS_PAUSED); 228 case CSPL_MBOX_CMD_RESUME: 229 return (sts == CSPL_MBOX_STS_RUNNING); 230 case CSPL_MBOX_CMD_REINIT: 231 return (sts == CSPL_MBOX_STS_RUNNING); 232 case CSPL_MBOX_CMD_STOP_PRE_REINIT: 233 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT); 234 default: 235 return false; 236 } 237 } 238 239 static int cs35l41_set_cspl_mbox_cmd(struct cs35l41_private *cs35l41, 240 enum cs35l41_cspl_mbox_cmd cmd) 241 { 242 unsigned int sts = 0, i; 243 int ret; 244 245 // Set mailbox cmd 246 ret = regmap_write(cs35l41->regmap, CS35L41_DSP_VIRT1_MBOX_1, cmd); 247 if (ret < 0) { 248 dev_err(cs35l41->dev, "Failed to write MBOX: %d\n", ret); 249 return ret; 250 } 251 252 // Read mailbox status and verify it is appropriate for the given cmd 253 for (i = 0; i < 5; i++) { 254 usleep_range(1000, 1100); 255 256 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &sts); 257 if (ret < 0) { 258 dev_err(cs35l41->dev, "Failed to read MBOX STS: %d\n", ret); 259 continue; 260 } 261 262 if (!cs35l41_check_cspl_mbox_sts(cmd, sts)) { 263 dev_dbg(cs35l41->dev, 264 "[%u] cmd %u returned invalid sts %u", 265 i, cmd, sts); 266 } else { 267 return 0; 268 } 269 } 270 271 dev_err(cs35l41->dev, 272 "Failed to set mailbox cmd %u (status %u)\n", 273 cmd, sts); 274 275 return -ENOMSG; 276 } 277 278 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w, 279 struct snd_kcontrol *kcontrol, int event) 280 { 281 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 282 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 283 unsigned int fw_status; 284 int ret; 285 286 switch (event) { 287 case SND_SOC_DAPM_POST_PMU: 288 if (!cs35l41->dsp.cs_dsp.running) 289 return wm_adsp_event(w, kcontrol, event); 290 291 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status); 292 if (ret < 0) { 293 dev_err(cs35l41->dev, 294 "Failed to read firmware status: %d\n", ret); 295 return ret; 296 } 297 298 switch (fw_status) { 299 case CSPL_MBOX_STS_RUNNING: 300 case CSPL_MBOX_STS_PAUSED: 301 break; 302 default: 303 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n", 304 fw_status); 305 return -EINVAL; 306 } 307 308 return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_RESUME); 309 case SND_SOC_DAPM_PRE_PMD: 310 return cs35l41_set_cspl_mbox_cmd(cs35l41, CSPL_MBOX_CMD_PAUSE); 311 default: 312 return 0; 313 } 314 } 315 316 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"}; 317 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32}; 318 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum, 319 CS35L41_DAC_PCM1_SRC, 320 0, CS35L41_ASP_SOURCE_MASK, 321 cs35l41_pcm_source_texts, 322 cs35l41_pcm_source_values); 323 324 static const struct snd_kcontrol_new pcm_source_mux = 325 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum); 326 327 static const char * const cs35l41_tx_input_texts[] = { 328 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON", 329 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2" 330 }; 331 332 static const unsigned int cs35l41_tx_input_values[] = { 333 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2, 334 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON, 335 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2 336 }; 337 338 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum, 339 CS35L41_ASP_TX1_SRC, 340 0, CS35L41_ASP_SOURCE_MASK, 341 cs35l41_tx_input_texts, 342 cs35l41_tx_input_values); 343 344 static const struct snd_kcontrol_new asp_tx1_mux = 345 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum); 346 347 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum, 348 CS35L41_ASP_TX2_SRC, 349 0, CS35L41_ASP_SOURCE_MASK, 350 cs35l41_tx_input_texts, 351 cs35l41_tx_input_values); 352 353 static const struct snd_kcontrol_new asp_tx2_mux = 354 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum); 355 356 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum, 357 CS35L41_ASP_TX3_SRC, 358 0, CS35L41_ASP_SOURCE_MASK, 359 cs35l41_tx_input_texts, 360 cs35l41_tx_input_values); 361 362 static const struct snd_kcontrol_new asp_tx3_mux = 363 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum); 364 365 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum, 366 CS35L41_ASP_TX4_SRC, 367 0, CS35L41_ASP_SOURCE_MASK, 368 cs35l41_tx_input_texts, 369 cs35l41_tx_input_values); 370 371 static const struct snd_kcontrol_new asp_tx4_mux = 372 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum); 373 374 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum, 375 CS35L41_DSP1_RX1_SRC, 376 0, CS35L41_ASP_SOURCE_MASK, 377 cs35l41_tx_input_texts, 378 cs35l41_tx_input_values); 379 380 static const struct snd_kcontrol_new dsp_rx1_mux = 381 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum); 382 383 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum, 384 CS35L41_DSP1_RX2_SRC, 385 0, CS35L41_ASP_SOURCE_MASK, 386 cs35l41_tx_input_texts, 387 cs35l41_tx_input_values); 388 389 static const struct snd_kcontrol_new dsp_rx2_mux = 390 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum); 391 392 static const struct snd_kcontrol_new cs35l41_aud_controls[] = { 393 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL, 394 3, 0x4CF, 0x391, dig_vol_tlv), 395 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0, 396 amp_gain_tlv), 397 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp), 398 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0), 399 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0), 400 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0), 401 SOC_SINGLE("Aux Noise Gate CH1 Enable", 402 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0), 403 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay", 404 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0), 405 SOC_SINGLE("Aux Noise Gate CH1 Threshold", 406 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0), 407 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay", 408 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0), 409 SOC_SINGLE("Aux Noise Gate CH2 Enable", 410 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0), 411 SOC_SINGLE("Aux Noise Gate CH2 Threshold", 412 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0), 413 SOC_SINGLE("SCLK Force", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0), 414 SOC_SINGLE("LRCLK Force", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0), 415 SOC_SINGLE("Invert Class D", CS35L41_AMP_DIG_VOL_CTRL, 416 CS35L41_AMP_INV_PCM_SHIFT, 1, 0), 417 SOC_SINGLE("Amp Gain ZC", CS35L41_AMP_GAIN_CTRL, 418 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0), 419 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1), 420 WM_ADSP_FW_CONTROL("DSP1", 0), 421 }; 422 423 static const struct cs35l41_otp_map_element_t *cs35l41_find_otp_map(u32 otp_id) 424 { 425 int i; 426 427 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { 428 if (cs35l41_otp_map_map[i].id == otp_id) 429 return &cs35l41_otp_map_map[i]; 430 } 431 432 return NULL; 433 } 434 435 static int cs35l41_otp_unpack(void *data) 436 { 437 const struct cs35l41_otp_map_element_t *otp_map_match; 438 const struct cs35l41_otp_packed_element_t *otp_map; 439 struct cs35l41_private *cs35l41 = data; 440 int bit_offset, word_offset, ret, i; 441 unsigned int orig_spi_freq; 442 unsigned int bit_sum = 8; 443 u32 otp_val, otp_id_reg; 444 u32 *otp_mem; 445 446 otp_mem = kmalloc_array(CS35L41_OTP_SIZE_WORDS, sizeof(*otp_mem), GFP_KERNEL); 447 if (!otp_mem) 448 return -ENOMEM; 449 450 ret = regmap_read(cs35l41->regmap, CS35L41_OTPID, &otp_id_reg); 451 if (ret < 0) { 452 dev_err(cs35l41->dev, "Read OTP ID failed: %d\n", ret); 453 goto err_otp_unpack; 454 } 455 456 otp_map_match = cs35l41_find_otp_map(otp_id_reg); 457 458 if (!otp_map_match) { 459 dev_err(cs35l41->dev, "OTP Map matching ID %d not found\n", 460 otp_id_reg); 461 ret = -EINVAL; 462 goto err_otp_unpack; 463 } 464 465 if (cs35l41->otp_setup) 466 cs35l41->otp_setup(cs35l41, true, &orig_spi_freq); 467 468 ret = regmap_bulk_read(cs35l41->regmap, CS35L41_OTP_MEM0, otp_mem, 469 CS35L41_OTP_SIZE_WORDS); 470 if (ret < 0) { 471 dev_err(cs35l41->dev, "Read OTP Mem failed: %d\n", ret); 472 goto err_otp_unpack; 473 } 474 475 if (cs35l41->otp_setup) 476 cs35l41->otp_setup(cs35l41, false, &orig_spi_freq); 477 478 otp_map = otp_map_match->map; 479 480 bit_offset = otp_map_match->bit_offset; 481 word_offset = otp_map_match->word_offset; 482 483 ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000055); 484 if (ret < 0) { 485 dev_err(cs35l41->dev, "Write Unlock key failed 1/2: %d\n", ret); 486 goto err_otp_unpack; 487 } 488 ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000AA); 489 if (ret < 0) { 490 dev_err(cs35l41->dev, "Write Unlock key failed 2/2: %d\n", ret); 491 goto err_otp_unpack; 492 } 493 494 for (i = 0; i < otp_map_match->num_elements; i++) { 495 dev_dbg(cs35l41->dev, 496 "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d\n", 497 bit_offset, word_offset, bit_sum % 32); 498 if (bit_offset + otp_map[i].size - 1 >= 32) { 499 otp_val = (otp_mem[word_offset] & 500 GENMASK(31, bit_offset)) >> 501 bit_offset; 502 otp_val |= (otp_mem[++word_offset] & 503 GENMASK(bit_offset + 504 otp_map[i].size - 33, 0)) << 505 (32 - bit_offset); 506 bit_offset += otp_map[i].size - 32; 507 } else { 508 otp_val = (otp_mem[word_offset] & 509 GENMASK(bit_offset + otp_map[i].size - 1, 510 bit_offset)) >> bit_offset; 511 bit_offset += otp_map[i].size; 512 } 513 bit_sum += otp_map[i].size; 514 515 if (bit_offset == 32) { 516 bit_offset = 0; 517 word_offset++; 518 } 519 520 if (otp_map[i].reg != 0) { 521 ret = regmap_update_bits(cs35l41->regmap, 522 otp_map[i].reg, 523 GENMASK(otp_map[i].shift + 524 otp_map[i].size - 1, 525 otp_map[i].shift), 526 otp_val << otp_map[i].shift); 527 if (ret < 0) { 528 dev_err(cs35l41->dev, "Write OTP val failed: %d\n", 529 ret); 530 goto err_otp_unpack; 531 } 532 } 533 } 534 535 ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x000000CC); 536 if (ret < 0) { 537 dev_err(cs35l41->dev, "Write Lock key failed 1/2: %d\n", ret); 538 goto err_otp_unpack; 539 } 540 ret = regmap_write(cs35l41->regmap, CS35L41_TEST_KEY_CTL, 0x00000033); 541 if (ret < 0) { 542 dev_err(cs35l41->dev, "Write Lock key failed 2/2: %d\n", ret); 543 goto err_otp_unpack; 544 } 545 ret = 0; 546 547 err_otp_unpack: 548 kfree(otp_mem); 549 return ret; 550 } 551 552 static irqreturn_t cs35l41_irq(int irq, void *data) 553 { 554 struct cs35l41_private *cs35l41 = data; 555 unsigned int status[4] = { 0, 0, 0, 0 }; 556 unsigned int masks[4] = { 0, 0, 0, 0 }; 557 int ret = IRQ_NONE; 558 unsigned int i; 559 560 for (i = 0; i < ARRAY_SIZE(status); i++) { 561 regmap_read(cs35l41->regmap, 562 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE), 563 &status[i]); 564 regmap_read(cs35l41->regmap, 565 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE), 566 &masks[i]); 567 } 568 569 /* Check to see if unmasked bits are active */ 570 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) && 571 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) 572 return IRQ_NONE; 573 574 if (status[3] & CS35L41_OTP_BOOT_DONE) { 575 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4, 576 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE); 577 } 578 579 /* 580 * The following interrupts require a 581 * protection release cycle to get the 582 * speaker out of Safe-Mode. 583 */ 584 if (status[0] & CS35L41_AMP_SHORT_ERR) { 585 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n"); 586 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 587 CS35L41_AMP_SHORT_ERR); 588 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 589 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 590 CS35L41_AMP_SHORT_ERR_RLS, 591 CS35L41_AMP_SHORT_ERR_RLS); 592 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 593 CS35L41_AMP_SHORT_ERR_RLS, 0); 594 ret = IRQ_HANDLED; 595 } 596 597 if (status[0] & CS35L41_TEMP_WARN) { 598 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n"); 599 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 600 CS35L41_TEMP_WARN); 601 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 602 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 603 CS35L41_TEMP_WARN_ERR_RLS, 604 CS35L41_TEMP_WARN_ERR_RLS); 605 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 606 CS35L41_TEMP_WARN_ERR_RLS, 0); 607 ret = IRQ_HANDLED; 608 } 609 610 if (status[0] & CS35L41_TEMP_ERR) { 611 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n"); 612 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 613 CS35L41_TEMP_ERR); 614 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 615 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 616 CS35L41_TEMP_ERR_RLS, 617 CS35L41_TEMP_ERR_RLS); 618 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 619 CS35L41_TEMP_ERR_RLS, 0); 620 ret = IRQ_HANDLED; 621 } 622 623 if (status[0] & CS35L41_BST_OVP_ERR) { 624 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n"); 625 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 626 CS35L41_BST_EN_MASK, 0); 627 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 628 CS35L41_BST_OVP_ERR); 629 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 630 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 631 CS35L41_BST_OVP_ERR_RLS, 632 CS35L41_BST_OVP_ERR_RLS); 633 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 634 CS35L41_BST_OVP_ERR_RLS, 0); 635 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 636 CS35L41_BST_EN_MASK, 637 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 638 ret = IRQ_HANDLED; 639 } 640 641 if (status[0] & CS35L41_BST_DCM_UVP_ERR) { 642 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n"); 643 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 644 CS35L41_BST_EN_MASK, 0); 645 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 646 CS35L41_BST_DCM_UVP_ERR); 647 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 648 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 649 CS35L41_BST_UVP_ERR_RLS, 650 CS35L41_BST_UVP_ERR_RLS); 651 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 652 CS35L41_BST_UVP_ERR_RLS, 0); 653 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 654 CS35L41_BST_EN_MASK, 655 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 656 ret = IRQ_HANDLED; 657 } 658 659 if (status[0] & CS35L41_BST_SHORT_ERR) { 660 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n"); 661 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 662 CS35L41_BST_EN_MASK, 0); 663 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 664 CS35L41_BST_SHORT_ERR); 665 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0); 666 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 667 CS35L41_BST_SHORT_ERR_RLS, 668 CS35L41_BST_SHORT_ERR_RLS); 669 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 670 CS35L41_BST_SHORT_ERR_RLS, 0); 671 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 672 CS35L41_BST_EN_MASK, 673 CS35L41_BST_EN_DEFAULT << CS35L41_BST_EN_SHIFT); 674 ret = IRQ_HANDLED; 675 } 676 677 return ret; 678 } 679 680 static const struct reg_sequence cs35l41_pup_patch[] = { 681 { 0x00000040, 0x00000055 }, 682 { 0x00000040, 0x000000AA }, 683 { 0x00002084, 0x002F1AA0 }, 684 { 0x00000040, 0x000000CC }, 685 { 0x00000040, 0x00000033 }, 686 }; 687 688 static const struct reg_sequence cs35l41_pdn_patch[] = { 689 { 0x00000040, 0x00000055 }, 690 { 0x00000040, 0x000000AA }, 691 { 0x00002084, 0x002F1AA3 }, 692 { 0x00000040, 0x000000CC }, 693 { 0x00000040, 0x00000033 }, 694 }; 695 696 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w, 697 struct snd_kcontrol *kcontrol, int event) 698 { 699 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 700 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 701 unsigned int val; 702 int ret = 0; 703 704 switch (event) { 705 case SND_SOC_DAPM_POST_PMU: 706 regmap_multi_reg_write_bypassed(cs35l41->regmap, 707 cs35l41_pup_patch, 708 ARRAY_SIZE(cs35l41_pup_patch)); 709 710 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, 711 CS35L41_GLOBAL_EN_MASK, 712 1 << CS35L41_GLOBAL_EN_SHIFT); 713 714 usleep_range(1000, 1100); 715 break; 716 case SND_SOC_DAPM_POST_PMD: 717 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL1, 718 CS35L41_GLOBAL_EN_MASK, 0); 719 720 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 721 val, val & CS35L41_PDN_DONE_MASK, 722 1000, 100000); 723 if (ret) 724 dev_warn(cs35l41->dev, "PDN failed: %d\n", ret); 725 726 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, 727 CS35L41_PDN_DONE_MASK); 728 729 regmap_multi_reg_write_bypassed(cs35l41->regmap, 730 cs35l41_pdn_patch, 731 ARRAY_SIZE(cs35l41_pdn_patch)); 732 break; 733 default: 734 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event); 735 ret = -EINVAL; 736 } 737 738 return ret; 739 } 740 741 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = { 742 SND_SOC_DAPM_SPK("DSP1 Preload", NULL), 743 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0, 744 cs35l41_dsp_preload_ev, 745 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 746 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, 747 cs35l41_dsp_audio_ev, 748 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 749 750 SND_SOC_DAPM_OUTPUT("SPK"), 751 752 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0), 753 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0), 754 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0), 755 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0), 756 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0), 757 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0), 758 759 SND_SOC_DAPM_SIGGEN("VSENSE"), 760 SND_SOC_DAPM_SIGGEN("ISENSE"), 761 SND_SOC_DAPM_SIGGEN("VP"), 762 SND_SOC_DAPM_SIGGEN("VBST"), 763 SND_SOC_DAPM_SIGGEN("TEMP"), 764 765 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0), 766 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0), 767 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0), 768 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0), 769 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0), 770 771 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0), 772 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0), 773 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 774 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0), 775 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0), 776 777 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0), 778 779 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0, 780 cs35l41_main_amp_event, 781 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 782 783 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux), 784 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux), 785 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux), 786 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux), 787 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux), 788 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux), 789 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux), 790 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl), 791 }; 792 793 static const struct snd_soc_dapm_route cs35l41_audio_map[] = { 794 {"DSP RX1 Source", "ASPRX1", "ASPRX1"}, 795 {"DSP RX1 Source", "ASPRX2", "ASPRX2"}, 796 {"DSP RX2 Source", "ASPRX1", "ASPRX1"}, 797 {"DSP RX2 Source", "ASPRX2", "ASPRX2"}, 798 799 {"DSP1", NULL, "DSP RX1 Source"}, 800 {"DSP1", NULL, "DSP RX2 Source"}, 801 802 {"ASP TX1 Source", "VMON", "VMON ADC"}, 803 {"ASP TX1 Source", "IMON", "IMON ADC"}, 804 {"ASP TX1 Source", "VPMON", "VPMON ADC"}, 805 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"}, 806 {"ASP TX1 Source", "DSPTX1", "DSP1"}, 807 {"ASP TX1 Source", "DSPTX2", "DSP1"}, 808 {"ASP TX1 Source", "ASPRX1", "ASPRX1" }, 809 {"ASP TX1 Source", "ASPRX2", "ASPRX2" }, 810 {"ASP TX2 Source", "VMON", "VMON ADC"}, 811 {"ASP TX2 Source", "IMON", "IMON ADC"}, 812 {"ASP TX2 Source", "VPMON", "VPMON ADC"}, 813 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"}, 814 {"ASP TX2 Source", "DSPTX1", "DSP1"}, 815 {"ASP TX2 Source", "DSPTX2", "DSP1"}, 816 {"ASP TX2 Source", "ASPRX1", "ASPRX1" }, 817 {"ASP TX2 Source", "ASPRX2", "ASPRX2" }, 818 {"ASP TX3 Source", "VMON", "VMON ADC"}, 819 {"ASP TX3 Source", "IMON", "IMON ADC"}, 820 {"ASP TX3 Source", "VPMON", "VPMON ADC"}, 821 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"}, 822 {"ASP TX3 Source", "DSPTX1", "DSP1"}, 823 {"ASP TX3 Source", "DSPTX2", "DSP1"}, 824 {"ASP TX3 Source", "ASPRX1", "ASPRX1" }, 825 {"ASP TX3 Source", "ASPRX2", "ASPRX2" }, 826 {"ASP TX4 Source", "VMON", "VMON ADC"}, 827 {"ASP TX4 Source", "IMON", "IMON ADC"}, 828 {"ASP TX4 Source", "VPMON", "VPMON ADC"}, 829 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"}, 830 {"ASP TX4 Source", "DSPTX1", "DSP1"}, 831 {"ASP TX4 Source", "DSPTX2", "DSP1"}, 832 {"ASP TX4 Source", "ASPRX1", "ASPRX1" }, 833 {"ASP TX4 Source", "ASPRX2", "ASPRX2" }, 834 {"ASPTX1", NULL, "ASP TX1 Source"}, 835 {"ASPTX2", NULL, "ASP TX2 Source"}, 836 {"ASPTX3", NULL, "ASP TX3 Source"}, 837 {"ASPTX4", NULL, "ASP TX4 Source"}, 838 {"AMP Capture", NULL, "ASPTX1"}, 839 {"AMP Capture", NULL, "ASPTX2"}, 840 {"AMP Capture", NULL, "ASPTX3"}, 841 {"AMP Capture", NULL, "ASPTX4"}, 842 843 {"DSP1", NULL, "VMON"}, 844 {"DSP1", NULL, "IMON"}, 845 {"DSP1", NULL, "VPMON"}, 846 {"DSP1", NULL, "VBSTMON"}, 847 {"DSP1", NULL, "TEMPMON"}, 848 849 {"VMON ADC", NULL, "VMON"}, 850 {"IMON ADC", NULL, "IMON"}, 851 {"VPMON ADC", NULL, "VPMON"}, 852 {"VBSTMON ADC", NULL, "VBSTMON"}, 853 {"TEMPMON ADC", NULL, "TEMPMON"}, 854 855 {"VMON ADC", NULL, "VSENSE"}, 856 {"IMON ADC", NULL, "ISENSE"}, 857 {"VPMON ADC", NULL, "VP"}, 858 {"VBSTMON ADC", NULL, "VBST"}, 859 {"TEMPMON ADC", NULL, "TEMP"}, 860 861 {"DSP1 Preload", NULL, "DSP1 Preloader"}, 862 {"DSP1", NULL, "DSP1 Preloader"}, 863 864 {"ASPRX1", NULL, "AMP Playback"}, 865 {"ASPRX2", NULL, "AMP Playback"}, 866 {"DRE", "Switch", "CLASS H"}, 867 {"Main AMP", NULL, "CLASS H"}, 868 {"Main AMP", NULL, "DRE"}, 869 {"SPK", NULL, "Main AMP"}, 870 871 {"PCM Source", "ASP", "ASPRX1"}, 872 {"PCM Source", "DSP", "DSP1"}, 873 {"CLASS H", NULL, "PCM Source"}, 874 }; 875 876 static const struct cs_dsp_region cs35l41_dsp1_regions[] = { 877 { .type = WMFW_HALO_PM_PACKED, .base = CS35L41_DSP1_PMEM_0 }, 878 { .type = WMFW_HALO_XM_PACKED, .base = CS35L41_DSP1_XMEM_PACK_0 }, 879 { .type = WMFW_HALO_YM_PACKED, .base = CS35L41_DSP1_YMEM_PACK_0 }, 880 {. type = WMFW_ADSP2_XM, .base = CS35L41_DSP1_XMEM_UNPACK24_0}, 881 {. type = WMFW_ADSP2_YM, .base = CS35L41_DSP1_YMEM_UNPACK24_0}, 882 }; 883 884 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, 885 unsigned int *tx_slot, unsigned int rx_num, 886 unsigned int *rx_slot) 887 { 888 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 889 unsigned int val, mask; 890 int i; 891 892 if (tx_num > 4 || rx_num > 2) 893 return -EINVAL; 894 895 val = 0; 896 mask = 0; 897 for (i = 0; i < rx_num; i++) { 898 dev_dbg(cs35l41->dev, "rx slot %d position = %d\n", i, rx_slot[i]); 899 val |= rx_slot[i] << (i * 8); 900 mask |= 0x3F << (i * 8); 901 } 902 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_RX_SLOT, mask, val); 903 904 val = 0; 905 mask = 0; 906 for (i = 0; i < tx_num; i++) { 907 dev_dbg(cs35l41->dev, "tx slot %d position = %d\n", i, tx_slot[i]); 908 val |= tx_slot[i] << (i * 8); 909 mask |= 0x3F << (i * 8); 910 } 911 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FRAME_TX_SLOT, mask, val); 912 913 return 0; 914 } 915 916 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 917 { 918 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 919 unsigned int daifmt = 0; 920 921 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 922 case SND_SOC_DAIFMT_CBP_CFP: 923 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK; 924 break; 925 case SND_SOC_DAIFMT_CBC_CFC: 926 break; 927 default: 928 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n"); 929 return -EINVAL; 930 } 931 932 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 933 case SND_SOC_DAIFMT_DSP_A: 934 break; 935 case SND_SOC_DAIFMT_I2S: 936 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT; 937 break; 938 default: 939 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n"); 940 return -EINVAL; 941 } 942 943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 944 case SND_SOC_DAIFMT_NB_IF: 945 daifmt |= CS35L41_LRCLK_INV_MASK; 946 break; 947 case SND_SOC_DAIFMT_IB_NF: 948 daifmt |= CS35L41_SCLK_INV_MASK; 949 break; 950 case SND_SOC_DAIFMT_IB_IF: 951 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK; 952 break; 953 case SND_SOC_DAIFMT_NB_NF: 954 break; 955 default: 956 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n"); 957 return -EINVAL; 958 } 959 960 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 961 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK | 962 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK | 963 CS35L41_SCLK_INV_MASK, daifmt); 964 } 965 966 struct cs35l41_global_fs_config { 967 int rate; 968 int fs_cfg; 969 }; 970 971 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = { 972 { 12000, 0x01 }, 973 { 24000, 0x02 }, 974 { 48000, 0x03 }, 975 { 96000, 0x04 }, 976 { 192000, 0x05 }, 977 { 11025, 0x09 }, 978 { 22050, 0x0A }, 979 { 44100, 0x0B }, 980 { 88200, 0x0C }, 981 { 176400, 0x0D }, 982 { 8000, 0x11 }, 983 { 16000, 0x12 }, 984 { 32000, 0x13 }, 985 }; 986 987 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream, 988 struct snd_pcm_hw_params *params, 989 struct snd_soc_dai *dai) 990 { 991 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 992 unsigned int rate = params_rate(params); 993 u8 asp_wl; 994 int i; 995 996 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) { 997 if (rate == cs35l41_fs_rates[i].rate) 998 break; 999 } 1000 1001 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) { 1002 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate); 1003 return -EINVAL; 1004 } 1005 1006 asp_wl = params_width(params); 1007 1008 if (i < ARRAY_SIZE(cs35l41_fs_rates)) 1009 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL, 1010 CS35L41_GLOBAL_FS_MASK, 1011 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT); 1012 1013 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1014 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 1015 CS35L41_ASP_WIDTH_RX_MASK, 1016 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT); 1017 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL, 1018 CS35L41_ASP_RX_WL_MASK, 1019 asp_wl << CS35L41_ASP_RX_WL_SHIFT); 1020 } else { 1021 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT, 1022 CS35L41_ASP_WIDTH_TX_MASK, 1023 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT); 1024 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL, 1025 CS35L41_ASP_TX_WL_MASK, 1026 asp_wl << CS35L41_ASP_TX_WL_SHIFT); 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int cs35l41_get_clk_config(int freq) 1033 { 1034 int i; 1035 1036 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) { 1037 if (cs35l41_pll_sysclk[i].freq == freq) 1038 return cs35l41_pll_sysclk[i].clk_cfg; 1039 } 1040 1041 return -EINVAL; 1042 } 1043 1044 static const unsigned int cs35l41_src_rates[] = { 1045 8000, 12000, 11025, 16000, 22050, 24000, 32000, 1046 44100, 48000, 88200, 96000, 176400, 192000 1047 }; 1048 1049 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = { 1050 .count = ARRAY_SIZE(cs35l41_src_rates), 1051 .list = cs35l41_src_rates, 1052 }; 1053 1054 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream, 1055 struct snd_soc_dai *dai) 1056 { 1057 if (substream->runtime) 1058 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1059 SNDRV_PCM_HW_PARAM_RATE, 1060 &cs35l41_constraints); 1061 return 0; 1062 } 1063 1064 static int cs35l41_component_set_sysclk(struct snd_soc_component *component, 1065 int clk_id, int source, 1066 unsigned int freq, int dir) 1067 { 1068 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 1069 int extclk_cfg, clksrc; 1070 1071 switch (clk_id) { 1072 case CS35L41_CLKID_SCLK: 1073 clksrc = CS35L41_PLLSRC_SCLK; 1074 break; 1075 case CS35L41_CLKID_LRCLK: 1076 clksrc = CS35L41_PLLSRC_LRCLK; 1077 break; 1078 case CS35L41_CLKID_MCLK: 1079 clksrc = CS35L41_PLLSRC_MCLK; 1080 break; 1081 default: 1082 dev_err(cs35l41->dev, "Invalid CLK Config\n"); 1083 return -EINVAL; 1084 } 1085 1086 extclk_cfg = cs35l41_get_clk_config(freq); 1087 1088 if (extclk_cfg < 0) { 1089 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n", 1090 extclk_cfg, freq); 1091 return -EINVAL; 1092 } 1093 1094 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1095 CS35L41_PLL_OPENLOOP_MASK, 1096 1 << CS35L41_PLL_OPENLOOP_SHIFT); 1097 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1098 CS35L41_REFCLK_FREQ_MASK, 1099 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT); 1100 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1101 CS35L41_PLL_CLK_EN_MASK, 1102 0 << CS35L41_PLL_CLK_EN_SHIFT); 1103 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1104 CS35L41_PLL_CLK_SEL_MASK, clksrc); 1105 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1106 CS35L41_PLL_OPENLOOP_MASK, 1107 0 << CS35L41_PLL_OPENLOOP_SHIFT); 1108 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL, 1109 CS35L41_PLL_CLK_EN_MASK, 1110 1 << CS35L41_PLL_CLK_EN_SHIFT); 1111 1112 return 0; 1113 } 1114 1115 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai, 1116 int clk_id, unsigned int freq, int dir) 1117 { 1118 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component); 1119 unsigned int fs1_val; 1120 unsigned int fs2_val; 1121 unsigned int val; 1122 int fsindex; 1123 1124 fsindex = cs35l41_get_fs_mon_config_index(freq); 1125 if (fsindex < 0) { 1126 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq); 1127 return -EINVAL; 1128 } 1129 1130 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq); 1131 1132 if (freq <= 6144000) { 1133 /* Use the lookup table */ 1134 fs1_val = cs35l41_fs_mon[fsindex].fs1; 1135 fs2_val = cs35l41_fs_mon[fsindex].fs2; 1136 } else { 1137 /* Use hard-coded values */ 1138 fs1_val = 0x10; 1139 fs2_val = 0x24; 1140 } 1141 1142 val = fs1_val; 1143 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK; 1144 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val); 1145 1146 return 0; 1147 } 1148 1149 static int cs35l41_boost_config(struct cs35l41_private *cs35l41, 1150 int boost_ind, int boost_cap, int boost_ipk) 1151 { 1152 unsigned char bst_lbst_val, bst_cbst_range, bst_ipk_scaled; 1153 struct regmap *regmap = cs35l41->regmap; 1154 struct device *dev = cs35l41->dev; 1155 int ret; 1156 1157 switch (boost_ind) { 1158 case 1000: /* 1.0 uH */ 1159 bst_lbst_val = 0; 1160 break; 1161 case 1200: /* 1.2 uH */ 1162 bst_lbst_val = 1; 1163 break; 1164 case 1500: /* 1.5 uH */ 1165 bst_lbst_val = 2; 1166 break; 1167 case 2200: /* 2.2 uH */ 1168 bst_lbst_val = 3; 1169 break; 1170 default: 1171 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); 1172 return -EINVAL; 1173 } 1174 1175 switch (boost_cap) { 1176 case 0 ... 19: 1177 bst_cbst_range = 0; 1178 break; 1179 case 20 ... 50: 1180 bst_cbst_range = 1; 1181 break; 1182 case 51 ... 100: 1183 bst_cbst_range = 2; 1184 break; 1185 case 101 ... 200: 1186 bst_cbst_range = 3; 1187 break; 1188 default: /* 201 uF and greater */ 1189 bst_cbst_range = 4; 1190 } 1191 1192 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_COEFF, 1193 CS35L41_BST_K1_MASK | CS35L41_BST_K2_MASK, 1194 cs35l41_bst_k1_table[bst_lbst_val][bst_cbst_range] 1195 << CS35L41_BST_K1_SHIFT | 1196 cs35l41_bst_k2_table[bst_lbst_val][bst_cbst_range] 1197 << CS35L41_BST_K2_SHIFT); 1198 if (ret) { 1199 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); 1200 return ret; 1201 } 1202 1203 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_SLOPE_LBST, 1204 CS35L41_BST_SLOPE_MASK | CS35L41_BST_LBST_VAL_MASK, 1205 cs35l41_bst_slope_table[bst_lbst_val] 1206 << CS35L41_BST_SLOPE_SHIFT | 1207 bst_lbst_val << CS35L41_BST_LBST_VAL_SHIFT); 1208 if (ret) { 1209 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); 1210 return ret; 1211 } 1212 1213 if (boost_ipk < 1600 || boost_ipk > 4500) { 1214 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", 1215 boost_ipk); 1216 return -EINVAL; 1217 } 1218 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; 1219 1220 ret = regmap_update_bits(regmap, CS35L41_BSTCVRT_PEAK_CUR, 1221 CS35L41_BST_IPK_MASK, 1222 bst_ipk_scaled << CS35L41_BST_IPK_SHIFT); 1223 if (ret) { 1224 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); 1225 return ret; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) 1232 { 1233 int ret; 1234 1235 /* Set Platform Data */ 1236 /* Required */ 1237 if (cs35l41->pdata.bst_ipk && 1238 cs35l41->pdata.bst_ind && cs35l41->pdata.bst_cap) { 1239 ret = cs35l41_boost_config(cs35l41, cs35l41->pdata.bst_ind, 1240 cs35l41->pdata.bst_cap, 1241 cs35l41->pdata.bst_ipk); 1242 if (ret) { 1243 dev_err(cs35l41->dev, "Error in Boost DT config: %d\n", ret); 1244 return ret; 1245 } 1246 } else { 1247 dev_err(cs35l41->dev, "Incomplete Boost component DT config\n"); 1248 return -EINVAL; 1249 } 1250 1251 /* Optional */ 1252 if (cs35l41->pdata.dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && 1253 cs35l41->pdata.dout_hiz >= 0) 1254 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, 1255 CS35L41_ASP_DOUT_HIZ_MASK, 1256 cs35l41->pdata.dout_hiz); 1257 1258 return 0; 1259 } 1260 1261 static int cs35l41_irq_gpio_config(struct cs35l41_private *cs35l41) 1262 { 1263 struct cs35l41_irq_cfg *irq_gpio_cfg1 = &cs35l41->pdata.irq_config1; 1264 struct cs35l41_irq_cfg *irq_gpio_cfg2 = &cs35l41->pdata.irq_config2; 1265 int irq_pol = IRQF_TRIGGER_NONE; 1266 1267 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, 1268 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1269 irq_gpio_cfg1->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | 1270 !irq_gpio_cfg1->irq_out_en << CS35L41_GPIO_DIR_SHIFT); 1271 1272 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, 1273 CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, 1274 irq_gpio_cfg1->irq_pol_inv << CS35L41_GPIO_POL_SHIFT | 1275 !irq_gpio_cfg1->irq_out_en << CS35L41_GPIO_DIR_SHIFT); 1276 1277 regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, 1278 CS35L41_GPIO1_CTRL_MASK | CS35L41_GPIO2_CTRL_MASK, 1279 irq_gpio_cfg1->irq_src_sel << CS35L41_GPIO1_CTRL_SHIFT | 1280 irq_gpio_cfg2->irq_src_sel << CS35L41_GPIO2_CTRL_SHIFT); 1281 1282 if ((irq_gpio_cfg2->irq_src_sel == 1283 (CS35L41_GPIO_CTRL_ACTV_LO | CS35L41_VALID_PDATA)) || 1284 (irq_gpio_cfg2->irq_src_sel == 1285 (CS35L41_GPIO_CTRL_OPEN_INT | CS35L41_VALID_PDATA))) 1286 irq_pol = IRQF_TRIGGER_LOW; 1287 else if (irq_gpio_cfg2->irq_src_sel == 1288 (CS35L41_GPIO_CTRL_ACTV_HI | CS35L41_VALID_PDATA)) 1289 irq_pol = IRQF_TRIGGER_HIGH; 1290 1291 return irq_pol; 1292 } 1293 1294 static int cs35l41_component_probe(struct snd_soc_component *component) 1295 { 1296 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 1297 1298 return wm_adsp2_component_probe(&cs35l41->dsp, component); 1299 } 1300 1301 static void cs35l41_component_remove(struct snd_soc_component *component) 1302 { 1303 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); 1304 1305 wm_adsp2_component_remove(&cs35l41->dsp, component); 1306 } 1307 1308 static const struct snd_soc_dai_ops cs35l41_ops = { 1309 .startup = cs35l41_pcm_startup, 1310 .set_fmt = cs35l41_set_dai_fmt, 1311 .hw_params = cs35l41_pcm_hw_params, 1312 .set_sysclk = cs35l41_dai_set_sysclk, 1313 .set_channel_map = cs35l41_set_channel_map, 1314 }; 1315 1316 static struct snd_soc_dai_driver cs35l41_dai[] = { 1317 { 1318 .name = "cs35l41-pcm", 1319 .id = 0, 1320 .playback = { 1321 .stream_name = "AMP Playback", 1322 .channels_min = 1, 1323 .channels_max = 2, 1324 .rates = SNDRV_PCM_RATE_KNOT, 1325 .formats = CS35L41_RX_FORMATS, 1326 }, 1327 .capture = { 1328 .stream_name = "AMP Capture", 1329 .channels_min = 1, 1330 .channels_max = 8, 1331 .rates = SNDRV_PCM_RATE_KNOT, 1332 .formats = CS35L41_TX_FORMATS, 1333 }, 1334 .ops = &cs35l41_ops, 1335 .symmetric_rate = 1, 1336 }, 1337 }; 1338 1339 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = { 1340 .name = "cs35l41-codec", 1341 .probe = cs35l41_component_probe, 1342 .remove = cs35l41_component_remove, 1343 1344 .dapm_widgets = cs35l41_dapm_widgets, 1345 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets), 1346 .dapm_routes = cs35l41_audio_map, 1347 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map), 1348 1349 .controls = cs35l41_aud_controls, 1350 .num_controls = ARRAY_SIZE(cs35l41_aud_controls), 1351 .set_sysclk = cs35l41_component_set_sysclk, 1352 }; 1353 1354 static int cs35l41_handle_pdata(struct device *dev, 1355 struct cs35l41_platform_data *pdata, 1356 struct cs35l41_private *cs35l41) 1357 { 1358 struct cs35l41_irq_cfg *irq_gpio1_config = &pdata->irq_config1; 1359 struct cs35l41_irq_cfg *irq_gpio2_config = &pdata->irq_config2; 1360 unsigned int val; 1361 int ret; 1362 1363 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val); 1364 if (ret >= 0) 1365 pdata->bst_ipk = val; 1366 1367 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val); 1368 if (ret >= 0) 1369 pdata->bst_ind = val; 1370 1371 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val); 1372 if (ret >= 0) 1373 pdata->bst_cap = val; 1374 1375 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val); 1376 if (ret >= 0) 1377 pdata->dout_hiz = val; 1378 else 1379 pdata->dout_hiz = -1; 1380 1381 /* GPIO1 Pin Config */ 1382 irq_gpio1_config->irq_pol_inv = device_property_read_bool(dev, 1383 "cirrus,gpio1-polarity-invert"); 1384 irq_gpio1_config->irq_out_en = device_property_read_bool(dev, 1385 "cirrus,gpio1-output-enable"); 1386 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", 1387 &val); 1388 if (ret >= 0) 1389 irq_gpio1_config->irq_src_sel = val | CS35L41_VALID_PDATA; 1390 1391 /* GPIO2 Pin Config */ 1392 irq_gpio2_config->irq_pol_inv = device_property_read_bool(dev, 1393 "cirrus,gpio2-polarity-invert"); 1394 irq_gpio2_config->irq_out_en = device_property_read_bool(dev, 1395 "cirrus,gpio2-output-enable"); 1396 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", 1397 &val); 1398 if (ret >= 0) 1399 irq_gpio2_config->irq_src_sel = val | CS35L41_VALID_PDATA; 1400 1401 return 0; 1402 } 1403 1404 static const struct reg_sequence cs35l41_reva0_errata_patch[] = { 1405 { 0x00000040, 0x00005555 }, 1406 { 0x00000040, 0x0000AAAA }, 1407 { 0x00003854, 0x05180240 }, 1408 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 1409 { 0x00004310, 0x00000000 }, 1410 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 1411 { CS35L41_OTP_TRIM_30, 0x9091A1C8 }, 1412 { 0x00003014, 0x0200EE0E }, 1413 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 1414 { 0x00000054, 0x00000004 }, 1415 { CS35L41_IRQ1_DB3, 0x00000000 }, 1416 { CS35L41_IRQ2_DB3, 0x00000000 }, 1417 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 1418 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 1419 { 0x00000040, 0x0000CCCC }, 1420 { 0x00000040, 0x00003333 }, 1421 }; 1422 1423 static const struct reg_sequence cs35l41_revb0_errata_patch[] = { 1424 { 0x00000040, 0x00005555 }, 1425 { 0x00000040, 0x0000AAAA }, 1426 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 1427 { 0x00004310, 0x00000000 }, 1428 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 1429 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 1430 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 1431 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 1432 { 0x00000040, 0x0000CCCC }, 1433 { 0x00000040, 0x00003333 }, 1434 }; 1435 1436 static const struct reg_sequence cs35l41_revb2_errata_patch[] = { 1437 { 0x00000040, 0x00005555 }, 1438 { 0x00000040, 0x0000AAAA }, 1439 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 }, 1440 { 0x00004310, 0x00000000 }, 1441 { CS35L41_VPVBST_FS_SEL, 0x00000000 }, 1442 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 }, 1443 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 }, 1444 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 }, 1445 { 0x00000040, 0x0000CCCC }, 1446 { 0x00000040, 0x00003333 }, 1447 }; 1448 1449 static const struct reg_sequence cs35l41_fs_errata_patch[] = { 1450 { CS35L41_DSP1_RX1_RATE, 0x00000001 }, 1451 { CS35L41_DSP1_RX2_RATE, 0x00000001 }, 1452 { CS35L41_DSP1_RX3_RATE, 0x00000001 }, 1453 { CS35L41_DSP1_RX4_RATE, 0x00000001 }, 1454 { CS35L41_DSP1_RX5_RATE, 0x00000001 }, 1455 { CS35L41_DSP1_RX6_RATE, 0x00000001 }, 1456 { CS35L41_DSP1_RX7_RATE, 0x00000001 }, 1457 { CS35L41_DSP1_RX8_RATE, 0x00000001 }, 1458 { CS35L41_DSP1_TX1_RATE, 0x00000001 }, 1459 { CS35L41_DSP1_TX2_RATE, 0x00000001 }, 1460 { CS35L41_DSP1_TX3_RATE, 0x00000001 }, 1461 { CS35L41_DSP1_TX4_RATE, 0x00000001 }, 1462 { CS35L41_DSP1_TX5_RATE, 0x00000001 }, 1463 { CS35L41_DSP1_TX6_RATE, 0x00000001 }, 1464 { CS35L41_DSP1_TX7_RATE, 0x00000001 }, 1465 { CS35L41_DSP1_TX8_RATE, 0x00000001 }, 1466 }; 1467 1468 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41) 1469 { 1470 struct wm_adsp *dsp; 1471 int ret; 1472 1473 dsp = &cs35l41->dsp; 1474 dsp->part = "cs35l41"; 1475 dsp->cs_dsp.num = 1; 1476 dsp->cs_dsp.type = WMFW_HALO; 1477 dsp->cs_dsp.rev = 0; 1478 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */ 1479 dsp->cs_dsp.dev = cs35l41->dev; 1480 dsp->cs_dsp.regmap = cs35l41->regmap; 1481 dsp->cs_dsp.base = CS35L41_DSP1_CTRL_BASE; 1482 dsp->cs_dsp.base_sysinfo = CS35L41_DSP1_SYS_ID; 1483 dsp->cs_dsp.mem = cs35l41_dsp1_regions; 1484 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l41_dsp1_regions); 1485 dsp->cs_dsp.lock_regions = 0xFFFFFFFF; 1486 1487 ret = regmap_multi_reg_write(cs35l41->regmap, cs35l41_fs_errata_patch, 1488 ARRAY_SIZE(cs35l41_fs_errata_patch)); 1489 if (ret < 0) { 1490 dev_err(cs35l41->dev, "Failed to write fs errata: %d\n", ret); 1491 return ret; 1492 } 1493 1494 ret = wm_halo_init(dsp); 1495 if (ret) { 1496 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret); 1497 return ret; 1498 } 1499 1500 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC, 1501 CS35L41_INPUT_SRC_VPMON); 1502 if (ret < 0) { 1503 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret); 1504 goto err_dsp; 1505 } 1506 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC, 1507 CS35L41_INPUT_SRC_CLASSH); 1508 if (ret < 0) { 1509 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret); 1510 goto err_dsp; 1511 } 1512 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC, 1513 CS35L41_INPUT_SRC_TEMPMON); 1514 if (ret < 0) { 1515 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret); 1516 goto err_dsp; 1517 } 1518 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC, 1519 CS35L41_INPUT_SRC_RSVD); 1520 if (ret < 0) { 1521 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret); 1522 goto err_dsp; 1523 } 1524 1525 return 0; 1526 1527 err_dsp: 1528 wm_adsp2_remove(dsp); 1529 1530 return ret; 1531 } 1532 1533 int cs35l41_probe(struct cs35l41_private *cs35l41, 1534 struct cs35l41_platform_data *pdata) 1535 { 1536 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match; 1537 int irq_pol = 0; 1538 int ret; 1539 1540 if (pdata) { 1541 cs35l41->pdata = *pdata; 1542 } else { 1543 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->pdata, cs35l41); 1544 if (ret != 0) 1545 return ret; 1546 } 1547 1548 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++) 1549 cs35l41->supplies[i].supply = cs35l41_supplies[i]; 1550 1551 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES, 1552 cs35l41->supplies); 1553 if (ret != 0) { 1554 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret); 1555 return ret; 1556 } 1557 1558 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1559 if (ret != 0) { 1560 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret); 1561 return ret; 1562 } 1563 1564 /* returning NULL can be an option if in stereo mode */ 1565 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset", 1566 GPIOD_OUT_LOW); 1567 if (IS_ERR(cs35l41->reset_gpio)) { 1568 ret = PTR_ERR(cs35l41->reset_gpio); 1569 cs35l41->reset_gpio = NULL; 1570 if (ret == -EBUSY) { 1571 dev_info(cs35l41->dev, 1572 "Reset line busy, assuming shared reset\n"); 1573 } else { 1574 dev_err(cs35l41->dev, 1575 "Failed to get reset GPIO: %d\n", ret); 1576 goto err; 1577 } 1578 } 1579 if (cs35l41->reset_gpio) { 1580 /* satisfy minimum reset pulse width spec */ 1581 usleep_range(2000, 2100); 1582 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1); 1583 } 1584 1585 usleep_range(2000, 2100); 1586 1587 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4, 1588 int_status, int_status & CS35L41_OTP_BOOT_DONE, 1589 1000, 100000); 1590 if (ret) { 1591 dev_err(cs35l41->dev, 1592 "Failed waiting for OTP_BOOT_DONE: %d\n", ret); 1593 goto err; 1594 } 1595 1596 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status); 1597 if (int_status & CS35L41_OTP_BOOT_ERR) { 1598 dev_err(cs35l41->dev, "OTP Boot error\n"); 1599 ret = -EINVAL; 1600 goto err; 1601 } 1602 1603 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id); 1604 if (ret < 0) { 1605 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret); 1606 goto err; 1607 } 1608 1609 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid); 1610 if (ret < 0) { 1611 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret); 1612 goto err; 1613 } 1614 1615 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK; 1616 1617 /* CS35L41 will have even MTLREVID 1618 * CS35L41R will have odd MTLREVID 1619 */ 1620 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID; 1621 if (regid != chipid_match) { 1622 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n", 1623 regid, chipid_match); 1624 ret = -ENODEV; 1625 goto err; 1626 } 1627 1628 switch (reg_revid) { 1629 case CS35L41_REVID_A0: 1630 ret = regmap_register_patch(cs35l41->regmap, 1631 cs35l41_reva0_errata_patch, 1632 ARRAY_SIZE(cs35l41_reva0_errata_patch)); 1633 if (ret < 0) { 1634 dev_err(cs35l41->dev, 1635 "Failed to apply A0 errata patch: %d\n", ret); 1636 goto err; 1637 } 1638 break; 1639 case CS35L41_REVID_B0: 1640 ret = regmap_register_patch(cs35l41->regmap, 1641 cs35l41_revb0_errata_patch, 1642 ARRAY_SIZE(cs35l41_revb0_errata_patch)); 1643 if (ret < 0) { 1644 dev_err(cs35l41->dev, 1645 "Failed to apply B0 errata patch: %d\n", ret); 1646 goto err; 1647 } 1648 break; 1649 case CS35L41_REVID_B2: 1650 ret = regmap_register_patch(cs35l41->regmap, 1651 cs35l41_revb2_errata_patch, 1652 ARRAY_SIZE(cs35l41_revb2_errata_patch)); 1653 if (ret < 0) { 1654 dev_err(cs35l41->dev, 1655 "Failed to apply B2 errata patch: %d\n", ret); 1656 goto err; 1657 } 1658 break; 1659 } 1660 1661 irq_pol = cs35l41_irq_gpio_config(cs35l41); 1662 1663 /* Set interrupt masks for critical errors */ 1664 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 1665 CS35L41_INT1_MASK_DEFAULT); 1666 1667 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq, 1668 IRQF_ONESHOT | IRQF_SHARED | irq_pol, 1669 "cs35l41", cs35l41); 1670 1671 /* CS35L41 needs INT for PDN_DONE */ 1672 if (ret != 0) { 1673 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret); 1674 goto err; 1675 } 1676 1677 ret = cs35l41_otp_unpack(cs35l41); 1678 if (ret < 0) { 1679 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret); 1680 goto err; 1681 } 1682 1683 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_CCM_CORE_CTRL, 0); 1684 if (ret < 0) { 1685 dev_err(cs35l41->dev, "Write CCM_CORE_CTRL failed: %d\n", ret); 1686 goto err; 1687 } 1688 1689 ret = regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, 1690 CS35L41_AMP_EN_MASK, 0); 1691 if (ret < 0) { 1692 dev_err(cs35l41->dev, "Write CS35L41_PWR_CTRL2 failed: %d\n", ret); 1693 goto err; 1694 } 1695 1696 ret = regmap_update_bits(cs35l41->regmap, CS35L41_AMP_GAIN_CTRL, 1697 CS35L41_AMP_GAIN_PCM_MASK, 0); 1698 if (ret < 0) { 1699 dev_err(cs35l41->dev, "Write CS35L41_AMP_GAIN_CTRL failed: %d\n", ret); 1700 goto err; 1701 } 1702 1703 ret = cs35l41_set_pdata(cs35l41); 1704 if (ret < 0) { 1705 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret); 1706 goto err; 1707 } 1708 1709 ret = cs35l41_dsp_init(cs35l41); 1710 if (ret < 0) 1711 goto err; 1712 1713 ret = devm_snd_soc_register_component(cs35l41->dev, 1714 &soc_component_dev_cs35l41, 1715 cs35l41_dai, ARRAY_SIZE(cs35l41_dai)); 1716 if (ret < 0) { 1717 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret); 1718 goto err_dsp; 1719 } 1720 1721 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n", 1722 regid, reg_revid); 1723 1724 return 0; 1725 1726 err_dsp: 1727 wm_adsp2_remove(&cs35l41->dsp); 1728 err: 1729 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1730 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1731 1732 return ret; 1733 } 1734 EXPORT_SYMBOL_GPL(cs35l41_probe); 1735 1736 void cs35l41_remove(struct cs35l41_private *cs35l41) 1737 { 1738 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF); 1739 wm_adsp2_remove(&cs35l41->dsp); 1740 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies); 1741 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0); 1742 } 1743 EXPORT_SYMBOL_GPL(cs35l41_remove); 1744 1745 MODULE_DESCRIPTION("ASoC CS35L41 driver"); 1746 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>"); 1747 MODULE_LICENSE("GPL"); 1748