1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs35l33.c -- CS35L33 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: Paul Handrigan <paul.handrigan@cirrus.com> 8 */ 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/i2c.h> 15 #include <linux/slab.h> 16 #include <linux/workqueue.h> 17 #include <linux/platform_device.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/soc-dapm.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <linux/gpio/consumer.h> 26 #include <sound/cs35l33.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/regulator/machine.h> 30 #include <linux/of.h> 31 32 #include "cs35l33.h" 33 #include "cirrus_legacy.h" 34 35 #define CS35L33_BOOT_DELAY 50 36 37 struct cs35l33_private { 38 struct snd_soc_component *component; 39 struct cs35l33_pdata pdata; 40 struct regmap *regmap; 41 struct gpio_desc *reset_gpio; 42 bool amp_cal; 43 int mclk_int; 44 struct regulator_bulk_data core_supplies[2]; 45 int num_core_supplies; 46 bool is_tdm_mode; 47 bool enable_soft_ramp; 48 }; 49 50 static const struct reg_default cs35l33_reg[] = { 51 {CS35L33_PWRCTL1, 0x85}, 52 {CS35L33_PWRCTL2, 0xFE}, 53 {CS35L33_CLK_CTL, 0x0C}, 54 {CS35L33_BST_PEAK_CTL, 0x90}, 55 {CS35L33_PROTECT_CTL, 0x55}, 56 {CS35L33_BST_CTL1, 0x00}, 57 {CS35L33_BST_CTL2, 0x01}, 58 {CS35L33_ADSP_CTL, 0x00}, 59 {CS35L33_ADC_CTL, 0xC8}, 60 {CS35L33_DAC_CTL, 0x14}, 61 {CS35L33_DIG_VOL_CTL, 0x00}, 62 {CS35L33_CLASSD_CTL, 0x04}, 63 {CS35L33_AMP_CTL, 0x90}, 64 {CS35L33_INT_MASK_1, 0xFF}, 65 {CS35L33_INT_MASK_2, 0xFF}, 66 {CS35L33_DIAG_LOCK, 0x00}, 67 {CS35L33_DIAG_CTRL_1, 0x40}, 68 {CS35L33_DIAG_CTRL_2, 0x00}, 69 {CS35L33_HG_MEMLDO_CTL, 0x62}, 70 {CS35L33_HG_REL_RATE, 0x03}, 71 {CS35L33_LDO_DEL, 0x12}, 72 {CS35L33_HG_HEAD, 0x0A}, 73 {CS35L33_HG_EN, 0x05}, 74 {CS35L33_TX_VMON, 0x00}, 75 {CS35L33_TX_IMON, 0x03}, 76 {CS35L33_TX_VPMON, 0x02}, 77 {CS35L33_TX_VBSTMON, 0x05}, 78 {CS35L33_TX_FLAG, 0x06}, 79 {CS35L33_TX_EN1, 0x00}, 80 {CS35L33_TX_EN2, 0x00}, 81 {CS35L33_TX_EN3, 0x00}, 82 {CS35L33_TX_EN4, 0x00}, 83 {CS35L33_RX_AUD, 0x40}, 84 {CS35L33_RX_SPLY, 0x03}, 85 {CS35L33_RX_ALIVE, 0x04}, 86 {CS35L33_BST_CTL4, 0x63}, 87 }; 88 89 static const struct reg_sequence cs35l33_patch[] = { 90 { 0x00, 0x99, 0 }, 91 { 0x59, 0x02, 0 }, 92 { 0x52, 0x30, 0 }, 93 { 0x39, 0x45, 0 }, 94 { 0x57, 0x30, 0 }, 95 { 0x2C, 0x68, 0 }, 96 { 0x00, 0x00, 0 }, 97 }; 98 99 static bool cs35l33_volatile_register(struct device *dev, unsigned int reg) 100 { 101 switch (reg) { 102 case CS35L33_DEVID_AB: 103 case CS35L33_DEVID_CD: 104 case CS35L33_DEVID_E: 105 case CS35L33_REV_ID: 106 case CS35L33_INT_STATUS_1: 107 case CS35L33_INT_STATUS_2: 108 case CS35L33_HG_STATUS: 109 return true; 110 default: 111 return false; 112 } 113 } 114 115 static bool cs35l33_writeable_register(struct device *dev, unsigned int reg) 116 { 117 switch (reg) { 118 /* these are read only registers */ 119 case CS35L33_DEVID_AB: 120 case CS35L33_DEVID_CD: 121 case CS35L33_DEVID_E: 122 case CS35L33_REV_ID: 123 case CS35L33_INT_STATUS_1: 124 case CS35L33_INT_STATUS_2: 125 case CS35L33_HG_STATUS: 126 return false; 127 default: 128 return true; 129 } 130 } 131 132 static bool cs35l33_readable_register(struct device *dev, unsigned int reg) 133 { 134 switch (reg) { 135 case CS35L33_DEVID_AB: 136 case CS35L33_DEVID_CD: 137 case CS35L33_DEVID_E: 138 case CS35L33_REV_ID: 139 case CS35L33_PWRCTL1: 140 case CS35L33_PWRCTL2: 141 case CS35L33_CLK_CTL: 142 case CS35L33_BST_PEAK_CTL: 143 case CS35L33_PROTECT_CTL: 144 case CS35L33_BST_CTL1: 145 case CS35L33_BST_CTL2: 146 case CS35L33_ADSP_CTL: 147 case CS35L33_ADC_CTL: 148 case CS35L33_DAC_CTL: 149 case CS35L33_DIG_VOL_CTL: 150 case CS35L33_CLASSD_CTL: 151 case CS35L33_AMP_CTL: 152 case CS35L33_INT_MASK_1: 153 case CS35L33_INT_MASK_2: 154 case CS35L33_INT_STATUS_1: 155 case CS35L33_INT_STATUS_2: 156 case CS35L33_DIAG_LOCK: 157 case CS35L33_DIAG_CTRL_1: 158 case CS35L33_DIAG_CTRL_2: 159 case CS35L33_HG_MEMLDO_CTL: 160 case CS35L33_HG_REL_RATE: 161 case CS35L33_LDO_DEL: 162 case CS35L33_HG_HEAD: 163 case CS35L33_HG_EN: 164 case CS35L33_TX_VMON: 165 case CS35L33_TX_IMON: 166 case CS35L33_TX_VPMON: 167 case CS35L33_TX_VBSTMON: 168 case CS35L33_TX_FLAG: 169 case CS35L33_TX_EN1: 170 case CS35L33_TX_EN2: 171 case CS35L33_TX_EN3: 172 case CS35L33_TX_EN4: 173 case CS35L33_RX_AUD: 174 case CS35L33_RX_SPLY: 175 case CS35L33_RX_ALIVE: 176 case CS35L33_BST_CTL4: 177 return true; 178 default: 179 return false; 180 } 181 } 182 183 static DECLARE_TLV_DB_SCALE(classd_ctl_tlv, 900, 100, 0); 184 static DECLARE_TLV_DB_SCALE(dac_tlv, -10200, 50, 0); 185 186 static const struct snd_kcontrol_new cs35l33_snd_controls[] = { 187 188 SOC_SINGLE_TLV("SPK Amp Volume", CS35L33_AMP_CTL, 189 4, 0x09, 0, classd_ctl_tlv), 190 SOC_SINGLE_SX_TLV("DAC Volume", CS35L33_DIG_VOL_CTL, 191 0, 0x34, 0xE4, dac_tlv), 192 }; 193 194 static int cs35l33_spkrdrv_event(struct snd_soc_dapm_widget *w, 195 struct snd_kcontrol *kcontrol, int event) 196 { 197 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 198 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 199 200 switch (event) { 201 case SND_SOC_DAPM_POST_PMU: 202 if (!priv->amp_cal) { 203 usleep_range(8000, 9000); 204 priv->amp_cal = true; 205 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, 206 CS35L33_AMP_CAL, 0); 207 dev_dbg(component->dev, "Amp calibration done\n"); 208 } 209 dev_dbg(component->dev, "Amp turned on\n"); 210 break; 211 case SND_SOC_DAPM_POST_PMD: 212 dev_dbg(component->dev, "Amp turned off\n"); 213 break; 214 default: 215 dev_err(component->dev, "Invalid event = 0x%x\n", event); 216 break; 217 } 218 219 return 0; 220 } 221 222 static int cs35l33_sdin_event(struct snd_soc_dapm_widget *w, 223 struct snd_kcontrol *kcontrol, int event) 224 { 225 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 226 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 227 unsigned int val; 228 229 switch (event) { 230 case SND_SOC_DAPM_PRE_PMU: 231 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 232 CS35L33_PDN_BST, 0); 233 val = priv->is_tdm_mode ? 0 : CS35L33_PDN_TDM; 234 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 235 CS35L33_PDN_TDM, val); 236 dev_dbg(component->dev, "BST turned on\n"); 237 break; 238 case SND_SOC_DAPM_POST_PMU: 239 dev_dbg(component->dev, "SDIN turned on\n"); 240 if (!priv->amp_cal) { 241 regmap_update_bits(priv->regmap, CS35L33_CLASSD_CTL, 242 CS35L33_AMP_CAL, CS35L33_AMP_CAL); 243 dev_dbg(component->dev, "Amp calibration started\n"); 244 usleep_range(10000, 11000); 245 } 246 break; 247 case SND_SOC_DAPM_POST_PMD: 248 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 249 CS35L33_PDN_TDM, CS35L33_PDN_TDM); 250 usleep_range(4000, 4100); 251 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 252 CS35L33_PDN_BST, CS35L33_PDN_BST); 253 dev_dbg(component->dev, "BST and SDIN turned off\n"); 254 break; 255 default: 256 dev_err(component->dev, "Invalid event = 0x%x\n", event); 257 258 } 259 260 return 0; 261 } 262 263 static int cs35l33_sdout_event(struct snd_soc_dapm_widget *w, 264 struct snd_kcontrol *kcontrol, int event) 265 { 266 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 267 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 268 unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; 269 unsigned int mask2 = CS35L33_SDOUT_3ST_TDM; 270 unsigned int val, val2; 271 272 switch (event) { 273 case SND_SOC_DAPM_PRE_PMU: 274 if (priv->is_tdm_mode) { 275 /* set sdout_3st_i2s and reset pdn_tdm */ 276 val = CS35L33_SDOUT_3ST_I2S; 277 /* reset sdout_3st_tdm */ 278 val2 = 0; 279 } else { 280 /* reset sdout_3st_i2s and set pdn_tdm */ 281 val = CS35L33_PDN_TDM; 282 /* set sdout_3st_tdm */ 283 val2 = CS35L33_SDOUT_3ST_TDM; 284 } 285 dev_dbg(component->dev, "SDOUT turned on\n"); 286 break; 287 case SND_SOC_DAPM_PRE_PMD: 288 val = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; 289 val2 = CS35L33_SDOUT_3ST_TDM; 290 dev_dbg(component->dev, "SDOUT turned off\n"); 291 break; 292 default: 293 dev_err(component->dev, "Invalid event = 0x%x\n", event); 294 return 0; 295 } 296 297 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 298 mask, val); 299 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 300 mask2, val2); 301 302 return 0; 303 } 304 305 static const struct snd_soc_dapm_widget cs35l33_dapm_widgets[] = { 306 307 SND_SOC_DAPM_OUTPUT("SPK"), 308 SND_SOC_DAPM_OUT_DRV_E("SPKDRV", CS35L33_PWRCTL1, 7, 1, NULL, 0, 309 cs35l33_spkrdrv_event, 310 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 311 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L33_PWRCTL2, 312 2, 1, cs35l33_sdin_event, SND_SOC_DAPM_PRE_PMU | 313 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 314 315 SND_SOC_DAPM_INPUT("MON"), 316 317 SND_SOC_DAPM_ADC("VMON", NULL, 318 CS35L33_PWRCTL2, CS35L33_PDN_VMON_SHIFT, 1), 319 SND_SOC_DAPM_ADC("IMON", NULL, 320 CS35L33_PWRCTL2, CS35L33_PDN_IMON_SHIFT, 1), 321 SND_SOC_DAPM_ADC("VPMON", NULL, 322 CS35L33_PWRCTL2, CS35L33_PDN_VPMON_SHIFT, 1), 323 SND_SOC_DAPM_ADC("VBSTMON", NULL, 324 CS35L33_PWRCTL2, CS35L33_PDN_VBSTMON_SHIFT, 1), 325 326 SND_SOC_DAPM_AIF_OUT_E("SDOUT", NULL, 0, SND_SOC_NOPM, 0, 0, 327 cs35l33_sdout_event, SND_SOC_DAPM_PRE_PMU | 328 SND_SOC_DAPM_PRE_PMD), 329 }; 330 331 static const struct snd_soc_dapm_route cs35l33_audio_map[] = { 332 {"SDIN", NULL, "CS35L33 Playback"}, 333 {"SPKDRV", NULL, "SDIN"}, 334 {"SPK", NULL, "SPKDRV"}, 335 336 {"VMON", NULL, "MON"}, 337 {"IMON", NULL, "MON"}, 338 339 {"SDOUT", NULL, "VMON"}, 340 {"SDOUT", NULL, "IMON"}, 341 {"CS35L33 Capture", NULL, "SDOUT"}, 342 }; 343 344 static const struct snd_soc_dapm_route cs35l33_vphg_auto_route[] = { 345 {"SPKDRV", NULL, "VPMON"}, 346 {"VPMON", NULL, "CS35L33 Playback"}, 347 }; 348 349 static const struct snd_soc_dapm_route cs35l33_vp_vbst_mon_route[] = { 350 {"SDOUT", NULL, "VPMON"}, 351 {"VPMON", NULL, "MON"}, 352 {"SDOUT", NULL, "VBSTMON"}, 353 {"VBSTMON", NULL, "MON"}, 354 }; 355 356 static int cs35l33_set_bias_level(struct snd_soc_component *component, 357 enum snd_soc_bias_level level) 358 { 359 unsigned int val; 360 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 361 362 switch (level) { 363 case SND_SOC_BIAS_ON: 364 break; 365 case SND_SOC_BIAS_PREPARE: 366 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 367 CS35L33_PDN_ALL, 0); 368 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 369 CS35L33_MCLKDIS, 0); 370 break; 371 case SND_SOC_BIAS_STANDBY: 372 regmap_update_bits(priv->regmap, CS35L33_PWRCTL1, 373 CS35L33_PDN_ALL, CS35L33_PDN_ALL); 374 regmap_read(priv->regmap, CS35L33_INT_STATUS_2, &val); 375 usleep_range(1000, 1100); 376 if (val & CS35L33_PDN_DONE) 377 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 378 CS35L33_MCLKDIS, CS35L33_MCLKDIS); 379 break; 380 case SND_SOC_BIAS_OFF: 381 break; 382 default: 383 return -EINVAL; 384 } 385 386 return 0; 387 } 388 389 struct cs35l33_mclk_div { 390 int mclk; 391 int srate; 392 u8 adsp_rate; 393 u8 int_fs_ratio; 394 }; 395 396 static const struct cs35l33_mclk_div cs35l33_mclk_coeffs[] = { 397 /* MCLK, Sample Rate, adsp_rate, int_fs_ratio */ 398 {5644800, 11025, 0x4, CS35L33_INT_FS_RATE}, 399 {5644800, 22050, 0x8, CS35L33_INT_FS_RATE}, 400 {5644800, 44100, 0xC, CS35L33_INT_FS_RATE}, 401 402 {6000000, 8000, 0x1, 0}, 403 {6000000, 11025, 0x2, 0}, 404 {6000000, 11029, 0x3, 0}, 405 {6000000, 12000, 0x4, 0}, 406 {6000000, 16000, 0x5, 0}, 407 {6000000, 22050, 0x6, 0}, 408 {6000000, 22059, 0x7, 0}, 409 {6000000, 24000, 0x8, 0}, 410 {6000000, 32000, 0x9, 0}, 411 {6000000, 44100, 0xA, 0}, 412 {6000000, 44118, 0xB, 0}, 413 {6000000, 48000, 0xC, 0}, 414 415 {6144000, 8000, 0x1, CS35L33_INT_FS_RATE}, 416 {6144000, 12000, 0x4, CS35L33_INT_FS_RATE}, 417 {6144000, 16000, 0x5, CS35L33_INT_FS_RATE}, 418 {6144000, 24000, 0x8, CS35L33_INT_FS_RATE}, 419 {6144000, 32000, 0x9, CS35L33_INT_FS_RATE}, 420 {6144000, 48000, 0xC, CS35L33_INT_FS_RATE}, 421 }; 422 423 static int cs35l33_get_mclk_coeff(int mclk, int srate) 424 { 425 int i; 426 427 for (i = 0; i < ARRAY_SIZE(cs35l33_mclk_coeffs); i++) { 428 if (cs35l33_mclk_coeffs[i].mclk == mclk && 429 cs35l33_mclk_coeffs[i].srate == srate) 430 return i; 431 } 432 return -EINVAL; 433 } 434 435 static int cs35l33_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 436 { 437 struct snd_soc_component *component = codec_dai->component; 438 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 439 440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 441 case SND_SOC_DAIFMT_CBM_CFM: 442 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, 443 CS35L33_MS_MASK, CS35L33_MS_MASK); 444 dev_dbg(component->dev, "Audio port in master mode\n"); 445 break; 446 case SND_SOC_DAIFMT_CBS_CFS: 447 regmap_update_bits(priv->regmap, CS35L33_ADSP_CTL, 448 CS35L33_MS_MASK, 0); 449 dev_dbg(component->dev, "Audio port in slave mode\n"); 450 break; 451 default: 452 return -EINVAL; 453 } 454 455 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 456 case SND_SOC_DAIFMT_DSP_A: 457 /* 458 * tdm mode in cs35l33 resembles dsp-a mode very 459 * closely, it is dsp-a with fsync shifted left by half bclk 460 */ 461 priv->is_tdm_mode = true; 462 dev_dbg(component->dev, "Audio port in TDM mode\n"); 463 break; 464 case SND_SOC_DAIFMT_I2S: 465 priv->is_tdm_mode = false; 466 dev_dbg(component->dev, "Audio port in I2S mode\n"); 467 break; 468 default: 469 return -EINVAL; 470 } 471 472 return 0; 473 } 474 475 static int cs35l33_pcm_hw_params(struct snd_pcm_substream *substream, 476 struct snd_pcm_hw_params *params, 477 struct snd_soc_dai *dai) 478 { 479 struct snd_soc_component *component = dai->component; 480 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 481 int sample_size = params_width(params); 482 int coeff = cs35l33_get_mclk_coeff(priv->mclk_int, params_rate(params)); 483 484 if (coeff < 0) 485 return coeff; 486 487 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 488 CS35L33_ADSP_FS | CS35L33_INT_FS_RATE, 489 cs35l33_mclk_coeffs[coeff].int_fs_ratio 490 | cs35l33_mclk_coeffs[coeff].adsp_rate); 491 492 if (priv->is_tdm_mode) { 493 sample_size = (sample_size / 8) - 1; 494 if (sample_size > 2) 495 sample_size = 2; 496 regmap_update_bits(priv->regmap, CS35L33_RX_AUD, 497 CS35L33_AUDIN_RX_DEPTH, 498 sample_size << CS35L33_AUDIN_RX_DEPTH_SHIFT); 499 } 500 501 dev_dbg(component->dev, "sample rate=%d, bits per sample=%d\n", 502 params_rate(params), params_width(params)); 503 504 return 0; 505 } 506 507 static const unsigned int cs35l33_src_rates[] = { 508 8000, 11025, 11029, 12000, 16000, 22050, 509 22059, 24000, 32000, 44100, 44118, 48000 510 }; 511 512 static const struct snd_pcm_hw_constraint_list cs35l33_constraints = { 513 .count = ARRAY_SIZE(cs35l33_src_rates), 514 .list = cs35l33_src_rates, 515 }; 516 517 static int cs35l33_pcm_startup(struct snd_pcm_substream *substream, 518 struct snd_soc_dai *dai) 519 { 520 snd_pcm_hw_constraint_list(substream->runtime, 0, 521 SNDRV_PCM_HW_PARAM_RATE, 522 &cs35l33_constraints); 523 return 0; 524 } 525 526 static int cs35l33_set_tristate(struct snd_soc_dai *dai, int tristate) 527 { 528 struct snd_soc_component *component = dai->component; 529 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 530 531 if (tristate) { 532 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 533 CS35L33_SDOUT_3ST_I2S, CS35L33_SDOUT_3ST_I2S); 534 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 535 CS35L33_SDOUT_3ST_TDM, CS35L33_SDOUT_3ST_TDM); 536 } else { 537 regmap_update_bits(priv->regmap, CS35L33_PWRCTL2, 538 CS35L33_SDOUT_3ST_I2S, 0); 539 regmap_update_bits(priv->regmap, CS35L33_CLK_CTL, 540 CS35L33_SDOUT_3ST_TDM, 0); 541 } 542 543 return 0; 544 } 545 546 static int cs35l33_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 547 unsigned int rx_mask, int slots, int slot_width) 548 { 549 struct snd_soc_component *component = dai->component; 550 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 551 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 552 unsigned int reg, bit_pos, i; 553 int slot, slot_num; 554 555 if (slot_width != 8) 556 return -EINVAL; 557 558 /* scan rx_mask for aud slot */ 559 slot = ffs(rx_mask) - 1; 560 if (slot >= 0) { 561 regmap_update_bits(priv->regmap, CS35L33_RX_AUD, 562 CS35L33_X_LOC, slot); 563 dev_dbg(component->dev, "Audio starts from slots %d", slot); 564 } 565 566 /* 567 * scan tx_mask: vmon(2 slots); imon (2 slots); 568 * vpmon (1 slot) vbstmon (1 slot) 569 */ 570 slot = ffs(tx_mask) - 1; 571 slot_num = 0; 572 573 for (i = 0; i < 2 ; i++) { 574 /* disable vpmon/vbstmon: enable later if set in tx_mask */ 575 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON + i, 576 CS35L33_X_STATE | CS35L33_X_LOC, CS35L33_X_STATE 577 | CS35L33_X_LOC); 578 } 579 580 /* disconnect {vp,vbst}_mon routes: eanble later if set in tx_mask*/ 581 snd_soc_dapm_del_routes(dapm, cs35l33_vp_vbst_mon_route, 582 ARRAY_SIZE(cs35l33_vp_vbst_mon_route)); 583 584 while (slot >= 0) { 585 /* configure VMON_TX_LOC */ 586 if (slot_num == 0) { 587 regmap_update_bits(priv->regmap, CS35L33_TX_VMON, 588 CS35L33_X_STATE | CS35L33_X_LOC, slot); 589 dev_dbg(component->dev, "VMON enabled in slots %d-%d", 590 slot, slot + 1); 591 } 592 593 /* configure IMON_TX_LOC */ 594 if (slot_num == 3) { 595 regmap_update_bits(priv->regmap, CS35L33_TX_IMON, 596 CS35L33_X_STATE | CS35L33_X_LOC, slot); 597 dev_dbg(component->dev, "IMON enabled in slots %d-%d", 598 slot, slot + 1); 599 } 600 601 /* configure VPMON_TX_LOC */ 602 if (slot_num == 4) { 603 regmap_update_bits(priv->regmap, CS35L33_TX_VPMON, 604 CS35L33_X_STATE | CS35L33_X_LOC, slot); 605 snd_soc_dapm_add_routes(dapm, 606 &cs35l33_vp_vbst_mon_route[0], 2); 607 dev_dbg(component->dev, "VPMON enabled in slots %d", slot); 608 } 609 610 /* configure VBSTMON_TX_LOC */ 611 if (slot_num == 5) { 612 regmap_update_bits(priv->regmap, CS35L33_TX_VBSTMON, 613 CS35L33_X_STATE | CS35L33_X_LOC, slot); 614 snd_soc_dapm_add_routes(dapm, 615 &cs35l33_vp_vbst_mon_route[2], 2); 616 dev_dbg(component->dev, 617 "VBSTMON enabled in slots %d", slot); 618 } 619 620 /* Enable the relevant tx slot */ 621 reg = CS35L33_TX_EN4 - (slot/8); 622 bit_pos = slot - ((slot / 8) * (8)); 623 regmap_update_bits(priv->regmap, reg, 624 1 << bit_pos, 1 << bit_pos); 625 626 tx_mask &= ~(1 << slot); 627 slot = ffs(tx_mask) - 1; 628 slot_num++; 629 } 630 631 return 0; 632 } 633 634 static int cs35l33_component_set_sysclk(struct snd_soc_component *component, 635 int clk_id, int source, unsigned int freq, int dir) 636 { 637 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 638 639 switch (freq) { 640 case CS35L33_MCLK_5644: 641 case CS35L33_MCLK_6: 642 case CS35L33_MCLK_6144: 643 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 644 CS35L33_MCLKDIV2, 0); 645 cs35l33->mclk_int = freq; 646 break; 647 case CS35L33_MCLK_11289: 648 case CS35L33_MCLK_12: 649 case CS35L33_MCLK_12288: 650 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 651 CS35L33_MCLKDIV2, CS35L33_MCLKDIV2); 652 cs35l33->mclk_int = freq/2; 653 break; 654 default: 655 cs35l33->mclk_int = 0; 656 return -EINVAL; 657 } 658 659 dev_dbg(component->dev, "external mclk freq=%d, internal mclk freq=%d\n", 660 freq, cs35l33->mclk_int); 661 662 return 0; 663 } 664 665 static const struct snd_soc_dai_ops cs35l33_ops = { 666 .startup = cs35l33_pcm_startup, 667 .set_tristate = cs35l33_set_tristate, 668 .set_fmt = cs35l33_set_dai_fmt, 669 .hw_params = cs35l33_pcm_hw_params, 670 .set_tdm_slot = cs35l33_set_tdm_slot, 671 }; 672 673 static struct snd_soc_dai_driver cs35l33_dai = { 674 .name = "cs35l33-dai", 675 .id = 0, 676 .playback = { 677 .stream_name = "CS35L33 Playback", 678 .channels_min = 1, 679 .channels_max = 1, 680 .rates = CS35L33_RATES, 681 .formats = CS35L33_FORMATS, 682 }, 683 .capture = { 684 .stream_name = "CS35L33 Capture", 685 .channels_min = 2, 686 .channels_max = 2, 687 .rates = CS35L33_RATES, 688 .formats = CS35L33_FORMATS, 689 }, 690 .ops = &cs35l33_ops, 691 .symmetric_rate = 1, 692 }; 693 694 static int cs35l33_set_hg_data(struct snd_soc_component *component, 695 struct cs35l33_pdata *pdata) 696 { 697 struct cs35l33_hg *hg_config = &pdata->hg_config; 698 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 699 struct cs35l33_private *priv = snd_soc_component_get_drvdata(component); 700 701 if (hg_config->enable_hg_algo) { 702 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 703 CS35L33_MEM_DEPTH_MASK, 704 hg_config->mem_depth << CS35L33_MEM_DEPTH_SHIFT); 705 regmap_write(priv->regmap, CS35L33_HG_REL_RATE, 706 hg_config->release_rate); 707 regmap_update_bits(priv->regmap, CS35L33_HG_HEAD, 708 CS35L33_HD_RM_MASK, 709 hg_config->hd_rm << CS35L33_HD_RM_SHIFT); 710 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 711 CS35L33_LDO_THLD_MASK, 712 hg_config->ldo_thld << CS35L33_LDO_THLD_SHIFT); 713 regmap_update_bits(priv->regmap, CS35L33_HG_MEMLDO_CTL, 714 CS35L33_LDO_DISABLE_MASK, 715 hg_config->ldo_path_disable << 716 CS35L33_LDO_DISABLE_SHIFT); 717 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 718 CS35L33_LDO_ENTRY_DELAY_MASK, 719 hg_config->ldo_entry_delay << 720 CS35L33_LDO_ENTRY_DELAY_SHIFT); 721 if (hg_config->vp_hg_auto) { 722 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 723 CS35L33_VP_HG_AUTO_MASK, 724 CS35L33_VP_HG_AUTO_MASK); 725 snd_soc_dapm_add_routes(dapm, cs35l33_vphg_auto_route, 726 ARRAY_SIZE(cs35l33_vphg_auto_route)); 727 } 728 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 729 CS35L33_VP_HG_MASK, 730 hg_config->vp_hg << CS35L33_VP_HG_SHIFT); 731 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 732 CS35L33_VP_HG_RATE_MASK, 733 hg_config->vp_hg_rate << CS35L33_VP_HG_RATE_SHIFT); 734 regmap_update_bits(priv->regmap, CS35L33_LDO_DEL, 735 CS35L33_VP_HG_VA_MASK, 736 hg_config->vp_hg_va << CS35L33_VP_HG_VA_SHIFT); 737 regmap_update_bits(priv->regmap, CS35L33_HG_EN, 738 CS35L33_CLASS_HG_EN_MASK, CS35L33_CLASS_HG_EN_MASK); 739 } 740 return 0; 741 } 742 743 static int cs35l33_set_bst_ipk(struct snd_soc_component *component, unsigned int bst) 744 { 745 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 746 int ret = 0, steps = 0; 747 748 /* Boost current in uA */ 749 if (bst > 3600000 || bst < 1850000) { 750 dev_err(component->dev, "Invalid boost current %d\n", bst); 751 ret = -EINVAL; 752 goto err; 753 } 754 755 if (bst % 15625) { 756 dev_err(component->dev, "Current not a multiple of 15625uA (%d)\n", 757 bst); 758 ret = -EINVAL; 759 goto err; 760 } 761 762 while (bst > 1850000) { 763 bst -= 15625; 764 steps++; 765 } 766 767 regmap_write(cs35l33->regmap, CS35L33_BST_PEAK_CTL, 768 steps+0x70); 769 770 err: 771 return ret; 772 } 773 774 static int cs35l33_probe(struct snd_soc_component *component) 775 { 776 struct cs35l33_private *cs35l33 = snd_soc_component_get_drvdata(component); 777 778 cs35l33->component = component; 779 pm_runtime_get_sync(component->dev); 780 781 regmap_update_bits(cs35l33->regmap, CS35L33_PROTECT_CTL, 782 CS35L33_ALIVE_WD_DIS, 0x8); 783 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL2, 784 CS35L33_ALIVE_WD_DIS2, 785 CS35L33_ALIVE_WD_DIS2); 786 787 /* Set Platform Data */ 788 regmap_update_bits(cs35l33->regmap, CS35L33_BST_CTL1, 789 CS35L33_BST_CTL_MASK, cs35l33->pdata.boost_ctl); 790 regmap_update_bits(cs35l33->regmap, CS35L33_CLASSD_CTL, 791 CS35L33_AMP_DRV_SEL_MASK, 792 cs35l33->pdata.amp_drv_sel << CS35L33_AMP_DRV_SEL_SHIFT); 793 794 if (cs35l33->pdata.boost_ipk) 795 cs35l33_set_bst_ipk(component, cs35l33->pdata.boost_ipk); 796 797 if (cs35l33->enable_soft_ramp) { 798 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 799 CS35L33_DIGSFT, CS35L33_DIGSFT); 800 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 801 CS35L33_DSR_RATE, cs35l33->pdata.ramp_rate); 802 } else { 803 snd_soc_component_update_bits(component, CS35L33_DAC_CTL, 804 CS35L33_DIGSFT, 0); 805 } 806 807 /* update IMON scaling rate if different from default of 0x8 */ 808 if (cs35l33->pdata.imon_adc_scale != 0x8) 809 snd_soc_component_update_bits(component, CS35L33_ADC_CTL, 810 CS35L33_IMON_SCALE, cs35l33->pdata.imon_adc_scale); 811 812 cs35l33_set_hg_data(component, &(cs35l33->pdata)); 813 814 /* 815 * unmask important interrupts that causes the chip to enter 816 * speaker safe mode and hence deserves user attention 817 */ 818 regmap_update_bits(cs35l33->regmap, CS35L33_INT_MASK_1, 819 CS35L33_M_OTE | CS35L33_M_OTW | CS35L33_M_AMP_SHORT | 820 CS35L33_M_CAL_ERR, 0); 821 822 pm_runtime_put_sync(component->dev); 823 824 return 0; 825 } 826 827 static const struct snd_soc_component_driver soc_component_dev_cs35l33 = { 828 .probe = cs35l33_probe, 829 .set_bias_level = cs35l33_set_bias_level, 830 .set_sysclk = cs35l33_component_set_sysclk, 831 .controls = cs35l33_snd_controls, 832 .num_controls = ARRAY_SIZE(cs35l33_snd_controls), 833 .dapm_widgets = cs35l33_dapm_widgets, 834 .num_dapm_widgets = ARRAY_SIZE(cs35l33_dapm_widgets), 835 .dapm_routes = cs35l33_audio_map, 836 .num_dapm_routes = ARRAY_SIZE(cs35l33_audio_map), 837 .use_pmdown_time = 1, 838 .endianness = 1, 839 }; 840 841 static const struct regmap_config cs35l33_regmap = { 842 .reg_bits = 8, 843 .val_bits = 8, 844 845 .max_register = CS35L33_MAX_REGISTER, 846 .reg_defaults = cs35l33_reg, 847 .num_reg_defaults = ARRAY_SIZE(cs35l33_reg), 848 .volatile_reg = cs35l33_volatile_register, 849 .readable_reg = cs35l33_readable_register, 850 .writeable_reg = cs35l33_writeable_register, 851 .cache_type = REGCACHE_MAPLE, 852 .use_single_read = true, 853 .use_single_write = true, 854 }; 855 856 static int __maybe_unused cs35l33_runtime_resume(struct device *dev) 857 { 858 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); 859 int ret; 860 861 dev_dbg(dev, "%s\n", __func__); 862 863 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); 864 865 ret = regulator_bulk_enable(cs35l33->num_core_supplies, 866 cs35l33->core_supplies); 867 if (ret != 0) { 868 dev_err(dev, "Failed to enable core supplies: %d\n", ret); 869 return ret; 870 } 871 872 regcache_cache_only(cs35l33->regmap, false); 873 874 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); 875 876 msleep(CS35L33_BOOT_DELAY); 877 878 ret = regcache_sync(cs35l33->regmap); 879 if (ret != 0) { 880 dev_err(dev, "Failed to restore register cache\n"); 881 goto err; 882 } 883 884 return 0; 885 886 err: 887 regcache_cache_only(cs35l33->regmap, true); 888 regulator_bulk_disable(cs35l33->num_core_supplies, 889 cs35l33->core_supplies); 890 891 return ret; 892 } 893 894 static int __maybe_unused cs35l33_runtime_suspend(struct device *dev) 895 { 896 struct cs35l33_private *cs35l33 = dev_get_drvdata(dev); 897 898 dev_dbg(dev, "%s\n", __func__); 899 900 /* redo the calibration in next power up */ 901 cs35l33->amp_cal = false; 902 903 regcache_cache_only(cs35l33->regmap, true); 904 regcache_mark_dirty(cs35l33->regmap); 905 regulator_bulk_disable(cs35l33->num_core_supplies, 906 cs35l33->core_supplies); 907 908 return 0; 909 } 910 911 static const struct dev_pm_ops cs35l33_pm_ops = { 912 SET_RUNTIME_PM_OPS(cs35l33_runtime_suspend, 913 cs35l33_runtime_resume, 914 NULL) 915 }; 916 917 static int cs35l33_get_hg_data(const struct device_node *np, 918 struct cs35l33_pdata *pdata) 919 { 920 struct device_node *hg; 921 struct cs35l33_hg *hg_config = &pdata->hg_config; 922 u32 val32; 923 924 hg = of_get_child_by_name(np, "cirrus,hg-algo"); 925 hg_config->enable_hg_algo = hg ? true : false; 926 927 if (hg_config->enable_hg_algo) { 928 if (of_property_read_u32(hg, "cirrus,mem-depth", &val32) >= 0) 929 hg_config->mem_depth = val32; 930 if (of_property_read_u32(hg, "cirrus,release-rate", 931 &val32) >= 0) 932 hg_config->release_rate = val32; 933 if (of_property_read_u32(hg, "cirrus,ldo-thld", &val32) >= 0) 934 hg_config->ldo_thld = val32; 935 if (of_property_read_u32(hg, "cirrus,ldo-path-disable", 936 &val32) >= 0) 937 hg_config->ldo_path_disable = val32; 938 if (of_property_read_u32(hg, "cirrus,ldo-entry-delay", 939 &val32) >= 0) 940 hg_config->ldo_entry_delay = val32; 941 942 hg_config->vp_hg_auto = of_property_read_bool(hg, 943 "cirrus,vp-hg-auto"); 944 945 if (of_property_read_u32(hg, "cirrus,vp-hg", &val32) >= 0) 946 hg_config->vp_hg = val32; 947 if (of_property_read_u32(hg, "cirrus,vp-hg-rate", &val32) >= 0) 948 hg_config->vp_hg_rate = val32; 949 if (of_property_read_u32(hg, "cirrus,vp-hg-va", &val32) >= 0) 950 hg_config->vp_hg_va = val32; 951 } 952 953 of_node_put(hg); 954 955 return 0; 956 } 957 958 static irqreturn_t cs35l33_irq_thread(int irq, void *data) 959 { 960 struct cs35l33_private *cs35l33 = data; 961 struct snd_soc_component *component = cs35l33->component; 962 unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; 963 964 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_2, 965 &sticky_val2); 966 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, 967 &sticky_val1); 968 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_2, &mask2); 969 regmap_read(cs35l33->regmap, CS35L33_INT_MASK_1, &mask1); 970 971 /* Check to see if the unmasked bits are active, 972 * if not then exit. 973 */ 974 if (!(sticky_val1 & ~mask1) && !(sticky_val2 & ~mask2)) 975 return IRQ_NONE; 976 977 regmap_read(cs35l33->regmap, CS35L33_INT_STATUS_1, 978 ¤t_val); 979 980 /* handle the interrupts */ 981 982 if (sticky_val1 & CS35L33_AMP_SHORT) { 983 dev_crit(component->dev, "Amp short error\n"); 984 if (!(current_val & CS35L33_AMP_SHORT)) { 985 dev_dbg(component->dev, 986 "Amp short error release\n"); 987 regmap_update_bits(cs35l33->regmap, 988 CS35L33_AMP_CTL, 989 CS35L33_AMP_SHORT_RLS, 0); 990 regmap_update_bits(cs35l33->regmap, 991 CS35L33_AMP_CTL, 992 CS35L33_AMP_SHORT_RLS, 993 CS35L33_AMP_SHORT_RLS); 994 regmap_update_bits(cs35l33->regmap, 995 CS35L33_AMP_CTL, CS35L33_AMP_SHORT_RLS, 996 0); 997 } 998 } 999 1000 if (sticky_val1 & CS35L33_CAL_ERR) { 1001 dev_err(component->dev, "Cal error\n"); 1002 1003 /* redo the calibration in next power up */ 1004 cs35l33->amp_cal = false; 1005 1006 if (!(current_val & CS35L33_CAL_ERR)) { 1007 dev_dbg(component->dev, "Cal error release\n"); 1008 regmap_update_bits(cs35l33->regmap, 1009 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1010 0); 1011 regmap_update_bits(cs35l33->regmap, 1012 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1013 CS35L33_CAL_ERR_RLS); 1014 regmap_update_bits(cs35l33->regmap, 1015 CS35L33_AMP_CTL, CS35L33_CAL_ERR_RLS, 1016 0); 1017 } 1018 } 1019 1020 if (sticky_val1 & CS35L33_OTE) { 1021 dev_crit(component->dev, "Over temperature error\n"); 1022 if (!(current_val & CS35L33_OTE)) { 1023 dev_dbg(component->dev, 1024 "Over temperature error release\n"); 1025 regmap_update_bits(cs35l33->regmap, 1026 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); 1027 regmap_update_bits(cs35l33->regmap, 1028 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 1029 CS35L33_OTE_RLS); 1030 regmap_update_bits(cs35l33->regmap, 1031 CS35L33_AMP_CTL, CS35L33_OTE_RLS, 0); 1032 } 1033 } 1034 1035 if (sticky_val1 & CS35L33_OTW) { 1036 dev_err(component->dev, "Over temperature warning\n"); 1037 if (!(current_val & CS35L33_OTW)) { 1038 dev_dbg(component->dev, 1039 "Over temperature warning release\n"); 1040 regmap_update_bits(cs35l33->regmap, 1041 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); 1042 regmap_update_bits(cs35l33->regmap, 1043 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 1044 CS35L33_OTW_RLS); 1045 regmap_update_bits(cs35l33->regmap, 1046 CS35L33_AMP_CTL, CS35L33_OTW_RLS, 0); 1047 } 1048 } 1049 if (CS35L33_ALIVE_ERR & sticky_val1) 1050 dev_err(component->dev, "ERROR: ADSPCLK Interrupt\n"); 1051 1052 if (CS35L33_MCLK_ERR & sticky_val1) 1053 dev_err(component->dev, "ERROR: MCLK Interrupt\n"); 1054 1055 if (CS35L33_VMON_OVFL & sticky_val2) 1056 dev_err(component->dev, 1057 "ERROR: VMON Overflow Interrupt\n"); 1058 1059 if (CS35L33_IMON_OVFL & sticky_val2) 1060 dev_err(component->dev, 1061 "ERROR: IMON Overflow Interrupt\n"); 1062 1063 if (CS35L33_VPMON_OVFL & sticky_val2) 1064 dev_err(component->dev, 1065 "ERROR: VPMON Overflow Interrupt\n"); 1066 1067 return IRQ_HANDLED; 1068 } 1069 1070 static const char * const cs35l33_core_supplies[] = { 1071 "VA", 1072 "VP", 1073 }; 1074 1075 static int cs35l33_of_get_pdata(struct device *dev, 1076 struct cs35l33_private *cs35l33) 1077 { 1078 struct device_node *np = dev->of_node; 1079 struct cs35l33_pdata *pdata = &cs35l33->pdata; 1080 u32 val32; 1081 1082 if (!np) 1083 return 0; 1084 1085 if (of_property_read_u32(np, "cirrus,boost-ctl", &val32) >= 0) { 1086 pdata->boost_ctl = val32; 1087 pdata->amp_drv_sel = 1; 1088 } 1089 1090 if (of_property_read_u32(np, "cirrus,ramp-rate", &val32) >= 0) { 1091 pdata->ramp_rate = val32; 1092 cs35l33->enable_soft_ramp = true; 1093 } 1094 1095 if (of_property_read_u32(np, "cirrus,boost-ipk", &val32) >= 0) 1096 pdata->boost_ipk = val32; 1097 1098 if (of_property_read_u32(np, "cirrus,imon-adc-scale", &val32) >= 0) { 1099 if ((val32 == 0x0) || (val32 == 0x7) || (val32 == 0x6)) 1100 pdata->imon_adc_scale = val32; 1101 else 1102 /* use default value */ 1103 pdata->imon_adc_scale = 0x8; 1104 } else { 1105 /* use default value */ 1106 pdata->imon_adc_scale = 0x8; 1107 } 1108 1109 cs35l33_get_hg_data(np, pdata); 1110 1111 return 0; 1112 } 1113 1114 static int cs35l33_i2c_probe(struct i2c_client *i2c_client) 1115 { 1116 struct cs35l33_private *cs35l33; 1117 struct cs35l33_pdata *pdata = dev_get_platdata(&i2c_client->dev); 1118 int ret, devid, i; 1119 unsigned int reg; 1120 1121 cs35l33 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs35l33_private), 1122 GFP_KERNEL); 1123 if (!cs35l33) 1124 return -ENOMEM; 1125 1126 i2c_set_clientdata(i2c_client, cs35l33); 1127 cs35l33->regmap = devm_regmap_init_i2c(i2c_client, &cs35l33_regmap); 1128 if (IS_ERR(cs35l33->regmap)) { 1129 ret = PTR_ERR(cs35l33->regmap); 1130 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1131 return ret; 1132 } 1133 1134 regcache_cache_only(cs35l33->regmap, true); 1135 1136 for (i = 0; i < ARRAY_SIZE(cs35l33_core_supplies); i++) 1137 cs35l33->core_supplies[i].supply 1138 = cs35l33_core_supplies[i]; 1139 cs35l33->num_core_supplies = ARRAY_SIZE(cs35l33_core_supplies); 1140 1141 ret = devm_regulator_bulk_get(&i2c_client->dev, 1142 cs35l33->num_core_supplies, 1143 cs35l33->core_supplies); 1144 if (ret != 0) { 1145 dev_err(&i2c_client->dev, 1146 "Failed to request core supplies: %d\n", 1147 ret); 1148 return ret; 1149 } 1150 1151 if (pdata) { 1152 cs35l33->pdata = *pdata; 1153 } else { 1154 cs35l33_of_get_pdata(&i2c_client->dev, cs35l33); 1155 pdata = &cs35l33->pdata; 1156 } 1157 1158 ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL, 1159 cs35l33_irq_thread, IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1160 "cs35l33", cs35l33); 1161 if (ret != 0) 1162 dev_warn(&i2c_client->dev, "Failed to request IRQ: %d\n", ret); 1163 1164 /* We could issue !RST or skip it based on AMP topology */ 1165 cs35l33->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1166 "reset", GPIOD_OUT_HIGH); 1167 if (IS_ERR(cs35l33->reset_gpio)) { 1168 dev_err(&i2c_client->dev, "%s ERROR: Can't get reset GPIO\n", 1169 __func__); 1170 return PTR_ERR(cs35l33->reset_gpio); 1171 } 1172 1173 ret = regulator_bulk_enable(cs35l33->num_core_supplies, 1174 cs35l33->core_supplies); 1175 if (ret != 0) { 1176 dev_err(&i2c_client->dev, 1177 "Failed to enable core supplies: %d\n", 1178 ret); 1179 return ret; 1180 } 1181 1182 gpiod_set_value_cansleep(cs35l33->reset_gpio, 1); 1183 1184 msleep(CS35L33_BOOT_DELAY); 1185 regcache_cache_only(cs35l33->regmap, false); 1186 1187 /* initialize codec */ 1188 devid = cirrus_read_device_id(cs35l33->regmap, CS35L33_DEVID_AB); 1189 if (devid < 0) { 1190 ret = devid; 1191 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret); 1192 goto err_enable; 1193 } 1194 1195 if (devid != CS35L33_CHIP_ID) { 1196 dev_err(&i2c_client->dev, 1197 "CS35L33 Device ID (%X). Expected ID %X\n", 1198 devid, CS35L33_CHIP_ID); 1199 ret = -EINVAL; 1200 goto err_enable; 1201 } 1202 1203 ret = regmap_read(cs35l33->regmap, CS35L33_REV_ID, ®); 1204 if (ret < 0) { 1205 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1206 goto err_enable; 1207 } 1208 1209 dev_info(&i2c_client->dev, 1210 "Cirrus Logic CS35L33, Revision: %02X\n", reg & 0xFF); 1211 1212 ret = regmap_register_patch(cs35l33->regmap, 1213 cs35l33_patch, ARRAY_SIZE(cs35l33_patch)); 1214 if (ret < 0) { 1215 dev_err(&i2c_client->dev, 1216 "Error in applying regmap patch: %d\n", ret); 1217 goto err_enable; 1218 } 1219 1220 /* disable mclk and tdm */ 1221 regmap_update_bits(cs35l33->regmap, CS35L33_CLK_CTL, 1222 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM, 1223 CS35L33_MCLKDIS | CS35L33_SDOUT_3ST_TDM); 1224 1225 pm_runtime_set_autosuspend_delay(&i2c_client->dev, 100); 1226 pm_runtime_use_autosuspend(&i2c_client->dev); 1227 pm_runtime_set_active(&i2c_client->dev); 1228 pm_runtime_enable(&i2c_client->dev); 1229 1230 ret = devm_snd_soc_register_component(&i2c_client->dev, 1231 &soc_component_dev_cs35l33, &cs35l33_dai, 1); 1232 if (ret < 0) { 1233 dev_err(&i2c_client->dev, "%s: Register component failed\n", 1234 __func__); 1235 goto err_enable; 1236 } 1237 1238 return 0; 1239 1240 err_enable: 1241 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); 1242 1243 regulator_bulk_disable(cs35l33->num_core_supplies, 1244 cs35l33->core_supplies); 1245 1246 return ret; 1247 } 1248 1249 static void cs35l33_i2c_remove(struct i2c_client *client) 1250 { 1251 struct cs35l33_private *cs35l33 = i2c_get_clientdata(client); 1252 1253 gpiod_set_value_cansleep(cs35l33->reset_gpio, 0); 1254 1255 pm_runtime_disable(&client->dev); 1256 regulator_bulk_disable(cs35l33->num_core_supplies, 1257 cs35l33->core_supplies); 1258 } 1259 1260 static const struct of_device_id cs35l33_of_match[] = { 1261 { .compatible = "cirrus,cs35l33", }, 1262 {}, 1263 }; 1264 MODULE_DEVICE_TABLE(of, cs35l33_of_match); 1265 1266 static const struct i2c_device_id cs35l33_id[] = { 1267 {"cs35l33", 0}, 1268 {} 1269 }; 1270 1271 MODULE_DEVICE_TABLE(i2c, cs35l33_id); 1272 1273 static struct i2c_driver cs35l33_i2c_driver = { 1274 .driver = { 1275 .name = "cs35l33", 1276 .pm = &cs35l33_pm_ops, 1277 .of_match_table = cs35l33_of_match, 1278 1279 }, 1280 .id_table = cs35l33_id, 1281 .probe = cs35l33_i2c_probe, 1282 .remove = cs35l33_i2c_remove, 1283 1284 }; 1285 module_i2c_driver(cs35l33_i2c_driver); 1286 1287 MODULE_DESCRIPTION("ASoC CS35L33 driver"); 1288 MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>"); 1289 MODULE_LICENSE("GPL"); 1290