1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC CPCAP codec driver 4 * 5 * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org> 6 * 7 * Very loosely based on original driver from Motorola: 8 * Copyright (C) 2007 - 2009 Motorola, Inc. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/platform_device.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/mfd/motorola-cpcap.h> 16 #include <sound/core.h> 17 #include <linux/input.h> 18 #include <sound/jack.h> 19 #include <sound/soc.h> 20 #include <sound/tlv.h> 21 22 /* Register 8 - CPCAP_REG_INTS1 --- Interrupt Sense 1 */ 23 #define CPCAP_BIT_HS_S 9 /* Headset */ 24 #define CPCAP_BIT_MB2_S 10 /* Mic Bias2 */ 25 26 /* Register 9 - CPCAP_REG_INTS2 --- Interrupt Sense 2 */ 27 #define CPCAP_BIT_PTT_S 11 /* Push To Talk */ 28 29 /* Register 513 CPCAP_REG_CC --- CODEC */ 30 #define CPCAP_BIT_CDC_CLK2 15 31 #define CPCAP_BIT_CDC_CLK1 14 32 #define CPCAP_BIT_CDC_CLK0 13 33 #define CPCAP_BIT_CDC_SR3 12 34 #define CPCAP_BIT_CDC_SR2 11 35 #define CPCAP_BIT_CDC_SR1 10 36 #define CPCAP_BIT_CDC_SR0 9 37 #define CPCAP_BIT_CDC_CLOCK_TREE_RESET 8 38 #define CPCAP_BIT_MIC2_CDC_EN 7 39 #define CPCAP_BIT_CDC_EN_RX 6 40 #define CPCAP_BIT_DF_RESET 5 41 #define CPCAP_BIT_MIC1_CDC_EN 4 42 #define CPCAP_BIT_AUDOHPF_1 3 43 #define CPCAP_BIT_AUDOHPF_0 2 44 #define CPCAP_BIT_AUDIHPF_1 1 45 #define CPCAP_BIT_AUDIHPF_0 0 46 47 /* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */ 48 #define CPCAP_BIT_CDC_PLL_SEL 15 49 #define CPCAP_BIT_CLK_IN_SEL 13 50 #define CPCAP_BIT_DIG_AUD_IN 12 51 #define CPCAP_BIT_CDC_CLK_EN 11 52 #define CPCAP_BIT_CDC_DIG_AUD_FS1 10 53 #define CPCAP_BIT_CDC_DIG_AUD_FS0 9 54 #define CPCAP_BIT_MIC2_TIMESLOT2 8 55 #define CPCAP_BIT_MIC2_TIMESLOT1 7 56 #define CPCAP_BIT_MIC2_TIMESLOT0 6 57 #define CPCAP_BIT_MIC1_RX_TIMESLOT2 5 58 #define CPCAP_BIT_MIC1_RX_TIMESLOT1 4 59 #define CPCAP_BIT_MIC1_RX_TIMESLOT0 3 60 #define CPCAP_BIT_FS_INV 2 61 #define CPCAP_BIT_CLK_INV 1 62 #define CPCAP_BIT_SMB_CDC 0 63 64 /* Register 515 CPCAP_REG_SDAC --- Stereo DAC */ 65 #define CPCAP_BIT_FSYNC_CLK_IN_COMMON 11 66 #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT 10 67 #define CPCAP_BIT_ST_CLOCK_TREE_RESET 9 68 #define CPCAP_BIT_DF_RESET_ST_DAC 8 69 #define CPCAP_BIT_ST_SR3 7 70 #define CPCAP_BIT_ST_SR2 6 71 #define CPCAP_BIT_ST_SR1 5 72 #define CPCAP_BIT_ST_SR0 4 73 #define CPCAP_BIT_ST_DAC_CLK2 3 74 #define CPCAP_BIT_ST_DAC_CLK1 2 75 #define CPCAP_BIT_ST_DAC_CLK0 1 76 #define CPCAP_BIT_ST_DAC_EN 0 77 78 /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */ 79 #define CPCAP_BIT_ST_L_TIMESLOT2 13 80 #define CPCAP_BIT_ST_L_TIMESLOT1 12 81 #define CPCAP_BIT_ST_L_TIMESLOT0 11 82 #define CPCAP_BIT_ST_R_TIMESLOT2 10 83 #define CPCAP_BIT_ST_R_TIMESLOT1 9 84 #define CPCAP_BIT_ST_R_TIMESLOT0 8 85 #define CPCAP_BIT_ST_DAC_CLK_IN_SEL 7 86 #define CPCAP_BIT_ST_FS_INV 6 87 #define CPCAP_BIT_ST_CLK_INV 5 88 #define CPCAP_BIT_ST_DIG_AUD_FS1 4 89 #define CPCAP_BIT_ST_DIG_AUD_FS0 3 90 #define CPCAP_BIT_DIG_AUD_IN_ST_DAC 2 91 #define CPCAP_BIT_ST_CLK_EN 1 92 #define CPCAP_BIT_SMB_ST_DAC 0 93 94 /* Register 517 CPCAP_REG_TXI --- TX Interface */ 95 #define CPCAP_BIT_PTT_TH 15 96 #define CPCAP_BIT_PTT_CMP_EN 14 97 #define CPCAP_BIT_HS_ID_TX 13 98 #define CPCAP_BIT_MB_ON2 12 99 #define CPCAP_BIT_MB_ON1L 11 100 #define CPCAP_BIT_MB_ON1R 10 101 #define CPCAP_BIT_RX_L_ENCODE 9 102 #define CPCAP_BIT_RX_R_ENCODE 8 103 #define CPCAP_BIT_MIC2_MUX 7 104 #define CPCAP_BIT_MIC2_PGA_EN 6 105 #define CPCAP_BIT_CDET_DIS 5 106 #define CPCAP_BIT_EMU_MIC_MUX 4 107 #define CPCAP_BIT_HS_MIC_MUX 3 108 #define CPCAP_BIT_MIC1_MUX 2 109 #define CPCAP_BIT_MIC1_PGA_EN 1 110 #define CPCAP_BIT_DLM 0 111 112 /* Register 518 CPCAP_REG_TXMP --- Mic Gain */ 113 #define CPCAP_BIT_MB_BIAS_R1 11 114 #define CPCAP_BIT_MB_BIAS_R0 10 115 #define CPCAP_BIT_MIC2_GAIN_4 9 116 #define CPCAP_BIT_MIC2_GAIN_3 8 117 #define CPCAP_BIT_MIC2_GAIN_2 7 118 #define CPCAP_BIT_MIC2_GAIN_1 6 119 #define CPCAP_BIT_MIC2_GAIN_0 5 120 #define CPCAP_BIT_MIC1_GAIN_4 4 121 #define CPCAP_BIT_MIC1_GAIN_3 3 122 #define CPCAP_BIT_MIC1_GAIN_2 2 123 #define CPCAP_BIT_MIC1_GAIN_1 1 124 #define CPCAP_BIT_MIC1_GAIN_0 0 125 126 /* Register 519 CPCAP_REG_RXOA --- RX Output Amplifier */ 127 #define CPCAP_BIT_UNUSED_519_15 15 128 #define CPCAP_BIT_UNUSED_519_14 14 129 #define CPCAP_BIT_UNUSED_519_13 13 130 #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12 131 #define CPCAP_BIT_HS_LOW_PWR 11 132 #define CPCAP_BIT_HS_ID_RX 10 133 #define CPCAP_BIT_ST_HS_CP_EN 9 134 #define CPCAP_BIT_EMU_SPKR_R_EN 8 135 #define CPCAP_BIT_EMU_SPKR_L_EN 7 136 #define CPCAP_BIT_HS_L_EN 6 137 #define CPCAP_BIT_HS_R_EN 5 138 #define CPCAP_BIT_A4_LINEOUT_L_EN 4 139 #define CPCAP_BIT_A4_LINEOUT_R_EN 3 140 #define CPCAP_BIT_A2_LDSP_L_EN 2 141 #define CPCAP_BIT_A2_LDSP_R_EN 1 142 #define CPCAP_BIT_A1_EAR_EN 0 143 144 /* Register 520 CPCAP_REG_RXVC --- RX Volume Control */ 145 #define CPCAP_BIT_VOL_EXT3 15 146 #define CPCAP_BIT_VOL_EXT2 14 147 #define CPCAP_BIT_VOL_EXT1 13 148 #define CPCAP_BIT_VOL_EXT0 12 149 #define CPCAP_BIT_VOL_DAC3 11 150 #define CPCAP_BIT_VOL_DAC2 10 151 #define CPCAP_BIT_VOL_DAC1 9 152 #define CPCAP_BIT_VOL_DAC0 8 153 #define CPCAP_BIT_VOL_DAC_LSB_1dB1 7 154 #define CPCAP_BIT_VOL_DAC_LSB_1dB0 6 155 #define CPCAP_BIT_VOL_CDC3 5 156 #define CPCAP_BIT_VOL_CDC2 4 157 #define CPCAP_BIT_VOL_CDC1 3 158 #define CPCAP_BIT_VOL_CDC0 2 159 #define CPCAP_BIT_VOL_CDC_LSB_1dB1 1 160 #define CPCAP_BIT_VOL_CDC_LSB_1dB0 0 161 162 /* Register 521 CPCAP_REG_RXCOA --- Codec to Output Amp Switches */ 163 #define CPCAP_BIT_PGA_CDC_EN 10 164 #define CPCAP_BIT_CDC_SW 9 165 #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW 8 166 #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW 7 167 #define CPCAP_BIT_ALEFT_HS_CDC_SW 6 168 #define CPCAP_BIT_ARIGHT_HS_CDC_SW 5 169 #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW 4 170 #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW 3 171 #define CPCAP_BIT_A2_LDSP_L_CDC_SW 2 172 #define CPCAP_BIT_A2_LDSP_R_CDC_SW 1 173 #define CPCAP_BIT_A1_EAR_CDC_SW 0 174 175 /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */ 176 #define CPCAP_BIT_PGA_DAC_EN 12 177 #define CPCAP_BIT_ST_DAC_SW 11 178 #define CPCAP_BIT_MONO_DAC1 10 179 #define CPCAP_BIT_MONO_DAC0 9 180 #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW 8 181 #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW 7 182 #define CPCAP_BIT_ALEFT_HS_DAC_SW 6 183 #define CPCAP_BIT_ARIGHT_HS_DAC_SW 5 184 #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW 4 185 #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW 3 186 #define CPCAP_BIT_A2_LDSP_L_DAC_SW 2 187 #define CPCAP_BIT_A2_LDSP_R_DAC_SW 1 188 #define CPCAP_BIT_A1_EAR_DAC_SW 0 189 190 /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */ 191 #define CPCAP_BIT_PGA_EXT_L_EN 14 192 #define CPCAP_BIT_PGA_EXT_R_EN 13 193 #define CPCAP_BIT_PGA_IN_L_SW 12 194 #define CPCAP_BIT_PGA_IN_R_SW 11 195 #define CPCAP_BIT_MONO_EXT1 10 196 #define CPCAP_BIT_MONO_EXT0 9 197 #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW 8 198 #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW 7 199 #define CPCAP_BIT_ALEFT_HS_EXT_SW 6 200 #define CPCAP_BIT_ARIGHT_HS_EXT_SW 5 201 #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW 4 202 #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW 3 203 #define CPCAP_BIT_A2_LDSP_L_EXT_SW 2 204 #define CPCAP_BIT_A2_LDSP_R_EXT_SW 1 205 #define CPCAP_BIT_A1_EAR_EXT_SW 0 206 207 /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */ 208 #define CPCAP_BIT_NCP_CLK_SYNC 7 209 #define CPCAP_BIT_A2_CLK_SYNC 6 210 #define CPCAP_BIT_A2_FREE_RUN 5 211 #define CPCAP_BIT_A2_CLK2 4 212 #define CPCAP_BIT_A2_CLK1 3 213 #define CPCAP_BIT_A2_CLK0 2 214 #define CPCAP_BIT_A2_CLK_IN 1 215 #define CPCAP_BIT_A2_CONFIG 0 216 217 #define SLEEP_ACTIVATE_POWER 2 218 #define CLOCK_TREE_RESET_TIME 1 219 220 /* constants for ST delay workaround */ 221 #define STM_STDAC_ACTIVATE_RAMP_TIME 1 222 #define STM_STDAC_EN_TEST_PRE 0x090C 223 #define STM_STDAC_EN_TEST_POST 0x0000 224 #define STM_STDAC_EN_ST_TEST1_PRE 0x2400 225 #define STM_STDAC_EN_ST_TEST1_POST 0x0400 226 227 struct cpcap_reg_info { 228 u16 reg; 229 u16 mask; 230 u16 val; 231 }; 232 233 static const struct cpcap_reg_info cpcap_default_regs[] = { 234 { CPCAP_REG_CC, 0xFFFF, 0x0000 }, 235 { CPCAP_REG_CC, 0xFFFF, 0x0000 }, 236 { CPCAP_REG_CDI, 0xBFFF, 0x0000 }, 237 { CPCAP_REG_SDAC, 0x0FFF, 0x0000 }, 238 { CPCAP_REG_SDACDI, 0x3FFF, 0x0000 }, 239 { CPCAP_REG_TXI, 0x0FDF, 0x0000 }, 240 { CPCAP_REG_TXMP, 0x0FFF, 0x0400 }, 241 { CPCAP_REG_RXOA, 0x01FF, 0x0000 }, 242 { CPCAP_REG_RXVC, 0xFF3C, 0x0000 }, 243 { CPCAP_REG_RXCOA, 0x07FF, 0x0000 }, 244 { CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 }, 245 { CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 }, 246 { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN), 247 BIT(CPCAP_BIT_A2_FREE_RUN) }, 248 }; 249 250 enum cpcap_dai { 251 CPCAP_DAI_HIFI, 252 CPCAP_DAI_VOICE, 253 }; 254 255 struct cpcap_audio { 256 struct snd_soc_component *component; 257 struct regmap *regmap; 258 259 u16 vendor; 260 261 int codec_clk_id; 262 int codec_freq; 263 int codec_format; 264 struct regulator *vaudio; 265 int hsirq; 266 int mb2irq; 267 struct snd_soc_jack jack; 268 }; 269 270 static int cpcap_st_workaround(struct snd_soc_dapm_widget *w, 271 struct snd_kcontrol *kcontrol, int event) 272 { 273 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 274 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 275 int err = 0; 276 277 /* Only CPCAP from ST requires workaround */ 278 if (cpcap->vendor != CPCAP_VENDOR_ST) 279 return 0; 280 281 switch (event) { 282 case SND_SOC_DAPM_PRE_PMU: 283 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST, 284 STM_STDAC_EN_TEST_PRE); 285 if (err) 286 return err; 287 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1, 288 STM_STDAC_EN_ST_TEST1_PRE); 289 break; 290 case SND_SOC_DAPM_POST_PMU: 291 msleep(STM_STDAC_ACTIVATE_RAMP_TIME); 292 293 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1, 294 STM_STDAC_EN_ST_TEST1_POST); 295 if (err) 296 return err; 297 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST, 298 STM_STDAC_EN_TEST_POST); 299 break; 300 default: 301 break; 302 } 303 304 return err; 305 } 306 307 /* Capture Gain Control: 0dB to 31dB in 1dB steps */ 308 static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0); 309 310 /* Playback Gain Control: -33dB to 12dB in 3dB steps */ 311 static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0); 312 313 static const struct snd_kcontrol_new cpcap_snd_controls[] = { 314 /* Playback Gain */ 315 SOC_SINGLE_TLV("HiFi Playback Volume", 316 CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv), 317 SOC_SINGLE_TLV("Voice Playback Volume", 318 CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv), 319 SOC_SINGLE_TLV("Ext Playback Volume", 320 CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv), 321 322 /* Capture Gain */ 323 SOC_SINGLE_TLV("Mic1 Capture Volume", 324 CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv), 325 SOC_SINGLE_TLV("Mic2 Capture Volume", 326 CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv), 327 328 /* Phase Invert */ 329 SOC_SINGLE("Hifi Left Phase Invert Switch", 330 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0), 331 SOC_SINGLE("Ext Left Phase Invert Switch", 332 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0), 333 }; 334 335 static const char * const cpcap_out_mux_texts[] = { 336 "Off", "Voice", "HiFi", "Ext" 337 }; 338 339 static const char * const cpcap_in_right_mux_texts[] = { 340 "Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right" 341 }; 342 343 static const char * const cpcap_in_left_mux_texts[] = { 344 "Off", "Mic 2", "Ext Left" 345 }; 346 347 /* 348 * input muxes use unusual register layout, so that we need to use custom 349 * getter/setter methods 350 */ 351 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum, 352 cpcap_in_left_mux_texts); 353 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum, 354 cpcap_in_right_mux_texts); 355 356 /* 357 * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA; 358 * even though the register layout makes it look like a mixer, this is a mux. 359 * Enabling multiple inputs will result in no audio being forwarded. 360 */ 361 static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts); 362 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts); 363 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts); 364 static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts); 365 static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts); 366 static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts); 367 static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts); 368 static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts); 369 static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts); 370 371 static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol, 372 struct snd_ctl_elem_value *ucontrol) 373 { 374 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 375 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 376 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 377 unsigned int shift = e->shift_l; 378 int reg_voice, reg_hifi, reg_ext, status; 379 int err; 380 381 err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, ®_voice); 382 if (err) 383 return err; 384 err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, ®_hifi); 385 if (err) 386 return err; 387 err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, ®_ext); 388 if (err) 389 return err; 390 391 reg_voice = (reg_voice >> shift) & 1; 392 reg_hifi = (reg_hifi >> shift) & 1; 393 reg_ext = (reg_ext >> shift) & 1; 394 status = reg_ext << 2 | reg_hifi << 1 | reg_voice; 395 396 switch (status) { 397 case 0x04: 398 ucontrol->value.enumerated.item[0] = 3; 399 break; 400 case 0x02: 401 ucontrol->value.enumerated.item[0] = 2; 402 break; 403 case 0x01: 404 ucontrol->value.enumerated.item[0] = 1; 405 break; 406 default: 407 ucontrol->value.enumerated.item[0] = 0; 408 break; 409 } 410 411 return 0; 412 } 413 414 static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol, 415 struct snd_ctl_elem_value *ucontrol) 416 { 417 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 418 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 419 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 420 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 421 unsigned int muxval = ucontrol->value.enumerated.item[0]; 422 unsigned int mask = BIT(e->shift_l); 423 u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00; 424 int err; 425 426 switch (muxval) { 427 case 1: 428 reg_voice = mask; 429 break; 430 case 2: 431 reg_hifi = mask; 432 break; 433 case 3: 434 reg_ext = mask; 435 break; 436 default: 437 break; 438 } 439 440 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA, 441 mask, reg_voice); 442 if (err) 443 return err; 444 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA, 445 mask, reg_hifi); 446 if (err) 447 return err; 448 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA, 449 mask, reg_ext); 450 if (err) 451 return err; 452 453 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 454 455 return 0; 456 } 457 458 static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol, 459 struct snd_ctl_elem_value *ucontrol) 460 { 461 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 462 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 463 int regval, mask; 464 int err; 465 466 err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); 467 if (err) 468 return err; 469 470 mask = 0; 471 mask |= BIT(CPCAP_BIT_MIC1_MUX); 472 mask |= BIT(CPCAP_BIT_HS_MIC_MUX); 473 mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); 474 mask |= BIT(CPCAP_BIT_RX_R_ENCODE); 475 476 switch (regval & mask) { 477 case BIT(CPCAP_BIT_RX_R_ENCODE): 478 ucontrol->value.enumerated.item[0] = 4; 479 break; 480 case BIT(CPCAP_BIT_EMU_MIC_MUX): 481 ucontrol->value.enumerated.item[0] = 3; 482 break; 483 case BIT(CPCAP_BIT_HS_MIC_MUX): 484 ucontrol->value.enumerated.item[0] = 2; 485 break; 486 case BIT(CPCAP_BIT_MIC1_MUX): 487 ucontrol->value.enumerated.item[0] = 1; 488 break; 489 default: 490 ucontrol->value.enumerated.item[0] = 0; 491 break; 492 } 493 494 return 0; 495 } 496 497 static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol, 498 struct snd_ctl_elem_value *ucontrol) 499 { 500 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 501 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 502 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 503 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 504 unsigned int muxval = ucontrol->value.enumerated.item[0]; 505 int regval = 0, mask; 506 int err; 507 508 mask = 0; 509 mask |= BIT(CPCAP_BIT_MIC1_MUX); 510 mask |= BIT(CPCAP_BIT_HS_MIC_MUX); 511 mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); 512 mask |= BIT(CPCAP_BIT_RX_R_ENCODE); 513 514 switch (muxval) { 515 case 1: 516 regval = BIT(CPCAP_BIT_MIC1_MUX); 517 break; 518 case 2: 519 regval = BIT(CPCAP_BIT_HS_MIC_MUX); 520 break; 521 case 3: 522 regval = BIT(CPCAP_BIT_EMU_MIC_MUX); 523 break; 524 case 4: 525 regval = BIT(CPCAP_BIT_RX_R_ENCODE); 526 break; 527 default: 528 break; 529 } 530 531 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 532 mask, regval); 533 if (err) 534 return err; 535 536 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 537 538 return 0; 539 } 540 541 static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol, 542 struct snd_ctl_elem_value *ucontrol) 543 { 544 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 545 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 546 int regval, mask; 547 int err; 548 549 err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); 550 if (err) 551 return err; 552 553 mask = 0; 554 mask |= BIT(CPCAP_BIT_MIC2_MUX); 555 mask |= BIT(CPCAP_BIT_RX_L_ENCODE); 556 557 switch (regval & mask) { 558 case BIT(CPCAP_BIT_RX_L_ENCODE): 559 ucontrol->value.enumerated.item[0] = 2; 560 break; 561 case BIT(CPCAP_BIT_MIC2_MUX): 562 ucontrol->value.enumerated.item[0] = 1; 563 break; 564 default: 565 ucontrol->value.enumerated.item[0] = 0; 566 break; 567 } 568 569 return 0; 570 } 571 572 static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol, 573 struct snd_ctl_elem_value *ucontrol) 574 { 575 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 576 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 577 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 578 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 579 unsigned int muxval = ucontrol->value.enumerated.item[0]; 580 int regval = 0, mask; 581 int err; 582 583 mask = 0; 584 mask |= BIT(CPCAP_BIT_MIC2_MUX); 585 mask |= BIT(CPCAP_BIT_RX_L_ENCODE); 586 587 switch (muxval) { 588 case 1: 589 regval = BIT(CPCAP_BIT_MIC2_MUX); 590 break; 591 case 2: 592 regval = BIT(CPCAP_BIT_RX_L_ENCODE); 593 break; 594 default: 595 break; 596 } 597 598 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 599 mask, regval); 600 if (err) 601 return err; 602 603 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 604 605 return 0; 606 } 607 608 static const struct snd_kcontrol_new cpcap_input_left_mux = 609 SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum, 610 cpcap_input_left_mux_get_enum, 611 cpcap_input_left_mux_put_enum); 612 static const struct snd_kcontrol_new cpcap_input_right_mux = 613 SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum, 614 cpcap_input_right_mux_get_enum, 615 cpcap_input_right_mux_put_enum); 616 static const struct snd_kcontrol_new cpcap_emu_left_mux = 617 SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum, 618 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 619 static const struct snd_kcontrol_new cpcap_emu_right_mux = 620 SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum, 621 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 622 static const struct snd_kcontrol_new cpcap_hs_left_mux = 623 SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum, 624 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 625 static const struct snd_kcontrol_new cpcap_hs_right_mux = 626 SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum, 627 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 628 static const struct snd_kcontrol_new cpcap_line_left_mux = 629 SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum, 630 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 631 static const struct snd_kcontrol_new cpcap_line_right_mux = 632 SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum, 633 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 634 static const struct snd_kcontrol_new cpcap_speaker_left_mux = 635 SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum, 636 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 637 static const struct snd_kcontrol_new cpcap_speaker_right_mux = 638 SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum, 639 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 640 static const struct snd_kcontrol_new cpcap_earpiece_mux = 641 SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum, 642 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 643 644 static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = { 645 SOC_DAPM_SINGLE("HiFi Mono Playback Switch", 646 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0), 647 }; 648 static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = { 649 SOC_DAPM_SINGLE("Ext Mono Playback Switch", 650 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0), 651 }; 652 653 static const struct snd_kcontrol_new cpcap_extr_mute_control = 654 SOC_DAPM_SINGLE("Switch", 655 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0); 656 static const struct snd_kcontrol_new cpcap_extl_mute_control = 657 SOC_DAPM_SINGLE("Switch", 658 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0); 659 660 static const struct snd_kcontrol_new cpcap_voice_loopback = 661 SOC_DAPM_SINGLE("Switch", 662 CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0); 663 664 static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = { 665 /* DAIs */ 666 SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0), 667 SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0), 668 SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0), 669 670 /* Power Supply */ 671 SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0), 672 673 /* Highpass Filters */ 674 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX", 675 CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0), 676 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX", 677 CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0), 678 679 /* Clocks */ 680 SND_SOC_DAPM_SUPPLY("HiFi DAI Clock", 681 CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0), 682 SND_SOC_DAPM_SUPPLY("Voice DAI Clock", 683 CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0), 684 685 /* Microphone Bias */ 686 SND_SOC_DAPM_SUPPLY("MIC1R Bias", 687 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0), 688 SND_SOC_DAPM_SUPPLY("MIC1L Bias", 689 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0), 690 SND_SOC_DAPM_SUPPLY("MIC2 Bias", 691 CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0), 692 693 /* Inputs */ 694 SND_SOC_DAPM_INPUT("MICR"), 695 SND_SOC_DAPM_INPUT("HSMIC"), 696 SND_SOC_DAPM_INPUT("EMUMIC"), 697 SND_SOC_DAPM_INPUT("MICL"), 698 SND_SOC_DAPM_INPUT("EXTR"), 699 SND_SOC_DAPM_INPUT("EXTL"), 700 701 /* Capture Route */ 702 SND_SOC_DAPM_MUX("Right Capture Route", 703 SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux), 704 SND_SOC_DAPM_MUX("Left Capture Route", 705 SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux), 706 707 /* Capture PGAs */ 708 SND_SOC_DAPM_PGA("Microphone 1 PGA", 709 CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0), 710 SND_SOC_DAPM_PGA("Microphone 2 PGA", 711 CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0), 712 713 /* ADC */ 714 SND_SOC_DAPM_ADC("ADC Right", NULL, 715 CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0), 716 SND_SOC_DAPM_ADC("ADC Left", NULL, 717 CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0), 718 719 /* DAC */ 720 SND_SOC_DAPM_DAC_E("DAC HiFi", NULL, 721 CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0, 722 cpcap_st_workaround, 723 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 724 SND_SOC_DAPM_DAC_E("DAC Voice", NULL, 725 CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0, 726 cpcap_st_workaround, 727 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 728 729 /* Playback PGA */ 730 SND_SOC_DAPM_PGA("HiFi PGA", 731 CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0), 732 SND_SOC_DAPM_PGA("Voice PGA", 733 CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0), 734 SND_SOC_DAPM_PGA_E("Ext Right PGA", 735 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0, 736 NULL, 0, 737 cpcap_st_workaround, 738 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 739 SND_SOC_DAPM_PGA_E("Ext Left PGA", 740 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0, 741 NULL, 0, 742 cpcap_st_workaround, 743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 744 745 /* Playback Switch */ 746 SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0, 747 &cpcap_extr_mute_control), 748 SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0, 749 &cpcap_extl_mute_control), 750 751 /* Loopback Switch */ 752 SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0, 753 &cpcap_voice_loopback), 754 755 /* Mono Mixer */ 756 SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0, 757 cpcap_hifi_mono_mixer_controls), 758 SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0, 759 cpcap_hifi_mono_mixer_controls), 760 SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0, 761 cpcap_ext_mono_mixer_controls), 762 SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0, 763 cpcap_ext_mono_mixer_controls), 764 765 /* Output Routes */ 766 SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0, 767 &cpcap_earpiece_mux), 768 SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0, 769 &cpcap_speaker_right_mux), 770 SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0, 771 &cpcap_speaker_left_mux), 772 SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0, 773 &cpcap_line_right_mux), 774 SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0, 775 &cpcap_line_left_mux), 776 SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0, 777 &cpcap_hs_right_mux), 778 SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0, 779 &cpcap_hs_left_mux), 780 SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0, 781 &cpcap_emu_right_mux), 782 SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0, 783 &cpcap_emu_left_mux), 784 785 /* Output Amplifier */ 786 SND_SOC_DAPM_PGA("Earpiece PGA", 787 CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0), 788 SND_SOC_DAPM_PGA("Speaker Right PGA", 789 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0), 790 SND_SOC_DAPM_PGA("Speaker Left PGA", 791 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0), 792 SND_SOC_DAPM_PGA("Lineout Right PGA", 793 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0), 794 SND_SOC_DAPM_PGA("Lineout Left PGA", 795 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0), 796 SND_SOC_DAPM_PGA("Headset Right PGA", 797 CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0), 798 SND_SOC_DAPM_PGA("Headset Left PGA", 799 CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0), 800 SND_SOC_DAPM_PGA("EMU Right PGA", 801 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0), 802 SND_SOC_DAPM_PGA("EMU Left PGA", 803 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0), 804 805 /* Headet Charge Pump */ 806 SND_SOC_DAPM_SUPPLY("Headset Charge Pump", 807 CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0), 808 809 /* Outputs */ 810 SND_SOC_DAPM_OUTPUT("EP"), 811 SND_SOC_DAPM_OUTPUT("SPKR"), 812 SND_SOC_DAPM_OUTPUT("SPKL"), 813 SND_SOC_DAPM_OUTPUT("LINER"), 814 SND_SOC_DAPM_OUTPUT("LINEL"), 815 SND_SOC_DAPM_OUTPUT("HSR"), 816 SND_SOC_DAPM_OUTPUT("HSL"), 817 SND_SOC_DAPM_OUTPUT("EMUR"), 818 SND_SOC_DAPM_OUTPUT("EMUL"), 819 }; 820 821 static const struct snd_soc_dapm_route intercon[] = { 822 /* Power Supply */ 823 {"HiFi PGA", NULL, "VAUDIO"}, 824 {"Voice PGA", NULL, "VAUDIO"}, 825 {"Ext Right PGA", NULL, "VAUDIO"}, 826 {"Ext Left PGA", NULL, "VAUDIO"}, 827 {"Microphone 1 PGA", NULL, "VAUDIO"}, 828 {"Microphone 2 PGA", NULL, "VAUDIO"}, 829 830 /* Stream -> AIF */ 831 {"HiFi RX", NULL, "HiFi Playback"}, 832 {"Voice RX", NULL, "Voice Playback"}, 833 {"Voice Capture", NULL, "Voice TX"}, 834 835 /* AIF clocks */ 836 {"HiFi RX", NULL, "HiFi DAI Clock"}, 837 {"Voice RX", NULL, "Voice DAI Clock"}, 838 {"Voice TX", NULL, "Voice DAI Clock"}, 839 840 /* Digital Loopback */ 841 {"Voice Loopback", "Switch", "Voice TX"}, 842 {"Voice RX", NULL, "Voice Loopback"}, 843 844 /* Highpass Filters */ 845 {"Highpass Filter RX", NULL, "Voice RX"}, 846 {"Voice TX", NULL, "Highpass Filter TX"}, 847 848 /* AIF -> DAC mapping */ 849 {"DAC HiFi", NULL, "HiFi RX"}, 850 {"DAC Voice", NULL, "Highpass Filter RX"}, 851 852 /* DAC -> PGA */ 853 {"HiFi PGA", NULL, "DAC HiFi"}, 854 {"Voice PGA", NULL, "DAC Voice"}, 855 856 /* Ext Input -> PGA */ 857 {"Ext Right PGA", NULL, "EXTR"}, 858 {"Ext Left PGA", NULL, "EXTL"}, 859 860 /* Ext PGA -> Ext Playback Switch */ 861 {"Ext Right Enable", "Switch", "Ext Right PGA"}, 862 {"Ext Left Enable", "Switch", "Ext Left PGA"}, 863 864 /* HiFi PGA -> Mono Mixer */ 865 {"HiFi Mono Left Mixer", NULL, "HiFi PGA"}, 866 {"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"}, 867 {"HiFi Mono Right Mixer", NULL, "HiFi PGA"}, 868 {"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"}, 869 870 /* Ext Playback Switch -> Ext Mono Mixer */ 871 {"Ext Mono Right Mixer", NULL, "Ext Right Enable"}, 872 {"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"}, 873 {"Ext Mono Left Mixer", NULL, "Ext Left Enable"}, 874 {"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"}, 875 876 /* HiFi Mono Mixer -> Output Route */ 877 {"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 878 {"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 879 {"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 880 {"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 881 {"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 882 {"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 883 {"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 884 {"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 885 {"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 886 887 /* Voice PGA -> Output Route */ 888 {"Earpiece Playback Route", "Voice", "Voice PGA"}, 889 {"Speaker Right Playback Route", "Voice", "Voice PGA"}, 890 {"Speaker Left Playback Route", "Voice", "Voice PGA"}, 891 {"Lineout Right Playback Route", "Voice", "Voice PGA"}, 892 {"Lineout Left Playback Route", "Voice", "Voice PGA"}, 893 {"Headset Right Playback Route", "Voice", "Voice PGA"}, 894 {"Headset Left Playback Route", "Voice", "Voice PGA"}, 895 {"EMU Right Playback Route", "Voice", "Voice PGA"}, 896 {"EMU Left Playback Route", "Voice", "Voice PGA"}, 897 898 /* Ext Mono Mixer -> Output Route */ 899 {"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"}, 900 {"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 901 {"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 902 {"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 903 {"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 904 {"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 905 {"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 906 {"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 907 {"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 908 909 /* Output Route -> Output Amplifier */ 910 {"Earpiece PGA", NULL, "Earpiece Playback Route"}, 911 {"Speaker Right PGA", NULL, "Speaker Right Playback Route"}, 912 {"Speaker Left PGA", NULL, "Speaker Left Playback Route"}, 913 {"Lineout Right PGA", NULL, "Lineout Right Playback Route"}, 914 {"Lineout Left PGA", NULL, "Lineout Left Playback Route"}, 915 {"Headset Right PGA", NULL, "Headset Right Playback Route"}, 916 {"Headset Left PGA", NULL, "Headset Left Playback Route"}, 917 {"EMU Right PGA", NULL, "EMU Right Playback Route"}, 918 {"EMU Left PGA", NULL, "EMU Left Playback Route"}, 919 920 /* Output Amplifier -> Output */ 921 {"EP", NULL, "Earpiece PGA"}, 922 {"SPKR", NULL, "Speaker Right PGA"}, 923 {"SPKL", NULL, "Speaker Left PGA"}, 924 {"LINER", NULL, "Lineout Right PGA"}, 925 {"LINEL", NULL, "Lineout Left PGA"}, 926 {"HSR", NULL, "Headset Right PGA"}, 927 {"HSL", NULL, "Headset Left PGA"}, 928 {"EMUR", NULL, "EMU Right PGA"}, 929 {"EMUL", NULL, "EMU Left PGA"}, 930 931 /* Headset Charge Pump -> Headset */ 932 {"HSR", NULL, "Headset Charge Pump"}, 933 {"HSL", NULL, "Headset Charge Pump"}, 934 935 /* Mic -> Mic Route */ 936 {"Right Capture Route", "Mic 1", "MICR"}, 937 {"Right Capture Route", "Headset Mic", "HSMIC"}, 938 {"Right Capture Route", "EMU Mic", "EMUMIC"}, 939 {"Right Capture Route", "Ext Right", "EXTR"}, 940 {"Left Capture Route", "Mic 2", "MICL"}, 941 {"Left Capture Route", "Ext Left", "EXTL"}, 942 943 /* Input Route -> Microphone PGA */ 944 {"Microphone 1 PGA", NULL, "Right Capture Route"}, 945 {"Microphone 2 PGA", NULL, "Left Capture Route"}, 946 947 /* Microphone PGA -> ADC */ 948 {"ADC Right", NULL, "Microphone 1 PGA"}, 949 {"ADC Left", NULL, "Microphone 2 PGA"}, 950 951 /* ADC -> Stream */ 952 {"Highpass Filter TX", NULL, "ADC Right"}, 953 {"Highpass Filter TX", NULL, "ADC Left"}, 954 955 /* Mic Bias */ 956 {"MICL", NULL, "MIC1L Bias"}, 957 {"MICR", NULL, "MIC1R Bias"}, 958 }; 959 960 static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai, 961 int clk_id, int freq) 962 { 963 u16 clkfreqreg, clkfreqshift; 964 u16 clkfreqmask, clkfreqval; 965 u16 clkidreg, clkidshift; 966 u16 mask, val; 967 int err; 968 969 switch (dai) { 970 case CPCAP_DAI_HIFI: 971 clkfreqreg = CPCAP_REG_SDAC; 972 clkfreqshift = CPCAP_BIT_ST_DAC_CLK0; 973 clkidreg = CPCAP_REG_SDACDI; 974 clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL; 975 break; 976 case CPCAP_DAI_VOICE: 977 clkfreqreg = CPCAP_REG_CC; 978 clkfreqshift = CPCAP_BIT_CDC_CLK0; 979 clkidreg = CPCAP_REG_CDI; 980 clkidshift = CPCAP_BIT_CLK_IN_SEL; 981 break; 982 default: 983 dev_err(cpcap->component->dev, "invalid DAI: %d", dai); 984 return -EINVAL; 985 } 986 987 /* setup clk id */ 988 if (clk_id < 0 || clk_id > 1) { 989 dev_err(cpcap->component->dev, "invalid clk id %d", clk_id); 990 return -EINVAL; 991 } 992 err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift), 993 clk_id ? BIT(clkidshift) : 0); 994 if (err) 995 return err; 996 997 /* enable PLL for Voice DAI */ 998 if (dai == CPCAP_DAI_VOICE) { 999 mask = BIT(CPCAP_BIT_CDC_PLL_SEL); 1000 val = BIT(CPCAP_BIT_CDC_PLL_SEL); 1001 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1002 mask, val); 1003 if (err) 1004 return err; 1005 } 1006 1007 /* setup frequency */ 1008 clkfreqmask = 0x7 << clkfreqshift; 1009 switch (freq) { 1010 case 15360000: 1011 clkfreqval = 0x01 << clkfreqshift; 1012 break; 1013 case 16800000: 1014 clkfreqval = 0x02 << clkfreqshift; 1015 break; 1016 case 19200000: 1017 clkfreqval = 0x03 << clkfreqshift; 1018 break; 1019 case 26000000: 1020 clkfreqval = 0x04 << clkfreqshift; 1021 break; 1022 case 33600000: 1023 clkfreqval = 0x05 << clkfreqshift; 1024 break; 1025 case 38400000: 1026 clkfreqval = 0x06 << clkfreqshift; 1027 break; 1028 default: 1029 dev_err(cpcap->component->dev, "unsupported freq %u", freq); 1030 return -EINVAL; 1031 } 1032 1033 err = regmap_update_bits(cpcap->regmap, clkfreqreg, 1034 clkfreqmask, clkfreqval); 1035 if (err) 1036 return err; 1037 1038 if (dai == CPCAP_DAI_VOICE) { 1039 cpcap->codec_clk_id = clk_id; 1040 cpcap->codec_freq = freq; 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai, 1047 int samplerate) 1048 { 1049 struct snd_soc_component *component = cpcap->component; 1050 u16 sampreg, sampmask, sampshift, sampval, sampreset; 1051 int err, sampreadval; 1052 1053 switch (dai) { 1054 case CPCAP_DAI_HIFI: 1055 sampreg = CPCAP_REG_SDAC; 1056 sampshift = CPCAP_BIT_ST_SR0; 1057 sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) | 1058 BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET); 1059 break; 1060 case CPCAP_DAI_VOICE: 1061 sampreg = CPCAP_REG_CC; 1062 sampshift = CPCAP_BIT_CDC_SR0; 1063 sampreset = BIT(CPCAP_BIT_DF_RESET) | 1064 BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET); 1065 break; 1066 default: 1067 dev_err(component->dev, "invalid DAI: %d", dai); 1068 return -EINVAL; 1069 } 1070 1071 sampmask = 0xF << sampshift | sampreset; 1072 switch (samplerate) { 1073 case 48000: 1074 sampval = 0x8 << sampshift; 1075 break; 1076 case 44100: 1077 sampval = 0x7 << sampshift; 1078 break; 1079 case 32000: 1080 sampval = 0x6 << sampshift; 1081 break; 1082 case 24000: 1083 sampval = 0x5 << sampshift; 1084 break; 1085 case 22050: 1086 sampval = 0x4 << sampshift; 1087 break; 1088 case 16000: 1089 sampval = 0x3 << sampshift; 1090 break; 1091 case 12000: 1092 sampval = 0x2 << sampshift; 1093 break; 1094 case 11025: 1095 sampval = 0x1 << sampshift; 1096 break; 1097 case 8000: 1098 sampval = 0x0 << sampshift; 1099 break; 1100 default: 1101 dev_err(component->dev, "unsupported samplerate %d", samplerate); 1102 return -EINVAL; 1103 } 1104 err = regmap_update_bits(cpcap->regmap, sampreg, 1105 sampmask, sampval | sampreset); 1106 if (err) 1107 return err; 1108 1109 /* Wait for clock tree reset to complete */ 1110 mdelay(CLOCK_TREE_RESET_TIME); 1111 1112 err = regmap_read(cpcap->regmap, sampreg, &sampreadval); 1113 if (err) 1114 return err; 1115 1116 if (sampreadval & sampreset) { 1117 dev_err(component->dev, "reset self-clear failed: %04x", 1118 sampreadval); 1119 return -EIO; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream, 1126 struct snd_pcm_hw_params *params, 1127 struct snd_soc_dai *dai) 1128 { 1129 struct snd_soc_component *component = dai->component; 1130 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1131 int rate = params_rate(params); 1132 1133 dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate); 1134 return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate); 1135 } 1136 1137 static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 1138 unsigned int freq, int dir) 1139 { 1140 struct snd_soc_component *component = codec_dai->component; 1141 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1142 struct device *dev = component->dev; 1143 1144 dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq); 1145 return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq); 1146 } 1147 1148 static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai, 1149 unsigned int fmt) 1150 { 1151 struct snd_soc_component *component = codec_dai->component; 1152 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1153 struct device *dev = component->dev; 1154 static const u16 reg = CPCAP_REG_SDACDI; 1155 static const u16 mask = 1156 BIT(CPCAP_BIT_SMB_ST_DAC) | 1157 BIT(CPCAP_BIT_ST_CLK_INV) | 1158 BIT(CPCAP_BIT_ST_FS_INV) | 1159 BIT(CPCAP_BIT_ST_DIG_AUD_FS0) | 1160 BIT(CPCAP_BIT_ST_DIG_AUD_FS1) | 1161 BIT(CPCAP_BIT_ST_L_TIMESLOT0) | 1162 BIT(CPCAP_BIT_ST_L_TIMESLOT1) | 1163 BIT(CPCAP_BIT_ST_L_TIMESLOT2) | 1164 BIT(CPCAP_BIT_ST_R_TIMESLOT0) | 1165 BIT(CPCAP_BIT_ST_R_TIMESLOT1) | 1166 BIT(CPCAP_BIT_ST_R_TIMESLOT2); 1167 u16 val = 0x0000; 1168 1169 dev_dbg(dev, "HiFi setup dai format (%08x)", fmt); 1170 1171 /* 1172 * "HiFi Playback" should always be configured as 1173 * SND_SOC_DAIFMT_CBP_CFP - codec clk & frm provider 1174 * SND_SOC_DAIFMT_I2S - I2S mode 1175 */ 1176 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1177 case SND_SOC_DAIFMT_CBP_CFP: 1178 val &= ~BIT(CPCAP_BIT_SMB_ST_DAC); 1179 break; 1180 default: 1181 dev_err(dev, "HiFi dai fmt failed: CPCAP should be provider"); 1182 return -EINVAL; 1183 } 1184 1185 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1186 case SND_SOC_DAIFMT_IB_IF: 1187 val |= BIT(CPCAP_BIT_ST_FS_INV); 1188 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1189 break; 1190 case SND_SOC_DAIFMT_IB_NF: 1191 val &= ~BIT(CPCAP_BIT_ST_FS_INV); 1192 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1193 break; 1194 case SND_SOC_DAIFMT_NB_IF: 1195 val |= BIT(CPCAP_BIT_ST_FS_INV); 1196 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1197 break; 1198 case SND_SOC_DAIFMT_NB_NF: 1199 val &= ~BIT(CPCAP_BIT_ST_FS_INV); 1200 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1201 break; 1202 default: 1203 dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode"); 1204 return -EINVAL; 1205 } 1206 1207 if (val & BIT(CPCAP_BIT_ST_CLK_INV)) 1208 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1209 else 1210 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1211 1212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1213 case SND_SOC_DAIFMT_I2S: 1214 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); 1215 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1); 1216 break; 1217 default: 1218 /* 01 - 4 slots network mode */ 1219 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); 1220 val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1); 1221 /* L on slot 1 */ 1222 val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0); 1223 break; 1224 } 1225 1226 dev_dbg(dev, "HiFi dai format: val=%04x", val); 1227 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1228 } 1229 1230 static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction) 1231 { 1232 struct snd_soc_component *component = dai->component; 1233 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1234 static const u16 reg = CPCAP_REG_RXSDOA; 1235 static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW); 1236 u16 val; 1237 1238 if (mute) 1239 val = 0; 1240 else 1241 val = BIT(CPCAP_BIT_ST_DAC_SW); 1242 1243 dev_dbg(component->dev, "HiFi mute: %d", mute); 1244 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1245 } 1246 1247 static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = { 1248 .hw_params = cpcap_hifi_hw_params, 1249 .set_sysclk = cpcap_hifi_set_dai_sysclk, 1250 .set_fmt = cpcap_hifi_set_dai_fmt, 1251 .mute_stream = cpcap_hifi_set_mute, 1252 .no_capture_mute = 1, 1253 }; 1254 1255 static int cpcap_voice_hw_params(struct snd_pcm_substream *substream, 1256 struct snd_pcm_hw_params *params, 1257 struct snd_soc_dai *dai) 1258 { 1259 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1260 struct snd_soc_component *component = dai->component; 1261 struct device *dev = component->dev; 1262 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1263 static const u16 reg_cdi = CPCAP_REG_CDI; 1264 int rate = params_rate(params); 1265 int channels = params_channels(params); 1266 int direction = substream->stream; 1267 u16 val, mask; 1268 int err; 1269 1270 dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d", 1271 rate, direction, channels); 1272 1273 err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate); 1274 if (err) 1275 return err; 1276 1277 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 1278 mask = 0x0000; 1279 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); 1280 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1); 1281 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2); 1282 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0); 1283 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1); 1284 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2); 1285 val = 0x0000; 1286 if (channels >= 2) 1287 val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); 1288 err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val); 1289 if (err) 1290 return err; 1291 } 1292 1293 return snd_soc_runtime_set_dai_fmt(rtd, rtd->dai_link->dai_fmt); 1294 } 1295 1296 static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 1297 unsigned int freq, int dir) 1298 { 1299 struct snd_soc_component *component = codec_dai->component; 1300 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1301 1302 dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u", 1303 clk_id, freq); 1304 return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq); 1305 } 1306 1307 static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, 1308 unsigned int fmt) 1309 { 1310 struct snd_soc_component *component = codec_dai->component; 1311 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1312 static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) | 1313 BIT(CPCAP_BIT_CLK_INV) | 1314 BIT(CPCAP_BIT_FS_INV) | 1315 BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) | 1316 BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1317 u16 val = 0x0000; 1318 int err; 1319 1320 dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt); 1321 1322 /* 1323 * "Voice Playback" and "Voice Capture" should always be 1324 * configured as SND_SOC_DAIFMT_CBP_CFP - codec clk & frm 1325 * provider 1326 */ 1327 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1328 case SND_SOC_DAIFMT_CBP_CFP: 1329 val &= ~BIT(CPCAP_BIT_SMB_CDC); 1330 break; 1331 default: 1332 dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the provider"); 1333 val &= ~BIT(CPCAP_BIT_SMB_CDC); 1334 break; 1335 } 1336 1337 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1338 case SND_SOC_DAIFMT_IB_IF: 1339 val |= BIT(CPCAP_BIT_CLK_INV); 1340 val |= BIT(CPCAP_BIT_FS_INV); 1341 break; 1342 case SND_SOC_DAIFMT_IB_NF: 1343 val |= BIT(CPCAP_BIT_CLK_INV); 1344 val &= ~BIT(CPCAP_BIT_FS_INV); 1345 break; 1346 case SND_SOC_DAIFMT_NB_IF: 1347 val &= ~BIT(CPCAP_BIT_CLK_INV); 1348 val |= BIT(CPCAP_BIT_FS_INV); 1349 break; 1350 case SND_SOC_DAIFMT_NB_NF: 1351 val &= ~BIT(CPCAP_BIT_CLK_INV); 1352 val &= ~BIT(CPCAP_BIT_FS_INV); 1353 break; 1354 default: 1355 dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode"); 1356 break; 1357 } 1358 1359 if (val & BIT(CPCAP_BIT_CLK_INV)) 1360 val &= ~BIT(CPCAP_BIT_CLK_INV); 1361 else 1362 val |= BIT(CPCAP_BIT_CLK_INV); 1363 1364 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1365 case SND_SOC_DAIFMT_I2S: 1366 /* 11 - true I2S mode */ 1367 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); 1368 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1369 break; 1370 default: 1371 /* 4 timeslots network mode */ 1372 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); 1373 val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1374 break; 1375 } 1376 1377 dev_dbg(component->dev, "Voice dai format: val=%04x", val); 1378 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val); 1379 if (err) 1380 return err; 1381 1382 cpcap->codec_format = val; 1383 return 0; 1384 } 1385 1386 static int cpcap_voice_set_mute(struct snd_soc_dai *dai, 1387 int mute, int direction) 1388 { 1389 struct snd_soc_component *component = dai->component; 1390 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1391 static const u16 reg = CPCAP_REG_RXCOA; 1392 static const u16 mask = BIT(CPCAP_BIT_CDC_SW); 1393 u16 val; 1394 1395 if (mute) 1396 val = 0; 1397 else 1398 val = BIT(CPCAP_BIT_CDC_SW); 1399 1400 dev_dbg(component->dev, "Voice mute: %d", mute); 1401 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1402 }; 1403 1404 static const struct snd_soc_dai_ops cpcap_dai_voice_ops = { 1405 .hw_params = cpcap_voice_hw_params, 1406 .set_sysclk = cpcap_voice_set_dai_sysclk, 1407 .set_fmt = cpcap_voice_set_dai_fmt, 1408 .mute_stream = cpcap_voice_set_mute, 1409 .no_capture_mute = 1, 1410 }; 1411 1412 static struct snd_soc_dai_driver cpcap_dai[] = { 1413 { 1414 .id = 0, 1415 .name = "cpcap-hifi", 1416 .playback = { 1417 .stream_name = "HiFi Playback", 1418 .channels_min = 2, 1419 .channels_max = 2, 1420 .rates = SNDRV_PCM_RATE_8000_48000, 1421 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE, 1422 }, 1423 .ops = &cpcap_dai_hifi_ops, 1424 }, 1425 { 1426 .id = 1, 1427 .name = "cpcap-voice", 1428 .playback = { 1429 .stream_name = "Voice Playback", 1430 .channels_min = 1, 1431 .channels_max = 1, 1432 .rates = SNDRV_PCM_RATE_8000_48000, 1433 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1434 }, 1435 .capture = { 1436 .stream_name = "Voice Capture", 1437 .channels_min = 1, 1438 .channels_max = 2, 1439 .rates = SNDRV_PCM_RATE_8000_48000, 1440 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1441 }, 1442 .ops = &cpcap_dai_voice_ops, 1443 }, 1444 }; 1445 1446 static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration) 1447 { 1448 u16 hifi_val, voice_val; 1449 u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC); 1450 u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN); 1451 int err; 1452 1453 1454 1455 if (!swap_dai_configuration) { 1456 /* Codec on DAI0, HiFi on DAI1 */ 1457 voice_val = 0; 1458 hifi_val = hifi_mask; 1459 } else { 1460 /* Codec on DAI1, HiFi on DAI0 */ 1461 voice_val = voice_mask; 1462 hifi_val = 0; 1463 } 1464 1465 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1466 voice_mask, voice_val); 1467 if (err) 1468 return err; 1469 1470 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI, 1471 hifi_mask, hifi_val); 1472 if (err) 1473 return err; 1474 1475 return 0; 1476 } 1477 1478 static int cpcap_audio_reset(struct snd_soc_component *component, 1479 bool swap_dai_configuration) 1480 { 1481 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1482 int i, err = 0; 1483 1484 dev_dbg(component->dev, "init audio codec"); 1485 1486 for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) { 1487 err = regmap_update_bits(cpcap->regmap, 1488 cpcap_default_regs[i].reg, 1489 cpcap_default_regs[i].mask, 1490 cpcap_default_regs[i].val); 1491 if (err) 1492 return err; 1493 } 1494 1495 /* setup default settings */ 1496 err = cpcap_dai_mux(cpcap, swap_dai_configuration); 1497 if (err) 1498 return err; 1499 1500 err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000); 1501 if (err) 1502 return err; 1503 err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000); 1504 if (err) 1505 return err; 1506 1507 err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000); 1508 if (err) 1509 return err; 1510 1511 err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000); 1512 if (err) 1513 return err; 1514 1515 return 0; 1516 } 1517 1518 static irqreturn_t cpcap_hs_irq_thread(int irq, void *data) 1519 { 1520 struct snd_soc_component *component = data; 1521 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1522 struct regmap *regmap = cpcap->regmap; 1523 int status = 0; 1524 int mask = SND_JACK_HEADSET; 1525 int val; 1526 1527 if (!regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S))) { 1528 val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN); 1529 regmap_update_bits(regmap, CPCAP_REG_TXI, val, val); 1530 1531 val = BIT(CPCAP_BIT_ST_HS_CP_EN); 1532 regmap_update_bits(regmap, CPCAP_REG_RXOA, val, val); 1533 1534 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL); 1535 1536 /* Give PTTS time to settle */ 1537 msleep(20); 1538 1539 if (!regmap_test_bits(regmap, CPCAP_REG_INTS2, 1540 BIT(CPCAP_BIT_PTT_S))) { 1541 /* Headphones detected. (May also be a headset with the 1542 * MFB pressed.) 1543 */ 1544 status = SND_JACK_HEADPHONE; 1545 dev_info(component->dev, "HP plugged in\n"); 1546 } else if (regmap_test_bits(regmap, CPCAP_REG_INTS1, 1547 BIT(CPCAP_BIT_MB2_S)) == 1) { 1548 status = SND_JACK_HEADSET; 1549 dev_info(component->dev, "HS plugged in\n"); 1550 } else 1551 dev_info(component->dev, "Unsupported HS plugged in\n"); 1552 } else { 1553 bool mic = cpcap->jack.status & SND_JACK_MICROPHONE; 1554 1555 dev_info(component->dev, "H%s disconnect\n", mic ? "S" : "P"); 1556 val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN); 1557 regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, val, 0); 1558 1559 val = BIT(CPCAP_BIT_ST_HS_CP_EN); 1560 regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA, val, 0); 1561 1562 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY); 1563 1564 mask |= SND_JACK_BTN_0; 1565 } 1566 1567 snd_soc_jack_report(&cpcap->jack, status, mask); 1568 1569 return IRQ_HANDLED; 1570 } 1571 1572 static irqreturn_t cpcap_mb2_irq_thread(int irq, void *data) 1573 { 1574 struct snd_soc_component *component = data; 1575 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1576 struct regmap *regmap = cpcap->regmap; 1577 int status = 0; 1578 int mb2; 1579 int ptt; 1580 1581 if (regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S)) == 1) 1582 return IRQ_HANDLED; 1583 1584 mb2 = regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_MB2_S)); 1585 ptt = regmap_test_bits(regmap, CPCAP_REG_INTS2, BIT(CPCAP_BIT_PTT_S)); 1586 1587 /* Initial detection might have been with MFB pressed */ 1588 if (!(cpcap->jack.status & SND_JACK_MICROPHONE)) { 1589 if (ptt == 1 && mb2 == 1) { 1590 dev_info(component->dev, "MIC plugged in\n"); 1591 snd_soc_jack_report(&cpcap->jack, SND_JACK_MICROPHONE, 1592 SND_JACK_MICROPHONE); 1593 } 1594 1595 return IRQ_HANDLED; 1596 } 1597 1598 if (!mb2 || !ptt) 1599 status = SND_JACK_BTN_0; 1600 1601 snd_soc_jack_report(&cpcap->jack, status, SND_JACK_BTN_0); 1602 1603 return IRQ_HANDLED; 1604 } 1605 1606 static int cpcap_soc_probe(struct snd_soc_component *component) 1607 { 1608 struct platform_device *pdev = to_platform_device(component->dev); 1609 struct snd_soc_card *card = component->card; 1610 struct cpcap_audio *cpcap; 1611 int err; 1612 1613 cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL); 1614 if (!cpcap) 1615 return -ENOMEM; 1616 1617 snd_soc_component_set_drvdata(component, cpcap); 1618 cpcap->component = component; 1619 1620 cpcap->vaudio = devm_regulator_get(component->dev, "VAUDIO"); 1621 if (IS_ERR(cpcap->vaudio)) 1622 return dev_err_probe(component->dev, PTR_ERR(cpcap->vaudio), 1623 "Cannot get VAUDIO regulator\n"); 1624 1625 err = snd_soc_card_jack_new(card, "Headphones", 1626 SND_JACK_HEADSET | SND_JACK_BTN_0, 1627 &cpcap->jack); 1628 if (err < 0) { 1629 dev_err(component->dev, "Cannot create HS jack: %i\n", err); 1630 return err; 1631 } 1632 1633 snd_jack_set_key(cpcap->jack.jack, SND_JACK_BTN_0, KEY_MEDIA); 1634 1635 cpcap->regmap = dev_get_regmap(component->dev->parent, NULL); 1636 if (!cpcap->regmap) 1637 return -ENODEV; 1638 snd_soc_component_init_regmap(component, cpcap->regmap); 1639 1640 err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor); 1641 if (err) 1642 return err; 1643 1644 cpcap->hsirq = platform_get_irq_byname(pdev, "hs"); 1645 if (cpcap->hsirq < 0) 1646 return cpcap->hsirq; 1647 1648 err = devm_request_threaded_irq(component->dev, cpcap->hsirq, NULL, 1649 cpcap_hs_irq_thread, 1650 IRQF_TRIGGER_RISING | 1651 IRQF_TRIGGER_FALLING | 1652 IRQF_ONESHOT, 1653 "cpcap-codec-hs", 1654 component); 1655 if (err) { 1656 dev_warn(component->dev, "no HS irq%i: %i\n", 1657 cpcap->hsirq, err); 1658 return err; 1659 } 1660 1661 cpcap->mb2irq = platform_get_irq_byname(pdev, "mb2"); 1662 if (cpcap->mb2irq < 0) 1663 return cpcap->mb2irq; 1664 1665 err = devm_request_threaded_irq(component->dev, cpcap->mb2irq, NULL, 1666 cpcap_mb2_irq_thread, 1667 IRQF_TRIGGER_RISING | 1668 IRQF_TRIGGER_FALLING | 1669 IRQF_ONESHOT, 1670 "cpcap-codec-mb2", 1671 component); 1672 if (err) { 1673 dev_warn(component->dev, "no MB2 irq%i: %i\n", 1674 cpcap->mb2irq, err); 1675 return err; 1676 } 1677 1678 err = cpcap_audio_reset(component, false); 1679 if (err) 1680 return err; 1681 1682 cpcap_hs_irq_thread(cpcap->hsirq, component); 1683 1684 enable_irq_wake(cpcap->hsirq); 1685 enable_irq_wake(cpcap->mb2irq); 1686 1687 return 0; 1688 } 1689 1690 static void cpcap_soc_remove(struct snd_soc_component *component) 1691 { 1692 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1693 1694 disable_irq_wake(cpcap->hsirq); 1695 disable_irq_wake(cpcap->mb2irq); 1696 } 1697 1698 static int cpcap_set_bias_level(struct snd_soc_component *component, 1699 enum snd_soc_bias_level level) 1700 { 1701 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1702 1703 /* VAIDIO should be kept in normal mode in order MIC/PTT to work */ 1704 if (cpcap->jack.status & SND_JACK_MICROPHONE) 1705 return 0; 1706 1707 switch (level) { 1708 case SND_SOC_BIAS_OFF: 1709 break; 1710 case SND_SOC_BIAS_PREPARE: 1711 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL); 1712 break; 1713 case SND_SOC_BIAS_STANDBY: 1714 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY); 1715 break; 1716 case SND_SOC_BIAS_ON: 1717 break; 1718 } 1719 1720 return 0; 1721 } 1722 1723 static const struct snd_soc_component_driver soc_codec_dev_cpcap = { 1724 .probe = cpcap_soc_probe, 1725 .remove = cpcap_soc_remove, 1726 .controls = cpcap_snd_controls, 1727 .num_controls = ARRAY_SIZE(cpcap_snd_controls), 1728 .dapm_widgets = cpcap_dapm_widgets, 1729 .num_dapm_widgets = ARRAY_SIZE(cpcap_dapm_widgets), 1730 .dapm_routes = intercon, 1731 .num_dapm_routes = ARRAY_SIZE(intercon), 1732 .set_bias_level = cpcap_set_bias_level, 1733 .idle_bias_on = 1, 1734 .use_pmdown_time = 1, 1735 .endianness = 1, 1736 }; 1737 1738 static int cpcap_codec_probe(struct platform_device *pdev) 1739 { 1740 struct device_node *codec_node = 1741 of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec"); 1742 if (!codec_node) 1743 return -ENODEV; 1744 1745 pdev->dev.of_node = codec_node; 1746 1747 return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap, 1748 cpcap_dai, ARRAY_SIZE(cpcap_dai)); 1749 } 1750 1751 static struct platform_driver cpcap_codec_driver = { 1752 .probe = cpcap_codec_probe, 1753 .driver = { 1754 .name = "cpcap-codec", 1755 }, 1756 }; 1757 module_platform_driver(cpcap_codec_driver); 1758 1759 MODULE_ALIAS("platform:cpcap-codec"); 1760 MODULE_DESCRIPTION("ASoC CPCAP codec driver"); 1761 MODULE_AUTHOR("Sebastian Reichel"); 1762 MODULE_LICENSE("GPL v2"); 1763