1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC CPCAP codec driver 4 * 5 * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org> 6 * 7 * Very loosely based on original driver from Motorola: 8 * Copyright (C) 2007 - 2009 Motorola, Inc. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/platform_device.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/mfd/motorola-cpcap.h> 16 #include <sound/core.h> 17 #include <linux/input.h> 18 #include <sound/jack.h> 19 #include <sound/soc.h> 20 #include <sound/tlv.h> 21 22 /* Register 8 - CPCAP_REG_INTS1 --- Interrupt Sense 1 */ 23 #define CPCAP_BIT_HS_S 9 /* Headset */ 24 #define CPCAP_BIT_MB2_S 10 /* Mic Bias2 */ 25 26 /* Register 9 - CPCAP_REG_INTS2 --- Interrupt Sense 2 */ 27 #define CPCAP_BIT_PTT_S 11 /* Push To Talk */ 28 29 /* Register 512 CPCAP_REG_VAUDIOC --- Audio Regulator and Bias Voltage */ 30 #define CPCAP_BIT_AUDIO_LOW_PWR 6 31 #define CPCAP_BIT_AUD_LOWPWR_SPEED 5 32 #define CPCAP_BIT_VAUDIOPRISTBY 4 33 #define CPCAP_BIT_VAUDIO_MODE1 2 34 #define CPCAP_BIT_VAUDIO_MODE0 1 35 #define CPCAP_BIT_V_AUDIO_EN 0 36 37 /* Register 513 CPCAP_REG_CC --- CODEC */ 38 #define CPCAP_BIT_CDC_CLK2 15 39 #define CPCAP_BIT_CDC_CLK1 14 40 #define CPCAP_BIT_CDC_CLK0 13 41 #define CPCAP_BIT_CDC_SR3 12 42 #define CPCAP_BIT_CDC_SR2 11 43 #define CPCAP_BIT_CDC_SR1 10 44 #define CPCAP_BIT_CDC_SR0 9 45 #define CPCAP_BIT_CDC_CLOCK_TREE_RESET 8 46 #define CPCAP_BIT_MIC2_CDC_EN 7 47 #define CPCAP_BIT_CDC_EN_RX 6 48 #define CPCAP_BIT_DF_RESET 5 49 #define CPCAP_BIT_MIC1_CDC_EN 4 50 #define CPCAP_BIT_AUDOHPF_1 3 51 #define CPCAP_BIT_AUDOHPF_0 2 52 #define CPCAP_BIT_AUDIHPF_1 1 53 #define CPCAP_BIT_AUDIHPF_0 0 54 55 /* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */ 56 #define CPCAP_BIT_CDC_PLL_SEL 15 57 #define CPCAP_BIT_CLK_IN_SEL 13 58 #define CPCAP_BIT_DIG_AUD_IN 12 59 #define CPCAP_BIT_CDC_CLK_EN 11 60 #define CPCAP_BIT_CDC_DIG_AUD_FS1 10 61 #define CPCAP_BIT_CDC_DIG_AUD_FS0 9 62 #define CPCAP_BIT_MIC2_TIMESLOT2 8 63 #define CPCAP_BIT_MIC2_TIMESLOT1 7 64 #define CPCAP_BIT_MIC2_TIMESLOT0 6 65 #define CPCAP_BIT_MIC1_RX_TIMESLOT2 5 66 #define CPCAP_BIT_MIC1_RX_TIMESLOT1 4 67 #define CPCAP_BIT_MIC1_RX_TIMESLOT0 3 68 #define CPCAP_BIT_FS_INV 2 69 #define CPCAP_BIT_CLK_INV 1 70 #define CPCAP_BIT_SMB_CDC 0 71 72 /* Register 515 CPCAP_REG_SDAC --- Stereo DAC */ 73 #define CPCAP_BIT_FSYNC_CLK_IN_COMMON 11 74 #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT 10 75 #define CPCAP_BIT_ST_CLOCK_TREE_RESET 9 76 #define CPCAP_BIT_DF_RESET_ST_DAC 8 77 #define CPCAP_BIT_ST_SR3 7 78 #define CPCAP_BIT_ST_SR2 6 79 #define CPCAP_BIT_ST_SR1 5 80 #define CPCAP_BIT_ST_SR0 4 81 #define CPCAP_BIT_ST_DAC_CLK2 3 82 #define CPCAP_BIT_ST_DAC_CLK1 2 83 #define CPCAP_BIT_ST_DAC_CLK0 1 84 #define CPCAP_BIT_ST_DAC_EN 0 85 86 /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */ 87 #define CPCAP_BIT_ST_L_TIMESLOT2 13 88 #define CPCAP_BIT_ST_L_TIMESLOT1 12 89 #define CPCAP_BIT_ST_L_TIMESLOT0 11 90 #define CPCAP_BIT_ST_R_TIMESLOT2 10 91 #define CPCAP_BIT_ST_R_TIMESLOT1 9 92 #define CPCAP_BIT_ST_R_TIMESLOT0 8 93 #define CPCAP_BIT_ST_DAC_CLK_IN_SEL 7 94 #define CPCAP_BIT_ST_FS_INV 6 95 #define CPCAP_BIT_ST_CLK_INV 5 96 #define CPCAP_BIT_ST_DIG_AUD_FS1 4 97 #define CPCAP_BIT_ST_DIG_AUD_FS0 3 98 #define CPCAP_BIT_DIG_AUD_IN_ST_DAC 2 99 #define CPCAP_BIT_ST_CLK_EN 1 100 #define CPCAP_BIT_SMB_ST_DAC 0 101 102 /* Register 517 CPCAP_REG_TXI --- TX Interface */ 103 #define CPCAP_BIT_PTT_TH 15 104 #define CPCAP_BIT_PTT_CMP_EN 14 105 #define CPCAP_BIT_HS_ID_TX 13 106 #define CPCAP_BIT_MB_ON2 12 107 #define CPCAP_BIT_MB_ON1L 11 108 #define CPCAP_BIT_MB_ON1R 10 109 #define CPCAP_BIT_RX_L_ENCODE 9 110 #define CPCAP_BIT_RX_R_ENCODE 8 111 #define CPCAP_BIT_MIC2_MUX 7 112 #define CPCAP_BIT_MIC2_PGA_EN 6 113 #define CPCAP_BIT_CDET_DIS 5 114 #define CPCAP_BIT_EMU_MIC_MUX 4 115 #define CPCAP_BIT_HS_MIC_MUX 3 116 #define CPCAP_BIT_MIC1_MUX 2 117 #define CPCAP_BIT_MIC1_PGA_EN 1 118 #define CPCAP_BIT_DLM 0 119 120 /* Register 518 CPCAP_REG_TXMP --- Mic Gain */ 121 #define CPCAP_BIT_MB_BIAS_R1 11 122 #define CPCAP_BIT_MB_BIAS_R0 10 123 #define CPCAP_BIT_MIC2_GAIN_4 9 124 #define CPCAP_BIT_MIC2_GAIN_3 8 125 #define CPCAP_BIT_MIC2_GAIN_2 7 126 #define CPCAP_BIT_MIC2_GAIN_1 6 127 #define CPCAP_BIT_MIC2_GAIN_0 5 128 #define CPCAP_BIT_MIC1_GAIN_4 4 129 #define CPCAP_BIT_MIC1_GAIN_3 3 130 #define CPCAP_BIT_MIC1_GAIN_2 2 131 #define CPCAP_BIT_MIC1_GAIN_1 1 132 #define CPCAP_BIT_MIC1_GAIN_0 0 133 134 /* Register 519 CPCAP_REG_RXOA --- RX Output Amplifier */ 135 #define CPCAP_BIT_UNUSED_519_15 15 136 #define CPCAP_BIT_UNUSED_519_14 14 137 #define CPCAP_BIT_UNUSED_519_13 13 138 #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12 139 #define CPCAP_BIT_HS_LOW_PWR 11 140 #define CPCAP_BIT_HS_ID_RX 10 141 #define CPCAP_BIT_ST_HS_CP_EN 9 142 #define CPCAP_BIT_EMU_SPKR_R_EN 8 143 #define CPCAP_BIT_EMU_SPKR_L_EN 7 144 #define CPCAP_BIT_HS_L_EN 6 145 #define CPCAP_BIT_HS_R_EN 5 146 #define CPCAP_BIT_A4_LINEOUT_L_EN 4 147 #define CPCAP_BIT_A4_LINEOUT_R_EN 3 148 #define CPCAP_BIT_A2_LDSP_L_EN 2 149 #define CPCAP_BIT_A2_LDSP_R_EN 1 150 #define CPCAP_BIT_A1_EAR_EN 0 151 152 /* Register 520 CPCAP_REG_RXVC --- RX Volume Control */ 153 #define CPCAP_BIT_VOL_EXT3 15 154 #define CPCAP_BIT_VOL_EXT2 14 155 #define CPCAP_BIT_VOL_EXT1 13 156 #define CPCAP_BIT_VOL_EXT0 12 157 #define CPCAP_BIT_VOL_DAC3 11 158 #define CPCAP_BIT_VOL_DAC2 10 159 #define CPCAP_BIT_VOL_DAC1 9 160 #define CPCAP_BIT_VOL_DAC0 8 161 #define CPCAP_BIT_VOL_DAC_LSB_1dB1 7 162 #define CPCAP_BIT_VOL_DAC_LSB_1dB0 6 163 #define CPCAP_BIT_VOL_CDC3 5 164 #define CPCAP_BIT_VOL_CDC2 4 165 #define CPCAP_BIT_VOL_CDC1 3 166 #define CPCAP_BIT_VOL_CDC0 2 167 #define CPCAP_BIT_VOL_CDC_LSB_1dB1 1 168 #define CPCAP_BIT_VOL_CDC_LSB_1dB0 0 169 170 /* Register 521 CPCAP_REG_RXCOA --- Codec to Output Amp Switches */ 171 #define CPCAP_BIT_PGA_CDC_EN 10 172 #define CPCAP_BIT_CDC_SW 9 173 #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW 8 174 #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW 7 175 #define CPCAP_BIT_ALEFT_HS_CDC_SW 6 176 #define CPCAP_BIT_ARIGHT_HS_CDC_SW 5 177 #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW 4 178 #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW 3 179 #define CPCAP_BIT_A2_LDSP_L_CDC_SW 2 180 #define CPCAP_BIT_A2_LDSP_R_CDC_SW 1 181 #define CPCAP_BIT_A1_EAR_CDC_SW 0 182 183 /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */ 184 #define CPCAP_BIT_PGA_DAC_EN 12 185 #define CPCAP_BIT_ST_DAC_SW 11 186 #define CPCAP_BIT_MONO_DAC1 10 187 #define CPCAP_BIT_MONO_DAC0 9 188 #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW 8 189 #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW 7 190 #define CPCAP_BIT_ALEFT_HS_DAC_SW 6 191 #define CPCAP_BIT_ARIGHT_HS_DAC_SW 5 192 #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW 4 193 #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW 3 194 #define CPCAP_BIT_A2_LDSP_L_DAC_SW 2 195 #define CPCAP_BIT_A2_LDSP_R_DAC_SW 1 196 #define CPCAP_BIT_A1_EAR_DAC_SW 0 197 198 /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */ 199 #define CPCAP_BIT_PGA_EXT_L_EN 14 200 #define CPCAP_BIT_PGA_EXT_R_EN 13 201 #define CPCAP_BIT_PGA_IN_L_SW 12 202 #define CPCAP_BIT_PGA_IN_R_SW 11 203 #define CPCAP_BIT_MONO_EXT1 10 204 #define CPCAP_BIT_MONO_EXT0 9 205 #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW 8 206 #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW 7 207 #define CPCAP_BIT_ALEFT_HS_EXT_SW 6 208 #define CPCAP_BIT_ARIGHT_HS_EXT_SW 5 209 #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW 4 210 #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW 3 211 #define CPCAP_BIT_A2_LDSP_L_EXT_SW 2 212 #define CPCAP_BIT_A2_LDSP_R_EXT_SW 1 213 #define CPCAP_BIT_A1_EAR_EXT_SW 0 214 215 /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */ 216 #define CPCAP_BIT_NCP_CLK_SYNC 7 217 #define CPCAP_BIT_A2_CLK_SYNC 6 218 #define CPCAP_BIT_A2_FREE_RUN 5 219 #define CPCAP_BIT_A2_CLK2 4 220 #define CPCAP_BIT_A2_CLK1 3 221 #define CPCAP_BIT_A2_CLK0 2 222 #define CPCAP_BIT_A2_CLK_IN 1 223 #define CPCAP_BIT_A2_CONFIG 0 224 225 #define SLEEP_ACTIVATE_POWER 2 226 #define CLOCK_TREE_RESET_TIME 1 227 228 /* constants for ST delay workaround */ 229 #define STM_STDAC_ACTIVATE_RAMP_TIME 1 230 #define STM_STDAC_EN_TEST_PRE 0x090C 231 #define STM_STDAC_EN_TEST_POST 0x0000 232 #define STM_STDAC_EN_ST_TEST1_PRE 0x2400 233 #define STM_STDAC_EN_ST_TEST1_POST 0x0400 234 235 struct cpcap_reg_info { 236 u16 reg; 237 u16 mask; 238 u16 val; 239 }; 240 241 static const struct cpcap_reg_info cpcap_default_regs[] = { 242 { CPCAP_REG_VAUDIOC, 0x003F, 0x0000 }, 243 { CPCAP_REG_CC, 0xFFFF, 0x0000 }, 244 { CPCAP_REG_CC, 0xFFFF, 0x0000 }, 245 { CPCAP_REG_CDI, 0xBFFF, 0x0000 }, 246 { CPCAP_REG_SDAC, 0x0FFF, 0x0000 }, 247 { CPCAP_REG_SDACDI, 0x3FFF, 0x0000 }, 248 { CPCAP_REG_TXI, 0x0FDF, 0x0000 }, 249 { CPCAP_REG_TXMP, 0x0FFF, 0x0400 }, 250 { CPCAP_REG_RXOA, 0x01FF, 0x0000 }, 251 { CPCAP_REG_RXVC, 0xFF3C, 0x0000 }, 252 { CPCAP_REG_RXCOA, 0x07FF, 0x0000 }, 253 { CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 }, 254 { CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 }, 255 { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN), 256 BIT(CPCAP_BIT_A2_FREE_RUN) }, 257 }; 258 259 enum cpcap_dai { 260 CPCAP_DAI_HIFI, 261 CPCAP_DAI_VOICE, 262 }; 263 264 struct cpcap_audio { 265 struct snd_soc_component *component; 266 struct regmap *regmap; 267 268 u16 vendor; 269 270 int codec_clk_id; 271 int codec_freq; 272 int codec_format; 273 struct regulator *vaudio; 274 int hsirq; 275 int mb2irq; 276 struct snd_soc_jack jack; 277 }; 278 279 static int cpcap_st_workaround(struct snd_soc_dapm_widget *w, 280 struct snd_kcontrol *kcontrol, int event) 281 { 282 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 283 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 284 int err = 0; 285 286 /* Only CPCAP from ST requires workaround */ 287 if (cpcap->vendor != CPCAP_VENDOR_ST) 288 return 0; 289 290 switch (event) { 291 case SND_SOC_DAPM_PRE_PMU: 292 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST, 293 STM_STDAC_EN_TEST_PRE); 294 if (err) 295 return err; 296 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1, 297 STM_STDAC_EN_ST_TEST1_PRE); 298 break; 299 case SND_SOC_DAPM_POST_PMU: 300 msleep(STM_STDAC_ACTIVATE_RAMP_TIME); 301 302 err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1, 303 STM_STDAC_EN_ST_TEST1_POST); 304 if (err) 305 return err; 306 err = regmap_write(cpcap->regmap, CPCAP_REG_TEST, 307 STM_STDAC_EN_TEST_POST); 308 break; 309 default: 310 break; 311 } 312 313 return err; 314 } 315 316 /* Capture Gain Control: 0dB to 31dB in 1dB steps */ 317 static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0); 318 319 /* Playback Gain Control: -33dB to 12dB in 3dB steps */ 320 static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0); 321 322 static const struct snd_kcontrol_new cpcap_snd_controls[] = { 323 /* Playback Gain */ 324 SOC_SINGLE_TLV("HiFi Playback Volume", 325 CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv), 326 SOC_SINGLE_TLV("Voice Playback Volume", 327 CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv), 328 SOC_SINGLE_TLV("Ext Playback Volume", 329 CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv), 330 331 /* Capture Gain */ 332 SOC_SINGLE_TLV("Mic1 Capture Volume", 333 CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv), 334 SOC_SINGLE_TLV("Mic2 Capture Volume", 335 CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv), 336 337 /* Phase Invert */ 338 SOC_SINGLE("Hifi Left Phase Invert Switch", 339 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0), 340 SOC_SINGLE("Ext Left Phase Invert Switch", 341 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0), 342 }; 343 344 static const char * const cpcap_out_mux_texts[] = { 345 "Off", "Voice", "HiFi", "Ext" 346 }; 347 348 static const char * const cpcap_in_right_mux_texts[] = { 349 "Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right" 350 }; 351 352 static const char * const cpcap_in_left_mux_texts[] = { 353 "Off", "Mic 2", "Ext Left" 354 }; 355 356 /* 357 * input muxes use unusual register layout, so that we need to use custom 358 * getter/setter methods 359 */ 360 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum, 361 cpcap_in_left_mux_texts); 362 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum, 363 cpcap_in_right_mux_texts); 364 365 /* 366 * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA; 367 * even though the register layout makes it look like a mixer, this is a mux. 368 * Enabling multiple inputs will result in no audio being forwarded. 369 */ 370 static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts); 371 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts); 372 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts); 373 static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts); 374 static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts); 375 static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts); 376 static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts); 377 static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts); 378 static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts); 379 380 static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol, 381 struct snd_ctl_elem_value *ucontrol) 382 { 383 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 384 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 385 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 386 unsigned int shift = e->shift_l; 387 int reg_voice, reg_hifi, reg_ext, status; 388 int err; 389 390 err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, ®_voice); 391 if (err) 392 return err; 393 err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, ®_hifi); 394 if (err) 395 return err; 396 err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, ®_ext); 397 if (err) 398 return err; 399 400 reg_voice = (reg_voice >> shift) & 1; 401 reg_hifi = (reg_hifi >> shift) & 1; 402 reg_ext = (reg_ext >> shift) & 1; 403 status = reg_ext << 2 | reg_hifi << 1 | reg_voice; 404 405 switch (status) { 406 case 0x04: 407 ucontrol->value.enumerated.item[0] = 3; 408 break; 409 case 0x02: 410 ucontrol->value.enumerated.item[0] = 2; 411 break; 412 case 0x01: 413 ucontrol->value.enumerated.item[0] = 1; 414 break; 415 default: 416 ucontrol->value.enumerated.item[0] = 0; 417 break; 418 } 419 420 return 0; 421 } 422 423 static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol, 424 struct snd_ctl_elem_value *ucontrol) 425 { 426 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 427 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 428 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 429 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 430 unsigned int muxval = ucontrol->value.enumerated.item[0]; 431 unsigned int mask = BIT(e->shift_l); 432 u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00; 433 int err; 434 435 switch (muxval) { 436 case 1: 437 reg_voice = mask; 438 break; 439 case 2: 440 reg_hifi = mask; 441 break; 442 case 3: 443 reg_ext = mask; 444 break; 445 default: 446 break; 447 } 448 449 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA, 450 mask, reg_voice); 451 if (err) 452 return err; 453 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA, 454 mask, reg_hifi); 455 if (err) 456 return err; 457 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA, 458 mask, reg_ext); 459 if (err) 460 return err; 461 462 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 463 464 return 0; 465 } 466 467 static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol, 468 struct snd_ctl_elem_value *ucontrol) 469 { 470 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 471 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 472 int regval, mask; 473 int err; 474 475 err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); 476 if (err) 477 return err; 478 479 mask = 0; 480 mask |= BIT(CPCAP_BIT_MIC1_MUX); 481 mask |= BIT(CPCAP_BIT_HS_MIC_MUX); 482 mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); 483 mask |= BIT(CPCAP_BIT_RX_R_ENCODE); 484 485 switch (regval & mask) { 486 case BIT(CPCAP_BIT_RX_R_ENCODE): 487 ucontrol->value.enumerated.item[0] = 4; 488 break; 489 case BIT(CPCAP_BIT_EMU_MIC_MUX): 490 ucontrol->value.enumerated.item[0] = 3; 491 break; 492 case BIT(CPCAP_BIT_HS_MIC_MUX): 493 ucontrol->value.enumerated.item[0] = 2; 494 break; 495 case BIT(CPCAP_BIT_MIC1_MUX): 496 ucontrol->value.enumerated.item[0] = 1; 497 break; 498 default: 499 ucontrol->value.enumerated.item[0] = 0; 500 break; 501 } 502 503 return 0; 504 } 505 506 static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol, 507 struct snd_ctl_elem_value *ucontrol) 508 { 509 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 510 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 511 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 512 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 513 unsigned int muxval = ucontrol->value.enumerated.item[0]; 514 int regval = 0, mask; 515 int err; 516 517 mask = 0; 518 mask |= BIT(CPCAP_BIT_MIC1_MUX); 519 mask |= BIT(CPCAP_BIT_HS_MIC_MUX); 520 mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); 521 mask |= BIT(CPCAP_BIT_RX_R_ENCODE); 522 523 switch (muxval) { 524 case 1: 525 regval = BIT(CPCAP_BIT_MIC1_MUX); 526 break; 527 case 2: 528 regval = BIT(CPCAP_BIT_HS_MIC_MUX); 529 break; 530 case 3: 531 regval = BIT(CPCAP_BIT_EMU_MIC_MUX); 532 break; 533 case 4: 534 regval = BIT(CPCAP_BIT_RX_R_ENCODE); 535 break; 536 default: 537 break; 538 } 539 540 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 541 mask, regval); 542 if (err) 543 return err; 544 545 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 546 547 return 0; 548 } 549 550 static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol, 551 struct snd_ctl_elem_value *ucontrol) 552 { 553 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 554 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 555 int regval, mask; 556 int err; 557 558 err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, ®val); 559 if (err) 560 return err; 561 562 mask = 0; 563 mask |= BIT(CPCAP_BIT_MIC2_MUX); 564 mask |= BIT(CPCAP_BIT_RX_L_ENCODE); 565 566 switch (regval & mask) { 567 case BIT(CPCAP_BIT_RX_L_ENCODE): 568 ucontrol->value.enumerated.item[0] = 2; 569 break; 570 case BIT(CPCAP_BIT_MIC2_MUX): 571 ucontrol->value.enumerated.item[0] = 1; 572 break; 573 default: 574 ucontrol->value.enumerated.item[0] = 0; 575 break; 576 } 577 578 return 0; 579 } 580 581 static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol, 582 struct snd_ctl_elem_value *ucontrol) 583 { 584 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 585 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 586 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 587 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 588 unsigned int muxval = ucontrol->value.enumerated.item[0]; 589 int regval = 0, mask; 590 int err; 591 592 mask = 0; 593 mask |= BIT(CPCAP_BIT_MIC2_MUX); 594 mask |= BIT(CPCAP_BIT_RX_L_ENCODE); 595 596 switch (muxval) { 597 case 1: 598 regval = BIT(CPCAP_BIT_MIC2_MUX); 599 break; 600 case 2: 601 regval = BIT(CPCAP_BIT_RX_L_ENCODE); 602 break; 603 default: 604 break; 605 } 606 607 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 608 mask, regval); 609 if (err) 610 return err; 611 612 snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL); 613 614 return 0; 615 } 616 617 static const struct snd_kcontrol_new cpcap_input_left_mux = 618 SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum, 619 cpcap_input_left_mux_get_enum, 620 cpcap_input_left_mux_put_enum); 621 static const struct snd_kcontrol_new cpcap_input_right_mux = 622 SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum, 623 cpcap_input_right_mux_get_enum, 624 cpcap_input_right_mux_put_enum); 625 static const struct snd_kcontrol_new cpcap_emu_left_mux = 626 SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum, 627 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 628 static const struct snd_kcontrol_new cpcap_emu_right_mux = 629 SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum, 630 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 631 static const struct snd_kcontrol_new cpcap_hs_left_mux = 632 SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum, 633 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 634 static const struct snd_kcontrol_new cpcap_hs_right_mux = 635 SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum, 636 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 637 static const struct snd_kcontrol_new cpcap_line_left_mux = 638 SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum, 639 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 640 static const struct snd_kcontrol_new cpcap_line_right_mux = 641 SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum, 642 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 643 static const struct snd_kcontrol_new cpcap_speaker_left_mux = 644 SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum, 645 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 646 static const struct snd_kcontrol_new cpcap_speaker_right_mux = 647 SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum, 648 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 649 static const struct snd_kcontrol_new cpcap_earpiece_mux = 650 SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum, 651 cpcap_output_mux_get_enum, cpcap_output_mux_put_enum); 652 653 static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = { 654 SOC_DAPM_SINGLE("HiFi Mono Playback Switch", 655 CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0), 656 }; 657 static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = { 658 SOC_DAPM_SINGLE("Ext Mono Playback Switch", 659 CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0), 660 }; 661 662 static const struct snd_kcontrol_new cpcap_extr_mute_control = 663 SOC_DAPM_SINGLE("Switch", 664 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0); 665 static const struct snd_kcontrol_new cpcap_extl_mute_control = 666 SOC_DAPM_SINGLE("Switch", 667 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0); 668 669 static const struct snd_kcontrol_new cpcap_voice_loopback = 670 SOC_DAPM_SINGLE("Switch", 671 CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0); 672 673 static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = { 674 /* DAIs */ 675 SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0), 676 SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0), 677 SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0), 678 679 /* Power Supply */ 680 SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0), 681 682 /* Highpass Filters */ 683 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX", 684 CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0), 685 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX", 686 CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0), 687 688 /* Clocks */ 689 SND_SOC_DAPM_SUPPLY("HiFi DAI Clock", 690 CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0), 691 SND_SOC_DAPM_SUPPLY("Voice DAI Clock", 692 CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0), 693 694 /* Microphone Bias */ 695 SND_SOC_DAPM_SUPPLY("MIC1R Bias", 696 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0), 697 SND_SOC_DAPM_SUPPLY("MIC1L Bias", 698 CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0), 699 SND_SOC_DAPM_SUPPLY("MIC2 Bias", 700 CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0), 701 702 /* Inputs */ 703 SND_SOC_DAPM_INPUT("MICR"), 704 SND_SOC_DAPM_INPUT("HSMIC"), 705 SND_SOC_DAPM_INPUT("EMUMIC"), 706 SND_SOC_DAPM_INPUT("MICL"), 707 SND_SOC_DAPM_INPUT("EXTR"), 708 SND_SOC_DAPM_INPUT("EXTL"), 709 710 /* Capture Route */ 711 SND_SOC_DAPM_MUX("Right Capture Route", 712 SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux), 713 SND_SOC_DAPM_MUX("Left Capture Route", 714 SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux), 715 716 /* Capture PGAs */ 717 SND_SOC_DAPM_PGA("Microphone 1 PGA", 718 CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0), 719 SND_SOC_DAPM_PGA("Microphone 2 PGA", 720 CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0), 721 722 /* ADC */ 723 SND_SOC_DAPM_ADC("ADC Right", NULL, 724 CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0), 725 SND_SOC_DAPM_ADC("ADC Left", NULL, 726 CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0), 727 728 /* DAC */ 729 SND_SOC_DAPM_DAC_E("DAC HiFi", NULL, 730 CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0, 731 cpcap_st_workaround, 732 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 733 SND_SOC_DAPM_DAC_E("DAC Voice", NULL, 734 CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0, 735 cpcap_st_workaround, 736 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 737 738 /* Playback PGA */ 739 SND_SOC_DAPM_PGA("HiFi PGA", 740 CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0), 741 SND_SOC_DAPM_PGA("Voice PGA", 742 CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0), 743 SND_SOC_DAPM_PGA_E("Ext Right PGA", 744 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0, 745 NULL, 0, 746 cpcap_st_workaround, 747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 748 SND_SOC_DAPM_PGA_E("Ext Left PGA", 749 CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0, 750 NULL, 0, 751 cpcap_st_workaround, 752 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 753 754 /* Playback Switch */ 755 SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0, 756 &cpcap_extr_mute_control), 757 SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0, 758 &cpcap_extl_mute_control), 759 760 /* Loopback Switch */ 761 SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0, 762 &cpcap_voice_loopback), 763 764 /* Mono Mixer */ 765 SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0, 766 cpcap_hifi_mono_mixer_controls), 767 SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0, 768 cpcap_hifi_mono_mixer_controls), 769 SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0, 770 cpcap_ext_mono_mixer_controls), 771 SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0, 772 cpcap_ext_mono_mixer_controls), 773 774 /* Output Routes */ 775 SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0, 776 &cpcap_earpiece_mux), 777 SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0, 778 &cpcap_speaker_right_mux), 779 SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0, 780 &cpcap_speaker_left_mux), 781 SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0, 782 &cpcap_line_right_mux), 783 SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0, 784 &cpcap_line_left_mux), 785 SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0, 786 &cpcap_hs_right_mux), 787 SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0, 788 &cpcap_hs_left_mux), 789 SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0, 790 &cpcap_emu_right_mux), 791 SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0, 792 &cpcap_emu_left_mux), 793 794 /* Output Amplifier */ 795 SND_SOC_DAPM_PGA("Earpiece PGA", 796 CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0), 797 SND_SOC_DAPM_PGA("Speaker Right PGA", 798 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0), 799 SND_SOC_DAPM_PGA("Speaker Left PGA", 800 CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0), 801 SND_SOC_DAPM_PGA("Lineout Right PGA", 802 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0), 803 SND_SOC_DAPM_PGA("Lineout Left PGA", 804 CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0), 805 SND_SOC_DAPM_PGA("Headset Right PGA", 806 CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0), 807 SND_SOC_DAPM_PGA("Headset Left PGA", 808 CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0), 809 SND_SOC_DAPM_PGA("EMU Right PGA", 810 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0), 811 SND_SOC_DAPM_PGA("EMU Left PGA", 812 CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0), 813 814 /* Headet Charge Pump */ 815 SND_SOC_DAPM_SUPPLY("Headset Charge Pump", 816 CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0), 817 818 /* Outputs */ 819 SND_SOC_DAPM_OUTPUT("EP"), 820 SND_SOC_DAPM_OUTPUT("SPKR"), 821 SND_SOC_DAPM_OUTPUT("SPKL"), 822 SND_SOC_DAPM_OUTPUT("LINER"), 823 SND_SOC_DAPM_OUTPUT("LINEL"), 824 SND_SOC_DAPM_OUTPUT("HSR"), 825 SND_SOC_DAPM_OUTPUT("HSL"), 826 SND_SOC_DAPM_OUTPUT("EMUR"), 827 SND_SOC_DAPM_OUTPUT("EMUL"), 828 }; 829 830 static const struct snd_soc_dapm_route intercon[] = { 831 /* Power Supply */ 832 {"HiFi PGA", NULL, "VAUDIO"}, 833 {"Voice PGA", NULL, "VAUDIO"}, 834 {"Ext Right PGA", NULL, "VAUDIO"}, 835 {"Ext Left PGA", NULL, "VAUDIO"}, 836 {"Microphone 1 PGA", NULL, "VAUDIO"}, 837 {"Microphone 2 PGA", NULL, "VAUDIO"}, 838 839 /* Stream -> AIF */ 840 {"HiFi RX", NULL, "HiFi Playback"}, 841 {"Voice RX", NULL, "Voice Playback"}, 842 {"Voice Capture", NULL, "Voice TX"}, 843 844 /* AIF clocks */ 845 {"HiFi RX", NULL, "HiFi DAI Clock"}, 846 {"Voice RX", NULL, "Voice DAI Clock"}, 847 {"Voice TX", NULL, "Voice DAI Clock"}, 848 849 /* Digital Loopback */ 850 {"Voice Loopback", "Switch", "Voice TX"}, 851 {"Voice RX", NULL, "Voice Loopback"}, 852 853 /* Highpass Filters */ 854 {"Highpass Filter RX", NULL, "Voice RX"}, 855 {"Voice TX", NULL, "Highpass Filter TX"}, 856 857 /* AIF -> DAC mapping */ 858 {"DAC HiFi", NULL, "HiFi RX"}, 859 {"DAC Voice", NULL, "Highpass Filter RX"}, 860 861 /* DAC -> PGA */ 862 {"HiFi PGA", NULL, "DAC HiFi"}, 863 {"Voice PGA", NULL, "DAC Voice"}, 864 865 /* Ext Input -> PGA */ 866 {"Ext Right PGA", NULL, "EXTR"}, 867 {"Ext Left PGA", NULL, "EXTL"}, 868 869 /* Ext PGA -> Ext Playback Switch */ 870 {"Ext Right Enable", "Switch", "Ext Right PGA"}, 871 {"Ext Left Enable", "Switch", "Ext Left PGA"}, 872 873 /* HiFi PGA -> Mono Mixer */ 874 {"HiFi Mono Left Mixer", NULL, "HiFi PGA"}, 875 {"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"}, 876 {"HiFi Mono Right Mixer", NULL, "HiFi PGA"}, 877 {"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"}, 878 879 /* Ext Playback Switch -> Ext Mono Mixer */ 880 {"Ext Mono Right Mixer", NULL, "Ext Right Enable"}, 881 {"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"}, 882 {"Ext Mono Left Mixer", NULL, "Ext Left Enable"}, 883 {"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"}, 884 885 /* HiFi Mono Mixer -> Output Route */ 886 {"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 887 {"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 888 {"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 889 {"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 890 {"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 891 {"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 892 {"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 893 {"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"}, 894 {"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"}, 895 896 /* Voice PGA -> Output Route */ 897 {"Earpiece Playback Route", "Voice", "Voice PGA"}, 898 {"Speaker Right Playback Route", "Voice", "Voice PGA"}, 899 {"Speaker Left Playback Route", "Voice", "Voice PGA"}, 900 {"Lineout Right Playback Route", "Voice", "Voice PGA"}, 901 {"Lineout Left Playback Route", "Voice", "Voice PGA"}, 902 {"Headset Right Playback Route", "Voice", "Voice PGA"}, 903 {"Headset Left Playback Route", "Voice", "Voice PGA"}, 904 {"EMU Right Playback Route", "Voice", "Voice PGA"}, 905 {"EMU Left Playback Route", "Voice", "Voice PGA"}, 906 907 /* Ext Mono Mixer -> Output Route */ 908 {"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"}, 909 {"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 910 {"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 911 {"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 912 {"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 913 {"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 914 {"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 915 {"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"}, 916 {"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"}, 917 918 /* Output Route -> Output Amplifier */ 919 {"Earpiece PGA", NULL, "Earpiece Playback Route"}, 920 {"Speaker Right PGA", NULL, "Speaker Right Playback Route"}, 921 {"Speaker Left PGA", NULL, "Speaker Left Playback Route"}, 922 {"Lineout Right PGA", NULL, "Lineout Right Playback Route"}, 923 {"Lineout Left PGA", NULL, "Lineout Left Playback Route"}, 924 {"Headset Right PGA", NULL, "Headset Right Playback Route"}, 925 {"Headset Left PGA", NULL, "Headset Left Playback Route"}, 926 {"EMU Right PGA", NULL, "EMU Right Playback Route"}, 927 {"EMU Left PGA", NULL, "EMU Left Playback Route"}, 928 929 /* Output Amplifier -> Output */ 930 {"EP", NULL, "Earpiece PGA"}, 931 {"SPKR", NULL, "Speaker Right PGA"}, 932 {"SPKL", NULL, "Speaker Left PGA"}, 933 {"LINER", NULL, "Lineout Right PGA"}, 934 {"LINEL", NULL, "Lineout Left PGA"}, 935 {"HSR", NULL, "Headset Right PGA"}, 936 {"HSL", NULL, "Headset Left PGA"}, 937 {"EMUR", NULL, "EMU Right PGA"}, 938 {"EMUL", NULL, "EMU Left PGA"}, 939 940 /* Headset Charge Pump -> Headset */ 941 {"HSR", NULL, "Headset Charge Pump"}, 942 {"HSL", NULL, "Headset Charge Pump"}, 943 944 /* Mic -> Mic Route */ 945 {"Right Capture Route", "Mic 1", "MICR"}, 946 {"Right Capture Route", "Headset Mic", "HSMIC"}, 947 {"Right Capture Route", "EMU Mic", "EMUMIC"}, 948 {"Right Capture Route", "Ext Right", "EXTR"}, 949 {"Left Capture Route", "Mic 2", "MICL"}, 950 {"Left Capture Route", "Ext Left", "EXTL"}, 951 952 /* Input Route -> Microphone PGA */ 953 {"Microphone 1 PGA", NULL, "Right Capture Route"}, 954 {"Microphone 2 PGA", NULL, "Left Capture Route"}, 955 956 /* Microphone PGA -> ADC */ 957 {"ADC Right", NULL, "Microphone 1 PGA"}, 958 {"ADC Left", NULL, "Microphone 2 PGA"}, 959 960 /* ADC -> Stream */ 961 {"Highpass Filter TX", NULL, "ADC Right"}, 962 {"Highpass Filter TX", NULL, "ADC Left"}, 963 964 /* Mic Bias */ 965 {"MICL", NULL, "MIC1L Bias"}, 966 {"MICR", NULL, "MIC1R Bias"}, 967 }; 968 969 static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai, 970 int clk_id, int freq) 971 { 972 u16 clkfreqreg, clkfreqshift; 973 u16 clkfreqmask, clkfreqval; 974 u16 clkidreg, clkidshift; 975 u16 mask, val; 976 int err; 977 978 switch (dai) { 979 case CPCAP_DAI_HIFI: 980 clkfreqreg = CPCAP_REG_SDAC; 981 clkfreqshift = CPCAP_BIT_ST_DAC_CLK0; 982 clkidreg = CPCAP_REG_SDACDI; 983 clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL; 984 break; 985 case CPCAP_DAI_VOICE: 986 clkfreqreg = CPCAP_REG_CC; 987 clkfreqshift = CPCAP_BIT_CDC_CLK0; 988 clkidreg = CPCAP_REG_CDI; 989 clkidshift = CPCAP_BIT_CLK_IN_SEL; 990 break; 991 default: 992 dev_err(cpcap->component->dev, "invalid DAI: %d", dai); 993 return -EINVAL; 994 } 995 996 /* setup clk id */ 997 if (clk_id < 0 || clk_id > 1) { 998 dev_err(cpcap->component->dev, "invalid clk id %d", clk_id); 999 return -EINVAL; 1000 } 1001 err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift), 1002 clk_id ? BIT(clkidshift) : 0); 1003 if (err) 1004 return err; 1005 1006 /* enable PLL for Voice DAI */ 1007 if (dai == CPCAP_DAI_VOICE) { 1008 mask = BIT(CPCAP_BIT_CDC_PLL_SEL); 1009 val = BIT(CPCAP_BIT_CDC_PLL_SEL); 1010 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1011 mask, val); 1012 if (err) 1013 return err; 1014 } 1015 1016 /* setup frequency */ 1017 clkfreqmask = 0x7 << clkfreqshift; 1018 switch (freq) { 1019 case 15360000: 1020 clkfreqval = 0x01 << clkfreqshift; 1021 break; 1022 case 16800000: 1023 clkfreqval = 0x02 << clkfreqshift; 1024 break; 1025 case 19200000: 1026 clkfreqval = 0x03 << clkfreqshift; 1027 break; 1028 case 26000000: 1029 clkfreqval = 0x04 << clkfreqshift; 1030 break; 1031 case 33600000: 1032 clkfreqval = 0x05 << clkfreqshift; 1033 break; 1034 case 38400000: 1035 clkfreqval = 0x06 << clkfreqshift; 1036 break; 1037 default: 1038 dev_err(cpcap->component->dev, "unsupported freq %u", freq); 1039 return -EINVAL; 1040 } 1041 1042 err = regmap_update_bits(cpcap->regmap, clkfreqreg, 1043 clkfreqmask, clkfreqval); 1044 if (err) 1045 return err; 1046 1047 if (dai == CPCAP_DAI_VOICE) { 1048 cpcap->codec_clk_id = clk_id; 1049 cpcap->codec_freq = freq; 1050 } 1051 1052 return 0; 1053 } 1054 1055 static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai, 1056 int samplerate) 1057 { 1058 struct snd_soc_component *component = cpcap->component; 1059 u16 sampreg, sampmask, sampshift, sampval, sampreset; 1060 int err, sampreadval; 1061 1062 switch (dai) { 1063 case CPCAP_DAI_HIFI: 1064 sampreg = CPCAP_REG_SDAC; 1065 sampshift = CPCAP_BIT_ST_SR0; 1066 sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) | 1067 BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET); 1068 break; 1069 case CPCAP_DAI_VOICE: 1070 sampreg = CPCAP_REG_CC; 1071 sampshift = CPCAP_BIT_CDC_SR0; 1072 sampreset = BIT(CPCAP_BIT_DF_RESET) | 1073 BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET); 1074 break; 1075 default: 1076 dev_err(component->dev, "invalid DAI: %d", dai); 1077 return -EINVAL; 1078 } 1079 1080 sampmask = 0xF << sampshift | sampreset; 1081 switch (samplerate) { 1082 case 48000: 1083 sampval = 0x8 << sampshift; 1084 break; 1085 case 44100: 1086 sampval = 0x7 << sampshift; 1087 break; 1088 case 32000: 1089 sampval = 0x6 << sampshift; 1090 break; 1091 case 24000: 1092 sampval = 0x5 << sampshift; 1093 break; 1094 case 22050: 1095 sampval = 0x4 << sampshift; 1096 break; 1097 case 16000: 1098 sampval = 0x3 << sampshift; 1099 break; 1100 case 12000: 1101 sampval = 0x2 << sampshift; 1102 break; 1103 case 11025: 1104 sampval = 0x1 << sampshift; 1105 break; 1106 case 8000: 1107 sampval = 0x0 << sampshift; 1108 break; 1109 default: 1110 dev_err(component->dev, "unsupported samplerate %d", samplerate); 1111 return -EINVAL; 1112 } 1113 err = regmap_update_bits(cpcap->regmap, sampreg, 1114 sampmask, sampval | sampreset); 1115 if (err) 1116 return err; 1117 1118 /* Wait for clock tree reset to complete */ 1119 mdelay(CLOCK_TREE_RESET_TIME); 1120 1121 err = regmap_read(cpcap->regmap, sampreg, &sampreadval); 1122 if (err) 1123 return err; 1124 1125 if (sampreadval & sampreset) { 1126 dev_err(component->dev, "reset self-clear failed: %04x", 1127 sampreadval); 1128 return -EIO; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream, 1135 struct snd_pcm_hw_params *params, 1136 struct snd_soc_dai *dai) 1137 { 1138 struct snd_soc_component *component = dai->component; 1139 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1140 int rate = params_rate(params); 1141 1142 dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate); 1143 return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate); 1144 } 1145 1146 static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 1147 unsigned int freq, int dir) 1148 { 1149 struct snd_soc_component *component = codec_dai->component; 1150 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1151 struct device *dev = component->dev; 1152 1153 dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq); 1154 return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq); 1155 } 1156 1157 static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai, 1158 unsigned int fmt) 1159 { 1160 struct snd_soc_component *component = codec_dai->component; 1161 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1162 struct device *dev = component->dev; 1163 static const u16 reg = CPCAP_REG_SDACDI; 1164 static const u16 mask = 1165 BIT(CPCAP_BIT_SMB_ST_DAC) | 1166 BIT(CPCAP_BIT_ST_CLK_INV) | 1167 BIT(CPCAP_BIT_ST_FS_INV) | 1168 BIT(CPCAP_BIT_ST_DIG_AUD_FS0) | 1169 BIT(CPCAP_BIT_ST_DIG_AUD_FS1) | 1170 BIT(CPCAP_BIT_ST_L_TIMESLOT0) | 1171 BIT(CPCAP_BIT_ST_L_TIMESLOT1) | 1172 BIT(CPCAP_BIT_ST_L_TIMESLOT2) | 1173 BIT(CPCAP_BIT_ST_R_TIMESLOT0) | 1174 BIT(CPCAP_BIT_ST_R_TIMESLOT1) | 1175 BIT(CPCAP_BIT_ST_R_TIMESLOT2); 1176 u16 val = 0x0000; 1177 1178 dev_dbg(dev, "HiFi setup dai format (%08x)", fmt); 1179 1180 /* 1181 * "HiFi Playback" should always be configured as 1182 * SND_SOC_DAIFMT_CBP_CFP - codec clk & frm provider 1183 * SND_SOC_DAIFMT_I2S - I2S mode 1184 */ 1185 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1186 case SND_SOC_DAIFMT_CBP_CFP: 1187 val &= ~BIT(CPCAP_BIT_SMB_ST_DAC); 1188 break; 1189 default: 1190 dev_err(dev, "HiFi dai fmt failed: CPCAP should be provider"); 1191 return -EINVAL; 1192 } 1193 1194 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1195 case SND_SOC_DAIFMT_IB_IF: 1196 val |= BIT(CPCAP_BIT_ST_FS_INV); 1197 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1198 break; 1199 case SND_SOC_DAIFMT_IB_NF: 1200 val &= ~BIT(CPCAP_BIT_ST_FS_INV); 1201 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1202 break; 1203 case SND_SOC_DAIFMT_NB_IF: 1204 val |= BIT(CPCAP_BIT_ST_FS_INV); 1205 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1206 break; 1207 case SND_SOC_DAIFMT_NB_NF: 1208 val &= ~BIT(CPCAP_BIT_ST_FS_INV); 1209 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1210 break; 1211 default: 1212 dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode"); 1213 return -EINVAL; 1214 } 1215 1216 if (val & BIT(CPCAP_BIT_ST_CLK_INV)) 1217 val &= ~BIT(CPCAP_BIT_ST_CLK_INV); 1218 else 1219 val |= BIT(CPCAP_BIT_ST_CLK_INV); 1220 1221 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1222 case SND_SOC_DAIFMT_I2S: 1223 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); 1224 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1); 1225 break; 1226 default: 1227 /* 01 - 4 slots network mode */ 1228 val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0); 1229 val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1); 1230 /* L on slot 1 */ 1231 val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0); 1232 break; 1233 } 1234 1235 dev_dbg(dev, "HiFi dai format: val=%04x", val); 1236 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1237 } 1238 1239 static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction) 1240 { 1241 struct snd_soc_component *component = dai->component; 1242 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1243 static const u16 reg = CPCAP_REG_RXSDOA; 1244 static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW); 1245 u16 val; 1246 1247 if (mute) 1248 val = 0; 1249 else 1250 val = BIT(CPCAP_BIT_ST_DAC_SW); 1251 1252 dev_dbg(component->dev, "HiFi mute: %d", mute); 1253 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1254 } 1255 1256 static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = { 1257 .hw_params = cpcap_hifi_hw_params, 1258 .set_sysclk = cpcap_hifi_set_dai_sysclk, 1259 .set_fmt = cpcap_hifi_set_dai_fmt, 1260 .mute_stream = cpcap_hifi_set_mute, 1261 .no_capture_mute = 1, 1262 }; 1263 1264 static int cpcap_voice_hw_params(struct snd_pcm_substream *substream, 1265 struct snd_pcm_hw_params *params, 1266 struct snd_soc_dai *dai) 1267 { 1268 struct snd_soc_component *component = dai->component; 1269 struct device *dev = component->dev; 1270 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1271 static const u16 reg_cdi = CPCAP_REG_CDI; 1272 int rate = params_rate(params); 1273 int channels = params_channels(params); 1274 int direction = substream->stream; 1275 u16 val, mask; 1276 int err; 1277 1278 dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d", 1279 rate, direction, channels); 1280 1281 err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate); 1282 if (err) 1283 return err; 1284 1285 if (direction == SNDRV_PCM_STREAM_CAPTURE) { 1286 mask = 0x0000; 1287 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); 1288 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1); 1289 mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2); 1290 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0); 1291 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1); 1292 mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2); 1293 val = 0x0000; 1294 if (channels >= 2) 1295 val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0); 1296 err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val); 1297 if (err) 1298 return err; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, 1305 unsigned int freq, int dir) 1306 { 1307 struct snd_soc_component *component = codec_dai->component; 1308 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1309 1310 dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u", 1311 clk_id, freq); 1312 return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq); 1313 } 1314 1315 static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, 1316 unsigned int fmt) 1317 { 1318 struct snd_soc_component *component = codec_dai->component; 1319 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1320 static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) | 1321 BIT(CPCAP_BIT_CLK_INV) | 1322 BIT(CPCAP_BIT_FS_INV) | 1323 BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) | 1324 BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1325 u16 val = 0x0000; 1326 int err; 1327 1328 dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt); 1329 1330 /* 1331 * "Voice Playback" and "Voice Capture" should always be 1332 * configured as SND_SOC_DAIFMT_CBP_CFP - codec clk & frm 1333 * provider 1334 */ 1335 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1336 case SND_SOC_DAIFMT_CBP_CFP: 1337 val &= ~BIT(CPCAP_BIT_SMB_CDC); 1338 break; 1339 default: 1340 dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the provider"); 1341 val &= ~BIT(CPCAP_BIT_SMB_CDC); 1342 break; 1343 } 1344 1345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1346 case SND_SOC_DAIFMT_IB_IF: 1347 val |= BIT(CPCAP_BIT_CLK_INV); 1348 val |= BIT(CPCAP_BIT_FS_INV); 1349 break; 1350 case SND_SOC_DAIFMT_IB_NF: 1351 val |= BIT(CPCAP_BIT_CLK_INV); 1352 val &= ~BIT(CPCAP_BIT_FS_INV); 1353 break; 1354 case SND_SOC_DAIFMT_NB_IF: 1355 val &= ~BIT(CPCAP_BIT_CLK_INV); 1356 val |= BIT(CPCAP_BIT_FS_INV); 1357 break; 1358 case SND_SOC_DAIFMT_NB_NF: 1359 val &= ~BIT(CPCAP_BIT_CLK_INV); 1360 val &= ~BIT(CPCAP_BIT_FS_INV); 1361 break; 1362 default: 1363 dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode"); 1364 break; 1365 } 1366 1367 if (val & BIT(CPCAP_BIT_CLK_INV)) 1368 val &= ~BIT(CPCAP_BIT_CLK_INV); 1369 else 1370 val |= BIT(CPCAP_BIT_CLK_INV); 1371 1372 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1373 case SND_SOC_DAIFMT_I2S: 1374 /* 11 - true I2S mode */ 1375 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); 1376 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1377 break; 1378 default: 1379 /* 4 timeslots network mode */ 1380 val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0); 1381 val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1); 1382 break; 1383 } 1384 1385 dev_dbg(component->dev, "Voice dai format: val=%04x", val); 1386 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val); 1387 if (err) 1388 return err; 1389 1390 cpcap->codec_format = val; 1391 return 0; 1392 } 1393 1394 1395 /* 1396 * Configure codec for voice call if requested. 1397 * 1398 * We can configure most with snd_soc_dai_set_sysclk(), snd_soc_dai_set_fmt() 1399 * and snd_soc_dai_set_tdm_slot(). This function configures the rest of the 1400 * cpcap related hardware as CPU is not involved in the voice call. 1401 */ 1402 static int cpcap_voice_call(struct cpcap_audio *cpcap, struct snd_soc_dai *dai, 1403 bool voice_call) 1404 { 1405 int mask, err; 1406 1407 /* Modem to codec VAUDIO_MODE1 */ 1408 mask = BIT(CPCAP_BIT_VAUDIO_MODE1); 1409 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_VAUDIOC, 1410 mask, voice_call ? mask : 0); 1411 if (err) 1412 return err; 1413 1414 /* Clear MIC1_MUX for call */ 1415 mask = BIT(CPCAP_BIT_MIC1_MUX); 1416 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 1417 mask, voice_call ? 0 : mask); 1418 if (err) 1419 return err; 1420 1421 /* Set MIC2_MUX for call */ 1422 mask = BIT(CPCAP_BIT_MB_ON1L) | BIT(CPCAP_BIT_MB_ON1R) | 1423 BIT(CPCAP_BIT_MIC2_MUX) | BIT(CPCAP_BIT_MIC2_PGA_EN); 1424 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, 1425 mask, voice_call ? mask : 0); 1426 if (err) 1427 return err; 1428 1429 /* Enable LDSP for call */ 1430 mask = BIT(CPCAP_BIT_A2_LDSP_L_EN) | BIT(CPCAP_BIT_A2_LDSP_R_EN); 1431 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA, 1432 mask, voice_call ? mask : 0); 1433 if (err) 1434 return err; 1435 1436 /* Enable CPCAP_BIT_PGA_CDC_EN for call */ 1437 mask = BIT(CPCAP_BIT_PGA_CDC_EN); 1438 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA, 1439 mask, voice_call ? mask : 0); 1440 if (err) 1441 return err; 1442 1443 /* Unmute voice for call */ 1444 if (dai) { 1445 err = snd_soc_dai_digital_mute(dai, !voice_call, 1446 SNDRV_PCM_STREAM_PLAYBACK); 1447 if (err) 1448 return err; 1449 } 1450 1451 /* Set modem to codec mic CDC and HPF for call */ 1452 mask = BIT(CPCAP_BIT_MIC2_CDC_EN) | BIT(CPCAP_BIT_CDC_EN_RX) | 1453 BIT(CPCAP_BIT_AUDOHPF_1) | BIT(CPCAP_BIT_AUDOHPF_0) | 1454 BIT(CPCAP_BIT_AUDIHPF_1) | BIT(CPCAP_BIT_AUDIHPF_0); 1455 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CC, 1456 mask, voice_call ? mask : 0); 1457 if (err) 1458 return err; 1459 1460 /* Enable modem to codec CDC for call*/ 1461 mask = BIT(CPCAP_BIT_CDC_CLK_EN); 1462 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1463 mask, voice_call ? mask : 0); 1464 1465 return err; 1466 } 1467 1468 static int cpcap_voice_set_tdm_slot(struct snd_soc_dai *dai, 1469 unsigned int tx_mask, unsigned int rx_mask, 1470 int slots, int slot_width) 1471 { 1472 struct snd_soc_component *component = dai->component; 1473 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1474 int err, ts_mask, mask; 1475 bool voice_call; 1476 1477 /* 1478 * Primitive test for voice call, probably needs more checks 1479 * later on for 16-bit calls detected, Bluetooth headset etc. 1480 */ 1481 if (tx_mask == 0 && rx_mask == 1 && slot_width == 8) 1482 voice_call = true; 1483 else 1484 voice_call = false; 1485 1486 ts_mask = 0x7 << CPCAP_BIT_MIC2_TIMESLOT0; 1487 ts_mask |= 0x7 << CPCAP_BIT_MIC1_RX_TIMESLOT0; 1488 1489 mask = (tx_mask & 0x7) << CPCAP_BIT_MIC2_TIMESLOT0; 1490 mask |= (rx_mask & 0x7) << CPCAP_BIT_MIC1_RX_TIMESLOT0; 1491 1492 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1493 ts_mask, mask); 1494 if (err) 1495 return err; 1496 1497 err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, slot_width * 1000); 1498 if (err) 1499 return err; 1500 1501 err = cpcap_voice_call(cpcap, dai, voice_call); 1502 if (err) 1503 return err; 1504 1505 return 0; 1506 } 1507 1508 static int cpcap_voice_set_mute(struct snd_soc_dai *dai, int mute, int direction) 1509 { 1510 struct snd_soc_component *component = dai->component; 1511 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1512 static const u16 reg = CPCAP_REG_RXCOA; 1513 static const u16 mask = BIT(CPCAP_BIT_CDC_SW); 1514 u16 val; 1515 1516 if (mute) 1517 val = 0; 1518 else 1519 val = BIT(CPCAP_BIT_CDC_SW); 1520 1521 dev_dbg(component->dev, "Voice mute: %d", mute); 1522 return regmap_update_bits(cpcap->regmap, reg, mask, val); 1523 }; 1524 1525 static const struct snd_soc_dai_ops cpcap_dai_voice_ops = { 1526 .hw_params = cpcap_voice_hw_params, 1527 .set_sysclk = cpcap_voice_set_dai_sysclk, 1528 .set_fmt = cpcap_voice_set_dai_fmt, 1529 .set_tdm_slot = cpcap_voice_set_tdm_slot, 1530 .mute_stream = cpcap_voice_set_mute, 1531 .no_capture_mute = 1, 1532 }; 1533 1534 static struct snd_soc_dai_driver cpcap_dai[] = { 1535 { 1536 .id = 0, 1537 .name = "cpcap-hifi", 1538 .playback = { 1539 .stream_name = "HiFi Playback", 1540 .channels_min = 2, 1541 .channels_max = 2, 1542 .rates = SNDRV_PCM_RATE_8000_48000, 1543 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE, 1544 }, 1545 .ops = &cpcap_dai_hifi_ops, 1546 }, 1547 { 1548 .id = 1, 1549 .name = "cpcap-voice", 1550 .playback = { 1551 .stream_name = "Voice Playback", 1552 .channels_min = 1, 1553 .channels_max = 1, 1554 .rates = SNDRV_PCM_RATE_8000_48000, 1555 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1556 }, 1557 .capture = { 1558 .stream_name = "Voice Capture", 1559 .channels_min = 1, 1560 .channels_max = 2, 1561 .rates = SNDRV_PCM_RATE_8000_48000, 1562 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1563 }, 1564 .ops = &cpcap_dai_voice_ops, 1565 }, 1566 }; 1567 1568 static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration) 1569 { 1570 u16 hifi_val, voice_val; 1571 u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC); 1572 u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN); 1573 int err; 1574 1575 1576 1577 if (!swap_dai_configuration) { 1578 /* Codec on DAI0, HiFi on DAI1 */ 1579 voice_val = 0; 1580 hifi_val = hifi_mask; 1581 } else { 1582 /* Codec on DAI1, HiFi on DAI0 */ 1583 voice_val = voice_mask; 1584 hifi_val = 0; 1585 } 1586 1587 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, 1588 voice_mask, voice_val); 1589 if (err) 1590 return err; 1591 1592 err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI, 1593 hifi_mask, hifi_val); 1594 if (err) 1595 return err; 1596 1597 return 0; 1598 } 1599 1600 static int cpcap_audio_reset(struct snd_soc_component *component, 1601 bool swap_dai_configuration) 1602 { 1603 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1604 int i, err = 0; 1605 1606 dev_dbg(component->dev, "init audio codec"); 1607 1608 for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) { 1609 err = regmap_update_bits(cpcap->regmap, 1610 cpcap_default_regs[i].reg, 1611 cpcap_default_regs[i].mask, 1612 cpcap_default_regs[i].val); 1613 if (err) 1614 return err; 1615 } 1616 1617 /* setup default settings */ 1618 err = cpcap_dai_mux(cpcap, swap_dai_configuration); 1619 if (err) 1620 return err; 1621 1622 err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000); 1623 if (err) 1624 return err; 1625 err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000); 1626 if (err) 1627 return err; 1628 1629 err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000); 1630 if (err) 1631 return err; 1632 1633 err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000); 1634 if (err) 1635 return err; 1636 1637 return 0; 1638 } 1639 1640 static irqreturn_t cpcap_hs_irq_thread(int irq, void *data) 1641 { 1642 struct snd_soc_component *component = data; 1643 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1644 struct regmap *regmap = cpcap->regmap; 1645 int status = 0; 1646 int mask = SND_JACK_HEADSET; 1647 int val; 1648 1649 if (!regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S))) { 1650 val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN); 1651 regmap_update_bits(regmap, CPCAP_REG_TXI, val, val); 1652 1653 val = BIT(CPCAP_BIT_ST_HS_CP_EN); 1654 regmap_update_bits(regmap, CPCAP_REG_RXOA, val, val); 1655 1656 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL); 1657 1658 /* Give PTTS time to settle */ 1659 msleep(20); 1660 1661 if (!regmap_test_bits(regmap, CPCAP_REG_INTS2, 1662 BIT(CPCAP_BIT_PTT_S))) { 1663 /* Headphones detected. (May also be a headset with the 1664 * MFB pressed.) 1665 */ 1666 status = SND_JACK_HEADPHONE; 1667 dev_info(component->dev, "HP plugged in\n"); 1668 } else if (regmap_test_bits(regmap, CPCAP_REG_INTS1, 1669 BIT(CPCAP_BIT_MB2_S)) == 1) { 1670 status = SND_JACK_HEADSET; 1671 dev_info(component->dev, "HS plugged in\n"); 1672 } else 1673 dev_info(component->dev, "Unsupported HS plugged in\n"); 1674 } else { 1675 bool mic = cpcap->jack.status & SND_JACK_MICROPHONE; 1676 1677 dev_info(component->dev, "H%s disconnect\n", mic ? "S" : "P"); 1678 val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN); 1679 regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, val, 0); 1680 1681 val = BIT(CPCAP_BIT_ST_HS_CP_EN); 1682 regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA, val, 0); 1683 1684 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY); 1685 1686 mask |= SND_JACK_BTN_0; 1687 } 1688 1689 snd_soc_jack_report(&cpcap->jack, status, mask); 1690 1691 return IRQ_HANDLED; 1692 } 1693 1694 static irqreturn_t cpcap_mb2_irq_thread(int irq, void *data) 1695 { 1696 struct snd_soc_component *component = data; 1697 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1698 struct regmap *regmap = cpcap->regmap; 1699 int status = 0; 1700 int mb2; 1701 int ptt; 1702 1703 if (regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S)) == 1) 1704 return IRQ_HANDLED; 1705 1706 mb2 = regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_MB2_S)); 1707 ptt = regmap_test_bits(regmap, CPCAP_REG_INTS2, BIT(CPCAP_BIT_PTT_S)); 1708 1709 /* Initial detection might have been with MFB pressed */ 1710 if (!(cpcap->jack.status & SND_JACK_MICROPHONE)) { 1711 if (ptt == 1 && mb2 == 1) { 1712 dev_info(component->dev, "MIC plugged in\n"); 1713 snd_soc_jack_report(&cpcap->jack, SND_JACK_MICROPHONE, 1714 SND_JACK_MICROPHONE); 1715 } 1716 1717 return IRQ_HANDLED; 1718 } 1719 1720 if (!mb2 || !ptt) 1721 status = SND_JACK_BTN_0; 1722 1723 snd_soc_jack_report(&cpcap->jack, status, SND_JACK_BTN_0); 1724 1725 return IRQ_HANDLED; 1726 } 1727 1728 static int cpcap_soc_probe(struct snd_soc_component *component) 1729 { 1730 struct platform_device *pdev = to_platform_device(component->dev); 1731 struct snd_soc_card *card = component->card; 1732 struct cpcap_audio *cpcap; 1733 int err; 1734 1735 cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL); 1736 if (!cpcap) 1737 return -ENOMEM; 1738 1739 snd_soc_component_set_drvdata(component, cpcap); 1740 cpcap->component = component; 1741 1742 cpcap->vaudio = devm_regulator_get(component->dev, "VAUDIO"); 1743 if (IS_ERR(cpcap->vaudio)) 1744 return dev_err_probe(component->dev, PTR_ERR(cpcap->vaudio), 1745 "Cannot get VAUDIO regulator\n"); 1746 1747 err = snd_soc_card_jack_new(card, "Headphones", 1748 SND_JACK_HEADSET | SND_JACK_BTN_0, 1749 &cpcap->jack); 1750 if (err < 0) { 1751 dev_err(component->dev, "Cannot create HS jack: %i\n", err); 1752 return err; 1753 } 1754 1755 snd_jack_set_key(cpcap->jack.jack, SND_JACK_BTN_0, KEY_MEDIA); 1756 1757 cpcap->regmap = dev_get_regmap(component->dev->parent, NULL); 1758 if (!cpcap->regmap) 1759 return -ENODEV; 1760 snd_soc_component_init_regmap(component, cpcap->regmap); 1761 1762 err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor); 1763 if (err) 1764 return err; 1765 1766 cpcap->hsirq = platform_get_irq_byname(pdev, "hs"); 1767 if (cpcap->hsirq < 0) 1768 return cpcap->hsirq; 1769 1770 err = devm_request_threaded_irq(component->dev, cpcap->hsirq, NULL, 1771 cpcap_hs_irq_thread, 1772 IRQF_TRIGGER_RISING | 1773 IRQF_TRIGGER_FALLING | 1774 IRQF_ONESHOT, 1775 "cpcap-codec-hs", 1776 component); 1777 if (err) { 1778 dev_warn(component->dev, "no HS irq%i: %i\n", 1779 cpcap->hsirq, err); 1780 return err; 1781 } 1782 1783 cpcap->mb2irq = platform_get_irq_byname(pdev, "mb2"); 1784 if (cpcap->mb2irq < 0) 1785 return cpcap->mb2irq; 1786 1787 err = devm_request_threaded_irq(component->dev, cpcap->mb2irq, NULL, 1788 cpcap_mb2_irq_thread, 1789 IRQF_TRIGGER_RISING | 1790 IRQF_TRIGGER_FALLING | 1791 IRQF_ONESHOT, 1792 "cpcap-codec-mb2", 1793 component); 1794 if (err) { 1795 dev_warn(component->dev, "no MB2 irq%i: %i\n", 1796 cpcap->mb2irq, err); 1797 return err; 1798 } 1799 1800 err = cpcap_audio_reset(component, false); 1801 if (err) 1802 return err; 1803 1804 cpcap_hs_irq_thread(cpcap->hsirq, component); 1805 1806 enable_irq_wake(cpcap->hsirq); 1807 enable_irq_wake(cpcap->mb2irq); 1808 1809 return 0; 1810 } 1811 1812 static void cpcap_soc_remove(struct snd_soc_component *component) 1813 { 1814 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1815 1816 disable_irq_wake(cpcap->hsirq); 1817 disable_irq_wake(cpcap->mb2irq); 1818 } 1819 1820 static int cpcap_set_bias_level(struct snd_soc_component *component, 1821 enum snd_soc_bias_level level) 1822 { 1823 struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component); 1824 1825 /* VAIDIO should be kept in normal mode in order MIC/PTT to work */ 1826 if (cpcap->jack.status & SND_JACK_MICROPHONE) 1827 return 0; 1828 1829 switch (level) { 1830 case SND_SOC_BIAS_OFF: 1831 break; 1832 case SND_SOC_BIAS_PREPARE: 1833 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL); 1834 break; 1835 case SND_SOC_BIAS_STANDBY: 1836 regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY); 1837 break; 1838 case SND_SOC_BIAS_ON: 1839 break; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static const struct snd_soc_component_driver soc_codec_dev_cpcap = { 1846 .probe = cpcap_soc_probe, 1847 .remove = cpcap_soc_remove, 1848 .controls = cpcap_snd_controls, 1849 .num_controls = ARRAY_SIZE(cpcap_snd_controls), 1850 .dapm_widgets = cpcap_dapm_widgets, 1851 .num_dapm_widgets = ARRAY_SIZE(cpcap_dapm_widgets), 1852 .dapm_routes = intercon, 1853 .num_dapm_routes = ARRAY_SIZE(intercon), 1854 .set_bias_level = cpcap_set_bias_level, 1855 .idle_bias_on = 1, 1856 .use_pmdown_time = 1, 1857 .endianness = 1, 1858 }; 1859 1860 static int cpcap_codec_probe(struct platform_device *pdev) 1861 { 1862 struct device_node *codec_node = 1863 of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec"); 1864 if (!codec_node) 1865 return -ENODEV; 1866 1867 pdev->dev.of_node = codec_node; 1868 1869 return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap, 1870 cpcap_dai, ARRAY_SIZE(cpcap_dai)); 1871 } 1872 1873 static struct platform_driver cpcap_codec_driver = { 1874 .probe = cpcap_codec_probe, 1875 .driver = { 1876 .name = "cpcap-codec", 1877 }, 1878 }; 1879 module_platform_driver(cpcap_codec_driver); 1880 1881 MODULE_ALIAS("platform:cpcap-codec"); 1882 MODULE_DESCRIPTION("ASoC CPCAP codec driver"); 1883 MODULE_AUTHOR("Sebastian Reichel"); 1884 MODULE_LICENSE("GPL v2"); 1885