1*8ade6cc7SWeidong Wang // SPDX-License-Identifier: GPL-2.0-only 2*8ade6cc7SWeidong Wang // 3*8ade6cc7SWeidong Wang // aw88399.h -- ALSA SoC AW88399 codec support 4*8ade6cc7SWeidong Wang // 5*8ade6cc7SWeidong Wang // Copyright (c) 2023 AWINIC Technology CO., LTD 6*8ade6cc7SWeidong Wang // 7*8ade6cc7SWeidong Wang // Author: Weidong Wang <wangweidong.a@awinic.com> 8*8ade6cc7SWeidong Wang // 9*8ade6cc7SWeidong Wang 10*8ade6cc7SWeidong Wang #ifndef __AW88399_H__ 11*8ade6cc7SWeidong Wang #define __AW88399_H__ 12*8ade6cc7SWeidong Wang 13*8ade6cc7SWeidong Wang /* registers list */ 14*8ade6cc7SWeidong Wang #define AW88399_ID_REG (0x00) 15*8ade6cc7SWeidong Wang #define AW88399_SYSST_REG (0x01) 16*8ade6cc7SWeidong Wang #define AW88399_SYSINT_REG (0x02) 17*8ade6cc7SWeidong Wang #define AW88399_SYSINTM_REG (0x03) 18*8ade6cc7SWeidong Wang #define AW88399_SYSCTRL_REG (0x04) 19*8ade6cc7SWeidong Wang #define AW88399_SYSCTRL2_REG (0x05) 20*8ade6cc7SWeidong Wang #define AW88399_I2SCTRL1_REG (0x06) 21*8ade6cc7SWeidong Wang #define AW88399_I2SCTRL2_REG (0x07) 22*8ade6cc7SWeidong Wang #define AW88399_I2SCTRL3_REG (0x08) 23*8ade6cc7SWeidong Wang #define AW88399_DACCFG1_REG (0x09) 24*8ade6cc7SWeidong Wang #define AW88399_DACCFG2_REG (0x0A) 25*8ade6cc7SWeidong Wang #define AW88399_DACCFG3_REG (0x0B) 26*8ade6cc7SWeidong Wang #define AW88399_DACCFG4_REG (0x0C) 27*8ade6cc7SWeidong Wang #define AW88399_DACCFG5_REG (0x0D) 28*8ade6cc7SWeidong Wang #define AW88399_DACCFG6_REG (0x0E) 29*8ade6cc7SWeidong Wang #define AW88399_DACCFG7_REG (0x0F) 30*8ade6cc7SWeidong Wang #define AW88399_MPDCFG1_REG (0x10) 31*8ade6cc7SWeidong Wang #define AW88399_MPDCFG2_REG (0x11) 32*8ade6cc7SWeidong Wang #define AW88399_MPDCFG3_REG (0x12) 33*8ade6cc7SWeidong Wang #define AW88399_MPDCFG4_REG (0x13) 34*8ade6cc7SWeidong Wang #define AW88399_PWMCTRL1_REG (0x14) 35*8ade6cc7SWeidong Wang #define AW88399_PWMCTRL2_REG (0x15) 36*8ade6cc7SWeidong Wang #define AW88399_PWMCTRL3_REG (0x16) 37*8ade6cc7SWeidong Wang #define AW88399_I2SCFG1_REG (0x17) 38*8ade6cc7SWeidong Wang #define AW88399_DBGCTRL_REG (0x18) 39*8ade6cc7SWeidong Wang #define AW88399_HAGCST_REG (0x20) 40*8ade6cc7SWeidong Wang #define AW88399_VBAT_REG (0x21) 41*8ade6cc7SWeidong Wang #define AW88399_TEMP_REG (0x22) 42*8ade6cc7SWeidong Wang #define AW88399_PVDD_REG (0x23) 43*8ade6cc7SWeidong Wang #define AW88399_ISNDAT_REG (0x24) 44*8ade6cc7SWeidong Wang #define AW88399_VSNDAT_REG (0x25) 45*8ade6cc7SWeidong Wang #define AW88399_I2SINT_REG (0x26) 46*8ade6cc7SWeidong Wang #define AW88399_I2SCAPCNT_REG (0x27) 47*8ade6cc7SWeidong Wang #define AW88399_ANASTA1_REG (0x28) 48*8ade6cc7SWeidong Wang #define AW88399_ANASTA2_REG (0x29) 49*8ade6cc7SWeidong Wang #define AW88399_ANASTA3_REG (0x2A) 50*8ade6cc7SWeidong Wang #define AW88399_TESTDET_REG (0x2B) 51*8ade6cc7SWeidong Wang #define AW88399_DSMCFG1_REG (0x30) 52*8ade6cc7SWeidong Wang #define AW88399_DSMCFG2_REG (0x31) 53*8ade6cc7SWeidong Wang #define AW88399_DSMCFG3_REG (0x32) 54*8ade6cc7SWeidong Wang #define AW88399_DSMCFG4_REG (0x33) 55*8ade6cc7SWeidong Wang #define AW88399_DSMCFG5_REG (0x34) 56*8ade6cc7SWeidong Wang #define AW88399_DSMCFG6_REG (0x35) 57*8ade6cc7SWeidong Wang #define AW88399_DSMCFG7_REG (0x36) 58*8ade6cc7SWeidong Wang #define AW88399_DSMCFG8_REG (0x37) 59*8ade6cc7SWeidong Wang #define AW88399_TESTIN_REG (0x38) 60*8ade6cc7SWeidong Wang #define AW88399_TESTOUT_REG (0x39) 61*8ade6cc7SWeidong Wang #define AW88399_MEMTEST_REG (0x3A) 62*8ade6cc7SWeidong Wang #define AW88399_VSNCTRL1_REG (0x3B) 63*8ade6cc7SWeidong Wang #define AW88399_ISNCTRL1_REG (0x3C) 64*8ade6cc7SWeidong Wang #define AW88399_ISNCTRL2_REG (0x3D) 65*8ade6cc7SWeidong Wang #define AW88399_DSPMADD_REG (0x40) 66*8ade6cc7SWeidong Wang #define AW88399_DSPMDAT_REG (0x41) 67*8ade6cc7SWeidong Wang #define AW88399_WDT_REG (0x42) 68*8ade6cc7SWeidong Wang #define AW88399_ACR1_REG (0x43) 69*8ade6cc7SWeidong Wang #define AW88399_ACR2_REG (0x44) 70*8ade6cc7SWeidong Wang #define AW88399_ASR1_REG (0x45) 71*8ade6cc7SWeidong Wang #define AW88399_ASR2_REG (0x46) 72*8ade6cc7SWeidong Wang #define AW88399_DSPCFG_REG (0x47) 73*8ade6cc7SWeidong Wang #define AW88399_ASR3_REG (0x48) 74*8ade6cc7SWeidong Wang #define AW88399_ASR4_REG (0x49) 75*8ade6cc7SWeidong Wang #define AW88399_DSPVCALB_REG (0x4A) 76*8ade6cc7SWeidong Wang #define AW88399_CRCCTRL_REG (0x4B) 77*8ade6cc7SWeidong Wang #define AW88399_DSPDBG1_REG (0x4C) 78*8ade6cc7SWeidong Wang #define AW88399_DSPDBG2_REG (0x4D) 79*8ade6cc7SWeidong Wang #define AW88399_DSPDBG3_REG (0x4E) 80*8ade6cc7SWeidong Wang #define AW88399_PLLCTRL1_REG (0x50) 81*8ade6cc7SWeidong Wang #define AW88399_PLLCTRL2_REG (0x51) 82*8ade6cc7SWeidong Wang #define AW88399_PLLCTRL3_REG (0x52) 83*8ade6cc7SWeidong Wang #define AW88399_CDACTRL1_REG (0x53) 84*8ade6cc7SWeidong Wang #define AW88399_CDACTRL2_REG (0x54) 85*8ade6cc7SWeidong Wang #define AW88399_CDACTRL3_REG (0x55) 86*8ade6cc7SWeidong Wang #define AW88399_SADCCTRL1_REG (0x56) 87*8ade6cc7SWeidong Wang #define AW88399_SADCCTRL2_REG (0x57) 88*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL1_REG (0x58) 89*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL2_REG (0x5A) 90*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL3_REG (0x5B) 91*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL4_REG (0x5C) 92*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL5_REG (0x5D) 93*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL6_REG (0x5E) 94*8ade6cc7SWeidong Wang #define AW88399_BOPCTRL7_REG (0x5F) 95*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL1_REG (0x60) 96*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL2_REG (0x61) 97*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL3_REG (0x62) 98*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL4_REG (0x63) 99*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL5_REG (0x64) 100*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL6_REG (0x65) 101*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL7_REG (0x66) 102*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL8_REG (0x67) 103*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL9_REG (0x68) 104*8ade6cc7SWeidong Wang #define AW88399_BSTCTRL10_REG (0x69) 105*8ade6cc7SWeidong Wang #define AW88399_CPCTRL_REG (0x6A) 106*8ade6cc7SWeidong Wang #define AW88399_EFWH_REG (0x6C) 107*8ade6cc7SWeidong Wang #define AW88399_EFWM2_REG (0x6D) 108*8ade6cc7SWeidong Wang #define AW88399_EFWM1_REG (0x6E) 109*8ade6cc7SWeidong Wang #define AW88399_EFWL_REG (0x6F) 110*8ade6cc7SWeidong Wang #define AW88399_TESTCTRL1_REG (0x70) 111*8ade6cc7SWeidong Wang #define AW88399_TESTCTRL2_REG (0x71) 112*8ade6cc7SWeidong Wang #define AW88399_EFCTRL1_REG (0x72) 113*8ade6cc7SWeidong Wang #define AW88399_EFCTRL2_REG (0x73) 114*8ade6cc7SWeidong Wang #define AW88399_EFRH4_REG (0x74) 115*8ade6cc7SWeidong Wang #define AW88399_EFRH3_REG (0x75) 116*8ade6cc7SWeidong Wang #define AW88399_EFRH2_REG (0x76) 117*8ade6cc7SWeidong Wang #define AW88399_EFRH1_REG (0x77) 118*8ade6cc7SWeidong Wang #define AW88399_EFRL4_REG (0x78) 119*8ade6cc7SWeidong Wang #define AW88399_EFRL3_REG (0x79) 120*8ade6cc7SWeidong Wang #define AW88399_EFRL2_REG (0x7A) 121*8ade6cc7SWeidong Wang #define AW88399_EFRL1_REG (0x7B) 122*8ade6cc7SWeidong Wang #define AW88399_TM_REG (0x7C) 123*8ade6cc7SWeidong Wang #define AW88399_TM2_REG (0x7D) 124*8ade6cc7SWeidong Wang 125*8ade6cc7SWeidong Wang #define AW88399_REG_MAX (0x7E) 126*8ade6cc7SWeidong Wang #define AW88399_MUTE_VOL (1023) 127*8ade6cc7SWeidong Wang 128*8ade6cc7SWeidong Wang #define AW88399_DSP_CFG_ADDR (0x9B00) 129*8ade6cc7SWeidong Wang #define AW88399_DSP_REG_CFG_ADPZ_RA (0x9B68) 130*8ade6cc7SWeidong Wang #define AW88399_DSP_FW_ADDR (0x8980) 131*8ade6cc7SWeidong Wang #define AW88399_DSP_ROM_CHECK_ADDR (0x1F40) 132*8ade6cc7SWeidong Wang #define AW88399_DSP_ROM_CHECK_DATA (0x4638) 133*8ade6cc7SWeidong Wang 134*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_HBITS_MASK (~(0xFFFF0000)) 135*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_HBITS_SHIFT (16) 136*8ade6cc7SWeidong Wang 137*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_LBITS_MASK (~(0xFFFF)) 138*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_LBITS_SHIFT (0) 139*8ade6cc7SWeidong Wang 140*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_START_BIT (9) 141*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_BITS_LEN (1) 142*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_MASK \ 143*8ade6cc7SWeidong Wang (~(((1<<AW88399_I2STXEN_BITS_LEN)-1) << AW88399_I2STXEN_START_BIT)) 144*8ade6cc7SWeidong Wang 145*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_DISABLE (0) 146*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_DISABLE_VALUE \ 147*8ade6cc7SWeidong Wang (AW88399_I2STXEN_DISABLE << AW88399_I2STXEN_START_BIT) 148*8ade6cc7SWeidong Wang 149*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_ENABLE (1) 150*8ade6cc7SWeidong Wang #define AW88399_I2STXEN_ENABLE_VALUE \ 151*8ade6cc7SWeidong Wang (AW88399_I2STXEN_ENABLE << AW88399_I2STXEN_START_BIT) 152*8ade6cc7SWeidong Wang 153*8ade6cc7SWeidong Wang #define AW88399_VOL_START_BIT (0) 154*8ade6cc7SWeidong Wang #define AW88399_VOL_BITS_LEN (10) 155*8ade6cc7SWeidong Wang #define AW88399_VOL_MASK \ 156*8ade6cc7SWeidong Wang (~(((1<<AW88399_VOL_BITS_LEN)-1) << AW88399_VOL_START_BIT)) 157*8ade6cc7SWeidong Wang 158*8ade6cc7SWeidong Wang #define AW88399_PWDN_START_BIT (0) 159*8ade6cc7SWeidong Wang #define AW88399_PWDN_BITS_LEN (1) 160*8ade6cc7SWeidong Wang #define AW88399_PWDN_MASK \ 161*8ade6cc7SWeidong Wang (~(((1<<AW88399_PWDN_BITS_LEN)-1) << AW88399_PWDN_START_BIT)) 162*8ade6cc7SWeidong Wang 163*8ade6cc7SWeidong Wang #define AW88399_PWDN_POWER_DOWN (1) 164*8ade6cc7SWeidong Wang #define AW88399_PWDN_POWER_DOWN_VALUE \ 165*8ade6cc7SWeidong Wang (AW88399_PWDN_POWER_DOWN << AW88399_PWDN_START_BIT) 166*8ade6cc7SWeidong Wang 167*8ade6cc7SWeidong Wang #define AW88399_PWDN_WORKING (0) 168*8ade6cc7SWeidong Wang #define AW88399_PWDN_WORKING_VALUE \ 169*8ade6cc7SWeidong Wang (AW88399_PWDN_WORKING << AW88399_PWDN_START_BIT) 170*8ade6cc7SWeidong Wang 171*8ade6cc7SWeidong Wang #define AW88399_DSPBY_START_BIT (2) 172*8ade6cc7SWeidong Wang #define AW88399_DSPBY_BITS_LEN (1) 173*8ade6cc7SWeidong Wang #define AW88399_DSPBY_MASK \ 174*8ade6cc7SWeidong Wang (~(((1<<AW88399_DSPBY_BITS_LEN)-1) << AW88399_DSPBY_START_BIT)) 175*8ade6cc7SWeidong Wang 176*8ade6cc7SWeidong Wang #define AW88399_DSPBY_WORKING (0) 177*8ade6cc7SWeidong Wang #define AW88399_DSPBY_WORKING_VALUE \ 178*8ade6cc7SWeidong Wang (AW88399_DSPBY_WORKING << AW88399_DSPBY_START_BIT) 179*8ade6cc7SWeidong Wang 180*8ade6cc7SWeidong Wang #define AW88399_DSPBY_BYPASS (1) 181*8ade6cc7SWeidong Wang #define AW88399_DSPBY_BYPASS_VALUE \ 182*8ade6cc7SWeidong Wang (AW88399_DSPBY_BYPASS << AW88399_DSPBY_START_BIT) 183*8ade6cc7SWeidong Wang 184*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_START_BIT (3) 185*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_BITS_LEN (1) 186*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_MASK \ 187*8ade6cc7SWeidong Wang (~(((1<<AW88399_MEM_CLKSEL_BITS_LEN)-1) << AW88399_MEM_CLKSEL_START_BIT)) 188*8ade6cc7SWeidong Wang 189*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_OSCCLK (0) 190*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_OSCCLK_VALUE \ 191*8ade6cc7SWeidong Wang (AW88399_MEM_CLKSEL_OSCCLK << AW88399_MEM_CLKSEL_START_BIT) 192*8ade6cc7SWeidong Wang 193*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_DAPHCLK (1) 194*8ade6cc7SWeidong Wang #define AW88399_MEM_CLKSEL_DAPHCLK_VALUE \ 195*8ade6cc7SWeidong Wang (AW88399_MEM_CLKSEL_DAPHCLK << AW88399_MEM_CLKSEL_START_BIT) 196*8ade6cc7SWeidong Wang 197*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_START_BIT (15) 198*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_BITS_LEN (1) 199*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_MASK \ 200*8ade6cc7SWeidong Wang (~(((1<<AW88399_DITHER_EN_BITS_LEN)-1) << AW88399_DITHER_EN_START_BIT)) 201*8ade6cc7SWeidong Wang 202*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_DISABLE (0) 203*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_DISABLE_VALUE \ 204*8ade6cc7SWeidong Wang (AW88399_DITHER_EN_DISABLE << AW88399_DITHER_EN_START_BIT) 205*8ade6cc7SWeidong Wang 206*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_ENABLE (1) 207*8ade6cc7SWeidong Wang #define AW88399_DITHER_EN_ENABLE_VALUE \ 208*8ade6cc7SWeidong Wang (AW88399_DITHER_EN_ENABLE << AW88399_DITHER_EN_START_BIT) 209*8ade6cc7SWeidong Wang 210*8ade6cc7SWeidong Wang #define AW88399_HMUTE_START_BIT (8) 211*8ade6cc7SWeidong Wang #define AW88399_HMUTE_BITS_LEN (1) 212*8ade6cc7SWeidong Wang #define AW88399_HMUTE_MASK \ 213*8ade6cc7SWeidong Wang (~(((1<<AW88399_HMUTE_BITS_LEN)-1) << AW88399_HMUTE_START_BIT)) 214*8ade6cc7SWeidong Wang 215*8ade6cc7SWeidong Wang #define AW88399_HMUTE_DISABLE (0) 216*8ade6cc7SWeidong Wang #define AW88399_HMUTE_DISABLE_VALUE \ 217*8ade6cc7SWeidong Wang (AW88399_HMUTE_DISABLE << AW88399_HMUTE_START_BIT) 218*8ade6cc7SWeidong Wang 219*8ade6cc7SWeidong Wang #define AW88399_HMUTE_ENABLE (1) 220*8ade6cc7SWeidong Wang #define AW88399_HMUTE_ENABLE_VALUE \ 221*8ade6cc7SWeidong Wang (AW88399_HMUTE_ENABLE << AW88399_HMUTE_START_BIT) 222*8ade6cc7SWeidong Wang 223*8ade6cc7SWeidong Wang #define AW88399_EF_DBMD_START_BIT (2) 224*8ade6cc7SWeidong Wang #define AW88399_EF_DBMD_BITS_LEN (1) 225*8ade6cc7SWeidong Wang #define AW88399_EF_DBMD_MASK \ 226*8ade6cc7SWeidong Wang (~(((1<<AW88399_EF_DBMD_BITS_LEN)-1) << AW88399_EF_DBMD_START_BIT)) 227*8ade6cc7SWeidong Wang 228*8ade6cc7SWeidong Wang #define AW88399_EF_DBMD_OR (1) 229*8ade6cc7SWeidong Wang #define AW88399_EF_DBMD_OR_VALUE \ 230*8ade6cc7SWeidong Wang (AW88399_EF_DBMD_OR << AW88399_EF_DBMD_START_BIT) 231*8ade6cc7SWeidong Wang 232*8ade6cc7SWeidong Wang #define AW88399_VDSEL_START_BIT (5) 233*8ade6cc7SWeidong Wang #define AW88399_VDSEL_BITS_LEN (1) 234*8ade6cc7SWeidong Wang #define AW88399_VDSEL_MASK \ 235*8ade6cc7SWeidong Wang (~(((1<<AW88399_VDSEL_BITS_LEN)-1) << AW88399_VDSEL_START_BIT)) 236*8ade6cc7SWeidong Wang 237*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_H_START_BIT (0) 238*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_H_BITS_LEN (10) 239*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_H_MASK \ 240*8ade6cc7SWeidong Wang (~(((1<<AW88399_EF_ISN_GESLP_H_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_H_START_BIT)) 241*8ade6cc7SWeidong Wang 242*8ade6cc7SWeidong Wang /* EF_VSN_GESLP_H bit 9:0 (EFRH3 0x75) */ 243*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_H_START_BIT (0) 244*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_H_BITS_LEN (10) 245*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_H_MASK \ 246*8ade6cc7SWeidong Wang (~(((1<<AW88399_EF_VSN_GESLP_H_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_H_START_BIT)) 247*8ade6cc7SWeidong Wang 248*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_L_START_BIT (0) 249*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_L_BITS_LEN (10) 250*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_L_MASK \ 251*8ade6cc7SWeidong Wang (~(((1<<AW88399_EF_ISN_GESLP_L_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_L_START_BIT)) 252*8ade6cc7SWeidong Wang 253*8ade6cc7SWeidong Wang /* EF_VSN_GESLP_L bit 9:0 (EFRL3 0x79) */ 254*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_L_START_BIT (0) 255*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_L_BITS_LEN (10) 256*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_L_MASK \ 257*8ade6cc7SWeidong Wang (~(((1<<AW88399_EF_VSN_GESLP_L_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_L_START_BIT)) 258*8ade6cc7SWeidong Wang 259*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_H_START_BIT (9) 260*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN (6) 261*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_H_MASK \ 262*8ade6cc7SWeidong Wang (~(((1<<AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_H_START_BIT)) 263*8ade6cc7SWeidong Wang 264*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_L_START_BIT (9) 265*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN (6) 266*8ade6cc7SWeidong Wang #define AW88399_INTERNAL_VSN_TRIM_L_MASK \ 267*8ade6cc7SWeidong Wang (~(((1<<AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_L_START_BIT)) 268*8ade6cc7SWeidong Wang 269*8ade6cc7SWeidong Wang #define AW88399_RCV_MODE_START_BIT (7) 270*8ade6cc7SWeidong Wang #define AW88399_RCV_MODE_BITS_LEN (1) 271*8ade6cc7SWeidong Wang #define AW88399_RCV_MODE_MASK \ 272*8ade6cc7SWeidong Wang (~(((1<<AW88399_RCV_MODE_BITS_LEN)-1) << AW88399_RCV_MODE_START_BIT)) 273*8ade6cc7SWeidong Wang 274*8ade6cc7SWeidong Wang #define AW88399_CLKI_START_BIT (4) 275*8ade6cc7SWeidong Wang #define AW88399_NOCLKI_START_BIT (5) 276*8ade6cc7SWeidong Wang #define AW88399_PLLI_START_BIT (0) 277*8ade6cc7SWeidong Wang #define AW88399_PLLI_INT_VALUE (1) 278*8ade6cc7SWeidong Wang #define AW88399_PLLI_INT_INTERRUPT \ 279*8ade6cc7SWeidong Wang (AW88399_PLLI_INT_VALUE << AW88399_PLLI_START_BIT) 280*8ade6cc7SWeidong Wang 281*8ade6cc7SWeidong Wang #define AW88399_CLKI_INT_VALUE (1) 282*8ade6cc7SWeidong Wang #define AW88399_CLKI_INT_INTERRUPT \ 283*8ade6cc7SWeidong Wang (AW88399_CLKI_INT_VALUE << AW88399_CLKI_START_BIT) 284*8ade6cc7SWeidong Wang 285*8ade6cc7SWeidong Wang #define AW88399_NOCLKI_INT_VALUE (1) 286*8ade6cc7SWeidong Wang #define AW88399_NOCLKI_INT_INTERRUPT \ 287*8ade6cc7SWeidong Wang (AW88399_NOCLKI_INT_VALUE << AW88399_NOCLKI_START_BIT) 288*8ade6cc7SWeidong Wang 289*8ade6cc7SWeidong Wang #define AW88399_BIT_SYSINT_CHECK \ 290*8ade6cc7SWeidong Wang (AW88399_PLLI_INT_INTERRUPT | \ 291*8ade6cc7SWeidong Wang AW88399_CLKI_INT_INTERRUPT | \ 292*8ade6cc7SWeidong Wang AW88399_NOCLKI_INT_INTERRUPT) 293*8ade6cc7SWeidong Wang 294*8ade6cc7SWeidong Wang #define AW88399_CRC_CHECK_START_BIT (12) 295*8ade6cc7SWeidong Wang #define AW88399_CRC_CHECK_BITS_LEN (3) 296*8ade6cc7SWeidong Wang #define AW88399_CRC_CHECK_BITS_MASK \ 297*8ade6cc7SWeidong Wang (~(((1<<AW88399_CRC_CHECK_BITS_LEN)-1) << AW88399_CRC_CHECK_START_BIT)) 298*8ade6cc7SWeidong Wang 299*8ade6cc7SWeidong Wang #define AW88399_RCV_MODE_RECEIVER (1) 300*8ade6cc7SWeidong Wang #define AW88399_RCV_MODE_RECEIVER_VALUE \ 301*8ade6cc7SWeidong Wang (AW88399_RCV_MODE_RECEIVER << AW88399_RCV_MODE_START_BIT) 302*8ade6cc7SWeidong Wang 303*8ade6cc7SWeidong Wang #define AW88399_AMPPD_START_BIT (1) 304*8ade6cc7SWeidong Wang #define AW88399_AMPPD_BITS_LEN (1) 305*8ade6cc7SWeidong Wang #define AW88399_AMPPD_MASK \ 306*8ade6cc7SWeidong Wang (~(((1<<AW88399_AMPPD_BITS_LEN)-1) << AW88399_AMPPD_START_BIT)) 307*8ade6cc7SWeidong Wang 308*8ade6cc7SWeidong Wang #define AW88399_AMPPD_WORKING (0) 309*8ade6cc7SWeidong Wang #define AW88399_AMPPD_WORKING_VALUE \ 310*8ade6cc7SWeidong Wang (AW88399_AMPPD_WORKING << AW88399_AMPPD_START_BIT) 311*8ade6cc7SWeidong Wang 312*8ade6cc7SWeidong Wang #define AW88399_AMPPD_POWER_DOWN (1) 313*8ade6cc7SWeidong Wang #define AW88399_AMPPD_POWER_DOWN_VALUE \ 314*8ade6cc7SWeidong Wang (AW88399_AMPPD_POWER_DOWN << AW88399_AMPPD_START_BIT) 315*8ade6cc7SWeidong Wang 316*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_START_BIT (0) 317*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_BITS_LEN (1) 318*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_MASK \ 319*8ade6cc7SWeidong Wang (~(((1<<AW88399_RAM_CG_BYP_BITS_LEN)-1) << AW88399_RAM_CG_BYP_START_BIT)) 320*8ade6cc7SWeidong Wang 321*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_WORK (0) 322*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_WORK_VALUE \ 323*8ade6cc7SWeidong Wang (AW88399_RAM_CG_BYP_WORK << AW88399_RAM_CG_BYP_START_BIT) 324*8ade6cc7SWeidong Wang 325*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_BYPASS (1) 326*8ade6cc7SWeidong Wang #define AW88399_RAM_CG_BYP_BYPASS_VALUE \ 327*8ade6cc7SWeidong Wang (AW88399_RAM_CG_BYP_BYPASS << AW88399_RAM_CG_BYP_START_BIT) 328*8ade6cc7SWeidong Wang 329*8ade6cc7SWeidong Wang #define AW88399_CRC_END_ADDR_START_BIT (0) 330*8ade6cc7SWeidong Wang #define AW88399_CRC_END_ADDR_BITS_LEN (12) 331*8ade6cc7SWeidong Wang #define AW88399_CRC_END_ADDR_MASK \ 332*8ade6cc7SWeidong Wang (~(((1<<AW88399_CRC_END_ADDR_BITS_LEN)-1) << AW88399_CRC_END_ADDR_START_BIT)) 333*8ade6cc7SWeidong Wang 334*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_START_BIT (13) 335*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_BITS_LEN (1) 336*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_MASK \ 337*8ade6cc7SWeidong Wang (~(((1<<AW88399_CRC_CODE_EN_BITS_LEN)-1) << AW88399_CRC_CODE_EN_START_BIT)) 338*8ade6cc7SWeidong Wang 339*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_DISABLE (0) 340*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_DISABLE_VALUE \ 341*8ade6cc7SWeidong Wang (AW88399_CRC_CODE_EN_DISABLE << AW88399_CRC_CODE_EN_START_BIT) 342*8ade6cc7SWeidong Wang 343*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_ENABLE (1) 344*8ade6cc7SWeidong Wang #define AW88399_CRC_CODE_EN_ENABLE_VALUE \ 345*8ade6cc7SWeidong Wang (AW88399_CRC_CODE_EN_ENABLE << AW88399_CRC_CODE_EN_START_BIT) 346*8ade6cc7SWeidong Wang 347*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_START_BIT (12) 348*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_BITS_LEN (1) 349*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_MASK \ 350*8ade6cc7SWeidong Wang (~(((1<<AW88399_CRC_CFG_EN_BITS_LEN)-1) << AW88399_CRC_CFG_EN_START_BIT)) 351*8ade6cc7SWeidong Wang 352*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_DISABLE (0) 353*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_DISABLE_VALUE \ 354*8ade6cc7SWeidong Wang (AW88399_CRC_CFG_EN_DISABLE << AW88399_CRC_CFG_EN_START_BIT) 355*8ade6cc7SWeidong Wang 356*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_ENABLE (1) 357*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_EN_ENABLE_VALUE \ 358*8ade6cc7SWeidong Wang (AW88399_CRC_CFG_EN_ENABLE << AW88399_CRC_CFG_EN_START_BIT) 359*8ade6cc7SWeidong Wang 360*8ade6cc7SWeidong Wang #define AW88399_OCDS_START_BIT (3) 361*8ade6cc7SWeidong Wang #define AW88399_OCDS_OC (1) 362*8ade6cc7SWeidong Wang #define AW88399_OCDS_OC_VALUE \ 363*8ade6cc7SWeidong Wang (AW88399_OCDS_OC << AW88399_OCDS_START_BIT) 364*8ade6cc7SWeidong Wang 365*8ade6cc7SWeidong Wang #define AW88399_NOCLKS_START_BIT (5) 366*8ade6cc7SWeidong Wang #define AW88399_NOCLKS_NO_CLOCK (1) 367*8ade6cc7SWeidong Wang #define AW88399_NOCLKS_NO_CLOCK_VALUE \ 368*8ade6cc7SWeidong Wang (AW88399_NOCLKS_NO_CLOCK << AW88399_NOCLKS_START_BIT) 369*8ade6cc7SWeidong Wang 370*8ade6cc7SWeidong Wang #define AW88399_SWS_START_BIT (8) 371*8ade6cc7SWeidong Wang #define AW88399_SWS_SWITCHING (1) 372*8ade6cc7SWeidong Wang #define AW88399_SWS_SWITCHING_VALUE \ 373*8ade6cc7SWeidong Wang (AW88399_SWS_SWITCHING << AW88399_SWS_START_BIT) 374*8ade6cc7SWeidong Wang 375*8ade6cc7SWeidong Wang #define AW88399_BSTS_START_BIT (9) 376*8ade6cc7SWeidong Wang #define AW88399_BSTS_FINISHED (1) 377*8ade6cc7SWeidong Wang #define AW88399_BSTS_FINISHED_VALUE \ 378*8ade6cc7SWeidong Wang (AW88399_BSTS_FINISHED << AW88399_BSTS_START_BIT) 379*8ade6cc7SWeidong Wang 380*8ade6cc7SWeidong Wang #define AW88399_UVLS_START_BIT (14) 381*8ade6cc7SWeidong Wang #define AW88399_UVLS_NORMAL (0) 382*8ade6cc7SWeidong Wang #define AW88399_UVLS_NORMAL_VALUE \ 383*8ade6cc7SWeidong Wang (AW88399_UVLS_NORMAL << AW88399_UVLS_START_BIT) 384*8ade6cc7SWeidong Wang 385*8ade6cc7SWeidong Wang #define AW88399_BSTOCS_START_BIT (11) 386*8ade6cc7SWeidong Wang #define AW88399_BSTOCS_OVER_CURRENT (1) 387*8ade6cc7SWeidong Wang #define AW88399_BSTOCS_OVER_CURRENT_VALUE \ 388*8ade6cc7SWeidong Wang (AW88399_BSTOCS_OVER_CURRENT << AW88399_BSTOCS_START_BIT) 389*8ade6cc7SWeidong Wang 390*8ade6cc7SWeidong Wang #define AW88399_OTHS_START_BIT (1) 391*8ade6cc7SWeidong Wang #define AW88399_OTHS_OT (1) 392*8ade6cc7SWeidong Wang #define AW88399_OTHS_OT_VALUE \ 393*8ade6cc7SWeidong Wang (AW88399_OTHS_OT << AW88399_OTHS_START_BIT) 394*8ade6cc7SWeidong Wang 395*8ade6cc7SWeidong Wang #define AW88399_PLLS_START_BIT (0) 396*8ade6cc7SWeidong Wang #define AW88399_PLLS_LOCKED (1) 397*8ade6cc7SWeidong Wang #define AW88399_PLLS_LOCKED_VALUE \ 398*8ade6cc7SWeidong Wang (AW88399_PLLS_LOCKED << AW88399_PLLS_START_BIT) 399*8ade6cc7SWeidong Wang 400*8ade6cc7SWeidong Wang #define AW88399_CLKS_START_BIT (4) 401*8ade6cc7SWeidong Wang #define AW88399_CLKS_STABLE (1) 402*8ade6cc7SWeidong Wang #define AW88399_CLKS_STABLE_VALUE \ 403*8ade6cc7SWeidong Wang (AW88399_CLKS_STABLE << AW88399_CLKS_START_BIT) 404*8ade6cc7SWeidong Wang 405*8ade6cc7SWeidong Wang #define AW88399_BIT_PLL_CHECK \ 406*8ade6cc7SWeidong Wang (AW88399_CLKS_STABLE_VALUE | \ 407*8ade6cc7SWeidong Wang AW88399_PLLS_LOCKED_VALUE) 408*8ade6cc7SWeidong Wang 409*8ade6cc7SWeidong Wang #define AW88399_BIT_SYSST_CHECK_MASK \ 410*8ade6cc7SWeidong Wang (~(AW88399_UVLS_NORMAL_VALUE | \ 411*8ade6cc7SWeidong Wang AW88399_BSTOCS_OVER_CURRENT_VALUE | \ 412*8ade6cc7SWeidong Wang AW88399_BSTS_FINISHED_VALUE | \ 413*8ade6cc7SWeidong Wang AW88399_SWS_SWITCHING_VALUE | \ 414*8ade6cc7SWeidong Wang AW88399_NOCLKS_NO_CLOCK_VALUE | \ 415*8ade6cc7SWeidong Wang AW88399_CLKS_STABLE_VALUE | \ 416*8ade6cc7SWeidong Wang AW88399_OCDS_OC_VALUE | \ 417*8ade6cc7SWeidong Wang AW88399_OTHS_OT_VALUE | \ 418*8ade6cc7SWeidong Wang AW88399_PLLS_LOCKED_VALUE)) 419*8ade6cc7SWeidong Wang 420*8ade6cc7SWeidong Wang #define AW88399_BIT_SYSST_NOSWS_CHECK \ 421*8ade6cc7SWeidong Wang (AW88399_BSTS_FINISHED_VALUE | \ 422*8ade6cc7SWeidong Wang AW88399_CLKS_STABLE_VALUE | \ 423*8ade6cc7SWeidong Wang AW88399_PLLS_LOCKED_VALUE) 424*8ade6cc7SWeidong Wang 425*8ade6cc7SWeidong Wang #define AW88399_BIT_SYSST_SWS_CHECK \ 426*8ade6cc7SWeidong Wang (AW88399_BSTS_FINISHED_VALUE | \ 427*8ade6cc7SWeidong Wang AW88399_CLKS_STABLE_VALUE | \ 428*8ade6cc7SWeidong Wang AW88399_PLLS_LOCKED_VALUE | \ 429*8ade6cc7SWeidong Wang AW88399_SWS_SWITCHING_VALUE) 430*8ade6cc7SWeidong Wang 431*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_START_BIT (14) 432*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_BITS_LEN (1) 433*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_MASK \ 434*8ade6cc7SWeidong Wang (~(((1<<AW88399_CCO_MUX_BITS_LEN)-1) << AW88399_CCO_MUX_START_BIT)) 435*8ade6cc7SWeidong Wang 436*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_DIVIDED (0) 437*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_DIVIDED_VALUE \ 438*8ade6cc7SWeidong Wang (AW88399_CCO_MUX_DIVIDED << AW88399_CCO_MUX_START_BIT) 439*8ade6cc7SWeidong Wang 440*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_BYPASS (1) 441*8ade6cc7SWeidong Wang #define AW88399_CCO_MUX_BYPASS_VALUE \ 442*8ade6cc7SWeidong Wang (AW88399_CCO_MUX_BYPASS << AW88399_CCO_MUX_START_BIT) 443*8ade6cc7SWeidong Wang 444*8ade6cc7SWeidong Wang #define AW88399_NOISE_GATE_EN_START_BIT (13) 445*8ade6cc7SWeidong Wang #define AW88399_NOISE_GATE_EN_BITS_LEN (1) 446*8ade6cc7SWeidong Wang #define AW88399_NOISE_GATE_EN_MASK \ 447*8ade6cc7SWeidong Wang (~(((1<<AW88399_NOISE_GATE_EN_BITS_LEN)-1) << AW88399_NOISE_GATE_EN_START_BIT)) 448*8ade6cc7SWeidong Wang 449*8ade6cc7SWeidong Wang #define AW88399_WDT_CNT_START_BIT (0) 450*8ade6cc7SWeidong Wang #define AW88399_WDT_CNT_BITS_LEN (8) 451*8ade6cc7SWeidong Wang #define AW88399_WDT_CNT_MASK \ 452*8ade6cc7SWeidong Wang (~(((1<<AW88399_WDT_CNT_BITS_LEN)-1) << AW88399_WDT_CNT_START_BIT)) 453*8ade6cc7SWeidong Wang 454*8ade6cc7SWeidong Wang #define AW88399_VOLUME_STEP_DB (64) 455*8ade6cc7SWeidong Wang #define AW88399_VOL_DEFAULT_VALUE (0) 456*8ade6cc7SWeidong Wang #define AW88399_DSP_ODD_NUM_BIT_TEST (0x5555) 457*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) 458*8ade6cc7SWeidong Wang #define AW88399_EF_ISN_GESLP_SIGN_NEG (0xfe00) 459*8ade6cc7SWeidong Wang 460*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) 461*8ade6cc7SWeidong Wang #define AW88399_EF_VSN_GESLP_SIGN_NEG (0xfe00) 462*8ade6cc7SWeidong Wang 463*8ade6cc7SWeidong Wang #define AW88399_TEM4_SIGN_MASK (~(1 << 5)) 464*8ade6cc7SWeidong Wang #define AW88399_TEM4_SIGN_NEG (0xffc0) 465*8ade6cc7SWeidong Wang 466*8ade6cc7SWeidong Wang #define AW88399_ICABLK_FACTOR (1) 467*8ade6cc7SWeidong Wang #define AW88399_VCABLK_FACTOR (1) 468*8ade6cc7SWeidong Wang #define AW88399_VCABLK_DAC_FACTOR (2) 469*8ade6cc7SWeidong Wang 470*8ade6cc7SWeidong Wang #define AW88399_VCALB_ADJ_FACTOR (12) 471*8ade6cc7SWeidong Wang #define AW88399_VCALB_ACCURACY (1 << 12) 472*8ade6cc7SWeidong Wang 473*8ade6cc7SWeidong Wang #define AW88399_ISCAL_FACTOR (3125) 474*8ade6cc7SWeidong Wang #define AW88399_VSCAL_FACTOR (18875) 475*8ade6cc7SWeidong Wang #define AW88399_ISCAL_DAC_FACTOR (3125) 476*8ade6cc7SWeidong Wang #define AW88399_VSCAL_DAC_FACTOR (12600) 477*8ade6cc7SWeidong Wang #define AW88399_CABL_BASE_VALUE (1000) 478*8ade6cc7SWeidong Wang 479*8ade6cc7SWeidong Wang #define AW88399_DEV_DEFAULT_CH (0) 480*8ade6cc7SWeidong Wang #define AW88399_DEV_DSP_CHECK_MAX (5) 481*8ade6cc7SWeidong Wang #define AW88399_MAX_RAM_WRITE_BYTE_SIZE (128) 482*8ade6cc7SWeidong Wang #define AW88399_DSP_RE_SHIFT (12) 483*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_MAX (15000) 484*8ade6cc7SWeidong Wang #define AW88399_CALI_RE_MIN (4000) 485*8ade6cc7SWeidong Wang #define AW_FW_ADDR_LEN (4) 486*8ade6cc7SWeidong Wang #define AW88399_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift)) 487*8ade6cc7SWeidong Wang #define AW88399_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000)) 488*8ade6cc7SWeidong Wang #define AW88399_CRC_CHECK_PASS_VAL (0x4) 489*8ade6cc7SWeidong Wang 490*8ade6cc7SWeidong Wang #define AW88399_CRC_CFG_BASE_ADDR (0xD80) 491*8ade6cc7SWeidong Wang #define AW88399_CRC_FW_BASE_ADDR (0x4C0) 492*8ade6cc7SWeidong Wang #define AW88399_ACF_FILE "aw88399_acf.bin" 493*8ade6cc7SWeidong Wang #define AW88399_DEV_SYSST_CHECK_MAX (10) 494*8ade6cc7SWeidong Wang 495*8ade6cc7SWeidong Wang #define AW88399_I2C_NAME "aw88399" 496*8ade6cc7SWeidong Wang 497*8ade6cc7SWeidong Wang #define AW88399_START_RETRIES (5) 498*8ade6cc7SWeidong Wang #define AW88399_START_WORK_DELAY_MS (0) 499*8ade6cc7SWeidong Wang 500*8ade6cc7SWeidong Wang #define AW88399_RATES (SNDRV_PCM_RATE_8000_48000 | \ 501*8ade6cc7SWeidong Wang SNDRV_PCM_RATE_96000) 502*8ade6cc7SWeidong Wang #define AW88399_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 503*8ade6cc7SWeidong Wang SNDRV_PCM_FMTBIT_S24_LE | \ 504*8ade6cc7SWeidong Wang SNDRV_PCM_FMTBIT_S32_LE) 505*8ade6cc7SWeidong Wang 506*8ade6cc7SWeidong Wang #define FADE_TIME_MAX 100000 507*8ade6cc7SWeidong Wang #define FADE_TIME_MIN 0 508*8ade6cc7SWeidong Wang 509*8ade6cc7SWeidong Wang #define AW88399_PROFILE_EXT(xname, profile_info, profile_get, profile_set) \ 510*8ade6cc7SWeidong Wang { \ 511*8ade6cc7SWeidong Wang .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 512*8ade6cc7SWeidong Wang .name = xname, \ 513*8ade6cc7SWeidong Wang .info = profile_info, \ 514*8ade6cc7SWeidong Wang .get = profile_get, \ 515*8ade6cc7SWeidong Wang .put = profile_set, \ 516*8ade6cc7SWeidong Wang } 517*8ade6cc7SWeidong Wang 518*8ade6cc7SWeidong Wang enum { 519*8ade6cc7SWeidong Wang AW_EF_AND_CHECK = 0, 520*8ade6cc7SWeidong Wang AW_EF_OR_CHECK, 521*8ade6cc7SWeidong Wang }; 522*8ade6cc7SWeidong Wang 523*8ade6cc7SWeidong Wang enum { 524*8ade6cc7SWeidong Wang AW88399_DEV_VDSEL_DAC = 0, 525*8ade6cc7SWeidong Wang AW88399_DEV_VDSEL_VSENSE = 1, 526*8ade6cc7SWeidong Wang }; 527*8ade6cc7SWeidong Wang 528*8ade6cc7SWeidong Wang enum { 529*8ade6cc7SWeidong Wang AW88399_DSP_CRC_NA = 0, 530*8ade6cc7SWeidong Wang AW88399_DSP_CRC_OK = 1, 531*8ade6cc7SWeidong Wang }; 532*8ade6cc7SWeidong Wang 533*8ade6cc7SWeidong Wang enum { 534*8ade6cc7SWeidong Wang AW88399_DSP_FW_UPDATE_OFF = 0, 535*8ade6cc7SWeidong Wang AW88399_DSP_FW_UPDATE_ON = 1, 536*8ade6cc7SWeidong Wang }; 537*8ade6cc7SWeidong Wang 538*8ade6cc7SWeidong Wang enum { 539*8ade6cc7SWeidong Wang AW88399_FORCE_UPDATE_OFF = 0, 540*8ade6cc7SWeidong Wang AW88399_FORCE_UPDATE_ON = 1, 541*8ade6cc7SWeidong Wang }; 542*8ade6cc7SWeidong Wang 543*8ade6cc7SWeidong Wang enum { 544*8ade6cc7SWeidong Wang AW88399_1000_US = 1000, 545*8ade6cc7SWeidong Wang AW88399_2000_US = 2000, 546*8ade6cc7SWeidong Wang AW88399_3000_US = 3000, 547*8ade6cc7SWeidong Wang AW88399_4000_US = 4000, 548*8ade6cc7SWeidong Wang }; 549*8ade6cc7SWeidong Wang 550*8ade6cc7SWeidong Wang enum AW88399_DEV_STATUS { 551*8ade6cc7SWeidong Wang AW88399_DEV_PW_OFF = 0, 552*8ade6cc7SWeidong Wang AW88399_DEV_PW_ON, 553*8ade6cc7SWeidong Wang }; 554*8ade6cc7SWeidong Wang 555*8ade6cc7SWeidong Wang enum AW88399_DEV_FW_STATUS { 556*8ade6cc7SWeidong Wang AW88399_DEV_FW_FAILED = 0, 557*8ade6cc7SWeidong Wang AW88399_DEV_FW_OK, 558*8ade6cc7SWeidong Wang }; 559*8ade6cc7SWeidong Wang 560*8ade6cc7SWeidong Wang enum AW88399_DEV_MEMCLK { 561*8ade6cc7SWeidong Wang AW88399_DEV_MEMCLK_OSC = 0, 562*8ade6cc7SWeidong Wang AW88399_DEV_MEMCLK_PLL = 1, 563*8ade6cc7SWeidong Wang }; 564*8ade6cc7SWeidong Wang 565*8ade6cc7SWeidong Wang enum AW88399_DEV_DSP_CFG { 566*8ade6cc7SWeidong Wang AW88399_DEV_DSP_WORK = 0, 567*8ade6cc7SWeidong Wang AW88399_DEV_DSP_BYPASS = 1, 568*8ade6cc7SWeidong Wang }; 569*8ade6cc7SWeidong Wang 570*8ade6cc7SWeidong Wang enum { 571*8ade6cc7SWeidong Wang AW88399_DSP_16_DATA = 0, 572*8ade6cc7SWeidong Wang AW88399_DSP_32_DATA = 1, 573*8ade6cc7SWeidong Wang }; 574*8ade6cc7SWeidong Wang 575*8ade6cc7SWeidong Wang enum { 576*8ade6cc7SWeidong Wang AW88399_NOT_RCV_MODE = 0, 577*8ade6cc7SWeidong Wang AW88399_RCV_MODE = 1, 578*8ade6cc7SWeidong Wang }; 579*8ade6cc7SWeidong Wang 580*8ade6cc7SWeidong Wang enum { 581*8ade6cc7SWeidong Wang AW88399_SYNC_START = 0, 582*8ade6cc7SWeidong Wang AW88399_ASYNC_START, 583*8ade6cc7SWeidong Wang }; 584*8ade6cc7SWeidong Wang 585*8ade6cc7SWeidong Wang struct aw88399 { 586*8ade6cc7SWeidong Wang struct aw_device *aw_pa; 587*8ade6cc7SWeidong Wang struct mutex lock; 588*8ade6cc7SWeidong Wang struct gpio_desc *reset_gpio; 589*8ade6cc7SWeidong Wang struct delayed_work start_work; 590*8ade6cc7SWeidong Wang struct regmap *regmap; 591*8ade6cc7SWeidong Wang struct aw_container *aw_cfg; 592*8ade6cc7SWeidong Wang 593*8ade6cc7SWeidong Wang unsigned int check_val; 594*8ade6cc7SWeidong Wang unsigned int crc_init_val; 595*8ade6cc7SWeidong Wang unsigned int vcalb_init_val; 596*8ade6cc7SWeidong Wang unsigned int dither_st; 597*8ade6cc7SWeidong Wang }; 598*8ade6cc7SWeidong Wang 599*8ade6cc7SWeidong Wang #endif 600