1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // aw88395_device.c -- AW88395 function for ALSA Audio Driver 4 // 5 // Copyright (c) 2022-2023 AWINIC Technology CO., LTD 6 // 7 // Author: Bruce zhao <zhaolei@awinic.com> 8 // Author: Ben Yi <yijiangtao@awinic.com> 9 // 10 11 #include <linux/crc32.h> 12 #include <linux/i2c.h> 13 #include <linux/regmap.h> 14 #include "aw88395_device.h" 15 #include "aw88395_reg.h" 16 17 static int aw_dev_dsp_write_16bit(struct aw_device *aw_dev, 18 unsigned short dsp_addr, unsigned int dsp_data) 19 { 20 int ret; 21 22 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr); 23 if (ret) { 24 dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret); 25 return ret; 26 } 27 28 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)dsp_data); 29 if (ret) { 30 dev_err(aw_dev->dev, "%s write data error, ret=%d", __func__, ret); 31 return ret; 32 } 33 34 return 0; 35 } 36 37 static int aw_dev_dsp_write_32bit(struct aw_device *aw_dev, 38 unsigned short dsp_addr, unsigned int dsp_data) 39 { 40 u16 temp_data; 41 int ret; 42 43 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr); 44 if (ret) { 45 dev_err(aw_dev->dev, "%s write addr error, ret=%d", __func__, ret); 46 return ret; 47 } 48 49 temp_data = dsp_data & AW88395_DSP_16_DATA_MASK; 50 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data); 51 if (ret) { 52 dev_err(aw_dev->dev, "%s write datal error, ret=%d", __func__, ret); 53 return ret; 54 } 55 56 temp_data = dsp_data >> 16; 57 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, (u16)temp_data); 58 if (ret) { 59 dev_err(aw_dev->dev, "%s write datah error, ret=%d", __func__, ret); 60 return ret; 61 } 62 63 return 0; 64 } 65 66 static int aw_dev_dsp_write(struct aw_device *aw_dev, 67 unsigned short dsp_addr, unsigned int dsp_data, unsigned char data_type) 68 { 69 u32 reg_value; 70 int ret; 71 72 mutex_lock(&aw_dev->dsp_lock); 73 switch (data_type) { 74 case AW88395_DSP_16_DATA: 75 ret = aw_dev_dsp_write_16bit(aw_dev, dsp_addr, dsp_data); 76 if (ret) 77 dev_err(aw_dev->dev, "write dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed", 78 (u32)dsp_addr, dsp_data); 79 break; 80 case AW88395_DSP_32_DATA: 81 ret = aw_dev_dsp_write_32bit(aw_dev, dsp_addr, dsp_data); 82 if (ret) 83 dev_err(aw_dev->dev, "write dsp_addr[0x%x] 32-bit dsp_data[0x%x] failed", 84 (u32)dsp_addr, dsp_data); 85 break; 86 default: 87 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type); 88 ret = -EINVAL; 89 break; 90 } 91 92 /* clear dsp chip select state*/ 93 if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value)) 94 dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret); 95 mutex_unlock(&aw_dev->dsp_lock); 96 97 return ret; 98 } 99 100 static int aw_dev_dsp_read_16bit(struct aw_device *aw_dev, 101 unsigned short dsp_addr, unsigned int *dsp_data) 102 { 103 unsigned int temp_data; 104 int ret; 105 106 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr); 107 if (ret) { 108 dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret); 109 return ret; 110 } 111 112 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data); 113 if (ret) { 114 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret); 115 return ret; 116 } 117 *dsp_data = temp_data; 118 119 return 0; 120 } 121 122 static int aw_dev_dsp_read_32bit(struct aw_device *aw_dev, 123 unsigned short dsp_addr, unsigned int *dsp_data) 124 { 125 unsigned int temp_data; 126 int ret; 127 128 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, dsp_addr); 129 if (ret) { 130 dev_err(aw_dev->dev, "%s write error, ret=%d", __func__, ret); 131 return ret; 132 } 133 134 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data); 135 if (ret) { 136 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret); 137 return ret; 138 } 139 *dsp_data = temp_data; 140 141 ret = regmap_read(aw_dev->regmap, AW88395_DSPMDAT_REG, &temp_data); 142 if (ret) { 143 dev_err(aw_dev->dev, "%s read error, ret=%d", __func__, ret); 144 return ret; 145 } 146 *dsp_data |= (temp_data << 16); 147 148 return 0; 149 } 150 151 static int aw_dev_dsp_read(struct aw_device *aw_dev, 152 unsigned short dsp_addr, unsigned int *dsp_data, unsigned char data_type) 153 { 154 u32 reg_value; 155 int ret; 156 157 mutex_lock(&aw_dev->dsp_lock); 158 switch (data_type) { 159 case AW88395_DSP_16_DATA: 160 ret = aw_dev_dsp_read_16bit(aw_dev, dsp_addr, dsp_data); 161 if (ret) 162 dev_err(aw_dev->dev, "read dsp_addr[0x%x] 16-bit dsp_data[0x%x] failed", 163 (u32)dsp_addr, *dsp_data); 164 break; 165 case AW88395_DSP_32_DATA: 166 ret = aw_dev_dsp_read_32bit(aw_dev, dsp_addr, dsp_data); 167 if (ret) 168 dev_err(aw_dev->dev, "read dsp_addr[0x%x] 32r-bit dsp_data[0x%x] failed", 169 (u32)dsp_addr, *dsp_data); 170 break; 171 default: 172 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type); 173 ret = -EINVAL; 174 break; 175 } 176 177 /* clear dsp chip select state*/ 178 if (regmap_read(aw_dev->regmap, AW88395_ID_REG, ®_value)) 179 dev_err(aw_dev->dev, "%s fail to clear chip state. Err=%d\n", __func__, ret); 180 mutex_unlock(&aw_dev->dsp_lock); 181 182 return ret; 183 } 184 185 186 static int aw_dev_read_chipid(struct aw_device *aw_dev, u16 *chip_id) 187 { 188 int reg_val; 189 int ret; 190 191 ret = regmap_read(aw_dev->regmap, AW88395_CHIP_ID_REG, ®_val); 192 if (ret) { 193 dev_err(aw_dev->dev, "%s read chipid error. ret = %d", __func__, ret); 194 return ret; 195 } 196 197 dev_info(aw_dev->dev, "chip id = %x\n", reg_val); 198 *chip_id = reg_val; 199 200 return 0; 201 } 202 203 static unsigned int reg_val_to_db(unsigned int value) 204 { 205 return (((value >> AW88395_VOL_6DB_START) * AW88395_VOLUME_STEP_DB) + 206 ((value & 0x3f) % AW88395_VOLUME_STEP_DB)); 207 } 208 209 static unsigned short db_to_reg_val(unsigned short value) 210 { 211 return (((value / AW88395_VOLUME_STEP_DB) << AW88395_VOL_6DB_START) + 212 (value % AW88395_VOLUME_STEP_DB)); 213 } 214 215 static int aw_dev_dsp_fw_check(struct aw_device *aw_dev) 216 { 217 struct aw_sec_data_desc *dsp_fw_desc; 218 struct aw_prof_desc *set_prof_desc; 219 u16 base_addr = AW88395_DSP_FW_ADDR; 220 u16 addr = base_addr; 221 u32 dsp_val; 222 u16 bin_val; 223 int ret, i; 224 225 ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_cur, &set_prof_desc); 226 if (ret) 227 return ret; 228 229 /* update reg */ 230 dsp_fw_desc = &set_prof_desc->sec_desc[AW88395_DATA_TYPE_DSP_FW]; 231 232 for (i = 0; i < AW88395_FW_CHECK_PART; i++) { 233 ret = aw_dev_dsp_read(aw_dev, addr, &dsp_val, AW88395_DSP_16_DATA); 234 if (ret) { 235 dev_err(aw_dev->dev, "dsp read failed"); 236 return ret; 237 } 238 239 bin_val = be16_to_cpup((void *)&dsp_fw_desc->data[2 * (addr - base_addr)]); 240 241 if (dsp_val != bin_val) { 242 dev_err(aw_dev->dev, "fw check failed, addr[0x%x], read[0x%x] != bindata[0x%x]", 243 addr, dsp_val, bin_val); 244 return -EINVAL; 245 } 246 247 addr += (dsp_fw_desc->len / 2) / AW88395_FW_CHECK_PART; 248 if ((addr - base_addr) > dsp_fw_desc->len) { 249 dev_err(aw_dev->dev, "fw check failed, addr[0x%x] too large", addr); 250 return -EINVAL; 251 } 252 } 253 254 return 0; 255 } 256 257 static int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value) 258 { 259 struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; 260 unsigned int reg_value; 261 u16 real_value, volume; 262 int ret; 263 264 volume = min((value + vol_desc->init_volume), (unsigned int)AW88395_MUTE_VOL); 265 real_value = db_to_reg_val(volume); 266 267 /* cal real value */ 268 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL2_REG, ®_value); 269 if (ret) 270 return ret; 271 272 dev_dbg(aw_dev->dev, "value 0x%x , reg:0x%x", value, real_value); 273 274 /* [15 : 6] volume */ 275 real_value = (real_value << AW88395_VOL_START_BIT) | (reg_value & AW88395_VOL_MASK); 276 277 /* write value */ 278 ret = regmap_write(aw_dev->regmap, AW88395_SYSCTRL2_REG, real_value); 279 280 return ret; 281 } 282 283 void aw88395_dev_set_volume(struct aw_device *aw_dev, unsigned short set_vol) 284 { 285 int ret; 286 287 ret = aw_dev_set_volume(aw_dev, set_vol); 288 if (ret) 289 dev_dbg(aw_dev->dev, "set volume failed"); 290 } 291 EXPORT_SYMBOL_GPL(aw88395_dev_set_volume); 292 293 static void aw_dev_fade_in(struct aw_device *aw_dev) 294 { 295 struct aw_volume_desc *desc = &aw_dev->volume_desc; 296 u16 fade_in_vol = desc->ctl_volume; 297 int fade_step = aw_dev->fade_step; 298 int i; 299 300 if (!aw_dev->fade_en) 301 return; 302 303 if (fade_step == 0 || aw_dev->fade_in_time == 0) { 304 aw_dev_set_volume(aw_dev, fade_in_vol); 305 return; 306 } 307 308 for (i = AW88395_MUTE_VOL; i >= fade_in_vol; i -= fade_step) { 309 aw_dev_set_volume(aw_dev, i); 310 usleep_range(aw_dev->fade_in_time, aw_dev->fade_in_time + 10); 311 } 312 313 if (i != fade_in_vol) 314 aw_dev_set_volume(aw_dev, fade_in_vol); 315 } 316 317 static void aw_dev_fade_out(struct aw_device *aw_dev) 318 { 319 struct aw_volume_desc *desc = &aw_dev->volume_desc; 320 int fade_step = aw_dev->fade_step; 321 int i; 322 323 if (!aw_dev->fade_en) 324 return; 325 326 if (fade_step == 0 || aw_dev->fade_out_time == 0) { 327 aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL); 328 return; 329 } 330 331 for (i = desc->ctl_volume; i <= AW88395_MUTE_VOL; i += fade_step) { 332 aw_dev_set_volume(aw_dev, i); 333 usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10); 334 } 335 336 if (i != AW88395_MUTE_VOL) { 337 aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL); 338 usleep_range(aw_dev->fade_out_time, aw_dev->fade_out_time + 10); 339 } 340 } 341 342 static int aw_dev_modify_dsp_cfg(struct aw_device *aw_dev, 343 unsigned int addr, unsigned int dsp_data, unsigned char data_type) 344 { 345 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; 346 unsigned int addr_offset; 347 __le16 data1; 348 __le32 data2; 349 350 dev_dbg(aw_dev->dev, "addr:0x%x, dsp_data:0x%x", addr, dsp_data); 351 352 addr_offset = (addr - AW88395_DSP_CFG_ADDR) * 2; 353 if (addr_offset > crc_dsp_cfg->len) { 354 dev_err(aw_dev->dev, "addr_offset[%d] > crc_dsp_cfg->len[%d]", 355 addr_offset, crc_dsp_cfg->len); 356 return -EINVAL; 357 } 358 switch (data_type) { 359 case AW88395_DSP_16_DATA: 360 data1 = cpu_to_le16((u16)dsp_data); 361 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data1, 2); 362 break; 363 case AW88395_DSP_32_DATA: 364 data2 = cpu_to_le32(dsp_data); 365 memcpy(crc_dsp_cfg->data + addr_offset, (u8 *)&data2, 4); 366 break; 367 default: 368 dev_err(aw_dev->dev, "data type[%d] unsupported", data_type); 369 return -EINVAL; 370 } 371 372 return 0; 373 } 374 375 static int aw_dev_dsp_set_cali_re(struct aw_device *aw_dev) 376 { 377 u32 cali_re; 378 int ret; 379 380 cali_re = AW88395_SHOW_RE_TO_DSP_RE((aw_dev->cali_desc.cali_re + 381 aw_dev->cali_desc.ra), AW88395_DSP_RE_SHIFT); 382 383 /* set cali re to device */ 384 ret = aw_dev_dsp_write(aw_dev, 385 AW88395_DSP_REG_CFG_ADPZ_RE, cali_re, AW88395_DSP_32_DATA); 386 if (ret) { 387 dev_err(aw_dev->dev, "set cali re error"); 388 return ret; 389 } 390 391 ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RE, 392 cali_re, AW88395_DSP_32_DATA); 393 if (ret) 394 dev_err(aw_dev->dev, "modify dsp cfg failed"); 395 396 return ret; 397 } 398 399 static void aw_dev_i2s_tx_enable(struct aw_device *aw_dev, bool flag) 400 { 401 int ret; 402 403 if (flag) { 404 ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG, 405 ~AW88395_I2STXEN_MASK, AW88395_I2STXEN_ENABLE_VALUE); 406 } else { 407 ret = regmap_update_bits(aw_dev->regmap, AW88395_I2SCFG1_REG, 408 ~AW88395_I2STXEN_MASK, AW88395_I2STXEN_DISABLE_VALUE); 409 } 410 411 if (ret) 412 dev_dbg(aw_dev->dev, "%s failed", __func__); 413 } 414 415 static int aw_dev_dsp_set_crc32(struct aw_device *aw_dev) 416 { 417 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; 418 u32 crc_value, crc_data_len; 419 420 /* get crc data len */ 421 crc_data_len = (AW88395_DSP_REG_CRC_ADDR - AW88395_DSP_CFG_ADDR) * 2; 422 if (crc_data_len > crc_dsp_cfg->len) { 423 dev_err(aw_dev->dev, "crc data len :%d > cfg_data len:%d", 424 crc_data_len, crc_dsp_cfg->len); 425 return -EINVAL; 426 } 427 428 if (crc_data_len & 0x11) { 429 dev_err(aw_dev->dev, "The crc data len :%d unsupport", crc_data_len); 430 return -EINVAL; 431 } 432 433 crc_value = __crc32c_le(0xFFFFFFFF, crc_dsp_cfg->data, crc_data_len) ^ 0xFFFFFFFF; 434 435 return aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_CRC_ADDR, crc_value, 436 AW88395_DSP_32_DATA); 437 } 438 439 static void aw_dev_dsp_check_crc_enable(struct aw_device *aw_dev, bool flag) 440 { 441 int ret; 442 443 if (flag) { 444 ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG, 445 ~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_ENABLE_VALUE); 446 } else { 447 ret = regmap_update_bits(aw_dev->regmap, AW88395_HAGCCFG7_REG, 448 ~AW88395_AGC_DSP_CTL_MASK, AW88395_AGC_DSP_CTL_DISABLE_VALUE); 449 } 450 if (ret) 451 dev_dbg(aw_dev->dev, "%s failed", __func__); 452 } 453 454 static int aw_dev_dsp_check_st(struct aw_device *aw_dev) 455 { 456 unsigned int reg_val; 457 int ret; 458 int i; 459 460 for (i = 0; i < AW88395_DSP_ST_CHECK_MAX; i++) { 461 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val); 462 if (ret) { 463 dev_err(aw_dev->dev, "read reg0x%x failed", AW88395_SYSST_REG); 464 continue; 465 } 466 467 if ((reg_val & (~AW88395_DSPS_MASK)) != AW88395_DSPS_NORMAL_VALUE) { 468 dev_err(aw_dev->dev, "check dsp st fail,reg_val:0x%04x", reg_val); 469 ret = -EPERM; 470 continue; 471 } else { 472 dev_dbg(aw_dev->dev, "dsp st check ok, reg_val:0x%04x", reg_val); 473 return 0; 474 } 475 } 476 477 return ret; 478 } 479 480 static void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable) 481 { 482 int ret; 483 484 if (is_enable) { 485 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 486 ~AW88395_DSPBY_MASK, AW88395_DSPBY_WORKING_VALUE); 487 if (ret) 488 dev_dbg(aw_dev->dev, "enable dsp failed"); 489 } else { 490 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 491 ~AW88395_DSPBY_MASK, AW88395_DSPBY_BYPASS_VALUE); 492 if (ret) 493 dev_dbg(aw_dev->dev, "disable dsp failed"); 494 } 495 } 496 497 static int aw_dev_dsp_check_crc32(struct aw_device *aw_dev) 498 { 499 int ret; 500 501 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_BYPASS) { 502 dev_info(aw_dev->dev, "dsp bypass"); 503 return 0; 504 } 505 506 ret = aw_dev_dsp_set_crc32(aw_dev); 507 if (ret) { 508 dev_err(aw_dev->dev, "set dsp crc32 failed"); 509 return ret; 510 } 511 512 aw_dev_dsp_check_crc_enable(aw_dev, true); 513 514 /* dsp enable */ 515 aw_dev_dsp_enable(aw_dev, true); 516 usleep_range(AW88395_5000_US, AW88395_5000_US + 100); 517 518 ret = aw_dev_dsp_check_st(aw_dev); 519 if (ret) { 520 dev_err(aw_dev->dev, "check crc32 fail"); 521 } else { 522 aw_dev_dsp_check_crc_enable(aw_dev, false); 523 aw_dev->dsp_crc_st = AW88395_DSP_CRC_OK; 524 } 525 526 return ret; 527 } 528 529 static void aw_dev_pwd(struct aw_device *aw_dev, bool pwd) 530 { 531 int ret; 532 533 if (pwd) { 534 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 535 ~AW88395_PWDN_MASK, AW88395_PWDN_POWER_DOWN_VALUE); 536 } else { 537 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 538 ~AW88395_PWDN_MASK, AW88395_PWDN_WORKING_VALUE); 539 } 540 if (ret) 541 dev_dbg(aw_dev->dev, "%s failed", __func__); 542 } 543 544 static void aw_dev_amppd(struct aw_device *aw_dev, bool amppd) 545 { 546 int ret; 547 548 if (amppd) { 549 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 550 ~AW88395_AMPPD_MASK, AW88395_AMPPD_POWER_DOWN_VALUE); 551 } else { 552 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 553 ~AW88395_AMPPD_MASK, AW88395_AMPPD_WORKING_VALUE); 554 } 555 if (ret) 556 dev_dbg(aw_dev->dev, "%s failed", __func__); 557 } 558 559 void aw88395_dev_mute(struct aw_device *aw_dev, bool is_mute) 560 { 561 int ret; 562 563 if (is_mute) { 564 aw_dev_fade_out(aw_dev); 565 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 566 ~AW88395_HMUTE_MASK, AW88395_HMUTE_ENABLE_VALUE); 567 } else { 568 ret = regmap_update_bits(aw_dev->regmap, AW88395_SYSCTRL_REG, 569 ~AW88395_HMUTE_MASK, AW88395_HMUTE_DISABLE_VALUE); 570 aw_dev_fade_in(aw_dev); 571 } 572 573 if (ret) 574 dev_dbg(aw_dev->dev, "%s failed", __func__); 575 } 576 EXPORT_SYMBOL_GPL(aw88395_dev_mute); 577 578 static int aw_dev_get_icalk(struct aw_device *aw_dev, int16_t *icalk) 579 { 580 unsigned int reg_val; 581 u16 reg_icalk; 582 int ret; 583 584 ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val); 585 if (ret) 586 return ret; 587 588 reg_icalk = reg_val & (~AW88395_EF_ISN_GESLP_MASK); 589 590 if (reg_icalk & (~AW88395_EF_ISN_GESLP_SIGN_MASK)) 591 reg_icalk = reg_icalk | AW88395_EF_ISN_GESLP_SIGN_NEG; 592 593 *icalk = (int16_t)reg_icalk; 594 595 return ret; 596 } 597 598 static int aw_dev_get_vcalk(struct aw_device *aw_dev, int16_t *vcalk) 599 { 600 unsigned int reg_val; 601 u16 reg_vcalk; 602 int ret; 603 604 ret = regmap_read(aw_dev->regmap, AW88395_EFRH_REG, ®_val); 605 if (ret) 606 return ret; 607 608 reg_val = reg_val >> AW88395_EF_VSENSE_GAIN_SHIFT; 609 610 reg_vcalk = (u16)reg_val & (~AW88395_EF_VSN_GESLP_MASK); 611 612 if (reg_vcalk & (~AW88395_EF_VSN_GESLP_SIGN_MASK)) 613 reg_vcalk = reg_vcalk | AW88395_EF_VSN_GESLP_SIGN_NEG; 614 615 *vcalk = (int16_t)reg_vcalk; 616 617 return ret; 618 } 619 620 static int aw_dev_get_vcalk_dac(struct aw_device *aw_dev, int16_t *vcalk) 621 { 622 unsigned int reg_val; 623 u16 reg_vcalk; 624 int ret; 625 626 ret = regmap_read(aw_dev->regmap, AW88395_EFRM2_REG, ®_val); 627 if (ret) 628 return ret; 629 630 reg_vcalk = reg_val >> AW88395_EF_DAC_GESLP_SHIFT; 631 632 if (reg_vcalk & AW88395_EF_DAC_GESLP_SIGN_MASK) 633 reg_vcalk = reg_vcalk | AW88395_EF_DAC_GESLP_SIGN_NEG; 634 635 *vcalk = (int16_t)reg_vcalk; 636 637 return ret; 638 } 639 640 static int aw_dev_vsense_select(struct aw_device *aw_dev, int *vsense_select) 641 { 642 unsigned int vsense_reg_val; 643 int ret; 644 645 ret = regmap_read(aw_dev->regmap, AW88395_I2SCFG3_REG, &vsense_reg_val); 646 if (ret) { 647 dev_err(aw_dev->dev, "read vsense_reg_val failed"); 648 return ret; 649 } 650 dev_dbg(aw_dev->dev, "vsense_reg = 0x%x", vsense_reg_val); 651 652 if (vsense_reg_val & (~AW88395_VDSEL_MASK)) { 653 *vsense_select = AW88395_DEV_VDSEL_VSENSE; 654 dev_dbg(aw_dev->dev, "vsense outside"); 655 } else { 656 *vsense_select = AW88395_DEV_VDSEL_DAC; 657 dev_dbg(aw_dev->dev, "vsense inside"); 658 } 659 660 return 0; 661 } 662 663 static int aw_dev_set_vcalb(struct aw_device *aw_dev) 664 { 665 int16_t icalk_val, vcalk_val; 666 int icalk, vsense_select; 667 u32 vcalb_adj, reg_val; 668 int vcalb, vcalk; 669 int ret; 670 671 ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VCALB, &vcalb_adj, AW88395_DSP_16_DATA); 672 if (ret) { 673 dev_err(aw_dev->dev, "read vcalb_adj failed"); 674 return ret; 675 } 676 677 ret = aw_dev_vsense_select(aw_dev, &vsense_select); 678 if (ret) 679 return ret; 680 dev_dbg(aw_dev->dev, "vsense_select = %d", vsense_select); 681 682 ret = aw_dev_get_icalk(aw_dev, &icalk_val); 683 if (ret) 684 return ret; 685 icalk = AW88395_CABL_BASE_VALUE + AW88395_ICABLK_FACTOR * icalk_val; 686 687 switch (vsense_select) { 688 case AW88395_DEV_VDSEL_VSENSE: 689 ret = aw_dev_get_vcalk(aw_dev, &vcalk_val); 690 if (ret) 691 return ret; 692 vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR * vcalk_val; 693 vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR / 694 AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj; 695 696 dev_dbg(aw_dev->dev, "vcalk_factor=%d, vscal_factor=%d, icalk=%d, vcalk=%d", 697 AW88395_VCABLK_FACTOR, AW88395_VSCAL_FACTOR, icalk, vcalk); 698 break; 699 case AW88395_DEV_VDSEL_DAC: 700 ret = aw_dev_get_vcalk_dac(aw_dev, &vcalk_val); 701 if (ret) 702 return ret; 703 vcalk = AW88395_CABL_BASE_VALUE + AW88395_VCABLK_FACTOR_DAC * vcalk_val; 704 vcalb = AW88395_VCAL_FACTOR * AW88395_VSCAL_FACTOR_DAC / 705 AW88395_ISCAL_FACTOR * icalk / vcalk * vcalb_adj; 706 707 dev_dbg(aw_dev->dev, "vcalk_dac_factor=%d, vscal_dac_factor=%d, icalk=%d, vcalk=%d", 708 AW88395_VCABLK_FACTOR_DAC, 709 AW88395_VSCAL_FACTOR_DAC, icalk, vcalk); 710 break; 711 default: 712 dev_err(aw_dev->dev, "unsupport vsense status"); 713 return -EINVAL; 714 } 715 716 if ((vcalk == 0) || (AW88395_ISCAL_FACTOR == 0)) { 717 dev_err(aw_dev->dev, "vcalk:%d or desc->iscal_factor:%d unsupported", 718 vcalk, AW88395_ISCAL_FACTOR); 719 return -EINVAL; 720 } 721 722 vcalb = vcalb >> AW88395_VCALB_ADJ_FACTOR; 723 reg_val = (u32)vcalb; 724 725 dev_dbg(aw_dev->dev, "vcalb=%d, reg_val=0x%x, vcalb_adj =0x%x", 726 vcalb, reg_val, vcalb_adj); 727 728 ret = aw_dev_dsp_write(aw_dev, AW88395_DSP_REG_VCALB, reg_val, AW88395_DSP_16_DATA); 729 if (ret) { 730 dev_err(aw_dev->dev, "write vcalb failed"); 731 return ret; 732 } 733 734 ret = aw_dev_modify_dsp_cfg(aw_dev, AW88395_DSP_REG_VCALB, 735 (u32)reg_val, AW88395_DSP_16_DATA); 736 if (ret) 737 dev_err(aw_dev->dev, "modify dsp cfg failed"); 738 739 return ret; 740 } 741 742 static int aw_dev_get_cali_f0_delay(struct aw_device *aw_dev) 743 { 744 struct aw_cali_delay_desc *desc = &aw_dev->cali_delay_desc; 745 u32 cali_delay; 746 int ret; 747 748 ret = aw_dev_dsp_read(aw_dev, 749 AW88395_DSP_CALI_F0_DELAY, &cali_delay, AW88395_DSP_16_DATA); 750 if (ret) 751 dev_err(aw_dev->dev, "read cali delay failed, ret=%d", ret); 752 else 753 desc->delay = AW88395_CALI_DELAY_CACL(cali_delay); 754 755 dev_dbg(aw_dev->dev, "read cali delay: %d ms", desc->delay); 756 757 return ret; 758 } 759 760 static void aw_dev_get_int_status(struct aw_device *aw_dev, unsigned short *int_status) 761 { 762 unsigned int reg_val; 763 int ret; 764 765 ret = regmap_read(aw_dev->regmap, AW88395_SYSINT_REG, ®_val); 766 if (ret) 767 dev_err(aw_dev->dev, "read interrupt reg fail, ret=%d", ret); 768 else 769 *int_status = reg_val; 770 771 dev_dbg(aw_dev->dev, "read interrupt reg = 0x%04x", *int_status); 772 } 773 774 static void aw_dev_clear_int_status(struct aw_device *aw_dev) 775 { 776 u16 int_status; 777 778 /* read int status and clear */ 779 aw_dev_get_int_status(aw_dev, &int_status); 780 /* make sure int status is clear */ 781 aw_dev_get_int_status(aw_dev, &int_status); 782 if (int_status) 783 dev_info(aw_dev->dev, "int status(%d) is not cleaned.\n", int_status); 784 } 785 786 static int aw_dev_get_iis_status(struct aw_device *aw_dev) 787 { 788 unsigned int reg_val; 789 int ret; 790 791 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val); 792 if (ret) 793 return -EIO; 794 if ((reg_val & AW88395_BIT_PLL_CHECK) != AW88395_BIT_PLL_CHECK) { 795 dev_err(aw_dev->dev, "check pll lock fail,reg_val:0x%04x", reg_val); 796 return -EINVAL; 797 } 798 799 return 0; 800 } 801 802 static int aw_dev_check_mode1_pll(struct aw_device *aw_dev) 803 { 804 int ret, i; 805 806 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) { 807 ret = aw_dev_get_iis_status(aw_dev); 808 if (ret < 0) { 809 dev_err(aw_dev->dev, "mode1 iis signal check error"); 810 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 811 } else { 812 return 0; 813 } 814 } 815 816 return -EPERM; 817 } 818 819 static int aw_dev_check_mode2_pll(struct aw_device *aw_dev) 820 { 821 unsigned int reg_val; 822 int ret, i; 823 824 ret = regmap_read(aw_dev->regmap, AW88395_PLLCTRL1_REG, ®_val); 825 if (ret) 826 return ret; 827 828 reg_val &= (~AW88395_CCO_MUX_MASK); 829 if (reg_val == AW88395_CCO_MUX_DIVIDED_VALUE) { 830 dev_dbg(aw_dev->dev, "CCO_MUX is already divider"); 831 return -EPERM; 832 } 833 834 /* change mode2 */ 835 ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG, 836 ~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_DIVIDED_VALUE); 837 if (ret) 838 return ret; 839 840 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) { 841 ret = aw_dev_get_iis_status(aw_dev); 842 if (ret) { 843 dev_err(aw_dev->dev, "mode2 iis signal check error"); 844 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 845 } else { 846 break; 847 } 848 } 849 850 /* change mode1 */ 851 ret = regmap_update_bits(aw_dev->regmap, AW88395_PLLCTRL1_REG, 852 ~AW88395_CCO_MUX_MASK, AW88395_CCO_MUX_BYPASS_VALUE); 853 if (ret == 0) { 854 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 855 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) { 856 ret = aw_dev_check_mode1_pll(aw_dev); 857 if (ret < 0) { 858 dev_err(aw_dev->dev, "mode2 switch to mode1, iis signal check error"); 859 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 860 } else { 861 break; 862 } 863 } 864 } 865 866 return ret; 867 } 868 869 static int aw_dev_check_syspll(struct aw_device *aw_dev) 870 { 871 int ret; 872 873 ret = aw_dev_check_mode1_pll(aw_dev); 874 if (ret) { 875 dev_dbg(aw_dev->dev, "mode1 check iis failed try switch to mode2 check"); 876 ret = aw_dev_check_mode2_pll(aw_dev); 877 if (ret) { 878 dev_err(aw_dev->dev, "mode2 check iis failed"); 879 return ret; 880 } 881 } 882 883 return ret; 884 } 885 886 static int aw_dev_check_sysst(struct aw_device *aw_dev) 887 { 888 unsigned int check_val; 889 unsigned int reg_val; 890 int ret, i; 891 892 for (i = 0; i < AW88395_DEV_SYSST_CHECK_MAX; i++) { 893 ret = regmap_read(aw_dev->regmap, AW88395_SYSST_REG, ®_val); 894 if (ret) 895 return ret; 896 897 check_val = reg_val & (~AW88395_BIT_SYSST_CHECK_MASK) 898 & AW88395_BIT_SYSST_CHECK; 899 if (check_val != AW88395_BIT_SYSST_CHECK) { 900 dev_err(aw_dev->dev, "check sysst fail, cnt=%d, reg_val=0x%04x, check:0x%x", 901 i, reg_val, AW88395_BIT_SYSST_CHECK); 902 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 903 } else { 904 return 0; 905 } 906 } 907 908 return -EPERM; 909 } 910 911 static int aw_dev_check_sysint(struct aw_device *aw_dev) 912 { 913 u16 reg_val; 914 915 aw_dev_get_int_status(aw_dev, ®_val); 916 917 if (reg_val & AW88395_BIT_SYSINT_CHECK) { 918 dev_err(aw_dev->dev, "pa stop check fail:0x%04x", reg_val); 919 return -EINVAL; 920 } 921 922 return 0; 923 } 924 925 static void aw_dev_get_cur_mode_st(struct aw_device *aw_dev) 926 { 927 struct aw_profctrl_desc *profctrl_desc = &aw_dev->profctrl_desc; 928 unsigned int reg_val; 929 int ret; 930 931 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val); 932 if (ret) { 933 dev_dbg(aw_dev->dev, "%s failed", __func__); 934 return; 935 } 936 if ((reg_val & (~AW88395_RCV_MODE_MASK)) == AW88395_RCV_MODE_RECEIVER_VALUE) 937 profctrl_desc->cur_mode = AW88395_RCV_MODE; 938 else 939 profctrl_desc->cur_mode = AW88395_NOT_RCV_MODE; 940 } 941 942 static void aw_dev_get_dsp_config(struct aw_device *aw_dev, unsigned char *dsp_cfg) 943 { 944 unsigned int reg_val = 0; 945 int ret; 946 947 ret = regmap_read(aw_dev->regmap, AW88395_SYSCTRL_REG, ®_val); 948 if (ret) { 949 dev_dbg(aw_dev->dev, "%s failed", __func__); 950 return; 951 } 952 if (reg_val & (~AW88395_DSPBY_MASK)) 953 *dsp_cfg = AW88395_DEV_DSP_BYPASS; 954 else 955 *dsp_cfg = AW88395_DEV_DSP_WORK; 956 } 957 958 static void aw_dev_select_memclk(struct aw_device *aw_dev, unsigned char flag) 959 { 960 int ret; 961 962 switch (flag) { 963 case AW88395_DEV_MEMCLK_PLL: 964 ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG, 965 ~AW88395_MEM_CLKSEL_MASK, 966 AW88395_MEM_CLKSEL_DAP_HCLK_VALUE); 967 if (ret) 968 dev_err(aw_dev->dev, "memclk select pll failed"); 969 break; 970 case AW88395_DEV_MEMCLK_OSC: 971 ret = regmap_update_bits(aw_dev->regmap, AW88395_DBGCTRL_REG, 972 ~AW88395_MEM_CLKSEL_MASK, 973 AW88395_MEM_CLKSEL_OSC_CLK_VALUE); 974 if (ret) 975 dev_err(aw_dev->dev, "memclk select OSC failed"); 976 break; 977 default: 978 dev_err(aw_dev->dev, "unknown memclk config, flag=0x%x", flag); 979 break; 980 } 981 } 982 983 static int aw_dev_get_dsp_status(struct aw_device *aw_dev) 984 { 985 unsigned int reg_val; 986 int ret; 987 988 ret = regmap_read(aw_dev->regmap, AW88395_WDT_REG, ®_val); 989 if (ret) 990 return ret; 991 if (!(reg_val & (~AW88395_WDT_CNT_MASK))) 992 ret = -EPERM; 993 994 return ret; 995 } 996 997 static int aw_dev_get_vmax(struct aw_device *aw_dev, unsigned int *vmax) 998 { 999 return aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_VMAX, vmax, AW88395_DSP_16_DATA); 1000 } 1001 1002 static int aw_dev_update_reg_container(struct aw_device *aw_dev, 1003 unsigned char *data, unsigned int len) 1004 { 1005 struct aw_volume_desc *vol_desc = &aw_dev->volume_desc; 1006 unsigned int read_val; 1007 int16_t *reg_data; 1008 int data_len; 1009 u16 read_vol; 1010 u16 reg_val; 1011 u8 reg_addr; 1012 int i, ret; 1013 1014 reg_data = (int16_t *)data; 1015 data_len = len >> 1; 1016 1017 if (data_len & 0x1) { 1018 dev_err(aw_dev->dev, "data len:%d unsupported", data_len); 1019 return -EINVAL; 1020 } 1021 1022 for (i = 0; i < data_len; i += 2) { 1023 reg_addr = reg_data[i]; 1024 reg_val = reg_data[i + 1]; 1025 1026 if (reg_addr == AW88395_SYSCTRL_REG) { 1027 ret = regmap_read(aw_dev->regmap, reg_addr, &read_val); 1028 if (ret) 1029 break; 1030 read_val &= (~AW88395_HMUTE_MASK); 1031 reg_val &= AW88395_HMUTE_MASK; 1032 reg_val |= read_val; 1033 } 1034 if (reg_addr == AW88395_HAGCCFG7_REG) 1035 reg_val &= AW88395_AGC_DSP_CTL_MASK; 1036 1037 if (reg_addr == AW88395_I2SCFG1_REG) { 1038 /* close tx */ 1039 reg_val &= AW88395_I2STXEN_MASK; 1040 reg_val |= AW88395_I2STXEN_DISABLE_VALUE; 1041 } 1042 1043 if (reg_addr == AW88395_SYSCTRL2_REG) { 1044 read_vol = (reg_val & (~AW88395_VOL_MASK)) >> 1045 AW88395_VOL_START_BIT; 1046 aw_dev->volume_desc.init_volume = 1047 reg_val_to_db(read_vol); 1048 } 1049 ret = regmap_write(aw_dev->regmap, reg_addr, reg_val); 1050 if (ret) 1051 break; 1052 1053 } 1054 1055 aw_dev_get_cur_mode_st(aw_dev); 1056 1057 if (aw_dev->prof_cur != aw_dev->prof_index) { 1058 /* clear control volume when PA change profile */ 1059 vol_desc->ctl_volume = 0; 1060 } else { 1061 /* keep control volume when PA start with sync mode */ 1062 aw_dev_set_volume(aw_dev, vol_desc->ctl_volume); 1063 } 1064 1065 /* keep min volume */ 1066 if (aw_dev->fade_en) 1067 aw_dev_set_volume(aw_dev, AW88395_MUTE_VOL); 1068 1069 aw_dev_get_dsp_config(aw_dev, &aw_dev->dsp_cfg); 1070 1071 return ret; 1072 } 1073 1074 static int aw_dev_reg_update(struct aw_device *aw_dev, 1075 unsigned char *data, unsigned int len) 1076 { 1077 int ret; 1078 1079 if (!len || !data) { 1080 dev_err(aw_dev->dev, "reg data is null or len is 0"); 1081 return -EINVAL; 1082 } 1083 1084 ret = aw_dev_update_reg_container(aw_dev, data, len); 1085 if (ret) { 1086 dev_err(aw_dev->dev, "reg update failed"); 1087 return ret; 1088 } 1089 1090 return 0; 1091 } 1092 1093 static int aw_dev_get_ra(struct aw_cali_desc *cali_desc) 1094 { 1095 struct aw_device *aw_dev = 1096 container_of(cali_desc, struct aw_device, cali_desc); 1097 u32 dsp_ra; 1098 int ret; 1099 1100 ret = aw_dev_dsp_read(aw_dev, AW88395_DSP_REG_CFG_ADPZ_RA, 1101 &dsp_ra, AW88395_DSP_32_DATA); 1102 if (ret) { 1103 dev_err(aw_dev->dev, "read ra error"); 1104 return ret; 1105 } 1106 1107 cali_desc->ra = AW88395_DSP_RE_TO_SHOW_RE(dsp_ra, 1108 AW88395_DSP_RE_SHIFT); 1109 1110 return ret; 1111 } 1112 1113 static int aw_dev_dsp_update_container(struct aw_device *aw_dev, 1114 unsigned char *data, unsigned int len, unsigned short base) 1115 { 1116 int i, ret; 1117 1118 #ifdef AW88395_DSP_I2C_WRITES 1119 u32 tmp_len; 1120 1121 mutex_lock(&aw_dev->dsp_lock); 1122 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base); 1123 if (ret) 1124 goto error_operation; 1125 1126 for (i = 0; i < len; i += AW88395_MAX_RAM_WRITE_BYTE_SIZE) { 1127 if ((len - i) < AW88395_MAX_RAM_WRITE_BYTE_SIZE) 1128 tmp_len = len - i; 1129 else 1130 tmp_len = AW88395_MAX_RAM_WRITE_BYTE_SIZE; 1131 1132 ret = regmap_raw_write(aw_dev->regmap, AW88395_DSPMDAT_REG, 1133 &data[i], tmp_len); 1134 if (ret) 1135 goto error_operation; 1136 } 1137 mutex_unlock(&aw_dev->dsp_lock); 1138 #else 1139 __be16 reg_val; 1140 1141 mutex_lock(&aw_dev->dsp_lock); 1142 /* i2c write */ 1143 ret = regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, base); 1144 if (ret) 1145 goto error_operation; 1146 for (i = 0; i < len; i += 2) { 1147 reg_val = cpu_to_be16p((u16 *)(data + i)); 1148 ret = regmap_write(aw_dev->regmap, AW88395_DSPMDAT_REG, 1149 (u16)reg_val); 1150 if (ret) 1151 goto error_operation; 1152 } 1153 mutex_unlock(&aw_dev->dsp_lock); 1154 #endif 1155 1156 return 0; 1157 1158 error_operation: 1159 mutex_unlock(&aw_dev->dsp_lock); 1160 return ret; 1161 } 1162 1163 static int aw_dev_dsp_update_fw(struct aw_device *aw_dev, 1164 unsigned char *data, unsigned int len) 1165 { 1166 1167 dev_dbg(aw_dev->dev, "dsp firmware len:%d", len); 1168 1169 if (!len || !data) { 1170 dev_err(aw_dev->dev, "dsp firmware data is null or len is 0"); 1171 return -EINVAL; 1172 } 1173 aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_FW_ADDR); 1174 aw_dev->dsp_fw_len = len; 1175 1176 return 0; 1177 } 1178 1179 static int aw_dev_copy_to_crc_dsp_cfg(struct aw_device *aw_dev, 1180 unsigned char *data, unsigned int size) 1181 { 1182 struct aw_sec_data_desc *crc_dsp_cfg = &aw_dev->crc_dsp_cfg; 1183 1184 if (!crc_dsp_cfg->data) { 1185 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL); 1186 if (!crc_dsp_cfg->data) 1187 return -ENOMEM; 1188 crc_dsp_cfg->len = size; 1189 } else if (crc_dsp_cfg->len < size) { 1190 devm_kfree(aw_dev->dev, crc_dsp_cfg->data); 1191 crc_dsp_cfg->data = devm_kzalloc(aw_dev->dev, size, GFP_KERNEL); 1192 if (!crc_dsp_cfg->data) 1193 return -ENOMEM; 1194 crc_dsp_cfg->len = size; 1195 } 1196 memcpy(crc_dsp_cfg->data, data, size); 1197 swab16_array((u16 *)crc_dsp_cfg->data, size >> 1); 1198 1199 return 0; 1200 } 1201 1202 static int aw_dev_dsp_update_cfg(struct aw_device *aw_dev, 1203 unsigned char *data, unsigned int len) 1204 { 1205 int ret; 1206 1207 dev_dbg(aw_dev->dev, "dsp config len:%d", len); 1208 1209 if (!len || !data) { 1210 dev_err(aw_dev->dev, "dsp config data is null or len is 0"); 1211 return -EINVAL; 1212 } 1213 1214 aw_dev_dsp_update_container(aw_dev, data, len, AW88395_DSP_CFG_ADDR); 1215 aw_dev->dsp_cfg_len = len; 1216 1217 ret = aw_dev_copy_to_crc_dsp_cfg(aw_dev, data, len); 1218 if (ret) 1219 return ret; 1220 1221 ret = aw_dev_set_vcalb(aw_dev); 1222 if (ret) 1223 return ret; 1224 ret = aw_dev_get_ra(&aw_dev->cali_desc); 1225 if (ret) 1226 return ret; 1227 ret = aw_dev_get_cali_f0_delay(aw_dev); 1228 if (ret) 1229 return ret; 1230 1231 ret = aw_dev_get_vmax(aw_dev, &aw_dev->vmax_desc.init_vmax); 1232 if (ret) { 1233 dev_err(aw_dev->dev, "get vmax failed"); 1234 return ret; 1235 } 1236 dev_dbg(aw_dev->dev, "get init vmax:0x%x", aw_dev->vmax_desc.init_vmax); 1237 aw_dev->dsp_crc_st = AW88395_DSP_CRC_NA; 1238 1239 return 0; 1240 } 1241 1242 static int aw_dev_check_sram(struct aw_device *aw_dev) 1243 { 1244 unsigned int reg_val; 1245 1246 mutex_lock(&aw_dev->dsp_lock); 1247 /* check the odd bits of reg 0x40 */ 1248 regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_ODD_NUM_BIT_TEST); 1249 regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val); 1250 if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) { 1251 dev_err(aw_dev->dev, "check reg 0x40 odd bit failed, read[0x%x] != write[0x%x]", 1252 reg_val, AW88395_DSP_ODD_NUM_BIT_TEST); 1253 goto error; 1254 } 1255 1256 /* check the even bits of reg 0x40 */ 1257 regmap_write(aw_dev->regmap, AW88395_DSPMADD_REG, AW88395_DSP_EVEN_NUM_BIT_TEST); 1258 regmap_read(aw_dev->regmap, AW88395_DSPMADD_REG, ®_val); 1259 if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) { 1260 dev_err(aw_dev->dev, "check reg 0x40 even bit failed, read[0x%x] != write[0x%x]", 1261 reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST); 1262 goto error; 1263 } 1264 1265 /* check dsp_fw_base_addr */ 1266 aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_FW_ADDR, AW88395_DSP_EVEN_NUM_BIT_TEST); 1267 aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_FW_ADDR, ®_val); 1268 if (reg_val != AW88395_DSP_EVEN_NUM_BIT_TEST) { 1269 dev_err(aw_dev->dev, "check dsp fw addr failed, read[0x%x] != write[0x%x]", 1270 reg_val, AW88395_DSP_EVEN_NUM_BIT_TEST); 1271 goto error; 1272 } 1273 1274 /* check dsp_cfg_base_addr */ 1275 aw_dev_dsp_write_16bit(aw_dev, AW88395_DSP_CFG_ADDR, AW88395_DSP_ODD_NUM_BIT_TEST); 1276 aw_dev_dsp_read_16bit(aw_dev, AW88395_DSP_CFG_ADDR, ®_val); 1277 if (reg_val != AW88395_DSP_ODD_NUM_BIT_TEST) { 1278 dev_err(aw_dev->dev, "check dsp cfg failed, read[0x%x] != write[0x%x]", 1279 reg_val, AW88395_DSP_ODD_NUM_BIT_TEST); 1280 goto error; 1281 } 1282 mutex_unlock(&aw_dev->dsp_lock); 1283 1284 return 0; 1285 1286 error: 1287 mutex_unlock(&aw_dev->dsp_lock); 1288 return -EPERM; 1289 } 1290 1291 int aw88395_dev_fw_update(struct aw_device *aw_dev, bool up_dsp_fw_en, bool force_up_en) 1292 { 1293 struct aw_prof_desc *prof_index_desc; 1294 struct aw_sec_data_desc *sec_desc; 1295 char *prof_name; 1296 int ret; 1297 1298 if ((aw_dev->prof_cur == aw_dev->prof_index) && 1299 (force_up_en == AW88395_FORCE_UPDATE_OFF)) { 1300 dev_dbg(aw_dev->dev, "scene no change, not update"); 1301 return 0; 1302 } 1303 1304 if (aw_dev->fw_status == AW88395_DEV_FW_FAILED) { 1305 dev_err(aw_dev->dev, "fw status[%d] error", aw_dev->fw_status); 1306 return -EPERM; 1307 } 1308 1309 prof_name = aw88395_dev_get_prof_name(aw_dev, aw_dev->prof_index); 1310 1311 dev_dbg(aw_dev->dev, "start update %s", prof_name); 1312 1313 ret = aw88395_dev_get_prof_data(aw_dev, aw_dev->prof_index, &prof_index_desc); 1314 if (ret) 1315 return ret; 1316 1317 /* update reg */ 1318 sec_desc = prof_index_desc->sec_desc; 1319 ret = aw_dev_reg_update(aw_dev, sec_desc[AW88395_DATA_TYPE_REG].data, 1320 sec_desc[AW88395_DATA_TYPE_REG].len); 1321 if (ret) { 1322 dev_err(aw_dev->dev, "update reg failed"); 1323 return ret; 1324 } 1325 1326 aw88395_dev_mute(aw_dev, true); 1327 1328 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK) 1329 aw_dev_dsp_enable(aw_dev, false); 1330 1331 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC); 1332 1333 if (up_dsp_fw_en) { 1334 ret = aw_dev_check_sram(aw_dev); 1335 if (ret) { 1336 dev_err(aw_dev->dev, "check sram failed"); 1337 goto error; 1338 } 1339 1340 /* update dsp firmware */ 1341 dev_dbg(aw_dev->dev, "fw_ver: [%x]", prof_index_desc->fw_ver); 1342 ret = aw_dev_dsp_update_fw(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_FW].data, 1343 sec_desc[AW88395_DATA_TYPE_DSP_FW].len); 1344 if (ret) { 1345 dev_err(aw_dev->dev, "update dsp fw failed"); 1346 goto error; 1347 } 1348 } 1349 1350 /* update dsp config */ 1351 ret = aw_dev_dsp_update_cfg(aw_dev, sec_desc[AW88395_DATA_TYPE_DSP_CFG].data, 1352 sec_desc[AW88395_DATA_TYPE_DSP_CFG].len); 1353 if (ret) { 1354 dev_err(aw_dev->dev, "update dsp cfg failed"); 1355 goto error; 1356 } 1357 1358 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL); 1359 1360 aw_dev->prof_cur = aw_dev->prof_index; 1361 1362 return 0; 1363 1364 error: 1365 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL); 1366 return ret; 1367 } 1368 EXPORT_SYMBOL_GPL(aw88395_dev_fw_update); 1369 1370 static int aw_dev_dsp_check(struct aw_device *aw_dev) 1371 { 1372 int ret, i; 1373 1374 switch (aw_dev->dsp_cfg) { 1375 case AW88395_DEV_DSP_BYPASS: 1376 dev_dbg(aw_dev->dev, "dsp bypass"); 1377 ret = 0; 1378 break; 1379 case AW88395_DEV_DSP_WORK: 1380 aw_dev_dsp_enable(aw_dev, false); 1381 aw_dev_dsp_enable(aw_dev, true); 1382 usleep_range(AW88395_1000_US, AW88395_1000_US + 10); 1383 for (i = 0; i < AW88395_DEV_DSP_CHECK_MAX; i++) { 1384 ret = aw_dev_get_dsp_status(aw_dev); 1385 if (ret) { 1386 dev_err(aw_dev->dev, "dsp wdt status error=%d", ret); 1387 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 1388 } 1389 } 1390 break; 1391 default: 1392 dev_err(aw_dev->dev, "unknown dsp cfg=%d", aw_dev->dsp_cfg); 1393 ret = -EINVAL; 1394 break; 1395 } 1396 1397 return ret; 1398 } 1399 1400 static void aw_dev_update_cali_re(struct aw_cali_desc *cali_desc) 1401 { 1402 struct aw_device *aw_dev = 1403 container_of(cali_desc, struct aw_device, cali_desc); 1404 int ret; 1405 1406 if ((aw_dev->cali_desc.cali_re < AW88395_CALI_RE_MAX) && 1407 (aw_dev->cali_desc.cali_re > AW88395_CALI_RE_MIN)) { 1408 1409 ret = aw_dev_dsp_set_cali_re(aw_dev); 1410 if (ret) 1411 dev_err(aw_dev->dev, "set cali re failed"); 1412 } 1413 } 1414 1415 int aw88395_dev_start(struct aw_device *aw_dev) 1416 { 1417 int ret; 1418 1419 if (aw_dev->status == AW88395_DEV_PW_ON) { 1420 dev_info(aw_dev->dev, "already power on"); 1421 return 0; 1422 } 1423 /* power on */ 1424 aw_dev_pwd(aw_dev, false); 1425 usleep_range(AW88395_2000_US, AW88395_2000_US + 10); 1426 1427 ret = aw_dev_check_syspll(aw_dev); 1428 if (ret) { 1429 dev_err(aw_dev->dev, "pll check failed cannot start"); 1430 goto pll_check_fail; 1431 } 1432 1433 /* amppd on */ 1434 aw_dev_amppd(aw_dev, false); 1435 usleep_range(AW88395_1000_US, AW88395_1000_US + 50); 1436 1437 /* check i2s status */ 1438 ret = aw_dev_check_sysst(aw_dev); 1439 if (ret) { 1440 dev_err(aw_dev->dev, "sysst check failed"); 1441 goto sysst_check_fail; 1442 } 1443 1444 if (aw_dev->dsp_cfg == AW88395_DEV_DSP_WORK) { 1445 /* dsp bypass */ 1446 aw_dev_dsp_enable(aw_dev, false); 1447 ret = aw_dev_dsp_fw_check(aw_dev); 1448 if (ret) 1449 goto dev_dsp_fw_check_fail; 1450 1451 aw_dev_update_cali_re(&aw_dev->cali_desc); 1452 1453 if (aw_dev->dsp_crc_st != AW88395_DSP_CRC_OK) { 1454 ret = aw_dev_dsp_check_crc32(aw_dev); 1455 if (ret) { 1456 dev_err(aw_dev->dev, "dsp crc check failed"); 1457 goto crc_check_fail; 1458 } 1459 } 1460 1461 ret = aw_dev_dsp_check(aw_dev); 1462 if (ret) { 1463 dev_err(aw_dev->dev, "dsp status check failed"); 1464 goto dsp_check_fail; 1465 } 1466 } else { 1467 dev_dbg(aw_dev->dev, "start pa with dsp bypass"); 1468 } 1469 1470 /* enable tx feedback */ 1471 aw_dev_i2s_tx_enable(aw_dev, true); 1472 1473 /* close mute */ 1474 aw88395_dev_mute(aw_dev, false); 1475 /* clear inturrupt */ 1476 aw_dev_clear_int_status(aw_dev); 1477 aw_dev->status = AW88395_DEV_PW_ON; 1478 1479 return 0; 1480 1481 dsp_check_fail: 1482 crc_check_fail: 1483 aw_dev_dsp_enable(aw_dev, false); 1484 dev_dsp_fw_check_fail: 1485 sysst_check_fail: 1486 aw_dev_clear_int_status(aw_dev); 1487 aw_dev_amppd(aw_dev, true); 1488 pll_check_fail: 1489 aw_dev_pwd(aw_dev, true); 1490 aw_dev->status = AW88395_DEV_PW_OFF; 1491 1492 return ret; 1493 } 1494 EXPORT_SYMBOL_GPL(aw88395_dev_start); 1495 1496 int aw88395_dev_stop(struct aw_device *aw_dev) 1497 { 1498 struct aw_sec_data_desc *dsp_cfg = 1499 &aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_CFG]; 1500 struct aw_sec_data_desc *dsp_fw = 1501 &aw_dev->prof_info.prof_desc[aw_dev->prof_cur].sec_desc[AW88395_DATA_TYPE_DSP_FW]; 1502 int int_st = 0; 1503 int ret; 1504 1505 if (aw_dev->status == AW88395_DEV_PW_OFF) { 1506 dev_info(aw_dev->dev, "already power off"); 1507 return 0; 1508 } 1509 1510 aw_dev->status = AW88395_DEV_PW_OFF; 1511 1512 /* set mute */ 1513 aw88395_dev_mute(aw_dev, true); 1514 usleep_range(AW88395_4000_US, AW88395_4000_US + 100); 1515 1516 /* close tx feedback */ 1517 aw_dev_i2s_tx_enable(aw_dev, false); 1518 usleep_range(AW88395_1000_US, AW88395_1000_US + 100); 1519 1520 /* check sysint state */ 1521 int_st = aw_dev_check_sysint(aw_dev); 1522 1523 /* close dsp */ 1524 aw_dev_dsp_enable(aw_dev, false); 1525 1526 /* enable amppd */ 1527 aw_dev_amppd(aw_dev, true); 1528 1529 if (int_st < 0) { 1530 /* system status anomaly */ 1531 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_OSC); 1532 ret = aw_dev_dsp_update_fw(aw_dev, dsp_fw->data, dsp_fw->len); 1533 if (ret) 1534 dev_err(aw_dev->dev, "update dsp fw failed"); 1535 ret = aw_dev_dsp_update_cfg(aw_dev, dsp_cfg->data, dsp_cfg->len); 1536 if (ret) 1537 dev_err(aw_dev->dev, "update dsp cfg failed"); 1538 aw_dev_select_memclk(aw_dev, AW88395_DEV_MEMCLK_PLL); 1539 } 1540 1541 /* set power down */ 1542 aw_dev_pwd(aw_dev, true); 1543 1544 return 0; 1545 } 1546 EXPORT_SYMBOL_GPL(aw88395_dev_stop); 1547 1548 int aw88395_dev_init(struct aw_device *aw_dev, struct aw_container *aw_cfg) 1549 { 1550 int ret; 1551 1552 if ((!aw_dev) || (!aw_cfg)) { 1553 pr_err("aw_dev is NULL or aw_cfg is NULL"); 1554 return -ENOMEM; 1555 } 1556 ret = aw88395_dev_cfg_load(aw_dev, aw_cfg); 1557 if (ret) { 1558 dev_err(aw_dev->dev, "aw_dev acf parse failed"); 1559 return -EINVAL; 1560 } 1561 aw_dev->fade_in_time = AW88395_1000_US / 10; 1562 aw_dev->fade_out_time = AW88395_1000_US >> 1; 1563 aw_dev->prof_cur = aw_dev->prof_info.prof_desc[0].id; 1564 aw_dev->prof_index = aw_dev->prof_info.prof_desc[0].id; 1565 1566 ret = aw88395_dev_fw_update(aw_dev, AW88395_FORCE_UPDATE_ON, AW88395_DSP_FW_UPDATE_ON); 1567 if (ret) { 1568 dev_err(aw_dev->dev, "fw update failed ret = %d\n", ret); 1569 return ret; 1570 } 1571 1572 /* set mute */ 1573 aw88395_dev_mute(aw_dev, true); 1574 usleep_range(AW88395_4000_US, AW88395_4000_US + 100); 1575 1576 /* close tx feedback */ 1577 aw_dev_i2s_tx_enable(aw_dev, false); 1578 usleep_range(AW88395_1000_US, AW88395_1000_US + 100); 1579 1580 /* close dsp */ 1581 aw_dev_dsp_enable(aw_dev, false); 1582 /* enable amppd */ 1583 aw_dev_amppd(aw_dev, true); 1584 /* set power down */ 1585 aw_dev_pwd(aw_dev, true); 1586 1587 return 0; 1588 } 1589 EXPORT_SYMBOL_GPL(aw88395_dev_init); 1590 1591 static void aw88395_parse_channel_dt(struct aw_device *aw_dev) 1592 { 1593 struct device_node *np = aw_dev->dev->of_node; 1594 u32 channel_value; 1595 int ret; 1596 1597 ret = of_property_read_u32(np, "sound-channel", &channel_value); 1598 if (ret) { 1599 dev_dbg(aw_dev->dev, 1600 "read sound-channel failed,use default 0"); 1601 aw_dev->channel = AW88395_DEV_DEFAULT_CH; 1602 return; 1603 } 1604 1605 dev_dbg(aw_dev->dev, "read sound-channel value is: %d", 1606 channel_value); 1607 aw_dev->channel = channel_value; 1608 } 1609 1610 static void aw88395_parse_fade_enable_dt(struct aw_device *aw_dev) 1611 { 1612 struct device_node *np = aw_dev->dev->of_node; 1613 u32 fade_en; 1614 int ret; 1615 1616 ret = of_property_read_u32(np, "fade-enable", &fade_en); 1617 if (ret) { 1618 dev_dbg(aw_dev->dev, 1619 "read fade-enable failed, close fade_in_out"); 1620 fade_en = AW88395_FADE_IN_OUT_DEFAULT; 1621 } 1622 1623 dev_dbg(aw_dev->dev, "read fade-enable value is: %d", fade_en); 1624 1625 aw_dev->fade_en = fade_en; 1626 } 1627 1628 static int aw_dev_init(struct aw_device *aw_dev) 1629 { 1630 aw_dev->chip_id = AW88395_CHIP_ID; 1631 /* call aw device init func */ 1632 aw_dev->acf = NULL; 1633 aw_dev->prof_info.prof_desc = NULL; 1634 aw_dev->prof_info.count = 0; 1635 aw_dev->prof_info.prof_type = AW88395_DEV_NONE_TYPE_ID; 1636 aw_dev->channel = 0; 1637 aw_dev->fw_status = AW88395_DEV_FW_FAILED; 1638 1639 aw_dev->fade_step = AW88395_VOLUME_STEP_DB; 1640 aw_dev->volume_desc.ctl_volume = AW88395_VOL_DEFAULT_VALUE; 1641 aw88395_parse_channel_dt(aw_dev); 1642 aw88395_parse_fade_enable_dt(aw_dev); 1643 1644 return 0; 1645 } 1646 1647 int aw88395_dev_get_profile_count(struct aw_device *aw_dev) 1648 { 1649 return aw_dev->prof_info.count; 1650 } 1651 EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_count); 1652 1653 int aw88395_dev_get_profile_index(struct aw_device *aw_dev) 1654 { 1655 return aw_dev->prof_index; 1656 } 1657 EXPORT_SYMBOL_GPL(aw88395_dev_get_profile_index); 1658 1659 int aw88395_dev_set_profile_index(struct aw_device *aw_dev, int index) 1660 { 1661 /* check the index whether is valid */ 1662 if ((index >= aw_dev->prof_info.count) || (index < 0)) 1663 return -EINVAL; 1664 /* check the index whether change */ 1665 if (aw_dev->prof_index == index) 1666 return -EINVAL; 1667 1668 aw_dev->prof_index = index; 1669 dev_dbg(aw_dev->dev, "set prof[%s]", 1670 aw_dev->prof_info.prof_name_list[aw_dev->prof_info.prof_desc[index].id]); 1671 1672 return 0; 1673 } 1674 EXPORT_SYMBOL_GPL(aw88395_dev_set_profile_index); 1675 1676 char *aw88395_dev_get_prof_name(struct aw_device *aw_dev, int index) 1677 { 1678 struct aw_prof_info *prof_info = &aw_dev->prof_info; 1679 struct aw_prof_desc *prof_desc; 1680 1681 if ((index >= aw_dev->prof_info.count) || (index < 0)) { 1682 dev_err(aw_dev->dev, "index[%d] overflow count[%d]", 1683 index, aw_dev->prof_info.count); 1684 return NULL; 1685 } 1686 1687 prof_desc = &aw_dev->prof_info.prof_desc[index]; 1688 1689 return prof_info->prof_name_list[prof_desc->id]; 1690 } 1691 EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_name); 1692 1693 int aw88395_dev_get_prof_data(struct aw_device *aw_dev, int index, 1694 struct aw_prof_desc **prof_desc) 1695 { 1696 if ((index >= aw_dev->prof_info.count) || (index < 0)) { 1697 dev_err(aw_dev->dev, "%s: index[%d] overflow count[%d]\n", 1698 __func__, index, aw_dev->prof_info.count); 1699 return -EINVAL; 1700 } 1701 1702 *prof_desc = &aw_dev->prof_info.prof_desc[index]; 1703 1704 return 0; 1705 } 1706 EXPORT_SYMBOL_GPL(aw88395_dev_get_prof_data); 1707 1708 int aw88395_init(struct aw_device **aw_dev, struct i2c_client *i2c, struct regmap *regmap) 1709 { 1710 u16 chip_id; 1711 int ret; 1712 1713 if (*aw_dev) { 1714 dev_info(&i2c->dev, "it should be initialized here.\n"); 1715 } else { 1716 *aw_dev = devm_kzalloc(&i2c->dev, sizeof(struct aw_device), GFP_KERNEL); 1717 if (!(*aw_dev)) 1718 return -ENOMEM; 1719 } 1720 1721 (*aw_dev)->i2c = i2c; 1722 (*aw_dev)->dev = &i2c->dev; 1723 (*aw_dev)->regmap = regmap; 1724 mutex_init(&(*aw_dev)->dsp_lock); 1725 1726 /* read chip id */ 1727 ret = aw_dev_read_chipid((*aw_dev), &chip_id); 1728 if (ret) { 1729 dev_err(&i2c->dev, "dev_read_chipid failed ret=%d", ret); 1730 return ret; 1731 } 1732 1733 switch (chip_id) { 1734 case AW88395_CHIP_ID: 1735 ret = aw_dev_init((*aw_dev)); 1736 break; 1737 default: 1738 ret = -EINVAL; 1739 dev_err((*aw_dev)->dev, "unsupported device"); 1740 break; 1741 } 1742 1743 return ret; 1744 } 1745 EXPORT_SYMBOL_GPL(aw88395_init); 1746 1747 MODULE_DESCRIPTION("AW88395 device lib"); 1748 MODULE_LICENSE("GPL v2"); 1749