1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 294d5f7c0SLeon Romanovsky /* 394d5f7c0SLeon Romanovsky * alc5632.h -- ALC5632 ALSA SoC Audio Codec 494d5f7c0SLeon Romanovsky * 594d5f7c0SLeon Romanovsky * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net> 694d5f7c0SLeon Romanovsky * 794d5f7c0SLeon Romanovsky * Authors: Leon Romanovsky <leon@leon.nu> 894d5f7c0SLeon Romanovsky * Andrey Danin <danindrey@mail.ru> 994d5f7c0SLeon Romanovsky * Ilya Petrov <ilya.muromec@gmail.com> 1094d5f7c0SLeon Romanovsky * Marc Dietrich <marvin24@gmx.de> 1194d5f7c0SLeon Romanovsky * 1294d5f7c0SLeon Romanovsky * Based on alc5623.h by Arnaud Patard 1394d5f7c0SLeon Romanovsky */ 1494d5f7c0SLeon Romanovsky 1594d5f7c0SLeon Romanovsky #ifndef _ALC5632_H 1694d5f7c0SLeon Romanovsky #define _ALC5632_H 1794d5f7c0SLeon Romanovsky 1894d5f7c0SLeon Romanovsky #define ALC5632_RESET 0x00 1994d5f7c0SLeon Romanovsky /* speaker output vol 2 2 */ 2094d5f7c0SLeon Romanovsky /* line output vol 4 2 */ 2194d5f7c0SLeon Romanovsky /* HP output vol 4 0 4 */ 2294d5f7c0SLeon Romanovsky #define ALC5632_SPK_OUT_VOL 0x02 /* spe out vol */ 2394d5f7c0SLeon Romanovsky #define ALC5632_SPK_OUT_VOL_STEP 1.5 2494d5f7c0SLeon Romanovsky #define ALC5632_HP_OUT_VOL 0x04 /* hp out vol */ 2594d5f7c0SLeon Romanovsky #define ALC5632_AUX_OUT_VOL 0x06 /* aux out vol */ 2694d5f7c0SLeon Romanovsky #define ALC5632_PHONE_IN_VOL 0x08 /* phone in vol */ 2794d5f7c0SLeon Romanovsky #define ALC5632_LINE_IN_VOL 0x0A /* line in vol */ 2894d5f7c0SLeon Romanovsky #define ALC5632_STEREO_DAC_IN_VOL 0x0C /* stereo dac in vol */ 2994d5f7c0SLeon Romanovsky #define ALC5632_MIC_VOL 0x0E /* mic in vol */ 3094d5f7c0SLeon Romanovsky /* stero dac/mic routing */ 3194d5f7c0SLeon Romanovsky #define ALC5632_MIC_ROUTING_CTRL 0x10 3294d5f7c0SLeon Romanovsky #define ALC5632_MIC_ROUTE_MONOMIX (1 << 0) 3394d5f7c0SLeon Romanovsky #define ALC5632_MIC_ROUTE_SPK (1 << 1) 3494d5f7c0SLeon Romanovsky #define ALC5632_MIC_ROUTE_HP (1 << 2) 3594d5f7c0SLeon Romanovsky 3694d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_GAIN 0x12 /* rec gain */ 3794d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_GAIN_RANGE 0x1F1F 3894d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_GAIN_BASE (-16.5) 3994d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_GAIN_STEP 1.5 4094d5f7c0SLeon Romanovsky 4194d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_MIXER 0x14 /* mixer control */ 4294d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_MIC1 (1 << 6) 4394d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_MIC2 (1 << 5) 4494d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_LINE_IN (1 << 4) 4594d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_AUX (1 << 3) 4694d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_HP (1 << 2) 4794d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_SPK (1 << 1) 4894d5f7c0SLeon Romanovsky #define ALC5632_ADC_REC_MONOMIX (1 << 0) 4994d5f7c0SLeon Romanovsky 5094d5f7c0SLeon Romanovsky #define ALC5632_VOICE_DAC_VOL 0x18 /* voice dac vol */ 5175b3566fSAndrey Danin #define ALC5632_I2S_OUT_CTL 0x1A /* undocumented reg. found in path scheme */ 5294d5f7c0SLeon Romanovsky /* ALC5632_OUTPUT_MIXER_CTRL : */ 5394d5f7c0SLeon Romanovsky /* same remark as for reg 2 line vs speaker */ 5494d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_CTRL 0x1C /* out mix ctrl */ 5594d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_RP (1 << 14) 5694d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_WEEK (1 << 12) 5794d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_HP (1 << 10) 5894d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_AUX_SPK (2 << 6) 5994d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_AUX_HP_LR (1 << 6) 6094d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_HP_R (1 << 8) 6194d5f7c0SLeon Romanovsky #define ALC5632_OUTPUT_MIXER_HP_L (1 << 9) 6294d5f7c0SLeon Romanovsky 6394d5f7c0SLeon Romanovsky #define ALC5632_MIC_CTRL 0x22 /* mic phone ctrl */ 6494d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_BYPASS 0 6594d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_20DB 1 6694d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_30DB 2 6794d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_40DB 3 6894d5f7c0SLeon Romanovsky 6994d5f7c0SLeon Romanovsky #define ALC5632_DIGI_BOOST_CTRL 0x24 /* digi mic / bost ctl */ 7094d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_RANGE 7 7194d5f7c0SLeon Romanovsky #define ALC5632_MIC_BOOST_STEP 6 7294d5f7c0SLeon Romanovsky #define ALC5632_PWR_DOWN_CTRL_STATUS 0x26 7394d5f7c0SLeon Romanovsky #define ALC5632_PWR_DOWN_CTRL_STATUS_MASK 0xEF00 7494d5f7c0SLeon Romanovsky #define ALC5632_PWR_VREF_PR3 (1 << 11) 7594d5f7c0SLeon Romanovsky #define ALC5632_PWR_VREF_PR2 (1 << 10) 7694d5f7c0SLeon Romanovsky #define ALC5632_PWR_VREF_STATUS (1 << 3) 7794d5f7c0SLeon Romanovsky #define ALC5632_PWR_AMIX_STATUS (1 << 2) 7894d5f7c0SLeon Romanovsky #define ALC5632_PWR_DAC_STATUS (1 << 1) 7994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADC_STATUS (1 << 0) 8094d5f7c0SLeon Romanovsky /* stereo/voice DAC / stereo adc func ctrl */ 8194d5f7c0SLeon Romanovsky #define ALC5632_DAC_FUNC_SELECT 0x2E 8294d5f7c0SLeon Romanovsky 8394d5f7c0SLeon Romanovsky /* Main serial data port ctrl (i2s) */ 8494d5f7c0SLeon Romanovsky #define ALC5632_DAI_CONTROL 0x34 8594d5f7c0SLeon Romanovsky 8694d5f7c0SLeon Romanovsky #define ALC5632_DAI_SDP_MASTER_MODE (0 << 15) 8794d5f7c0SLeon Romanovsky #define ALC5632_DAI_SDP_SLAVE_MODE (1 << 15) 8894d5f7c0SLeon Romanovsky #define ALC5632_DAI_SADLRCK_MODE (1 << 14) 8994d5f7c0SLeon Romanovsky /* 0:voice, 1:main */ 9094d5f7c0SLeon Romanovsky #define ALC5632_DAI_MAIN_I2S_SYSCLK_SEL (1 << 8) 9194d5f7c0SLeon Romanovsky #define ALC5632_DAI_MAIN_I2S_BCLK_POL_CTRL (1 << 7) 9294d5f7c0SLeon Romanovsky /* 0:normal, 1:invert */ 9394d5f7c0SLeon Romanovsky #define ALC5632_DAI_MAIN_I2S_LRCK_INV (1 << 6) 9494d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DL_MASK (3 << 2) 9594d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DL_8 (3 << 2) 9694d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DL_24 (2 << 2) 9794d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DL_20 (1 << 2) 9894d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DL_16 (0 << 2) 9994d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DF_MASK (3 << 0) 10094d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DF_PCM_B (3 << 0) 10194d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DF_PCM_A (2 << 0) 10294d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DF_LEFT (1 << 0) 10394d5f7c0SLeon Romanovsky #define ALC5632_DAI_I2S_DF_I2S (0 << 0) 10494d5f7c0SLeon Romanovsky /* extend serial data port control (VoDAC_i2c/pcm) */ 10594d5f7c0SLeon Romanovsky #define ALC5632_DAI_CONTROL2 0x36 10694d5f7c0SLeon Romanovsky /* 0:gpio func, 1:voice pcm */ 10794d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_PCM_ENABLE (1 << 15) 10894d5f7c0SLeon Romanovsky /* 0:master, 1:slave */ 10994d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_MODE_SEL (1 << 14) 11094d5f7c0SLeon Romanovsky /* 0:disable, 1:enable */ 11194d5f7c0SLeon Romanovsky #define ALC5632_DAI_HPF_CLK_CTRL (1 << 13) 11294d5f7c0SLeon Romanovsky /* 0:main, 1:voice */ 11394d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_I2S_SYSCLK_SEL (1 << 8) 11494d5f7c0SLeon Romanovsky /* 0:normal, 1:invert */ 11594d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_VBCLK_SYSCLK_SEL (1 << 7) 11694d5f7c0SLeon Romanovsky /* 0:normal, 1:invert */ 11794d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_I2S_LR_INV (1 << 6) 11894d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DL_MASK (3 << 2) 11994d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DL_16 (0 << 2) 12094d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DL_20 (1 << 2) 12194d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DL_24 (2 << 2) 12294d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DL_8 (3 << 2) 12394d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DF_MASK (3 << 0) 12494d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DF_I2S (0 << 0) 12594d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DF_LEFT (1 << 0) 12694d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DF_PCM_A (2 << 0) 12794d5f7c0SLeon Romanovsky #define ALC5632_DAI_VOICE_DF_PCM_B (3 << 0) 12894d5f7c0SLeon Romanovsky 12994d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD1 0x3A 13094d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD1_MASK 0xEFFF 13194d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_DAC_L_EN (1 << 15) 13294d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_DAC_R_EN (1 << 14) 13394d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_ZERO_CROSS (1 << 13) 13494d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MAIN_I2S_EN (1 << 11) 13594d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_SPK_AMP_EN (1 << 10) 13694d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_HP_OUT_AMP (1 << 9) 13794d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_HP_OUT_ENH_AMP (1 << 8) 13894d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_VOICE_DAC_MIX (1 << 7) 13994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_SOFTGEN_EN (1 << 6) 14094d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MIC1_SHORT_CURR (1 << 5) 14194d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MIC2_SHORT_CURR (1 << 4) 14294d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MIC1_EN (1 << 3) 14394d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MIC2_EN (1 << 2) 14494d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_MAIN_BIAS (1 << 1) 14594d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD1_DAC_REF (1 << 0) 14694d5f7c0SLeon Romanovsky 14794d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD2 0x3C 14894d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD2_MASK 0x7FFF 14994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_PLL1 (1 << 15) 15094d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_PLL2 (1 << 14) 15194d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_VREF (1 << 13) 15294d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_OVT_DET (1 << 12) 15394d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_VOICE_DAC (1 << 10) 15494d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_L_DAC_CLK (1 << 9) 15594d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_R_DAC_CLK (1 << 8) 15694d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_L_ADC_CLK_GAIN (1 << 7) 15794d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_R_ADC_CLK_GAIN (1 << 6) 15894d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_L_HP_MIXER (1 << 5) 15994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_R_HP_MIXER (1 << 4) 16094d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_SPK_MIXER (1 << 3) 16194d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_MONO_MIXER (1 << 2) 16294d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_L_ADC_REC_MIXER (1 << 1) 16394d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD2_R_ADC_REC_MIXER (1 << 0) 16494d5f7c0SLeon Romanovsky 16594d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD3 0x3E 16694d5f7c0SLeon Romanovsky #define ALC5632_PWR_MANAG_ADD3_MASK 0x7CFF 16794d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_AUXOUT_VOL (1 << 14) 16894d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_SPK_L_OUT (1 << 13) 16994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_SPK_R_OUT (1 << 12) 17094d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_HP_L_OUT_VOL (1 << 11) 17194d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_HP_R_OUT_VOL (1 << 10) 17294d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_LINEIN_L_VOL (1 << 7) 17394d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_LINEIN_R_VOL (1 << 6) 17494d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_AUXIN_VOL (1 << 5) 17594d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_AUXIN_MIX (1 << 4) 17694d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_MIC1_VOL (1 << 3) 17794d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_MIC2_VOL (1 << 2) 17894d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_MIC1_BOOST_AD (1 << 1) 17994d5f7c0SLeon Romanovsky #define ALC5632_PWR_ADD3_MIC2_BOOST_AD (1 << 0) 18094d5f7c0SLeon Romanovsky 18194d5f7c0SLeon Romanovsky #define ALC5632_GPCR1 0x40 18294d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_CLK_SYS_SRC_SEL_PLL1 (1 << 15) 18394d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_CLK_SYS_SRC_SEL_MCLK (0 << 15) 18494d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_DAC_HI_FLT_EN (1 << 10) 18594d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_SPK_AMP_CTRL (7 << 1) 18694d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_100 (5 << 1) 18794d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_125 (4 << 1) 18894d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_150 (3 << 1) 18994d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_175 (2 << 1) 19094d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_200 (1 << 1) 19194d5f7c0SLeon Romanovsky #define ALC5632_GPCR1_VDD_225 (0 << 1) 19294d5f7c0SLeon Romanovsky 19394d5f7c0SLeon Romanovsky #define ALC5632_GPCR2 0x42 19494d5f7c0SLeon Romanovsky #define ALC5632_GPCR2_PLL1_SOUR_SEL (3 << 12) 19594d5f7c0SLeon Romanovsky #define ALC5632_PLL_FR_MCLK (0 << 12) 19694d5f7c0SLeon Romanovsky #define ALC5632_PLL_FR_BCLK (2 << 12) 19794d5f7c0SLeon Romanovsky #define ALC5632_PLL_FR_VBCLK (3 << 12) 19894d5f7c0SLeon Romanovsky #define ALC5632_GPCR2_CLK_PLL_PRE_DIV1 (0 << 0) 19994d5f7c0SLeon Romanovsky 20094d5f7c0SLeon Romanovsky #define ALC5632_PLL1_CTRL 0x44 20194d5f7c0SLeon Romanovsky #define ALC5632_PLL1_CTRL_N_VAL(n) (((n) & 0x0f) << 8) 20294d5f7c0SLeon Romanovsky #define ALC5632_PLL1_M_BYPASS (1 << 7) 20394d5f7c0SLeon Romanovsky #define ALC5632_PLL1_CTRL_K_VAL(k) (((k) & 0x07) << 4) 20494d5f7c0SLeon Romanovsky #define ALC5632_PLL1_CTRL_M_VAL(m) (((m) & 0x0f) << 0) 20594d5f7c0SLeon Romanovsky 20694d5f7c0SLeon Romanovsky #define ALC5632_PLL2_CTRL 0x46 20794d5f7c0SLeon Romanovsky #define ALC5632_PLL2_EN (1 << 15) 20894d5f7c0SLeon Romanovsky #define ALC5632_PLL2_RATIO (0 << 15) 20994d5f7c0SLeon Romanovsky 21094d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_CONFIG 0x4C 21194d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_POLARITY 0x4E 21294d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_STICKY 0x50 21394d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_WAKEUP 0x52 21494d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_STATUS 0x54 21594d5f7c0SLeon Romanovsky #define ALC5632_GPIO_PIN_SHARING 0x56 21694d5f7c0SLeon Romanovsky #define ALC5632_OVER_CURR_STATUS 0x58 21794d5f7c0SLeon Romanovsky #define ALC5632_SOFTVOL_CTRL 0x5A 21894d5f7c0SLeon Romanovsky #define ALC5632_GPIO_OUPUT_PIN_CTRL 0x5C 21994d5f7c0SLeon Romanovsky 22094d5f7c0SLeon Romanovsky #define ALC5632_MISC_CTRL 0x5E 22194d5f7c0SLeon Romanovsky #define ALC5632_MISC_DISABLE_FAST_VREG (1 << 15) 22294d5f7c0SLeon Romanovsky #define ALC5632_MISC_AVC_TRGT_SEL (3 << 12) 22394d5f7c0SLeon Romanovsky #define ALC5632_MISC_AVC_TRGT_RIGHT (1 << 12) 22494d5f7c0SLeon Romanovsky #define ALC5632_MISC_AVC_TRGT_LEFT (2 << 12) 22594d5f7c0SLeon Romanovsky #define ALC5632_MISC_AVC_TRGT_BOTH (3 << 12) 22694d5f7c0SLeon Romanovsky #define ALC5632_MISC_HP_DEPOP_MODE1_EN (1 << 9) 22794d5f7c0SLeon Romanovsky #define ALC5632_MISC_HP_DEPOP_MODE2_EN (1 << 8) 22894d5f7c0SLeon Romanovsky #define ALC5632_MISC_HP_DEPOP_MUTE_L (1 << 7) 22994d5f7c0SLeon Romanovsky #define ALC5632_MISC_HP_DEPOP_MUTE_R (1 << 6) 23094d5f7c0SLeon Romanovsky #define ALC5632_MISC_HP_DEPOP_MUTE (1 << 5) 23194d5f7c0SLeon Romanovsky #define ALC5632_MISC_GPIO_WAKEUP_CTRL (1 << 1) 23294d5f7c0SLeon Romanovsky #define ALC5632_MISC_IRQOUT_INV_CTRL (1 << 0) 23394d5f7c0SLeon Romanovsky 23494d5f7c0SLeon Romanovsky #define ALC5632_DAC_CLK_CTRL1 0x60 23594d5f7c0SLeon Romanovsky #define ALC5632_DAC_CLK_CTRL2 0x62 23694d5f7c0SLeon Romanovsky #define ALC5632_DAC_CLK_CTRL2_DIV1_2 (1 << 0) 23794d5f7c0SLeon Romanovsky #define ALC5632_VOICE_DAC_PCM_CLK_CTRL1 0x64 23894d5f7c0SLeon Romanovsky #define ALC5632_PSEUDO_SPATIAL_CTRL 0x68 23994d5f7c0SLeon Romanovsky #define ALC5632_HID_CTRL_INDEX 0x6A 24094d5f7c0SLeon Romanovsky #define ALC5632_HID_CTRL_DATA 0x6C 24194d5f7c0SLeon Romanovsky #define ALC5632_EQ_CTRL 0x6E 24294d5f7c0SLeon Romanovsky 24394d5f7c0SLeon Romanovsky /* undocumented */ 24494d5f7c0SLeon Romanovsky #define ALC5632_VENDOR_ID1 0x7C 24594d5f7c0SLeon Romanovsky #define ALC5632_VENDOR_ID2 0x7E 24694d5f7c0SLeon Romanovsky 247bb39753cSLeon Romanovsky #define ALC5632_MAX_REGISTER 0x7E 248bb39753cSLeon Romanovsky 24994d5f7c0SLeon Romanovsky #endif 250