1 /* 2 * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on wm8731.c by Richard Purdie 8 * Based on ak4535.c by Richard Purdie 9 * Based on wm8753.c by Liam Girdwood 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 /* ** CAUTION ** 17 * 18 * This is very simple driver. 19 * It can use headphone output / stereo input only 20 * 21 * AK4642 is not tested. 22 * AK4643 is tested. 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/platform_device.h> 28 #include <linux/slab.h> 29 #include <sound/soc.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #define AK4642_VERSION "0.0.1" 34 35 #define PW_MGMT1 0x00 36 #define PW_MGMT2 0x01 37 #define SG_SL1 0x02 38 #define SG_SL2 0x03 39 #define MD_CTL1 0x04 40 #define MD_CTL2 0x05 41 #define TIMER 0x06 42 #define ALC_CTL1 0x07 43 #define ALC_CTL2 0x08 44 #define L_IVC 0x09 45 #define L_DVC 0x0a 46 #define ALC_CTL3 0x0b 47 #define R_IVC 0x0c 48 #define R_DVC 0x0d 49 #define MD_CTL3 0x0e 50 #define MD_CTL4 0x0f 51 #define PW_MGMT3 0x10 52 #define DF_S 0x11 53 #define FIL3_0 0x12 54 #define FIL3_1 0x13 55 #define FIL3_2 0x14 56 #define FIL3_3 0x15 57 #define EQ_0 0x16 58 #define EQ_1 0x17 59 #define EQ_2 0x18 60 #define EQ_3 0x19 61 #define EQ_4 0x1a 62 #define EQ_5 0x1b 63 #define FIL1_0 0x1c 64 #define FIL1_1 0x1d 65 #define FIL1_2 0x1e 66 #define FIL1_3 0x1f 67 #define PW_MGMT4 0x20 68 #define MD_CTL5 0x21 69 #define LO_MS 0x22 70 #define HP_MS 0x23 71 #define SPK_MS 0x24 72 73 #define AK4642_CACHEREGNUM 0x25 74 75 /* PW_MGMT1*/ 76 #define PMVCM (1 << 6) /* VCOM Power Management */ 77 #define PMMIN (1 << 5) /* MIN Input Power Management */ 78 #define PMDAC (1 << 2) /* DAC Power Management */ 79 #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */ 80 81 /* PW_MGMT2 */ 82 #define HPMTN (1 << 6) 83 #define PMHPL (1 << 5) 84 #define PMHPR (1 << 4) 85 #define MS (1 << 3) /* master/slave select */ 86 #define MCKO (1 << 1) 87 #define PMPLL (1 << 0) 88 89 #define PMHP_MASK (PMHPL | PMHPR) 90 #define PMHP PMHP_MASK 91 92 /* PW_MGMT3 */ 93 #define PMADR (1 << 0) /* MIC L / ADC R Power Management */ 94 95 /* SG_SL1 */ 96 #define MINS (1 << 6) /* Switch from MIN to Speaker */ 97 #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */ 98 #define PMMP (1 << 2) /* MPWR pin Power Management */ 99 #define MGAIN0 (1 << 0) /* MIC amp gain*/ 100 101 /* TIMER */ 102 #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */ 103 #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2)) 104 105 /* ALC_CTL1 */ 106 #define ALC (1 << 5) /* ALC Enable */ 107 #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */ 108 109 /* MD_CTL1 */ 110 #define PLL3 (1 << 7) 111 #define PLL2 (1 << 6) 112 #define PLL1 (1 << 5) 113 #define PLL0 (1 << 4) 114 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0) 115 116 #define BCKO_MASK (1 << 3) 117 #define BCKO_64 BCKO_MASK 118 119 #define DIF_MASK (3 << 0) 120 #define DSP (0 << 0) 121 #define RIGHT_J (1 << 0) 122 #define LEFT_J (2 << 0) 123 #define I2S (3 << 0) 124 125 /* MD_CTL2 */ 126 #define FS0 (1 << 0) 127 #define FS1 (1 << 1) 128 #define FS2 (1 << 2) 129 #define FS3 (1 << 5) 130 #define FS_MASK (FS0 | FS1 | FS2 | FS3) 131 132 /* MD_CTL3 */ 133 #define BST1 (1 << 3) 134 135 /* MD_CTL4 */ 136 #define DACH (1 << 0) 137 138 /* 139 * Playback Volume (table 39) 140 * 141 * max : 0x00 : +12.0 dB 142 * ( 0.5 dB step ) 143 * min : 0xFE : -115.0 dB 144 * mute: 0xFF 145 */ 146 static const DECLARE_TLV_DB_SCALE(out_tlv, -11500, 50, 1); 147 148 static const struct snd_kcontrol_new ak4642_snd_controls[] = { 149 150 SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC, 151 0, 0xFF, 1, out_tlv), 152 }; 153 154 155 /* codec private data */ 156 struct ak4642_priv { 157 unsigned int sysclk; 158 enum snd_soc_control_type control_type; 159 void *control_data; 160 }; 161 162 /* 163 * ak4642 register cache 164 */ 165 static const u16 ak4642_reg[AK4642_CACHEREGNUM] = { 166 0x0000, 0x0000, 0x0001, 0x0000, 167 0x0002, 0x0000, 0x0000, 0x0000, 168 0x00e1, 0x00e1, 0x0018, 0x0000, 169 0x00e1, 0x0018, 0x0011, 0x0008, 170 0x0000, 0x0000, 0x0000, 0x0000, 171 0x0000, 0x0000, 0x0000, 0x0000, 172 0x0000, 0x0000, 0x0000, 0x0000, 173 0x0000, 0x0000, 0x0000, 0x0000, 174 0x0000, 0x0000, 0x0000, 0x0000, 175 0x0000, 176 }; 177 178 /* 179 * read ak4642 register cache 180 */ 181 static inline unsigned int ak4642_read_reg_cache(struct snd_soc_codec *codec, 182 unsigned int reg) 183 { 184 u16 *cache = codec->reg_cache; 185 if (reg >= AK4642_CACHEREGNUM) 186 return -1; 187 return cache[reg]; 188 } 189 190 /* 191 * write ak4642 register cache 192 */ 193 static inline void ak4642_write_reg_cache(struct snd_soc_codec *codec, 194 u16 reg, unsigned int value) 195 { 196 u16 *cache = codec->reg_cache; 197 if (reg >= AK4642_CACHEREGNUM) 198 return; 199 200 cache[reg] = value; 201 } 202 203 /* 204 * write to the AK4642 register space 205 */ 206 static int ak4642_write(struct snd_soc_codec *codec, unsigned int reg, 207 unsigned int value) 208 { 209 u8 data[2]; 210 211 /* data is 212 * D15..D8 AK4642 register offset 213 * D7...D0 register data 214 */ 215 data[0] = reg & 0xff; 216 data[1] = value & 0xff; 217 218 if (codec->hw_write(codec->control_data, data, 2) == 2) { 219 ak4642_write_reg_cache(codec, reg, value); 220 return 0; 221 } else 222 return -EIO; 223 } 224 225 static int ak4642_sync(struct snd_soc_codec *codec) 226 { 227 u16 *cache = codec->reg_cache; 228 int i, r = 0; 229 230 for (i = 0; i < AK4642_CACHEREGNUM; i++) 231 r |= ak4642_write(codec, i, cache[i]); 232 233 return r; 234 }; 235 236 static int ak4642_dai_startup(struct snd_pcm_substream *substream, 237 struct snd_soc_dai *dai) 238 { 239 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 240 struct snd_soc_codec *codec = dai->codec; 241 242 if (is_play) { 243 /* 244 * start headphone output 245 * 246 * PLL, Master Mode 247 * Audio I/F Format :MSB justified (ADC & DAC) 248 * Bass Boost Level : Middle 249 * 250 * This operation came from example code of 251 * "ASAHI KASEI AK4642" (japanese) manual p97. 252 */ 253 snd_soc_update_bits(codec, MD_CTL4, DACH, DACH); 254 snd_soc_update_bits(codec, MD_CTL3, BST1, BST1); 255 ak4642_write(codec, L_IVC, 0x91); /* volume */ 256 ak4642_write(codec, R_IVC, 0x91); /* volume */ 257 snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMMIN | PMDAC, 258 PMVCM | PMMIN | PMDAC); 259 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, PMHP); 260 snd_soc_update_bits(codec, PW_MGMT2, HPMTN, HPMTN); 261 } else { 262 /* 263 * start stereo input 264 * 265 * PLL Master Mode 266 * Audio I/F Format:MSB justified (ADC & DAC) 267 * Pre MIC AMP:+20dB 268 * MIC Power On 269 * ALC setting:Refer to Table 35 270 * ALC bit=“1” 271 * 272 * This operation came from example code of 273 * "ASAHI KASEI AK4642" (japanese) manual p94. 274 */ 275 ak4642_write(codec, SG_SL1, PMMP | MGAIN0); 276 ak4642_write(codec, TIMER, ZTM(0x3) | WTM(0x3)); 277 ak4642_write(codec, ALC_CTL1, ALC | LMTH0); 278 snd_soc_update_bits(codec, PW_MGMT1, PMVCM | PMADL, 279 PMVCM | PMADL); 280 snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR); 281 } 282 283 return 0; 284 } 285 286 static void ak4642_dai_shutdown(struct snd_pcm_substream *substream, 287 struct snd_soc_dai *dai) 288 { 289 int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 290 struct snd_soc_codec *codec = dai->codec; 291 292 if (is_play) { 293 /* stop headphone output */ 294 snd_soc_update_bits(codec, PW_MGMT2, HPMTN, 0); 295 snd_soc_update_bits(codec, PW_MGMT2, PMHP_MASK, 0); 296 snd_soc_update_bits(codec, PW_MGMT1, PMMIN | PMDAC, 0); 297 snd_soc_update_bits(codec, MD_CTL3, BST1, 0); 298 snd_soc_update_bits(codec, MD_CTL4, DACH, 0); 299 } else { 300 /* stop stereo input */ 301 snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0); 302 snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0); 303 snd_soc_update_bits(codec, ALC_CTL1, ALC, 0); 304 } 305 } 306 307 static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai, 308 int clk_id, unsigned int freq, int dir) 309 { 310 struct snd_soc_codec *codec = codec_dai->codec; 311 u8 pll; 312 313 switch (freq) { 314 case 11289600: 315 pll = PLL2; 316 break; 317 case 12288000: 318 pll = PLL2 | PLL0; 319 break; 320 case 12000000: 321 pll = PLL2 | PLL1; 322 break; 323 case 24000000: 324 pll = PLL2 | PLL1 | PLL0; 325 break; 326 case 13500000: 327 pll = PLL3 | PLL2; 328 break; 329 case 27000000: 330 pll = PLL3 | PLL2 | PLL0; 331 break; 332 default: 333 return -EINVAL; 334 } 335 snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll); 336 337 return 0; 338 } 339 340 static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 341 { 342 struct snd_soc_codec *codec = dai->codec; 343 u8 data; 344 u8 bcko; 345 346 data = MCKO | PMPLL; /* use MCKO */ 347 bcko = 0; 348 349 /* set master/slave audio interface */ 350 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 351 case SND_SOC_DAIFMT_CBM_CFM: 352 data |= MS; 353 bcko = BCKO_64; 354 break; 355 case SND_SOC_DAIFMT_CBS_CFS: 356 break; 357 default: 358 return -EINVAL; 359 } 360 snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data); 361 snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko); 362 363 /* format type */ 364 data = 0; 365 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 366 case SND_SOC_DAIFMT_LEFT_J: 367 data = LEFT_J; 368 break; 369 case SND_SOC_DAIFMT_I2S: 370 data = I2S; 371 break; 372 /* FIXME 373 * Please add RIGHT_J / DSP support here 374 */ 375 default: 376 return -EINVAL; 377 break; 378 } 379 snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data); 380 381 return 0; 382 } 383 384 static int ak4642_dai_hw_params(struct snd_pcm_substream *substream, 385 struct snd_pcm_hw_params *params, 386 struct snd_soc_dai *dai) 387 { 388 struct snd_soc_codec *codec = dai->codec; 389 u8 rate; 390 391 switch (params_rate(params)) { 392 case 7350: 393 rate = FS2; 394 break; 395 case 8000: 396 rate = 0; 397 break; 398 case 11025: 399 rate = FS2 | FS0; 400 break; 401 case 12000: 402 rate = FS0; 403 break; 404 case 14700: 405 rate = FS2 | FS1; 406 break; 407 case 16000: 408 rate = FS1; 409 break; 410 case 22050: 411 rate = FS2 | FS1 | FS0; 412 break; 413 case 24000: 414 rate = FS1 | FS0; 415 break; 416 case 29400: 417 rate = FS3 | FS2 | FS1; 418 break; 419 case 32000: 420 rate = FS3 | FS1; 421 break; 422 case 44100: 423 rate = FS3 | FS2 | FS1 | FS0; 424 break; 425 case 48000: 426 rate = FS3 | FS1 | FS0; 427 break; 428 default: 429 return -EINVAL; 430 break; 431 } 432 snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate); 433 434 return 0; 435 } 436 437 static struct snd_soc_dai_ops ak4642_dai_ops = { 438 .startup = ak4642_dai_startup, 439 .shutdown = ak4642_dai_shutdown, 440 .set_sysclk = ak4642_dai_set_sysclk, 441 .set_fmt = ak4642_dai_set_fmt, 442 .hw_params = ak4642_dai_hw_params, 443 }; 444 445 static struct snd_soc_dai_driver ak4642_dai = { 446 .name = "ak4642-hifi", 447 .playback = { 448 .stream_name = "Playback", 449 .channels_min = 1, 450 .channels_max = 2, 451 .rates = SNDRV_PCM_RATE_8000_48000, 452 .formats = SNDRV_PCM_FMTBIT_S16_LE }, 453 .capture = { 454 .stream_name = "Capture", 455 .channels_min = 1, 456 .channels_max = 2, 457 .rates = SNDRV_PCM_RATE_8000_48000, 458 .formats = SNDRV_PCM_FMTBIT_S16_LE }, 459 .ops = &ak4642_dai_ops, 460 .symmetric_rates = 1, 461 }; 462 463 static int ak4642_resume(struct snd_soc_codec *codec) 464 { 465 ak4642_sync(codec); 466 return 0; 467 } 468 469 470 static int ak4642_probe(struct snd_soc_codec *codec) 471 { 472 struct ak4642_priv *ak4642 = snd_soc_codec_get_drvdata(codec); 473 474 dev_info(codec->dev, "AK4642 Audio Codec %s", AK4642_VERSION); 475 476 codec->hw_write = (hw_write_t)i2c_master_send; 477 codec->control_data = ak4642->control_data; 478 479 snd_soc_add_controls(codec, ak4642_snd_controls, 480 ARRAY_SIZE(ak4642_snd_controls)); 481 482 return 0; 483 } 484 485 static struct snd_soc_codec_driver soc_codec_dev_ak4642 = { 486 .probe = ak4642_probe, 487 .resume = ak4642_resume, 488 .read = ak4642_read_reg_cache, 489 .write = ak4642_write, 490 .reg_cache_size = ARRAY_SIZE(ak4642_reg), 491 .reg_word_size = sizeof(u8), 492 .reg_cache_default = ak4642_reg, 493 }; 494 495 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 496 static __devinit int ak4642_i2c_probe(struct i2c_client *i2c, 497 const struct i2c_device_id *id) 498 { 499 struct ak4642_priv *ak4642; 500 int ret; 501 502 ak4642 = kzalloc(sizeof(struct ak4642_priv), GFP_KERNEL); 503 if (!ak4642) 504 return -ENOMEM; 505 506 i2c_set_clientdata(i2c, ak4642); 507 ak4642->control_data = i2c; 508 ak4642->control_type = SND_SOC_I2C; 509 510 ret = snd_soc_register_codec(&i2c->dev, 511 &soc_codec_dev_ak4642, &ak4642_dai, 1); 512 if (ret < 0) 513 kfree(ak4642); 514 return ret; 515 } 516 517 static __devexit int ak4642_i2c_remove(struct i2c_client *client) 518 { 519 snd_soc_unregister_codec(&client->dev); 520 kfree(i2c_get_clientdata(client)); 521 return 0; 522 } 523 524 static const struct i2c_device_id ak4642_i2c_id[] = { 525 { "ak4642", 0 }, 526 { "ak4643", 0 }, 527 { } 528 }; 529 MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id); 530 531 static struct i2c_driver ak4642_i2c_driver = { 532 .driver = { 533 .name = "ak4642-codec", 534 .owner = THIS_MODULE, 535 }, 536 .probe = ak4642_i2c_probe, 537 .remove = __devexit_p(ak4642_i2c_remove), 538 .id_table = ak4642_i2c_id, 539 }; 540 #endif 541 542 static int __init ak4642_modinit(void) 543 { 544 int ret = 0; 545 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 546 ret = i2c_add_driver(&ak4642_i2c_driver); 547 #endif 548 return ret; 549 550 } 551 module_init(ak4642_modinit); 552 553 static void __exit ak4642_exit(void) 554 { 555 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 556 i2c_del_driver(&ak4642_i2c_driver); 557 #endif 558 559 } 560 module_exit(ak4642_exit); 561 562 MODULE_DESCRIPTION("Soc AK4642 driver"); 563 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 564 MODULE_LICENSE("GPL"); 565