1 /* 2 * ADAV80X Audio Codec driver supporting ADAV801, ADAV803 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * Author: Yi Li <yi.li@analog.com> 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/i2c.h> 15 #include <linux/spi/spi.h> 16 #include <linux/slab.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/tlv.h> 21 #include <sound/soc.h> 22 23 #include "adav80x.h" 24 25 #define ADAV80X_PLAYBACK_CTRL 0x04 26 #define ADAV80X_AUX_IN_CTRL 0x05 27 #define ADAV80X_REC_CTRL 0x06 28 #define ADAV80X_AUX_OUT_CTRL 0x07 29 #define ADAV80X_DPATH_CTRL1 0x62 30 #define ADAV80X_DPATH_CTRL2 0x63 31 #define ADAV80X_DAC_CTRL1 0x64 32 #define ADAV80X_DAC_CTRL2 0x65 33 #define ADAV80X_DAC_CTRL3 0x66 34 #define ADAV80X_DAC_L_VOL 0x68 35 #define ADAV80X_DAC_R_VOL 0x69 36 #define ADAV80X_PGA_L_VOL 0x6c 37 #define ADAV80X_PGA_R_VOL 0x6d 38 #define ADAV80X_ADC_CTRL1 0x6e 39 #define ADAV80X_ADC_CTRL2 0x6f 40 #define ADAV80X_ADC_L_VOL 0x70 41 #define ADAV80X_ADC_R_VOL 0x71 42 #define ADAV80X_PLL_CTRL1 0x74 43 #define ADAV80X_PLL_CTRL2 0x75 44 #define ADAV80X_ICLK_CTRL1 0x76 45 #define ADAV80X_ICLK_CTRL2 0x77 46 #define ADAV80X_PLL_CLK_SRC 0x78 47 #define ADAV80X_PLL_OUTE 0x7a 48 49 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 50 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) 51 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) 52 53 #define ADAV80X_ICLK_CTRL1_DAC_SRC(src) ((src) << 5) 54 #define ADAV80X_ICLK_CTRL1_ADC_SRC(src) ((src) << 2) 55 #define ADAV80X_ICLK_CTRL1_ICLK2_SRC(src) (src) 56 #define ADAV80X_ICLK_CTRL2_ICLK1_SRC(src) ((src) << 3) 57 58 #define ADAV80X_PLL_CTRL1_PLLDIV 0x10 59 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) 60 #define ADAV80X_PLL_CTRL1_XTLPD 0x02 61 62 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) 63 64 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) 65 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) 66 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) 67 68 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) 69 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) 70 #define ADAV80X_PLL_CTRL2_PLL_MASK(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0f) 71 72 #define ADAV80X_ADC_CTRL1_MODULATOR_MASK 0x80 73 #define ADAV80X_ADC_CTRL1_MODULATOR_128FS 0x00 74 #define ADAV80X_ADC_CTRL1_MODULATOR_64FS 0x80 75 76 #define ADAV80X_DAC_CTRL1_PD 0x80 77 78 #define ADAV80X_DAC_CTRL2_DIV1 0x00 79 #define ADAV80X_DAC_CTRL2_DIV1_5 0x10 80 #define ADAV80X_DAC_CTRL2_DIV2 0x20 81 #define ADAV80X_DAC_CTRL2_DIV3 0x30 82 #define ADAV80X_DAC_CTRL2_DIV_MASK 0x30 83 84 #define ADAV80X_DAC_CTRL2_INTERPOL_256FS 0x00 85 #define ADAV80X_DAC_CTRL2_INTERPOL_128FS 0x40 86 #define ADAV80X_DAC_CTRL2_INTERPOL_64FS 0x80 87 #define ADAV80X_DAC_CTRL2_INTERPOL_MASK 0xc0 88 89 #define ADAV80X_DAC_CTRL2_DEEMPH_NONE 0x00 90 #define ADAV80X_DAC_CTRL2_DEEMPH_44 0x01 91 #define ADAV80X_DAC_CTRL2_DEEMPH_32 0x02 92 #define ADAV80X_DAC_CTRL2_DEEMPH_48 0x03 93 #define ADAV80X_DAC_CTRL2_DEEMPH_MASK 0x01 94 95 #define ADAV80X_CAPTURE_MODE_MASTER 0x20 96 #define ADAV80X_CAPTURE_WORD_LEN24 0x00 97 #define ADAV80X_CAPTURE_WORD_LEN20 0x04 98 #define ADAV80X_CAPTRUE_WORD_LEN18 0x08 99 #define ADAV80X_CAPTURE_WORD_LEN16 0x0c 100 #define ADAV80X_CAPTURE_WORD_LEN_MASK 0x0c 101 102 #define ADAV80X_CAPTURE_MODE_LEFT_J 0x00 103 #define ADAV80X_CAPTURE_MODE_I2S 0x01 104 #define ADAV80X_CAPTURE_MODE_RIGHT_J 0x03 105 #define ADAV80X_CAPTURE_MODE_MASK 0x03 106 107 #define ADAV80X_PLAYBACK_MODE_MASTER 0x10 108 #define ADAV80X_PLAYBACK_MODE_LEFT_J 0x00 109 #define ADAV80X_PLAYBACK_MODE_I2S 0x01 110 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_24 0x04 111 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_20 0x05 112 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_18 0x06 113 #define ADAV80X_PLAYBACK_MODE_RIGHT_J_16 0x07 114 #define ADAV80X_PLAYBACK_MODE_MASK 0x07 115 116 #define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x)) 117 118 static struct reg_default adav80x_reg_defaults[] = { 119 { ADAV80X_PLAYBACK_CTRL, 0x01 }, 120 { ADAV80X_AUX_IN_CTRL, 0x01 }, 121 { ADAV80X_REC_CTRL, 0x02 }, 122 { ADAV80X_AUX_OUT_CTRL, 0x01 }, 123 { ADAV80X_DPATH_CTRL1, 0xc0 }, 124 { ADAV80X_DPATH_CTRL2, 0x11 }, 125 { ADAV80X_DAC_CTRL1, 0x00 }, 126 { ADAV80X_DAC_CTRL2, 0x00 }, 127 { ADAV80X_DAC_CTRL3, 0x00 }, 128 { ADAV80X_DAC_L_VOL, 0xff }, 129 { ADAV80X_DAC_R_VOL, 0xff }, 130 { ADAV80X_PGA_L_VOL, 0x00 }, 131 { ADAV80X_PGA_R_VOL, 0x00 }, 132 { ADAV80X_ADC_CTRL1, 0x00 }, 133 { ADAV80X_ADC_CTRL2, 0x00 }, 134 { ADAV80X_ADC_L_VOL, 0xff }, 135 { ADAV80X_ADC_R_VOL, 0xff }, 136 { ADAV80X_PLL_CTRL1, 0x00 }, 137 { ADAV80X_PLL_CTRL2, 0x00 }, 138 { ADAV80X_ICLK_CTRL1, 0x00 }, 139 { ADAV80X_ICLK_CTRL2, 0x00 }, 140 { ADAV80X_PLL_CLK_SRC, 0x00 }, 141 { ADAV80X_PLL_OUTE, 0x00 }, 142 }; 143 144 struct adav80x { 145 struct regmap *regmap; 146 147 enum adav80x_clk_src clk_src; 148 unsigned int sysclk; 149 enum adav80x_pll_src pll_src; 150 151 unsigned int dai_fmt[2]; 152 unsigned int rate; 153 bool deemph; 154 bool sysclk_pd[3]; 155 }; 156 157 static const char *adav80x_mux_text[] = { 158 "ADC", 159 "Playback", 160 "Aux Playback", 161 }; 162 163 static const unsigned int adav80x_mux_values[] = { 164 0, 2, 3, 165 }; 166 167 #define ADAV80X_MUX_ENUM_DECL(name, reg, shift) \ 168 SOC_VALUE_ENUM_DOUBLE_DECL(name, reg, shift, 7, \ 169 ARRAY_SIZE(adav80x_mux_text), adav80x_mux_text, \ 170 adav80x_mux_values) 171 172 static ADAV80X_MUX_ENUM_DECL(adav80x_aux_capture_enum, ADAV80X_DPATH_CTRL1, 0); 173 static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3); 174 static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3); 175 176 static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl = 177 SOC_DAPM_VALUE_ENUM("Route", adav80x_aux_capture_enum); 178 static const struct snd_kcontrol_new adav80x_capture_mux_ctrl = 179 SOC_DAPM_VALUE_ENUM("Route", adav80x_capture_enum); 180 static const struct snd_kcontrol_new adav80x_dac_mux_ctrl = 181 SOC_DAPM_VALUE_ENUM("Route", adav80x_dac_enum); 182 183 #define ADAV80X_MUX(name, ctrl) \ 184 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 185 186 static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = { 187 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1), 188 SND_SOC_DAPM_ADC("ADC", NULL, ADAV80X_ADC_CTRL1, 5, 1), 189 190 SND_SOC_DAPM_PGA("Right PGA", ADAV80X_ADC_CTRL1, 0, 1, NULL, 0), 191 SND_SOC_DAPM_PGA("Left PGA", ADAV80X_ADC_CTRL1, 1, 1, NULL, 0), 192 193 SND_SOC_DAPM_AIF_OUT("AIFOUT", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0), 194 SND_SOC_DAPM_AIF_IN("AIFIN", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 195 196 SND_SOC_DAPM_AIF_OUT("AIFAUXOUT", "Aux Capture", 0, SND_SOC_NOPM, 0, 0), 197 SND_SOC_DAPM_AIF_IN("AIFAUXIN", "Aux Playback", 0, SND_SOC_NOPM, 0, 0), 198 199 ADAV80X_MUX("Aux Capture Select", &adav80x_aux_capture_mux_ctrl), 200 ADAV80X_MUX("Capture Select", &adav80x_capture_mux_ctrl), 201 ADAV80X_MUX("DAC Select", &adav80x_dac_mux_ctrl), 202 203 SND_SOC_DAPM_INPUT("VINR"), 204 SND_SOC_DAPM_INPUT("VINL"), 205 SND_SOC_DAPM_OUTPUT("VOUTR"), 206 SND_SOC_DAPM_OUTPUT("VOUTL"), 207 208 SND_SOC_DAPM_SUPPLY("SYSCLK", SND_SOC_NOPM, 0, 0, NULL, 0), 209 SND_SOC_DAPM_SUPPLY("PLL1", ADAV80X_PLL_CTRL1, 2, 1, NULL, 0), 210 SND_SOC_DAPM_SUPPLY("PLL2", ADAV80X_PLL_CTRL1, 3, 1, NULL, 0), 211 SND_SOC_DAPM_SUPPLY("OSC", ADAV80X_PLL_CTRL1, 1, 1, NULL, 0), 212 }; 213 214 static int adav80x_dapm_sysclk_check(struct snd_soc_dapm_widget *source, 215 struct snd_soc_dapm_widget *sink) 216 { 217 struct snd_soc_codec *codec = source->codec; 218 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 219 const char *clk; 220 221 switch (adav80x->clk_src) { 222 case ADAV80X_CLK_PLL1: 223 clk = "PLL1"; 224 break; 225 case ADAV80X_CLK_PLL2: 226 clk = "PLL2"; 227 break; 228 case ADAV80X_CLK_XTAL: 229 clk = "OSC"; 230 break; 231 default: 232 return 0; 233 } 234 235 return strcmp(source->name, clk) == 0; 236 } 237 238 static int adav80x_dapm_pll_check(struct snd_soc_dapm_widget *source, 239 struct snd_soc_dapm_widget *sink) 240 { 241 struct snd_soc_codec *codec = source->codec; 242 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 243 244 return adav80x->pll_src == ADAV80X_PLL_SRC_XTAL; 245 } 246 247 248 static const struct snd_soc_dapm_route adav80x_dapm_routes[] = { 249 { "DAC Select", "ADC", "ADC" }, 250 { "DAC Select", "Playback", "AIFIN" }, 251 { "DAC Select", "Aux Playback", "AIFAUXIN" }, 252 { "DAC", NULL, "DAC Select" }, 253 254 { "Capture Select", "ADC", "ADC" }, 255 { "Capture Select", "Playback", "AIFIN" }, 256 { "Capture Select", "Aux Playback", "AIFAUXIN" }, 257 { "AIFOUT", NULL, "Capture Select" }, 258 259 { "Aux Capture Select", "ADC", "ADC" }, 260 { "Aux Capture Select", "Playback", "AIFIN" }, 261 { "Aux Capture Select", "Aux Playback", "AIFAUXIN" }, 262 { "AIFAUXOUT", NULL, "Aux Capture Select" }, 263 264 { "VOUTR", NULL, "DAC" }, 265 { "VOUTL", NULL, "DAC" }, 266 267 { "Left PGA", NULL, "VINL" }, 268 { "Right PGA", NULL, "VINR" }, 269 { "ADC", NULL, "Left PGA" }, 270 { "ADC", NULL, "Right PGA" }, 271 272 { "SYSCLK", NULL, "PLL1", adav80x_dapm_sysclk_check }, 273 { "SYSCLK", NULL, "PLL2", adav80x_dapm_sysclk_check }, 274 { "SYSCLK", NULL, "OSC", adav80x_dapm_sysclk_check }, 275 { "PLL1", NULL, "OSC", adav80x_dapm_pll_check }, 276 { "PLL2", NULL, "OSC", adav80x_dapm_pll_check }, 277 278 { "ADC", NULL, "SYSCLK" }, 279 { "DAC", NULL, "SYSCLK" }, 280 { "AIFOUT", NULL, "SYSCLK" }, 281 { "AIFAUXOUT", NULL, "SYSCLK" }, 282 { "AIFIN", NULL, "SYSCLK" }, 283 { "AIFAUXIN", NULL, "SYSCLK" }, 284 }; 285 286 static int adav80x_set_deemph(struct snd_soc_codec *codec) 287 { 288 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 289 unsigned int val; 290 291 if (adav80x->deemph) { 292 switch (adav80x->rate) { 293 case 32000: 294 val = ADAV80X_DAC_CTRL2_DEEMPH_32; 295 break; 296 case 44100: 297 val = ADAV80X_DAC_CTRL2_DEEMPH_44; 298 break; 299 case 48000: 300 case 64000: 301 case 88200: 302 case 96000: 303 val = ADAV80X_DAC_CTRL2_DEEMPH_48; 304 break; 305 default: 306 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; 307 break; 308 } 309 } else { 310 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; 311 } 312 313 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, 314 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val); 315 } 316 317 static int adav80x_put_deemph(struct snd_kcontrol *kcontrol, 318 struct snd_ctl_elem_value *ucontrol) 319 { 320 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 321 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 322 unsigned int deemph = ucontrol->value.enumerated.item[0]; 323 324 if (deemph > 1) 325 return -EINVAL; 326 327 adav80x->deemph = deemph; 328 329 return adav80x_set_deemph(codec); 330 } 331 332 static int adav80x_get_deemph(struct snd_kcontrol *kcontrol, 333 struct snd_ctl_elem_value *ucontrol) 334 { 335 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 336 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 337 338 ucontrol->value.enumerated.item[0] = adav80x->deemph; 339 return 0; 340 }; 341 342 static const DECLARE_TLV_DB_SCALE(adav80x_inpga_tlv, 0, 50, 0); 343 static const DECLARE_TLV_DB_MINMAX(adav80x_digital_tlv, -9563, 0); 344 345 static const struct snd_kcontrol_new adav80x_controls[] = { 346 SOC_DOUBLE_R_TLV("Master Playback Volume", ADAV80X_DAC_L_VOL, 347 ADAV80X_DAC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), 348 SOC_DOUBLE_R_TLV("Master Capture Volume", ADAV80X_ADC_L_VOL, 349 ADAV80X_ADC_R_VOL, 0, 0xff, 0, adav80x_digital_tlv), 350 351 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAV80X_PGA_L_VOL, 352 ADAV80X_PGA_R_VOL, 0, 0x30, 0, adav80x_inpga_tlv), 353 354 SOC_DOUBLE("Master Playback Switch", ADAV80X_DAC_CTRL1, 0, 1, 1, 0), 355 SOC_DOUBLE("Master Capture Switch", ADAV80X_ADC_CTRL1, 2, 3, 1, 1), 356 357 SOC_SINGLE("ADC High Pass Filter Switch", ADAV80X_ADC_CTRL1, 6, 1, 0), 358 359 SOC_SINGLE_BOOL_EXT("Playback De-emphasis Switch", 0, 360 adav80x_get_deemph, adav80x_put_deemph), 361 }; 362 363 static unsigned int adav80x_port_ctrl_regs[2][2] = { 364 { ADAV80X_REC_CTRL, ADAV80X_PLAYBACK_CTRL, }, 365 { ADAV80X_AUX_OUT_CTRL, ADAV80X_AUX_IN_CTRL }, 366 }; 367 368 static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 369 { 370 struct snd_soc_codec *codec = dai->codec; 371 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 372 unsigned int capture = 0x00; 373 unsigned int playback = 0x00; 374 375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 376 case SND_SOC_DAIFMT_CBM_CFM: 377 capture |= ADAV80X_CAPTURE_MODE_MASTER; 378 playback |= ADAV80X_PLAYBACK_MODE_MASTER; 379 case SND_SOC_DAIFMT_CBS_CFS: 380 break; 381 default: 382 return -EINVAL; 383 } 384 385 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 386 case SND_SOC_DAIFMT_I2S: 387 capture |= ADAV80X_CAPTURE_MODE_I2S; 388 playback |= ADAV80X_PLAYBACK_MODE_I2S; 389 break; 390 case SND_SOC_DAIFMT_LEFT_J: 391 capture |= ADAV80X_CAPTURE_MODE_LEFT_J; 392 playback |= ADAV80X_PLAYBACK_MODE_LEFT_J; 393 break; 394 case SND_SOC_DAIFMT_RIGHT_J: 395 capture |= ADAV80X_CAPTURE_MODE_RIGHT_J; 396 playback |= ADAV80X_PLAYBACK_MODE_RIGHT_J_24; 397 break; 398 default: 399 return -EINVAL; 400 } 401 402 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 403 case SND_SOC_DAIFMT_NB_NF: 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], 410 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER, 411 capture); 412 regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], 413 playback); 414 415 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 416 417 return 0; 418 } 419 420 static int adav80x_set_adc_clock(struct snd_soc_codec *codec, 421 unsigned int sample_rate) 422 { 423 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 424 unsigned int val; 425 426 if (sample_rate <= 48000) 427 val = ADAV80X_ADC_CTRL1_MODULATOR_128FS; 428 else 429 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS; 430 431 regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1, 432 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val); 433 434 return 0; 435 } 436 437 static int adav80x_set_dac_clock(struct snd_soc_codec *codec, 438 unsigned int sample_rate) 439 { 440 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 441 unsigned int val; 442 443 if (sample_rate <= 48000) 444 val = ADAV80X_DAC_CTRL2_DIV1 | ADAV80X_DAC_CTRL2_INTERPOL_256FS; 445 else 446 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS; 447 448 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2, 449 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK, 450 val); 451 452 return 0; 453 } 454 455 static int adav80x_set_capture_pcm_format(struct snd_soc_codec *codec, 456 struct snd_soc_dai *dai, snd_pcm_format_t format) 457 { 458 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 459 unsigned int val; 460 461 switch (format) { 462 case SNDRV_PCM_FORMAT_S16_LE: 463 val = ADAV80X_CAPTURE_WORD_LEN16; 464 break; 465 case SNDRV_PCM_FORMAT_S18_3LE: 466 val = ADAV80X_CAPTRUE_WORD_LEN18; 467 break; 468 case SNDRV_PCM_FORMAT_S20_3LE: 469 val = ADAV80X_CAPTURE_WORD_LEN20; 470 break; 471 case SNDRV_PCM_FORMAT_S24_LE: 472 val = ADAV80X_CAPTURE_WORD_LEN24; 473 break; 474 default: 475 return -EINVAL; 476 } 477 478 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0], 479 ADAV80X_CAPTURE_WORD_LEN_MASK, val); 480 481 return 0; 482 } 483 484 static int adav80x_set_playback_pcm_format(struct snd_soc_codec *codec, 485 struct snd_soc_dai *dai, snd_pcm_format_t format) 486 { 487 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 488 unsigned int val; 489 490 if (adav80x->dai_fmt[dai->id] != SND_SOC_DAIFMT_RIGHT_J) 491 return 0; 492 493 switch (format) { 494 case SNDRV_PCM_FORMAT_S16_LE: 495 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_16; 496 break; 497 case SNDRV_PCM_FORMAT_S18_3LE: 498 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_18; 499 break; 500 case SNDRV_PCM_FORMAT_S20_3LE: 501 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_20; 502 break; 503 case SNDRV_PCM_FORMAT_S24_LE: 504 val = ADAV80X_PLAYBACK_MODE_RIGHT_J_24; 505 break; 506 default: 507 return -EINVAL; 508 } 509 510 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1], 511 ADAV80X_PLAYBACK_MODE_MASK, val); 512 513 return 0; 514 } 515 516 static int adav80x_hw_params(struct snd_pcm_substream *substream, 517 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 518 { 519 struct snd_soc_codec *codec = dai->codec; 520 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 521 unsigned int rate = params_rate(params); 522 523 if (rate * 256 != adav80x->sysclk) 524 return -EINVAL; 525 526 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 527 adav80x_set_playback_pcm_format(codec, dai, 528 params_format(params)); 529 adav80x_set_dac_clock(codec, rate); 530 } else { 531 adav80x_set_capture_pcm_format(codec, dai, 532 params_format(params)); 533 adav80x_set_adc_clock(codec, rate); 534 } 535 adav80x->rate = rate; 536 adav80x_set_deemph(codec); 537 538 return 0; 539 } 540 541 static int adav80x_set_sysclk(struct snd_soc_codec *codec, 542 int clk_id, int source, 543 unsigned int freq, int dir) 544 { 545 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 546 547 if (dir == SND_SOC_CLOCK_IN) { 548 switch (clk_id) { 549 case ADAV80X_CLK_XIN: 550 case ADAV80X_CLK_XTAL: 551 case ADAV80X_CLK_MCLKI: 552 case ADAV80X_CLK_PLL1: 553 case ADAV80X_CLK_PLL2: 554 break; 555 default: 556 return -EINVAL; 557 } 558 559 adav80x->sysclk = freq; 560 561 if (adav80x->clk_src != clk_id) { 562 unsigned int iclk_ctrl1, iclk_ctrl2; 563 564 adav80x->clk_src = clk_id; 565 if (clk_id == ADAV80X_CLK_XTAL) 566 clk_id = ADAV80X_CLK_XIN; 567 568 iclk_ctrl1 = ADAV80X_ICLK_CTRL1_DAC_SRC(clk_id) | 569 ADAV80X_ICLK_CTRL1_ADC_SRC(clk_id) | 570 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); 571 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); 572 573 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1, 574 iclk_ctrl1); 575 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2, 576 iclk_ctrl2); 577 578 snd_soc_dapm_sync(&codec->dapm); 579 } 580 } else { 581 unsigned int mask; 582 583 switch (clk_id) { 584 case ADAV80X_CLK_SYSCLK1: 585 case ADAV80X_CLK_SYSCLK2: 586 case ADAV80X_CLK_SYSCLK3: 587 break; 588 default: 589 return -EINVAL; 590 } 591 592 clk_id -= ADAV80X_CLK_SYSCLK1; 593 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id); 594 595 if (freq == 0) { 596 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, 597 mask, mask); 598 adav80x->sysclk_pd[clk_id] = true; 599 } else { 600 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE, 601 mask, 0); 602 adav80x->sysclk_pd[clk_id] = false; 603 } 604 605 if (adav80x->sysclk_pd[0]) 606 snd_soc_dapm_disable_pin(&codec->dapm, "PLL1"); 607 else 608 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); 609 610 if (adav80x->sysclk_pd[1] || adav80x->sysclk_pd[2]) 611 snd_soc_dapm_disable_pin(&codec->dapm, "PLL2"); 612 else 613 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); 614 615 snd_soc_dapm_sync(&codec->dapm); 616 } 617 618 return 0; 619 } 620 621 static int adav80x_set_pll(struct snd_soc_codec *codec, int pll_id, 622 int source, unsigned int freq_in, unsigned int freq_out) 623 { 624 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 625 unsigned int pll_ctrl1 = 0; 626 unsigned int pll_ctrl2 = 0; 627 unsigned int pll_src; 628 629 switch (source) { 630 case ADAV80X_PLL_SRC_XTAL: 631 case ADAV80X_PLL_SRC_XIN: 632 case ADAV80X_PLL_SRC_MCLKI: 633 break; 634 default: 635 return -EINVAL; 636 } 637 638 if (!freq_out) 639 return 0; 640 641 switch (freq_in) { 642 case 27000000: 643 break; 644 case 54000000: 645 if (source == ADAV80X_PLL_SRC_XIN) { 646 pll_ctrl1 |= ADAV80X_PLL_CTRL1_PLLDIV; 647 break; 648 } 649 default: 650 return -EINVAL; 651 } 652 653 if (freq_out > 12288000) { 654 pll_ctrl2 |= ADAV80X_PLL_CTRL2_DOUB(pll_id); 655 freq_out /= 2; 656 } 657 658 /* freq_out = sample_rate * 256 */ 659 switch (freq_out) { 660 case 8192000: 661 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_32(pll_id); 662 break; 663 case 11289600: 664 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_44(pll_id); 665 break; 666 case 12288000: 667 pll_ctrl2 |= ADAV80X_PLL_CTRL2_FS_48(pll_id); 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1, 674 ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1); 675 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2, 676 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2); 677 678 if (source != adav80x->pll_src) { 679 if (source == ADAV80X_PLL_SRC_MCLKI) 680 pll_src = ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll_id); 681 else 682 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id); 683 684 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC, 685 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src); 686 687 adav80x->pll_src = source; 688 689 snd_soc_dapm_sync(&codec->dapm); 690 } 691 692 return 0; 693 } 694 695 static int adav80x_set_bias_level(struct snd_soc_codec *codec, 696 enum snd_soc_bias_level level) 697 { 698 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 699 unsigned int mask = ADAV80X_DAC_CTRL1_PD; 700 701 switch (level) { 702 case SND_SOC_BIAS_ON: 703 break; 704 case SND_SOC_BIAS_PREPARE: 705 break; 706 case SND_SOC_BIAS_STANDBY: 707 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, 708 0x00); 709 break; 710 case SND_SOC_BIAS_OFF: 711 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, 712 mask); 713 break; 714 } 715 716 codec->dapm.bias_level = level; 717 return 0; 718 } 719 720 /* Enforce the same sample rate on all audio interfaces */ 721 static int adav80x_dai_startup(struct snd_pcm_substream *substream, 722 struct snd_soc_dai *dai) 723 { 724 struct snd_soc_codec *codec = dai->codec; 725 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 726 727 if (!codec->active || !adav80x->rate) 728 return 0; 729 730 return snd_pcm_hw_constraint_minmax(substream->runtime, 731 SNDRV_PCM_HW_PARAM_RATE, adav80x->rate, adav80x->rate); 732 } 733 734 static void adav80x_dai_shutdown(struct snd_pcm_substream *substream, 735 struct snd_soc_dai *dai) 736 { 737 struct snd_soc_codec *codec = dai->codec; 738 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 739 740 if (!codec->active) 741 adav80x->rate = 0; 742 } 743 744 static const struct snd_soc_dai_ops adav80x_dai_ops = { 745 .set_fmt = adav80x_set_dai_fmt, 746 .hw_params = adav80x_hw_params, 747 .startup = adav80x_dai_startup, 748 .shutdown = adav80x_dai_shutdown, 749 }; 750 751 #define ADAV80X_PLAYBACK_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 752 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | \ 753 SNDRV_PCM_RATE_96000) 754 755 #define ADAV80X_CAPTURE_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) 756 757 #define ADAV80X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \ 758 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE) 759 760 static struct snd_soc_dai_driver adav80x_dais[] = { 761 { 762 .name = "adav80x-hifi", 763 .id = 0, 764 .playback = { 765 .stream_name = "HiFi Playback", 766 .channels_min = 2, 767 .channels_max = 2, 768 .rates = ADAV80X_PLAYBACK_RATES, 769 .formats = ADAV80X_FORMATS, 770 }, 771 .capture = { 772 .stream_name = "HiFi Capture", 773 .channels_min = 2, 774 .channels_max = 2, 775 .rates = ADAV80X_CAPTURE_RATES, 776 .formats = ADAV80X_FORMATS, 777 }, 778 .ops = &adav80x_dai_ops, 779 }, 780 { 781 .name = "adav80x-aux", 782 .id = 1, 783 .playback = { 784 .stream_name = "Aux Playback", 785 .channels_min = 2, 786 .channels_max = 2, 787 .rates = ADAV80X_PLAYBACK_RATES, 788 .formats = ADAV80X_FORMATS, 789 }, 790 .capture = { 791 .stream_name = "Aux Capture", 792 .channels_min = 2, 793 .channels_max = 2, 794 .rates = ADAV80X_CAPTURE_RATES, 795 .formats = ADAV80X_FORMATS, 796 }, 797 .ops = &adav80x_dai_ops, 798 }, 799 }; 800 801 static int adav80x_probe(struct snd_soc_codec *codec) 802 { 803 int ret; 804 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 805 806 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP); 807 if (ret) { 808 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 809 return ret; 810 } 811 812 /* Force PLLs on for SYSCLK output */ 813 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); 814 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); 815 816 /* Power down S/PDIF receiver, since it is currently not supported */ 817 regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20); 818 /* Disable DAC zero flag */ 819 regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6); 820 821 return adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 822 } 823 824 static int adav80x_suspend(struct snd_soc_codec *codec) 825 { 826 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 827 int ret; 828 829 ret = adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF); 830 regcache_cache_only(adav80x->regmap, true); 831 832 return ret; 833 } 834 835 static int adav80x_resume(struct snd_soc_codec *codec) 836 { 837 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 838 839 regcache_cache_only(adav80x->regmap, false); 840 adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 841 regcache_sync(adav80x->regmap); 842 843 return 0; 844 } 845 846 static int adav80x_remove(struct snd_soc_codec *codec) 847 { 848 return adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF); 849 } 850 851 static struct snd_soc_codec_driver adav80x_codec_driver = { 852 .probe = adav80x_probe, 853 .remove = adav80x_remove, 854 .suspend = adav80x_suspend, 855 .resume = adav80x_resume, 856 .set_bias_level = adav80x_set_bias_level, 857 858 .set_pll = adav80x_set_pll, 859 .set_sysclk = adav80x_set_sysclk, 860 861 .controls = adav80x_controls, 862 .num_controls = ARRAY_SIZE(adav80x_controls), 863 .dapm_widgets = adav80x_dapm_widgets, 864 .num_dapm_widgets = ARRAY_SIZE(adav80x_dapm_widgets), 865 .dapm_routes = adav80x_dapm_routes, 866 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes), 867 }; 868 869 static int adav80x_bus_probe(struct device *dev, struct regmap *regmap) 870 { 871 struct adav80x *adav80x; 872 int ret; 873 874 if (IS_ERR(regmap)) 875 return PTR_ERR(regmap); 876 877 adav80x = kzalloc(sizeof(*adav80x), GFP_KERNEL); 878 if (!adav80x) 879 return -ENOMEM; 880 881 882 dev_set_drvdata(dev, adav80x); 883 adav80x->regmap = regmap; 884 885 ret = snd_soc_register_codec(dev, &adav80x_codec_driver, 886 adav80x_dais, ARRAY_SIZE(adav80x_dais)); 887 if (ret) 888 kfree(adav80x); 889 890 return ret; 891 } 892 893 static int adav80x_bus_remove(struct device *dev) 894 { 895 snd_soc_unregister_codec(dev); 896 kfree(dev_get_drvdata(dev)); 897 return 0; 898 } 899 900 #if defined(CONFIG_SPI_MASTER) 901 static const struct regmap_config adav80x_spi_regmap_config = { 902 .val_bits = 8, 903 .pad_bits = 1, 904 .reg_bits = 7, 905 .read_flag_mask = 0x01, 906 907 .max_register = ADAV80X_PLL_OUTE, 908 909 .cache_type = REGCACHE_RBTREE, 910 .reg_defaults = adav80x_reg_defaults, 911 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults), 912 }; 913 914 static const struct spi_device_id adav80x_spi_id[] = { 915 { "adav801", 0 }, 916 { } 917 }; 918 MODULE_DEVICE_TABLE(spi, adav80x_spi_id); 919 920 static int adav80x_spi_probe(struct spi_device *spi) 921 { 922 return adav80x_bus_probe(&spi->dev, 923 devm_regmap_init_spi(spi, &adav80x_spi_regmap_config)); 924 } 925 926 static int adav80x_spi_remove(struct spi_device *spi) 927 { 928 return adav80x_bus_remove(&spi->dev); 929 } 930 931 static struct spi_driver adav80x_spi_driver = { 932 .driver = { 933 .name = "adav801", 934 .owner = THIS_MODULE, 935 }, 936 .probe = adav80x_spi_probe, 937 .remove = adav80x_spi_remove, 938 .id_table = adav80x_spi_id, 939 }; 940 #endif 941 942 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 943 static const struct regmap_config adav80x_i2c_regmap_config = { 944 .val_bits = 8, 945 .pad_bits = 1, 946 .reg_bits = 7, 947 948 .max_register = ADAV80X_PLL_OUTE, 949 950 .cache_type = REGCACHE_RBTREE, 951 .reg_defaults = adav80x_reg_defaults, 952 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults), 953 }; 954 955 static const struct i2c_device_id adav80x_i2c_id[] = { 956 { "adav803", 0 }, 957 { } 958 }; 959 MODULE_DEVICE_TABLE(i2c, adav80x_i2c_id); 960 961 static int adav80x_i2c_probe(struct i2c_client *client, 962 const struct i2c_device_id *id) 963 { 964 return adav80x_bus_probe(&client->dev, 965 devm_regmap_init_i2c(client, &adav80x_i2c_regmap_config)); 966 } 967 968 static int adav80x_i2c_remove(struct i2c_client *client) 969 { 970 return adav80x_bus_remove(&client->dev); 971 } 972 973 static struct i2c_driver adav80x_i2c_driver = { 974 .driver = { 975 .name = "adav803", 976 .owner = THIS_MODULE, 977 }, 978 .probe = adav80x_i2c_probe, 979 .remove = adav80x_i2c_remove, 980 .id_table = adav80x_i2c_id, 981 }; 982 #endif 983 984 static int __init adav80x_init(void) 985 { 986 int ret = 0; 987 988 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 989 ret = i2c_add_driver(&adav80x_i2c_driver); 990 if (ret) 991 return ret; 992 #endif 993 994 #if defined(CONFIG_SPI_MASTER) 995 ret = spi_register_driver(&adav80x_spi_driver); 996 #endif 997 998 return ret; 999 } 1000 module_init(adav80x_init); 1001 1002 static void __exit adav80x_exit(void) 1003 { 1004 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1005 i2c_del_driver(&adav80x_i2c_driver); 1006 #endif 1007 #if defined(CONFIG_SPI_MASTER) 1008 spi_unregister_driver(&adav80x_spi_driver); 1009 #endif 1010 } 1011 module_exit(adav80x_exit); 1012 1013 MODULE_DESCRIPTION("ASoC ADAV80x driver"); 1014 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 1015 MODULE_AUTHOR("Yi Li <yi.li@analog.com>>"); 1016 MODULE_LICENSE("GPL"); 1017