xref: /linux/sound/soc/codecs/adau17x1.h (revision b6ebbac51bedf9e98e837688bc838f400196da5e)
1 #ifndef __ADAU17X1_H__
2 #define __ADAU17X1_H__
3 
4 #include <linux/regmap.h>
5 #include <linux/platform_data/adau17x1.h>
6 
7 #include "sigmadsp.h"
8 
9 enum adau17x1_type {
10 	ADAU1361,
11 	ADAU1761,
12 	ADAU1381,
13 	ADAU1781,
14 };
15 
16 enum adau17x1_pll {
17 	ADAU17X1_PLL,
18 };
19 
20 enum adau17x1_pll_src {
21 	ADAU17X1_PLL_SRC_MCLK,
22 };
23 
24 enum adau17x1_clk_src {
25 	/* Automatically configure PLL based on the sample rate */
26 	ADAU17X1_CLK_SRC_PLL_AUTO,
27 	ADAU17X1_CLK_SRC_MCLK,
28 	ADAU17X1_CLK_SRC_PLL,
29 };
30 
31 struct clk;
32 
33 struct adau {
34 	unsigned int sysclk;
35 	unsigned int pll_freq;
36 	struct clk *mclk;
37 
38 	enum adau17x1_clk_src clk_src;
39 	enum adau17x1_type type;
40 	void (*switch_mode)(struct device *dev);
41 
42 	unsigned int dai_fmt;
43 
44 	uint8_t pll_regs[6];
45 
46 	bool master;
47 
48 	unsigned int tdm_slot[2];
49 	bool dsp_bypass[2];
50 
51 	struct regmap *regmap;
52 	struct sigmadsp *sigmadsp;
53 };
54 
55 int adau17x1_add_widgets(struct snd_soc_codec *codec);
56 int adau17x1_add_routes(struct snd_soc_codec *codec);
57 int adau17x1_probe(struct device *dev, struct regmap *regmap,
58 	enum adau17x1_type type, void (*switch_mode)(struct device *dev),
59 	const char *firmware_name);
60 void adau17x1_remove(struct device *dev);
61 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
62 	enum adau17x1_micbias_voltage micbias);
63 bool adau17x1_readable_register(struct device *dev, unsigned int reg);
64 bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
65 bool adau17x1_precious_register(struct device *dev, unsigned int reg);
66 int adau17x1_resume(struct snd_soc_codec *codec);
67 
68 extern const struct snd_soc_dai_ops adau17x1_dai_ops;
69 
70 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate);
71 bool adau17x1_has_dsp(struct adau *adau);
72 
73 #define ADAU17X1_CLOCK_CONTROL			0x4000
74 #define ADAU17X1_PLL_CONTROL			0x4002
75 #define ADAU17X1_REC_POWER_MGMT			0x4009
76 #define ADAU17X1_MICBIAS			0x4010
77 #define ADAU17X1_SERIAL_PORT0			0x4015
78 #define ADAU17X1_SERIAL_PORT1			0x4016
79 #define ADAU17X1_CONVERTER0			0x4017
80 #define ADAU17X1_CONVERTER1			0x4018
81 #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL		0x401a
82 #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL	0x401b
83 #define ADAU17X1_ADC_CONTROL			0x4019
84 #define ADAU17X1_PLAY_POWER_MGMT		0x4029
85 #define ADAU17X1_DAC_CONTROL0			0x402a
86 #define ADAU17X1_DAC_CONTROL1			0x402b
87 #define ADAU17X1_DAC_CONTROL2			0x402c
88 #define ADAU17X1_SERIAL_PORT_PAD		0x402d
89 #define ADAU17X1_CONTROL_PORT_PAD0		0x402f
90 #define ADAU17X1_CONTROL_PORT_PAD1		0x4030
91 #define ADAU17X1_DSP_SAMPLING_RATE		0x40eb
92 #define ADAU17X1_SERIAL_INPUT_ROUTE		0x40f2
93 #define ADAU17X1_SERIAL_OUTPUT_ROUTE		0x40f3
94 #define ADAU17X1_DSP_ENABLE			0x40f5
95 #define ADAU17X1_DSP_RUN			0x40f6
96 #define ADAU17X1_SERIAL_SAMPLING_RATE		0x40f8
97 
98 #define ADAU17X1_SERIAL_PORT0_BCLK_POL		BIT(4)
99 #define ADAU17X1_SERIAL_PORT0_LRCLK_POL		BIT(3)
100 #define ADAU17X1_SERIAL_PORT0_MASTER		BIT(0)
101 
102 #define ADAU17X1_SERIAL_PORT1_DELAY1		0x00
103 #define ADAU17X1_SERIAL_PORT1_DELAY0		0x01
104 #define ADAU17X1_SERIAL_PORT1_DELAY8		0x02
105 #define ADAU17X1_SERIAL_PORT1_DELAY16		0x03
106 #define ADAU17X1_SERIAL_PORT1_DELAY_MASK	0x03
107 
108 #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK	0x6
109 #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL	BIT(3)
110 #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN	BIT(0)
111 
112 #define ADAU17X1_SERIAL_PORT1_BCLK64		(0x0 << 5)
113 #define ADAU17X1_SERIAL_PORT1_BCLK32		(0x1 << 5)
114 #define ADAU17X1_SERIAL_PORT1_BCLK48		(0x2 << 5)
115 #define ADAU17X1_SERIAL_PORT1_BCLK128		(0x3 << 5)
116 #define ADAU17X1_SERIAL_PORT1_BCLK256		(0x4 << 5)
117 #define ADAU17X1_SERIAL_PORT1_BCLK_MASK		(0x7 << 5)
118 
119 #define ADAU17X1_SERIAL_PORT0_STEREO		(0x0 << 1)
120 #define ADAU17X1_SERIAL_PORT0_TDM4		(0x1 << 1)
121 #define ADAU17X1_SERIAL_PORT0_TDM8		(0x2 << 1)
122 #define ADAU17X1_SERIAL_PORT0_TDM_MASK		(0x3 << 1)
123 #define ADAU17X1_SERIAL_PORT0_PULSE_MODE	BIT(5)
124 
125 #define ADAU17X1_CONVERTER0_DAC_PAIR(x)		(((x) - 1) << 5)
126 #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK	(0x3 << 5)
127 #define ADAU17X1_CONVERTER1_ADC_PAIR(x)		((x) - 1)
128 #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK	0x3
129 
130 #define ADAU17X1_CONVERTER0_CONVSR_MASK		0x7
131 
132 
133 #endif
134