1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2012 4 * 5 * Author: Ola Lilja <ola.o.lilja@stericsson.com>, 6 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>, 7 * Roger Nilsson <roger.xr.nilsson@stericsson.com>, 8 * for ST-Ericsson. 9 * 10 * Based on the early work done by: 11 * Mikko J. Lehto <mikko.lehto@symbio.com>, 12 * Mikko Sarmanne <mikko.sarmanne@symbio.com>, 13 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>, 14 * for ST-Ericsson. 15 */ 16 17 #include <linux/cleanup.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/slab.h> 22 #include <linux/moduleparam.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/pm.h> 26 #include <linux/platform_device.h> 27 #include <linux/mutex.h> 28 #include <linux/mfd/abx500/ab8500.h> 29 #include <linux/mfd/abx500.h> 30 #include <linux/mfd/abx500/ab8500-sysctrl.h> 31 #include <linux/mfd/abx500/ab8500-codec.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/of.h> 34 35 #include <sound/core.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/initval.h> 39 #include <sound/soc.h> 40 #include <sound/soc-dapm.h> 41 #include <sound/tlv.h> 42 43 #include "ab8500-codec.h" 44 45 /* Macrocell value definitions */ 46 #define CLK_32K_OUT2_DISABLE 0x01 47 #define INACTIVE_RESET_AUDIO 0x02 48 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10 49 #define ENABLE_VINTCORE12_SUPPLY 0x04 50 #define GPIO27_DIR_OUTPUT 0x04 51 #define GPIO29_DIR_OUTPUT 0x10 52 #define GPIO31_DIR_OUTPUT 0x40 53 54 /* Macrocell register definitions */ 55 #define AB8500_GPIO_DIR4_REG 0x13 /* Bank AB8500_MISC */ 56 57 /* Nr of FIR/IIR-coeff banks in ANC-block */ 58 #define AB8500_NR_OF_ANC_COEFF_BANKS 2 59 60 /* Minimum duration to keep ANC IIR Init bit high or 61 low before proceeding with the configuration sequence */ 62 #define AB8500_ANC_SM_DELAY 2000 63 64 /* Sidetone states */ 65 static const char * const enum_sid_state[] = { 66 "Unconfigured", 67 "Apply FIR", 68 "FIR is configured", 69 }; 70 enum sid_state { 71 SID_UNCONFIGURED = 0, 72 SID_APPLY_FIR = 1, 73 SID_FIR_CONFIGURED = 2, 74 }; 75 76 /* Private data for AB8500 device-driver */ 77 struct ab8500_codec_drvdata { 78 struct regmap *regmap; 79 struct mutex ctrl_lock; 80 81 /* Sidetone */ 82 enum sid_state sid_status; 83 }; 84 85 static inline const char *amic_micbias_str(enum amic_micbias micbias) 86 { 87 switch (micbias) { 88 case AMIC_MICBIAS_VAMIC1: 89 return "VAMIC1"; 90 case AMIC_MICBIAS_VAMIC2: 91 return "VAMIC2"; 92 default: 93 return "Unknown"; 94 } 95 } 96 97 static inline const char *amic_type_str(enum amic_type type) 98 { 99 switch (type) { 100 case AMIC_TYPE_DIFFERENTIAL: 101 return "DIFFERENTIAL"; 102 case AMIC_TYPE_SINGLE_ENDED: 103 return "SINGLE ENDED"; 104 default: 105 return "Unknown"; 106 } 107 } 108 109 /* 110 * Read'n'write functions 111 */ 112 113 /* Read a register from the audio-bank of AB8500 */ 114 static int ab8500_codec_read_reg(void *context, unsigned int reg, 115 unsigned int *value) 116 { 117 struct device *dev = context; 118 int status; 119 120 u8 value8; 121 status = abx500_get_register_interruptible(dev, AB8500_AUDIO, 122 reg, &value8); 123 *value = (unsigned int)value8; 124 125 return status; 126 } 127 128 /* Write to a register in the audio-bank of AB8500 */ 129 static int ab8500_codec_write_reg(void *context, unsigned int reg, 130 unsigned int value) 131 { 132 struct device *dev = context; 133 134 return abx500_set_register_interruptible(dev, AB8500_AUDIO, 135 reg, value); 136 } 137 138 static const struct regmap_config ab8500_codec_regmap = { 139 .reg_read = ab8500_codec_read_reg, 140 .reg_write = ab8500_codec_write_reg, 141 }; 142 143 /* 144 * Controls - DAPM 145 */ 146 147 /* Earpiece */ 148 149 /* Earpiece source selector */ 150 static const char * const enum_ear_lineout_source[] = {"Headset Left", 151 "Speaker Left"}; 152 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF, 153 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source); 154 static const struct snd_kcontrol_new dapm_ear_lineout_source = 155 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source", 156 dapm_enum_ear_lineout_source); 157 158 /* LineOut */ 159 160 /* LineOut source selector */ 161 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"}; 162 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5, 163 AB8500_ANACONF5_HSLDACTOLOL, 164 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source); 165 static const struct snd_kcontrol_new dapm_lineout_source[] = { 166 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source), 167 }; 168 169 /* Handsfree */ 170 171 /* Speaker Left - ANC selector */ 172 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"}; 173 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2, 174 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel); 175 static const struct snd_kcontrol_new dapm_HFl_select[] = { 176 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel), 177 }; 178 179 /* Speaker Right - ANC selector */ 180 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2, 181 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel); 182 static const struct snd_kcontrol_new dapm_HFr_select[] = { 183 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel), 184 }; 185 186 /* Mic 1 */ 187 188 /* Mic 1 - Mic 1a or 1b selector */ 189 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"}; 190 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3, 191 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel); 192 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = { 193 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel), 194 }; 195 196 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */ 197 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"}; 198 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1, 199 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel); 200 static const struct snd_kcontrol_new dapm_ad3_select[] = { 201 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel), 202 }; 203 204 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */ 205 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"}; 206 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1, 207 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel); 208 static const struct snd_kcontrol_new dapm_ad6_select[] = { 209 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel), 210 }; 211 212 /* Mic 2 */ 213 214 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */ 215 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"}; 216 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1, 217 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel); 218 static const struct snd_kcontrol_new dapm_ad5_select[] = { 219 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel), 220 }; 221 222 /* LineIn */ 223 224 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */ 225 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"}; 226 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1, 227 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel); 228 static const struct snd_kcontrol_new dapm_ad1_select[] = { 229 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel), 230 }; 231 232 /* LineIn right - Mic 2 or LineIn Right selector */ 233 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"}; 234 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3, 235 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel); 236 static const struct snd_kcontrol_new dapm_mic2lr_select[] = { 237 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel), 238 }; 239 240 /* LineIn right - AD2 - LineIn Right or DMic2 selector */ 241 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"}; 242 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1, 243 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel); 244 static const struct snd_kcontrol_new dapm_ad2_select[] = { 245 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel), 246 }; 247 248 249 /* ANC */ 250 251 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6", 252 "Mic 2 / DMic 5"}; 253 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF, 254 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel); 255 static const struct snd_kcontrol_new dapm_anc_in_select[] = { 256 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel), 257 }; 258 259 /* ANC - Enable/Disable */ 260 static const struct snd_kcontrol_new dapm_anc_enable[] = { 261 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1, 262 AB8500_ANCCONF1_ENANC, 0, 0), 263 }; 264 265 /* ANC to Earpiece - Mute */ 266 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = { 267 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1, 268 AB8500_DIGMULTCONF1_ANCSEL, 1, 0), 269 }; 270 271 272 273 /* Sidetone left */ 274 275 /* Sidetone left - Input selector */ 276 static const char * const enum_stfir1_in_sel[] = { 277 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left" 278 }; 279 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2, 280 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel); 281 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = { 282 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel), 283 }; 284 285 /* Sidetone right path */ 286 287 /* Sidetone right - Input selector */ 288 static const char * const enum_stfir2_in_sel[] = { 289 "LineIn Right", "Mic 1", "DMic 4", "Headset Right" 290 }; 291 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2, 292 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel); 293 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = { 294 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel), 295 }; 296 297 /* Vibra */ 298 299 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"}; 300 301 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1, 302 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx); 303 304 static const struct snd_kcontrol_new dapm_pwm2vib1[] = { 305 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1), 306 }; 307 308 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1, 309 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx); 310 311 static const struct snd_kcontrol_new dapm_pwm2vib2[] = { 312 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2), 313 }; 314 315 /* 316 * DAPM-widgets 317 */ 318 319 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = { 320 321 /* Clocks */ 322 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"), 323 324 /* Regulators */ 325 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0), 326 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0), 327 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0), 328 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0), 329 330 /* Power */ 331 SND_SOC_DAPM_SUPPLY("Audio Power", 332 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0, 333 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 334 SND_SOC_DAPM_SUPPLY("Audio Analog Power", 335 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0, 336 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 337 338 /* Main supply node */ 339 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0, 340 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 341 342 /* DA/AD */ 343 344 SND_SOC_DAPM_INPUT("ADC Input"), 345 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0), 346 347 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0), 348 SND_SOC_DAPM_OUTPUT("DAC Output"), 349 350 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0), 351 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0), 352 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0), 353 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0), 354 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0), 355 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0), 356 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0), 357 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0), 358 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0), 359 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0), 360 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0), 361 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0), 362 363 /* Headset path */ 364 365 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5, 366 AB8500_ANACONF5_ENCPHS, 0, NULL, 0), 367 368 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p", 369 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0), 370 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p", 371 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0), 372 373 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0, 374 NULL, 0), 375 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0, 376 NULL, 0), 377 378 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p", 379 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0), 380 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p", 381 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0), 382 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF, 383 AB8500_MUTECONF_MUTDACHSL, 1, 384 NULL, 0), 385 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF, 386 AB8500_MUTECONF_MUTDACHSR, 1, 387 NULL, 0), 388 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p", 389 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0), 390 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p", 391 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0), 392 393 SND_SOC_DAPM_MIXER("HSL Mute", 394 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1, 395 NULL, 0), 396 SND_SOC_DAPM_MIXER("HSR Mute", 397 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1, 398 NULL, 0), 399 SND_SOC_DAPM_MIXER("HSL Enable", 400 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0, 401 NULL, 0), 402 SND_SOC_DAPM_MIXER("HSR Enable", 403 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0, 404 NULL, 0), 405 SND_SOC_DAPM_PGA("HSL Volume", 406 SND_SOC_NOPM, 0, 0, 407 NULL, 0), 408 SND_SOC_DAPM_PGA("HSR Volume", 409 SND_SOC_NOPM, 0, 0, 410 NULL, 0), 411 412 SND_SOC_DAPM_OUTPUT("Headset Left"), 413 SND_SOC_DAPM_OUTPUT("Headset Right"), 414 415 /* LineOut path */ 416 417 SND_SOC_DAPM_MUX("LineOut Source", 418 SND_SOC_NOPM, 0, 0, dapm_lineout_source), 419 420 SND_SOC_DAPM_MIXER("LOL Disable HFL", 421 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1, 422 NULL, 0), 423 SND_SOC_DAPM_MIXER("LOR Disable HFR", 424 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1, 425 NULL, 0), 426 427 SND_SOC_DAPM_MIXER("LOL Enable", 428 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0, 429 NULL, 0), 430 SND_SOC_DAPM_MIXER("LOR Enable", 431 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0, 432 NULL, 0), 433 434 SND_SOC_DAPM_OUTPUT("LineOut Left"), 435 SND_SOC_DAPM_OUTPUT("LineOut Right"), 436 437 /* Earpiece path */ 438 439 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source", 440 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source), 441 SND_SOC_DAPM_MIXER("EAR DAC", 442 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0, 443 NULL, 0), 444 SND_SOC_DAPM_MIXER("EAR Mute", 445 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1, 446 NULL, 0), 447 SND_SOC_DAPM_MIXER("EAR Enable", 448 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0, 449 NULL, 0), 450 451 SND_SOC_DAPM_OUTPUT("Earpiece"), 452 453 /* Handsfree path */ 454 455 SND_SOC_DAPM_MIXER("DA3 Channel Volume", 456 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0, 457 NULL, 0), 458 SND_SOC_DAPM_MIXER("DA4 Channel Volume", 459 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0, 460 NULL, 0), 461 SND_SOC_DAPM_MUX("Speaker Left Source", 462 SND_SOC_NOPM, 0, 0, dapm_HFl_select), 463 SND_SOC_DAPM_MUX("Speaker Right Source", 464 SND_SOC_NOPM, 0, 0, dapm_HFr_select), 465 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF, 466 AB8500_DAPATHCONF_ENDACHFL, 0, 467 NULL, 0), 468 SND_SOC_DAPM_MIXER("HFR DAC", 469 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0, 470 NULL, 0), 471 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR", 472 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0, 473 NULL, 0), 474 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL", 475 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0, 476 NULL, 0), 477 SND_SOC_DAPM_MIXER("HFL Enable", 478 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0, 479 NULL, 0), 480 SND_SOC_DAPM_MIXER("HFR Enable", 481 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0, 482 NULL, 0), 483 484 SND_SOC_DAPM_OUTPUT("Speaker Left"), 485 SND_SOC_DAPM_OUTPUT("Speaker Right"), 486 487 /* Vibrator path */ 488 489 SND_SOC_DAPM_INPUT("PWMGEN1"), 490 SND_SOC_DAPM_INPUT("PWMGEN2"), 491 492 SND_SOC_DAPM_MIXER("DA5 Channel Volume", 493 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0, 494 NULL, 0), 495 SND_SOC_DAPM_MIXER("DA6 Channel Volume", 496 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0, 497 NULL, 0), 498 SND_SOC_DAPM_MIXER("VIB1 DAC", 499 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0, 500 NULL, 0), 501 SND_SOC_DAPM_MIXER("VIB2 DAC", 502 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0, 503 NULL, 0), 504 SND_SOC_DAPM_MUX("Vibra 1 Controller", 505 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1), 506 SND_SOC_DAPM_MUX("Vibra 2 Controller", 507 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2), 508 SND_SOC_DAPM_MIXER("VIB1 Enable", 509 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0, 510 NULL, 0), 511 SND_SOC_DAPM_MIXER("VIB2 Enable", 512 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0, 513 NULL, 0), 514 515 SND_SOC_DAPM_OUTPUT("Vibra 1"), 516 SND_SOC_DAPM_OUTPUT("Vibra 2"), 517 518 /* Mic 1 */ 519 520 SND_SOC_DAPM_INPUT("Mic 1"), 521 522 SND_SOC_DAPM_MUX("Mic 1a or 1b Select", 523 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux), 524 SND_SOC_DAPM_MIXER("MIC1 Mute", 525 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1, 526 NULL, 0), 527 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable", 528 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 529 NULL, 0), 530 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable", 531 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0, 532 NULL, 0), 533 SND_SOC_DAPM_MIXER("MIC1 ADC", 534 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0, 535 NULL, 0), 536 SND_SOC_DAPM_MUX("AD3 Source Select", 537 SND_SOC_NOPM, 0, 0, dapm_ad3_select), 538 SND_SOC_DAPM_MIXER("AD3 Channel Volume", 539 SND_SOC_NOPM, 0, 0, 540 NULL, 0), 541 SND_SOC_DAPM_MIXER("AD3 Enable", 542 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0, 543 NULL, 0), 544 545 /* Mic 2 */ 546 547 SND_SOC_DAPM_INPUT("Mic 2"), 548 549 SND_SOC_DAPM_MIXER("MIC2 Mute", 550 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1, 551 NULL, 0), 552 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2, 553 AB8500_ANACONF2_ENMIC2, 0, 554 NULL, 0), 555 556 /* LineIn */ 557 558 SND_SOC_DAPM_INPUT("LineIn Left"), 559 SND_SOC_DAPM_INPUT("LineIn Right"), 560 561 SND_SOC_DAPM_MIXER("LINL Mute", 562 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1, 563 NULL, 0), 564 SND_SOC_DAPM_MIXER("LINR Mute", 565 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1, 566 NULL, 0), 567 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2, 568 AB8500_ANACONF2_ENLINL, 0, 569 NULL, 0), 570 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2, 571 AB8500_ANACONF2_ENLINR, 0, 572 NULL, 0), 573 574 /* LineIn Bypass path */ 575 SND_SOC_DAPM_MIXER("LINL to HSL Volume", 576 SND_SOC_NOPM, 0, 0, 577 NULL, 0), 578 SND_SOC_DAPM_MIXER("LINR to HSR Volume", 579 SND_SOC_NOPM, 0, 0, 580 NULL, 0), 581 582 /* LineIn, Mic 2 */ 583 SND_SOC_DAPM_MUX("Mic 2 or LINR Select", 584 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select), 585 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3, 586 AB8500_ANACONF3_ENADCLINL, 0, 587 NULL, 0), 588 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3, 589 AB8500_ANACONF3_ENADCLINR, 0, 590 NULL, 0), 591 SND_SOC_DAPM_MUX("AD1 Source Select", 592 SND_SOC_NOPM, 0, 0, dapm_ad1_select), 593 SND_SOC_DAPM_MUX("AD2 Source Select", 594 SND_SOC_NOPM, 0, 0, dapm_ad2_select), 595 SND_SOC_DAPM_MIXER("AD1 Channel Volume", 596 SND_SOC_NOPM, 0, 0, 597 NULL, 0), 598 SND_SOC_DAPM_MIXER("AD2 Channel Volume", 599 SND_SOC_NOPM, 0, 0, 600 NULL, 0), 601 602 SND_SOC_DAPM_MIXER("AD12 Enable", 603 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0, 604 NULL, 0), 605 606 /* HD Capture path */ 607 608 SND_SOC_DAPM_MUX("AD5 Source Select", 609 SND_SOC_NOPM, 0, 0, dapm_ad5_select), 610 SND_SOC_DAPM_MUX("AD6 Source Select", 611 SND_SOC_NOPM, 0, 0, dapm_ad6_select), 612 SND_SOC_DAPM_MIXER("AD5 Channel Volume", 613 SND_SOC_NOPM, 0, 0, 614 NULL, 0), 615 SND_SOC_DAPM_MIXER("AD6 Channel Volume", 616 SND_SOC_NOPM, 0, 0, 617 NULL, 0), 618 SND_SOC_DAPM_MIXER("AD57 Enable", 619 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 620 NULL, 0), 621 SND_SOC_DAPM_MIXER("AD68 Enable", 622 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0, 623 NULL, 0), 624 625 /* Digital Microphone path */ 626 627 SND_SOC_DAPM_INPUT("DMic 1"), 628 SND_SOC_DAPM_INPUT("DMic 2"), 629 SND_SOC_DAPM_INPUT("DMic 3"), 630 SND_SOC_DAPM_INPUT("DMic 4"), 631 SND_SOC_DAPM_INPUT("DMic 5"), 632 SND_SOC_DAPM_INPUT("DMic 6"), 633 634 SND_SOC_DAPM_MIXER("DMIC1", 635 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0, 636 NULL, 0), 637 SND_SOC_DAPM_MIXER("DMIC2", 638 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0, 639 NULL, 0), 640 SND_SOC_DAPM_MIXER("DMIC3", 641 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0, 642 NULL, 0), 643 SND_SOC_DAPM_MIXER("DMIC4", 644 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0, 645 NULL, 0), 646 SND_SOC_DAPM_MIXER("DMIC5", 647 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0, 648 NULL, 0), 649 SND_SOC_DAPM_MIXER("DMIC6", 650 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0, 651 NULL, 0), 652 SND_SOC_DAPM_MIXER("AD4 Channel Volume", 653 SND_SOC_NOPM, 0, 0, 654 NULL, 0), 655 SND_SOC_DAPM_MIXER("AD4 Enable", 656 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 657 0, NULL, 0), 658 659 /* Acoustical Noise Cancellation path */ 660 661 SND_SOC_DAPM_INPUT("ANC Configure Input"), 662 SND_SOC_DAPM_OUTPUT("ANC Configure Output"), 663 664 SND_SOC_DAPM_MUX("ANC Source", 665 SND_SOC_NOPM, 0, 0, 666 dapm_anc_in_select), 667 SND_SOC_DAPM_SWITCH("ANC", 668 SND_SOC_NOPM, 0, 0, 669 dapm_anc_enable), 670 SND_SOC_DAPM_SWITCH("ANC to Earpiece", 671 SND_SOC_NOPM, 0, 0, 672 dapm_anc_ear_mute), 673 674 /* Sidetone Filter path */ 675 676 SND_SOC_DAPM_MUX("Sidetone Left Source", 677 SND_SOC_NOPM, 0, 0, 678 dapm_stfir1_in_select), 679 SND_SOC_DAPM_MUX("Sidetone Right Source", 680 SND_SOC_NOPM, 0, 0, 681 dapm_stfir2_in_select), 682 SND_SOC_DAPM_MIXER("STFIR1 Control", 683 SND_SOC_NOPM, 0, 0, 684 NULL, 0), 685 SND_SOC_DAPM_MIXER("STFIR2 Control", 686 SND_SOC_NOPM, 0, 0, 687 NULL, 0), 688 SND_SOC_DAPM_MIXER("STFIR1 Volume", 689 SND_SOC_NOPM, 0, 0, 690 NULL, 0), 691 SND_SOC_DAPM_MIXER("STFIR2 Volume", 692 SND_SOC_NOPM, 0, 0, 693 NULL, 0), 694 }; 695 696 /* 697 * DAPM-routes 698 */ 699 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = { 700 /* Power AB8500 audio-block when AD/DA is active */ 701 {"Main Supply", NULL, "V-AUD"}, 702 {"Main Supply", NULL, "audioclk"}, 703 {"Main Supply", NULL, "Audio Power"}, 704 {"Main Supply", NULL, "Audio Analog Power"}, 705 706 {"DAC", NULL, "ab8500_0p"}, 707 {"DAC", NULL, "Main Supply"}, 708 {"ADC", NULL, "ab8500_0c"}, 709 {"ADC", NULL, "Main Supply"}, 710 711 /* ANC Configure */ 712 {"ANC Configure Input", NULL, "Main Supply"}, 713 {"ANC Configure Output", NULL, "ANC Configure Input"}, 714 715 /* AD/DA */ 716 {"ADC", NULL, "ADC Input"}, 717 {"DAC Output", NULL, "DAC"}, 718 719 /* Powerup charge pump if DA1/2 is in use */ 720 721 {"DA_IN1", NULL, "ab8500_0p"}, 722 {"DA_IN1", NULL, "Charge Pump"}, 723 {"DA_IN2", NULL, "ab8500_0p"}, 724 {"DA_IN2", NULL, "Charge Pump"}, 725 726 /* Headset path */ 727 728 {"DA1 Enable", NULL, "DA_IN1"}, 729 {"DA2 Enable", NULL, "DA_IN2"}, 730 731 {"HSL Digital Volume", NULL, "DA1 Enable"}, 732 {"HSR Digital Volume", NULL, "DA2 Enable"}, 733 734 {"HSL DAC", NULL, "HSL Digital Volume"}, 735 {"HSR DAC", NULL, "HSR Digital Volume"}, 736 737 {"HSL DAC Mute", NULL, "HSL DAC"}, 738 {"HSR DAC Mute", NULL, "HSR DAC"}, 739 740 {"HSL DAC Driver", NULL, "HSL DAC Mute"}, 741 {"HSR DAC Driver", NULL, "HSR DAC Mute"}, 742 743 {"HSL Mute", NULL, "HSL DAC Driver"}, 744 {"HSR Mute", NULL, "HSR DAC Driver"}, 745 746 {"HSL Enable", NULL, "HSL Mute"}, 747 {"HSR Enable", NULL, "HSR Mute"}, 748 749 {"HSL Volume", NULL, "HSL Enable"}, 750 {"HSR Volume", NULL, "HSR Enable"}, 751 752 {"Headset Left", NULL, "HSL Volume"}, 753 {"Headset Right", NULL, "HSR Volume"}, 754 755 /* HF or LineOut path */ 756 757 {"DA_IN3", NULL, "ab8500_0p"}, 758 {"DA3 Channel Volume", NULL, "DA_IN3"}, 759 {"DA_IN4", NULL, "ab8500_0p"}, 760 {"DA4 Channel Volume", NULL, "DA_IN4"}, 761 762 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"}, 763 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"}, 764 765 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"}, 766 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"}, 767 768 /* HF path */ 769 770 {"HFL DAC", NULL, "DA3 or ANC path to HfL"}, 771 {"HFR DAC", NULL, "DA4 or ANC path to HfR"}, 772 773 {"HFL Enable", NULL, "HFL DAC"}, 774 {"HFR Enable", NULL, "HFR DAC"}, 775 776 {"Speaker Left", NULL, "HFL Enable"}, 777 {"Speaker Right", NULL, "HFR Enable"}, 778 779 /* Earpiece path */ 780 781 {"Earpiece or LineOut Mono Source", "Headset Left", 782 "HSL Digital Volume"}, 783 {"Earpiece or LineOut Mono Source", "Speaker Left", 784 "DA3 or ANC path to HfL"}, 785 786 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"}, 787 788 {"EAR Mute", NULL, "EAR DAC"}, 789 790 {"EAR Enable", NULL, "EAR Mute"}, 791 792 {"Earpiece", NULL, "EAR Enable"}, 793 794 /* LineOut path stereo */ 795 796 {"LineOut Source", "Stereo Path", "HSL DAC Driver"}, 797 {"LineOut Source", "Stereo Path", "HSR DAC Driver"}, 798 799 /* LineOut path mono */ 800 801 {"LineOut Source", "Mono Path", "EAR DAC"}, 802 803 /* LineOut path */ 804 805 {"LOL Disable HFL", NULL, "LineOut Source"}, 806 {"LOR Disable HFR", NULL, "LineOut Source"}, 807 808 {"LOL Enable", NULL, "LOL Disable HFL"}, 809 {"LOR Enable", NULL, "LOR Disable HFR"}, 810 811 {"LineOut Left", NULL, "LOL Enable"}, 812 {"LineOut Right", NULL, "LOR Enable"}, 813 814 /* Vibrator path */ 815 816 {"DA_IN5", NULL, "ab8500_0p"}, 817 {"DA5 Channel Volume", NULL, "DA_IN5"}, 818 {"DA_IN6", NULL, "ab8500_0p"}, 819 {"DA6 Channel Volume", NULL, "DA_IN6"}, 820 821 {"VIB1 DAC", NULL, "DA5 Channel Volume"}, 822 {"VIB2 DAC", NULL, "DA6 Channel Volume"}, 823 824 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"}, 825 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"}, 826 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"}, 827 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"}, 828 829 {"VIB1 Enable", NULL, "Vibra 1 Controller"}, 830 {"VIB2 Enable", NULL, "Vibra 2 Controller"}, 831 832 {"Vibra 1", NULL, "VIB1 Enable"}, 833 {"Vibra 2", NULL, "VIB2 Enable"}, 834 835 836 /* Mic 2 */ 837 838 {"MIC2 V-AMICx Enable", NULL, "Mic 2"}, 839 840 /* LineIn */ 841 {"LINL Mute", NULL, "LineIn Left"}, 842 {"LINR Mute", NULL, "LineIn Right"}, 843 844 {"LINL Enable", NULL, "LINL Mute"}, 845 {"LINR Enable", NULL, "LINR Mute"}, 846 847 /* LineIn, Mic 2 */ 848 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"}, 849 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"}, 850 851 {"LINL ADC", NULL, "LINL Enable"}, 852 {"LINR ADC", NULL, "Mic 2 or LINR Select"}, 853 854 {"AD1 Source Select", "LineIn Left", "LINL ADC"}, 855 {"AD2 Source Select", "LineIn Right", "LINR ADC"}, 856 857 {"AD1 Channel Volume", NULL, "AD1 Source Select"}, 858 {"AD2 Channel Volume", NULL, "AD2 Source Select"}, 859 860 {"AD12 Enable", NULL, "AD1 Channel Volume"}, 861 {"AD12 Enable", NULL, "AD2 Channel Volume"}, 862 863 {"AD_OUT1", NULL, "ab8500_0c"}, 864 {"AD_OUT1", NULL, "AD12 Enable"}, 865 {"AD_OUT2", NULL, "ab8500_0c"}, 866 {"AD_OUT2", NULL, "AD12 Enable"}, 867 868 /* Mic 1 */ 869 870 {"MIC1 Mute", NULL, "Mic 1"}, 871 872 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"}, 873 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"}, 874 875 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"}, 876 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"}, 877 878 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"}, 879 880 {"AD3 Source Select", "Mic 1", "MIC1 ADC"}, 881 882 {"AD3 Channel Volume", NULL, "AD3 Source Select"}, 883 884 {"AD3 Enable", NULL, "AD3 Channel Volume"}, 885 886 {"AD_OUT3", NULL, "ab8500_0c"}, 887 {"AD_OUT3", NULL, "AD3 Enable"}, 888 889 /* HD Capture path */ 890 891 {"AD5 Source Select", "Mic 2", "LINR ADC"}, 892 {"AD6 Source Select", "Mic 1", "MIC1 ADC"}, 893 894 {"AD5 Channel Volume", NULL, "AD5 Source Select"}, 895 {"AD6 Channel Volume", NULL, "AD6 Source Select"}, 896 897 {"AD57 Enable", NULL, "AD5 Channel Volume"}, 898 {"AD68 Enable", NULL, "AD6 Channel Volume"}, 899 900 {"AD_OUT57", NULL, "ab8500_0c"}, 901 {"AD_OUT57", NULL, "AD57 Enable"}, 902 {"AD_OUT68", NULL, "ab8500_0c"}, 903 {"AD_OUT68", NULL, "AD68 Enable"}, 904 905 /* Digital Microphone path */ 906 907 {"DMic 1", NULL, "V-DMIC"}, 908 {"DMic 2", NULL, "V-DMIC"}, 909 {"DMic 3", NULL, "V-DMIC"}, 910 {"DMic 4", NULL, "V-DMIC"}, 911 {"DMic 5", NULL, "V-DMIC"}, 912 {"DMic 6", NULL, "V-DMIC"}, 913 914 {"AD1 Source Select", NULL, "DMic 1"}, 915 {"AD2 Source Select", NULL, "DMic 2"}, 916 {"AD3 Source Select", NULL, "DMic 3"}, 917 {"AD5 Source Select", NULL, "DMic 5"}, 918 {"AD6 Source Select", NULL, "DMic 6"}, 919 920 {"AD4 Channel Volume", NULL, "DMic 4"}, 921 {"AD4 Enable", NULL, "AD4 Channel Volume"}, 922 923 {"AD_OUT4", NULL, "ab8500_0c"}, 924 {"AD_OUT4", NULL, "AD4 Enable"}, 925 926 /* LineIn Bypass path */ 927 928 {"LINL to HSL Volume", NULL, "LINL Enable"}, 929 {"LINR to HSR Volume", NULL, "LINR Enable"}, 930 931 {"HSL DAC Driver", NULL, "LINL to HSL Volume"}, 932 {"HSR DAC Driver", NULL, "LINR to HSR Volume"}, 933 934 /* ANC path (Acoustic Noise Cancellation) */ 935 936 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"}, 937 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"}, 938 939 {"ANC", "Switch", "ANC Source"}, 940 941 {"Speaker Left Source", "ANC", "ANC"}, 942 {"Speaker Right Source", "ANC", "ANC"}, 943 {"ANC to Earpiece", "Switch", "ANC"}, 944 945 {"HSL Digital Volume", NULL, "ANC to Earpiece"}, 946 947 /* Sidetone Filter path */ 948 949 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"}, 950 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"}, 951 {"Sidetone Left Source", "Mic 1", "AD3 Enable"}, 952 {"Sidetone Left Source", "Headset Left", "DA_IN1"}, 953 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"}, 954 {"Sidetone Right Source", "Mic 1", "AD3 Enable"}, 955 {"Sidetone Right Source", "DMic 4", "AD4 Enable"}, 956 {"Sidetone Right Source", "Headset Right", "DA_IN2"}, 957 958 {"STFIR1 Control", NULL, "Sidetone Left Source"}, 959 {"STFIR2 Control", NULL, "Sidetone Right Source"}, 960 961 {"STFIR1 Volume", NULL, "STFIR1 Control"}, 962 {"STFIR2 Volume", NULL, "STFIR2 Control"}, 963 964 {"DA1 Enable", NULL, "STFIR1 Volume"}, 965 {"DA2 Enable", NULL, "STFIR2 Volume"}, 966 }; 967 968 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = { 969 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"}, 970 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"}, 971 }; 972 973 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = { 974 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"}, 975 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"}, 976 }; 977 978 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = { 979 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"}, 980 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"}, 981 }; 982 983 /* 984 * Control-events 985 */ 986 987 static int sid_status_control_get(struct snd_kcontrol *kcontrol, 988 struct snd_ctl_elem_value *ucontrol) 989 { 990 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 991 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev); 992 993 guard(mutex)(&drvdata->ctrl_lock); 994 ucontrol->value.enumerated.item[0] = drvdata->sid_status; 995 996 return 0; 997 } 998 999 /* Write sidetone FIR-coefficients configuration sequence */ 1000 static int sid_status_control_put(struct snd_kcontrol *kcontrol, 1001 struct snd_ctl_elem_value *ucontrol) 1002 { 1003 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1004 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(component->dev); 1005 unsigned int param, sidconf; 1006 int status = 1; 1007 1008 dev_dbg(component->dev, "%s: Enter\n", __func__); 1009 1010 if (ucontrol->value.enumerated.item[0] != SID_APPLY_FIR) { 1011 dev_err(component->dev, 1012 "%s: ERROR: This control supports '%s' only!\n", 1013 __func__, enum_sid_state[SID_APPLY_FIR]); 1014 return -EIO; 1015 } 1016 1017 guard(mutex)(&drvdata->ctrl_lock); 1018 1019 sidconf = snd_soc_component_read(component, AB8500_SIDFIRCONF); 1020 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) { 1021 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) { 1022 dev_err(component->dev, "%s: Sidetone busy while off!\n", 1023 __func__); 1024 status = -EPERM; 1025 } else { 1026 status = -EBUSY; 1027 } 1028 dev_dbg(component->dev, "%s: Exit\n", __func__); 1029 return status; 1030 } 1031 1032 snd_soc_component_write(component, AB8500_SIDFIRADR, 0); 1033 1034 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) { 1035 snd_soc_component_write(component, AB8500_SIDFIRCOEF1, 0); 1036 snd_soc_component_write(component, AB8500_SIDFIRCOEF2, 0); 1037 } 1038 1039 snd_soc_component_update_bits(component, AB8500_SIDFIRADR, 1040 BIT(AB8500_SIDFIRADR_FIRSIDSET), 1041 BIT(AB8500_SIDFIRADR_FIRSIDSET)); 1042 snd_soc_component_update_bits(component, AB8500_SIDFIRADR, 1043 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0); 1044 1045 drvdata->sid_status = SID_FIR_CONFIGURED; 1046 1047 dev_dbg(component->dev, "%s: Exit\n", __func__); 1048 1049 return status; 1050 } 1051 1052 /* 1053 * Controls - Non-DAPM ASoC 1054 */ 1055 1056 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1); 1057 /* -32dB = Mute */ 1058 1059 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1); 1060 /* -63dB = Mute */ 1061 1062 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1); 1063 /* -1dB = Mute */ 1064 1065 static const DECLARE_TLV_DB_RANGE(hs_gain_tlv, 1066 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0), 1067 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0) 1068 ); 1069 1070 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0); 1071 1072 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0); 1073 1074 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1); 1075 /* -38dB = Mute */ 1076 1077 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms", 1078 "5ms"}; 1079 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed, 1080 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed); 1081 1082 static const char * const enum_envdetthre[] = { 1083 "250mV", "300mV", "350mV", "400mV", 1084 "450mV", "500mV", "550mV", "600mV", 1085 "650mV", "700mV", "750mV", "800mV", 1086 "850mV", "900mV", "950mV", "1.00V" }; 1087 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre, 1088 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre); 1089 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre, 1090 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre); 1091 static const char * const enum_envdettime[] = { 1092 "26.6us", "53.2us", "106us", "213us", 1093 "426us", "851us", "1.70ms", "3.40ms", 1094 "6.81ms", "13.6ms", "27.2ms", "54.5ms", 1095 "109ms", "218ms", "436ms", "872ms" }; 1096 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime, 1097 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime); 1098 1099 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"}; 1100 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN, 1101 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31); 1102 1103 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"}; 1104 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN, 1105 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed); 1106 1107 /* Earpiece */ 1108 1109 static const char * const enum_lowpow[] = {"Normal", "Low Power"}; 1110 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1, 1111 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow); 1112 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1, 1113 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow); 1114 1115 static const char * const enum_av_mode[] = {"Audio", "Voice"}; 1116 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF, 1117 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode); 1118 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF, 1119 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode); 1120 1121 /* DA */ 1122 1123 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice, 1124 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE, 1125 enum_av_mode); 1126 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice, 1127 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE, 1128 enum_av_mode); 1129 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice, 1130 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE, 1131 enum_av_mode); 1132 1133 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"}; 1134 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1, 1135 AB8500_DIGMULTCONF1_DATOHSLEN, 1136 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr); 1137 1138 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"}; 1139 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF, 1140 AB8500_DMICFILTCONF_DMIC1SINC3, 1141 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53); 1142 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF, 1143 AB8500_DMICFILTCONF_DMIC3SINC3, 1144 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53); 1145 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF, 1146 AB8500_DMICFILTCONF_DMIC5SINC3, 1147 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53); 1148 1149 /* Digital interface - DA from slot mapping */ 1150 static const char * const enum_da_from_slot_map[] = {"SLOT0", 1151 "SLOT1", 1152 "SLOT2", 1153 "SLOT3", 1154 "SLOT4", 1155 "SLOT5", 1156 "SLOT6", 1157 "SLOT7", 1158 "SLOT8", 1159 "SLOT9", 1160 "SLOT10", 1161 "SLOT11", 1162 "SLOT12", 1163 "SLOT13", 1164 "SLOT14", 1165 "SLOT15", 1166 "SLOT16", 1167 "SLOT17", 1168 "SLOT18", 1169 "SLOT19", 1170 "SLOT20", 1171 "SLOT21", 1172 "SLOT22", 1173 "SLOT23", 1174 "SLOT24", 1175 "SLOT25", 1176 "SLOT26", 1177 "SLOT27", 1178 "SLOT28", 1179 "SLOT29", 1180 "SLOT30", 1181 "SLOT31"}; 1182 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap, 1183 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1184 enum_da_from_slot_map); 1185 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap, 1186 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1187 enum_da_from_slot_map); 1188 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap, 1189 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1190 enum_da_from_slot_map); 1191 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap, 1192 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1193 enum_da_from_slot_map); 1194 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap, 1195 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1196 enum_da_from_slot_map); 1197 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap, 1198 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1199 enum_da_from_slot_map); 1200 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap, 1201 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1202 enum_da_from_slot_map); 1203 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap, 1204 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT, 1205 enum_da_from_slot_map); 1206 1207 /* Digital interface - AD to slot mapping */ 1208 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1", 1209 "AD_OUT2", 1210 "AD_OUT3", 1211 "AD_OUT4", 1212 "AD_OUT5", 1213 "AD_OUT6", 1214 "AD_OUT7", 1215 "AD_OUT8", 1216 "zeroes", 1217 "zeroes", 1218 "zeroes", 1219 "zeroes", 1220 "tristate", 1221 "tristate", 1222 "tristate", 1223 "tristate"}; 1224 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map, 1225 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT, 1226 enum_ad_to_slot_map); 1227 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map, 1228 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT, 1229 enum_ad_to_slot_map); 1230 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map, 1231 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT, 1232 enum_ad_to_slot_map); 1233 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map, 1234 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT, 1235 enum_ad_to_slot_map); 1236 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map, 1237 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT, 1238 enum_ad_to_slot_map); 1239 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map, 1240 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT, 1241 enum_ad_to_slot_map); 1242 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map, 1243 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT, 1244 enum_ad_to_slot_map); 1245 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map, 1246 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT, 1247 enum_ad_to_slot_map); 1248 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map, 1249 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT, 1250 enum_ad_to_slot_map); 1251 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map, 1252 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT, 1253 enum_ad_to_slot_map); 1254 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map, 1255 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT, 1256 enum_ad_to_slot_map); 1257 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map, 1258 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT, 1259 enum_ad_to_slot_map); 1260 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map, 1261 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT, 1262 enum_ad_to_slot_map); 1263 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map, 1264 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT, 1265 enum_ad_to_slot_map); 1266 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map, 1267 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT, 1268 enum_ad_to_slot_map); 1269 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map, 1270 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT, 1271 enum_ad_to_slot_map); 1272 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map, 1273 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT, 1274 enum_ad_to_slot_map); 1275 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map, 1276 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT, 1277 enum_ad_to_slot_map); 1278 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map, 1279 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT, 1280 enum_ad_to_slot_map); 1281 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map, 1282 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT, 1283 enum_ad_to_slot_map); 1284 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map, 1285 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT, 1286 enum_ad_to_slot_map); 1287 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map, 1288 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT, 1289 enum_ad_to_slot_map); 1290 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map, 1291 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT, 1292 enum_ad_to_slot_map); 1293 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map, 1294 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT, 1295 enum_ad_to_slot_map); 1296 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map, 1297 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT, 1298 enum_ad_to_slot_map); 1299 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map, 1300 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT, 1301 enum_ad_to_slot_map); 1302 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map, 1303 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT, 1304 enum_ad_to_slot_map); 1305 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map, 1306 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT, 1307 enum_ad_to_slot_map); 1308 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map, 1309 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT, 1310 enum_ad_to_slot_map); 1311 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map, 1312 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT, 1313 enum_ad_to_slot_map); 1314 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map, 1315 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT, 1316 enum_ad_to_slot_map); 1317 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map, 1318 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT, 1319 enum_ad_to_slot_map); 1320 1321 /* Digital interface - Burst mode */ 1322 static const char * const enum_mask[] = {"Unmasked", "Masked"}; 1323 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask, 1324 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK, 1325 enum_mask); 1326 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"}; 1327 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2, 1328 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2, 1329 enum_bitclk0); 1330 static const char * const enum_slavemaster[] = {"Slave", "Master"}; 1331 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast, 1332 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT, 1333 enum_slavemaster); 1334 1335 /* Sidetone */ 1336 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state); 1337 1338 /* ANC */ 1339 1340 static struct snd_kcontrol_new ab8500_ctrls[] = { 1341 /* Charge pump */ 1342 SOC_ENUM("Charge Pump High Threshold For Low Voltage", 1343 soc_enum_envdeththre), 1344 SOC_ENUM("Charge Pump Low Threshold For Low Voltage", 1345 soc_enum_envdetlthre), 1346 SOC_SINGLE("Charge Pump Envelope Detection Switch", 1347 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN, 1348 1, 0), 1349 SOC_ENUM("Charge Pump Envelope Detection Decay Time", 1350 soc_enum_envdettime), 1351 1352 /* Headset */ 1353 SOC_ENUM("Headset Mode", soc_enum_da12voice), 1354 SOC_SINGLE("Headset High Pass Switch", 1355 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN, 1356 1, 0), 1357 SOC_SINGLE("Headset Low Power Switch", 1358 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW, 1359 1, 0), 1360 SOC_SINGLE("Headset DAC Low Power Switch", 1361 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1, 1362 1, 0), 1363 SOC_SINGLE("Headset DAC Drv Low Power Switch", 1364 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0, 1365 1, 0), 1366 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed), 1367 SOC_ENUM("Headset Source", soc_enum_da2hslr), 1368 SOC_ENUM("Headset Filter", soc_enum_hsesinc), 1369 SOC_DOUBLE_R_TLV("Headset Master Volume", 1370 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2, 1371 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1372 SOC_DOUBLE_R_TLV("Headset Digital Volume", 1373 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN, 1374 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv), 1375 SOC_DOUBLE_TLV("Headset Volume", 1376 AB8500_ANAGAIN3, 1377 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN, 1378 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv), 1379 1380 /* Earpiece */ 1381 SOC_ENUM("Earpiece DAC Mode", 1382 soc_enum_eardaclowpow), 1383 SOC_ENUM("Earpiece DAC Drv Mode", 1384 soc_enum_eardrvlowpow), 1385 1386 /* HandsFree */ 1387 SOC_ENUM("HF Mode", soc_enum_da34voice), 1388 SOC_SINGLE("HF and Headset Swap Switch", 1389 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34, 1390 1, 0), 1391 SOC_DOUBLE("HF Low EMI Mode Switch", 1392 AB8500_CLASSDCONF1, 1393 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN, 1394 1, 0), 1395 SOC_DOUBLE("HF FIR Bypass Switch", 1396 AB8500_CLASSDCONF2, 1397 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1, 1398 1, 0), 1399 SOC_DOUBLE("HF High Volume Switch", 1400 AB8500_CLASSDCONF2, 1401 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1, 1402 1, 0), 1403 SOC_SINGLE("HF L and R Bridge Switch", 1404 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF, 1405 1, 0), 1406 SOC_DOUBLE_R_TLV("HF Master Volume", 1407 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4, 1408 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1409 1410 /* Vibra */ 1411 SOC_DOUBLE("Vibra High Volume Switch", 1412 AB8500_CLASSDCONF2, 1413 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3, 1414 1, 0), 1415 SOC_DOUBLE("Vibra Low EMI Mode Switch", 1416 AB8500_CLASSDCONF1, 1417 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN, 1418 1, 0), 1419 SOC_DOUBLE("Vibra FIR Bypass Switch", 1420 AB8500_CLASSDCONF2, 1421 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3, 1422 1, 0), 1423 SOC_ENUM("Vibra Mode", soc_enum_da56voice), 1424 SOC_DOUBLE_R("Vibra PWM Duty Cycle N", 1425 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5, 1426 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1427 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1428 SOC_DOUBLE_R("Vibra PWM Duty Cycle P", 1429 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4, 1430 AB8500_PWMGENCONFX_PWMVIBXDUTCYC, 1431 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0), 1432 SOC_SINGLE("Vibra 1 and 2 Bridge Switch", 1433 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB, 1434 1, 0), 1435 SOC_DOUBLE_R_TLV("Vibra Master Volume", 1436 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6, 1437 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv), 1438 1439 /* HandsFree, Vibra */ 1440 SOC_SINGLE("ClassD High Pass Volume", 1441 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN, 1442 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0), 1443 SOC_SINGLE("ClassD White Volume", 1444 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN, 1445 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0), 1446 1447 /* Mic 1, Mic 2, LineIn */ 1448 SOC_DOUBLE_R_TLV("Mic Master Volume", 1449 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4, 1450 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1451 1452 /* Mic 1 */ 1453 SOC_SINGLE_TLV("Mic 1", 1454 AB8500_ANAGAIN1, 1455 AB8500_ANAGAINX_MICXGAIN, 1456 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1457 SOC_SINGLE("Mic 1 Low Power Switch", 1458 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX, 1459 1, 0), 1460 1461 /* Mic 2 */ 1462 SOC_DOUBLE("Mic High Pass Switch", 1463 AB8500_ADFILTCONF, 1464 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH, 1465 1, 1), 1466 SOC_ENUM("Mic Mode", soc_enum_ad34voice), 1467 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc), 1468 SOC_SINGLE_TLV("Mic 2", 1469 AB8500_ANAGAIN2, 1470 AB8500_ANAGAINX_MICXGAIN, 1471 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv), 1472 SOC_SINGLE("Mic 2 Low Power Switch", 1473 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX, 1474 1, 0), 1475 1476 /* LineIn */ 1477 SOC_DOUBLE("LineIn High Pass Switch", 1478 AB8500_ADFILTCONF, 1479 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH, 1480 1, 1), 1481 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc), 1482 SOC_ENUM("LineIn Mode", soc_enum_ad12voice), 1483 SOC_DOUBLE_R_TLV("LineIn Master Volume", 1484 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2, 1485 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1486 SOC_DOUBLE_TLV("LineIn", 1487 AB8500_ANAGAIN4, 1488 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN, 1489 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv), 1490 SOC_DOUBLE_R_TLV("LineIn to Headset Volume", 1491 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN, 1492 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN, 1493 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX, 1494 1, lin2hs_gain_tlv), 1495 1496 /* DMic */ 1497 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc), 1498 SOC_DOUBLE_R_TLV("DMic Master Volume", 1499 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6, 1500 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv), 1501 1502 /* Digital gains */ 1503 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed), 1504 1505 /* Analog loopback */ 1506 SOC_DOUBLE_R_TLV("Analog Loopback Volume", 1507 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2, 1508 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv), 1509 1510 /* Digital interface - DA from slot mapping */ 1511 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap), 1512 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap), 1513 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap), 1514 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap), 1515 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap), 1516 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap), 1517 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap), 1518 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap), 1519 1520 /* Digital interface - AD to slot mapping */ 1521 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map), 1522 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map), 1523 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map), 1524 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map), 1525 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map), 1526 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map), 1527 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map), 1528 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map), 1529 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map), 1530 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map), 1531 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map), 1532 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map), 1533 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map), 1534 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map), 1535 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map), 1536 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map), 1537 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map), 1538 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map), 1539 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map), 1540 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map), 1541 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map), 1542 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map), 1543 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map), 1544 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map), 1545 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map), 1546 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map), 1547 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map), 1548 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map), 1549 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map), 1550 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map), 1551 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map), 1552 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map), 1553 1554 /* Digital interface - Loopback */ 1555 SOC_SINGLE("Digital Interface AD 1 Loopback Switch", 1556 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1, 1557 1, 0), 1558 SOC_SINGLE("Digital Interface AD 2 Loopback Switch", 1559 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2, 1560 1, 0), 1561 SOC_SINGLE("Digital Interface AD 3 Loopback Switch", 1562 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3, 1563 1, 0), 1564 SOC_SINGLE("Digital Interface AD 4 Loopback Switch", 1565 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4, 1566 1, 0), 1567 SOC_SINGLE("Digital Interface AD 5 Loopback Switch", 1568 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5, 1569 1, 0), 1570 SOC_SINGLE("Digital Interface AD 6 Loopback Switch", 1571 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6, 1572 1, 0), 1573 SOC_SINGLE("Digital Interface AD 7 Loopback Switch", 1574 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7, 1575 1, 0), 1576 SOC_SINGLE("Digital Interface AD 8 Loopback Switch", 1577 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8, 1578 1, 0), 1579 1580 /* Digital interface - Burst FIFO */ 1581 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch", 1582 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN, 1583 1, 0), 1584 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask), 1585 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2), 1586 SOC_SINGLE("Burst FIFO Threshold", 1587 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT, 1588 AB8500_FIFOCONF1_BFIFOINT_MAX, 0), 1589 SOC_SINGLE("Burst FIFO Length", 1590 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT, 1591 AB8500_FIFOCONF2_BFIFOTX_MAX, 0), 1592 SOC_SINGLE("Burst FIFO EOS Extra Slots", 1593 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT, 1594 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0), 1595 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks", 1596 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT, 1597 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0), 1598 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast), 1599 1600 SOC_SINGLE("Burst FIFO Interface Switch", 1601 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT, 1602 1, 0), 1603 SOC_SINGLE("Burst FIFO Switch Frame Number", 1604 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT, 1605 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0), 1606 SOC_SINGLE("Burst FIFO Wake Up Delay", 1607 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT, 1608 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0), 1609 SOC_SINGLE("Burst FIFO Samples In FIFO", 1610 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT, 1611 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0), 1612 1613 /* ANC */ 1614 SOC_SINGLE_XR_SX("ANC Warp Delay Shift", 1615 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT, 1616 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0), 1617 SOC_SINGLE_XR_SX("ANC FIR Output Shift", 1618 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT, 1619 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0), 1620 SOC_SINGLE_XR_SX("ANC IIR Output Shift", 1621 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT, 1622 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0), 1623 SOC_SINGLE_XR_SX("ANC Warp Delay", 1624 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT, 1625 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0), 1626 1627 /* Sidetone */ 1628 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate, 1629 sid_status_control_get, sid_status_control_put), 1630 SOC_SINGLE_STROBE("Sidetone Reset", 1631 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0), 1632 }; 1633 1634 /* 1635 * Extended interface for codec-driver 1636 */ 1637 1638 static int ab8500_audio_init_audioblock(struct snd_soc_component *component) 1639 { 1640 int status; 1641 1642 dev_dbg(component->dev, "%s: Enter.\n", __func__); 1643 1644 /* Reset audio-registers and disable 32kHz-clock output 2 */ 1645 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3, 1646 AB8500_STW4500CTRL3_CLK32KOUT2DIS | 1647 AB8500_STW4500CTRL3_RESETAUDN, 1648 AB8500_STW4500CTRL3_RESETAUDN); 1649 if (status < 0) 1650 return status; 1651 1652 return 0; 1653 } 1654 1655 static int ab8500_audio_setup_mics(struct snd_soc_component *component, 1656 struct amic_settings *amics) 1657 { 1658 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1659 u8 value8; 1660 unsigned int value; 1661 int status; 1662 const struct snd_soc_dapm_route *route; 1663 1664 dev_dbg(component->dev, "%s: Enter.\n", __func__); 1665 1666 /* Set DMic-clocks to outputs */ 1667 status = abx500_get_register_interruptible(component->dev, AB8500_MISC, 1668 AB8500_GPIO_DIR4_REG, 1669 &value8); 1670 if (status < 0) 1671 return status; 1672 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT | 1673 GPIO31_DIR_OUTPUT; 1674 status = abx500_set_register_interruptible(component->dev, 1675 AB8500_MISC, 1676 AB8500_GPIO_DIR4_REG, 1677 value); 1678 if (status < 0) 1679 return status; 1680 1681 /* Attach regulators to AMic DAPM-paths */ 1682 dev_dbg(component->dev, "%s: Mic 1a regulator: %s\n", __func__, 1683 amic_micbias_str(amics->mic1a_micbias)); 1684 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias]; 1685 status = snd_soc_dapm_add_routes(dapm, route, 1); 1686 dev_dbg(component->dev, "%s: Mic 1b regulator: %s\n", __func__, 1687 amic_micbias_str(amics->mic1b_micbias)); 1688 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias]; 1689 status |= snd_soc_dapm_add_routes(dapm, route, 1); 1690 dev_dbg(component->dev, "%s: Mic 2 regulator: %s\n", __func__, 1691 amic_micbias_str(amics->mic2_micbias)); 1692 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias]; 1693 status |= snd_soc_dapm_add_routes(dapm, route, 1); 1694 if (status < 0) { 1695 dev_err(component->dev, 1696 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n", 1697 __func__, status); 1698 return status; 1699 } 1700 1701 /* Set AMic-configuration */ 1702 dev_dbg(component->dev, "%s: Mic 1 mic-type: %s\n", __func__, 1703 amic_type_str(amics->mic1_type)); 1704 snd_soc_component_update_bits(component, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX, 1705 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ? 1706 0 : AB8500_ANAGAINX_ENSEMICX); 1707 dev_dbg(component->dev, "%s: Mic 2 mic-type: %s\n", __func__, 1708 amic_type_str(amics->mic2_type)); 1709 snd_soc_component_update_bits(component, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX, 1710 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ? 1711 0 : AB8500_ANAGAINX_ENSEMICX); 1712 1713 return 0; 1714 } 1715 1716 static int ab8500_audio_set_ear_cmv(struct snd_soc_component *component, 1717 enum ear_cm_voltage ear_cmv) 1718 { 1719 char *cmv_str; 1720 1721 switch (ear_cmv) { 1722 case EAR_CMV_0_95V: 1723 cmv_str = "0.95V"; 1724 break; 1725 case EAR_CMV_1_10V: 1726 cmv_str = "1.10V"; 1727 break; 1728 case EAR_CMV_1_27V: 1729 cmv_str = "1.27V"; 1730 break; 1731 case EAR_CMV_1_58V: 1732 cmv_str = "1.58V"; 1733 break; 1734 default: 1735 dev_err(component->dev, 1736 "%s: Unknown earpiece CM-voltage (%d)!\n", 1737 __func__, (int)ear_cmv); 1738 return -EINVAL; 1739 } 1740 dev_dbg(component->dev, "%s: Earpiece CM-voltage: %s\n", __func__, 1741 cmv_str); 1742 snd_soc_component_update_bits(component, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM, 1743 ear_cmv); 1744 1745 return 0; 1746 } 1747 1748 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai, 1749 unsigned int delay) 1750 { 1751 unsigned int mask, val; 1752 struct snd_soc_component *component = dai->component; 1753 1754 mask = BIT(AB8500_DIGIFCONF2_IF0DEL); 1755 val = 0; 1756 1757 switch (delay) { 1758 case 0: 1759 break; 1760 case 1: 1761 val |= BIT(AB8500_DIGIFCONF2_IF0DEL); 1762 break; 1763 default: 1764 dev_err(dai->component->dev, 1765 "%s: ERROR: Unsupported bit-delay (0x%x)!\n", 1766 __func__, delay); 1767 return -EINVAL; 1768 } 1769 1770 dev_dbg(dai->component->dev, "%s: IF0 Bit-delay: %d bits.\n", 1771 __func__, delay); 1772 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1773 1774 return 0; 1775 } 1776 1777 /* Gates clocking according format mask */ 1778 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_component *component, 1779 unsigned int fmt) 1780 { 1781 unsigned int mask; 1782 unsigned int val; 1783 1784 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) | 1785 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 1786 1787 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN); 1788 1789 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) { 1790 case SND_SOC_DAIFMT_CONT: /* continuous clock */ 1791 dev_dbg(component->dev, "%s: IF0 Clock is continuous.\n", 1792 __func__); 1793 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0); 1794 break; 1795 case SND_SOC_DAIFMT_GATED: /* clock is gated */ 1796 dev_dbg(component->dev, "%s: IF0 Clock is gated.\n", 1797 __func__); 1798 break; 1799 default: 1800 dev_err(component->dev, 1801 "%s: ERROR: Unsupported clock mask (0x%x)!\n", 1802 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK); 1803 return -EINVAL; 1804 } 1805 1806 snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); 1807 1808 return 0; 1809 } 1810 1811 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1812 { 1813 unsigned int mask; 1814 unsigned int val; 1815 struct snd_soc_component *component = dai->component; 1816 int status; 1817 1818 dev_dbg(component->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt); 1819 1820 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) | 1821 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) | 1822 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) | 1823 BIT(AB8500_DIGIFCONF3_IF0MASTER); 1824 val = 0; 1825 1826 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1827 case SND_SOC_DAIFMT_CBP_CFP: 1828 dev_dbg(dai->component->dev, 1829 "%s: IF0 Master-mode: AB8500 provider.\n", __func__); 1830 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER); 1831 break; 1832 case SND_SOC_DAIFMT_CBC_CFC: 1833 dev_dbg(dai->component->dev, 1834 "%s: IF0 Master-mode: AB8500 consumer.\n", __func__); 1835 break; 1836 case SND_SOC_DAIFMT_CBC_CFP: 1837 case SND_SOC_DAIFMT_CBP_CFC: 1838 dev_err(dai->component->dev, 1839 "%s: ERROR: The device is either a provider or a consumer.\n", 1840 __func__); 1841 fallthrough; 1842 default: 1843 dev_err(dai->component->dev, 1844 "%s: ERROR: Unsupporter clocking mask 0x%x\n", 1845 __func__, fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 1846 return -EINVAL; 1847 } 1848 1849 snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val); 1850 1851 /* Set clock gating */ 1852 status = ab8500_codec_set_dai_clock_gate(component, fmt); 1853 if (status) { 1854 dev_err(dai->component->dev, 1855 "%s: ERROR: Failed to set clock gate (%d).\n", 1856 __func__, status); 1857 return status; 1858 } 1859 1860 /* Setting data transfer format */ 1861 1862 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) | 1863 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) | 1864 BIT(AB8500_DIGIFCONF2_FSYNC0P) | 1865 BIT(AB8500_DIGIFCONF2_BITCLK0P); 1866 val = 0; 1867 1868 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1869 case SND_SOC_DAIFMT_I2S: /* I2S mode */ 1870 dev_dbg(dai->component->dev, "%s: IF0 Protocol: I2S\n", __func__); 1871 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1); 1872 ab8500_audio_set_bit_delay(dai, 0); 1873 break; 1874 1875 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */ 1876 dev_dbg(dai->component->dev, 1877 "%s: IF0 Protocol: DSP A (TDM)\n", __func__); 1878 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 1879 ab8500_audio_set_bit_delay(dai, 1); 1880 break; 1881 1882 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */ 1883 dev_dbg(dai->component->dev, 1884 "%s: IF0 Protocol: DSP B (TDM)\n", __func__); 1885 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0); 1886 ab8500_audio_set_bit_delay(dai, 0); 1887 break; 1888 1889 default: 1890 dev_err(dai->component->dev, 1891 "%s: ERROR: Unsupported format (0x%x)!\n", 1892 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1893 return -EINVAL; 1894 } 1895 1896 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1897 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */ 1898 dev_dbg(dai->component->dev, 1899 "%s: IF0: Normal bit clock, normal frame\n", 1900 __func__); 1901 break; 1902 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */ 1903 dev_dbg(dai->component->dev, 1904 "%s: IF0: Normal bit clock, inverted frame\n", 1905 __func__); 1906 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 1907 break; 1908 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */ 1909 dev_dbg(dai->component->dev, 1910 "%s: IF0: Inverted bit clock, normal frame\n", 1911 __func__); 1912 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 1913 break; 1914 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */ 1915 dev_dbg(dai->component->dev, 1916 "%s: IF0: Inverted bit clock, inverted frame\n", 1917 __func__); 1918 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P); 1919 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P); 1920 break; 1921 default: 1922 dev_err(dai->component->dev, 1923 "%s: ERROR: Unsupported INV mask 0x%x\n", 1924 __func__, fmt & SND_SOC_DAIFMT_INV_MASK); 1925 return -EINVAL; 1926 } 1927 1928 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1929 1930 return 0; 1931 } 1932 1933 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai, 1934 unsigned int tx_mask, unsigned int rx_mask, 1935 int slots, int slot_width) 1936 { 1937 struct snd_soc_component *component = dai->component; 1938 unsigned int val, mask, slot, slots_active; 1939 1940 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) | 1941 BIT(AB8500_DIGIFCONF2_IF0WL1); 1942 val = 0; 1943 1944 switch (slot_width) { 1945 case 16: 1946 break; 1947 case 20: 1948 val |= BIT(AB8500_DIGIFCONF2_IF0WL0); 1949 break; 1950 case 24: 1951 val |= BIT(AB8500_DIGIFCONF2_IF0WL1); 1952 break; 1953 case 32: 1954 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) | 1955 BIT(AB8500_DIGIFCONF2_IF0WL0); 1956 break; 1957 default: 1958 dev_err(dai->component->dev, "%s: Unsupported slot-width 0x%x\n", 1959 __func__, slot_width); 1960 return -EINVAL; 1961 } 1962 1963 dev_dbg(dai->component->dev, "%s: IF0 slot-width: %d bits.\n", 1964 __func__, slot_width); 1965 snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); 1966 1967 /* Setup TDM clocking according to slot count */ 1968 dev_dbg(dai->component->dev, "%s: Slots, total: %d\n", __func__, slots); 1969 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 1970 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1971 switch (slots) { 1972 case 2: 1973 val = AB8500_MASK_NONE; 1974 break; 1975 case 4: 1976 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0); 1977 break; 1978 case 8: 1979 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1980 break; 1981 case 16: 1982 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | 1983 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1); 1984 break; 1985 default: 1986 dev_err(dai->component->dev, 1987 "%s: ERROR: Unsupported number of slots (%d)!\n", 1988 __func__, slots); 1989 return -EINVAL; 1990 } 1991 snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); 1992 1993 /* Setup TDM DA according to active tx slots */ 1994 1995 if (tx_mask & ~0xff) 1996 return -EINVAL; 1997 1998 mask = AB8500_DASLOTCONFX_SLTODAX_MASK; 1999 tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET; 2000 slots_active = hweight32(tx_mask); 2001 2002 dev_dbg(dai->component->dev, "%s: Slots, active, TX: %d\n", __func__, 2003 slots_active); 2004 2005 switch (slots_active) { 2006 case 0: 2007 break; 2008 case 1: 2009 slot = ffs(tx_mask); 2010 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); 2011 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); 2012 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); 2013 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); 2014 break; 2015 case 2: 2016 slot = ffs(tx_mask); 2017 snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); 2018 snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); 2019 slot = fls(tx_mask); 2020 snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); 2021 snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); 2022 break; 2023 case 8: 2024 dev_dbg(dai->component->dev, 2025 "%s: In 8-channel mode DA-from-slot mapping is set manually.", 2026 __func__); 2027 break; 2028 default: 2029 dev_err(dai->component->dev, 2030 "%s: Unsupported number of active TX-slots (%d)!\n", 2031 __func__, slots_active); 2032 return -EINVAL; 2033 } 2034 2035 /* Setup TDM AD according to active RX-slots */ 2036 2037 if (rx_mask & ~0xff) 2038 return -EINVAL; 2039 2040 rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET; 2041 slots_active = hweight32(rx_mask); 2042 2043 dev_dbg(dai->component->dev, "%s: Slots, active, RX: %d\n", __func__, 2044 slots_active); 2045 2046 switch (slots_active) { 2047 case 0: 2048 break; 2049 case 1: 2050 slot = ffs(rx_mask); 2051 snd_soc_component_update_bits(component, AB8500_ADSLOTSEL(slot), 2052 AB8500_MASK_SLOT(slot), 2053 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2054 break; 2055 case 2: 2056 slot = ffs(rx_mask); 2057 snd_soc_component_update_bits(component, 2058 AB8500_ADSLOTSEL(slot), 2059 AB8500_MASK_SLOT(slot), 2060 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2061 slot = fls(rx_mask); 2062 snd_soc_component_update_bits(component, 2063 AB8500_ADSLOTSEL(slot), 2064 AB8500_MASK_SLOT(slot), 2065 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot)); 2066 break; 2067 case 8: 2068 dev_dbg(dai->component->dev, 2069 "%s: In 8-channel mode AD-to-slot mapping is set manually.", 2070 __func__); 2071 break; 2072 default: 2073 dev_err(dai->component->dev, 2074 "%s: Unsupported number of active RX-slots (%d)!\n", 2075 __func__, slots_active); 2076 return -EINVAL; 2077 } 2078 2079 return 0; 2080 } 2081 2082 static const struct snd_soc_dai_ops ab8500_codec_ops = { 2083 .set_fmt = ab8500_codec_set_dai_fmt, 2084 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot, 2085 }; 2086 2087 static struct snd_soc_dai_driver ab8500_codec_dai[] = { 2088 { 2089 .name = "ab8500-codec-dai.0", 2090 .id = 0, 2091 .playback = { 2092 .stream_name = "ab8500_0p", 2093 .channels_min = 1, 2094 .channels_max = 8, 2095 .rates = AB8500_SUPPORTED_RATE, 2096 .formats = AB8500_SUPPORTED_FMT, 2097 }, 2098 .ops = &ab8500_codec_ops, 2099 .symmetric_rate = 1 2100 }, 2101 { 2102 .name = "ab8500-codec-dai.1", 2103 .id = 1, 2104 .capture = { 2105 .stream_name = "ab8500_0c", 2106 .channels_min = 1, 2107 .channels_max = 8, 2108 .rates = AB8500_SUPPORTED_RATE, 2109 .formats = AB8500_SUPPORTED_FMT, 2110 }, 2111 .ops = &ab8500_codec_ops, 2112 .symmetric_rate = 1 2113 } 2114 }; 2115 2116 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np, 2117 struct ab8500_codec_platform_data *codec) 2118 { 2119 u32 value; 2120 2121 if (of_property_read_bool(np, "stericsson,amic1-type-single-ended")) 2122 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED; 2123 else 2124 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL; 2125 2126 if (of_property_read_bool(np, "stericsson,amic2-type-single-ended")) 2127 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED; 2128 else 2129 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL; 2130 2131 /* Has a non-standard Vamic been requested? */ 2132 if (of_property_read_bool(np, "stericsson,amic1a-bias-vamic2")) 2133 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2; 2134 else 2135 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1; 2136 2137 if (of_property_read_bool(np, "stericsson,amic1b-bias-vamic2")) 2138 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2; 2139 else 2140 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1; 2141 2142 if (of_property_read_bool(np, "stericsson,amic2-bias-vamic1")) 2143 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1; 2144 else 2145 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2; 2146 2147 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) { 2148 switch (value) { 2149 case 950 : 2150 codec->ear_cmv = EAR_CMV_0_95V; 2151 break; 2152 case 1100 : 2153 codec->ear_cmv = EAR_CMV_1_10V; 2154 break; 2155 case 1270 : 2156 codec->ear_cmv = EAR_CMV_1_27V; 2157 break; 2158 case 1580 : 2159 codec->ear_cmv = EAR_CMV_1_58V; 2160 break; 2161 default : 2162 codec->ear_cmv = EAR_CMV_UNKNOWN; 2163 dev_err(dev, "Unsuitable earpiece voltage found in DT\n"); 2164 } 2165 } else { 2166 dev_warn(dev, "No earpiece voltage found in DT - using default\n"); 2167 codec->ear_cmv = EAR_CMV_0_95V; 2168 } 2169 } 2170 2171 static int ab8500_codec_probe(struct snd_soc_component *component) 2172 { 2173 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 2174 struct device *dev = component->dev; 2175 struct device_node *np = dev->of_node; 2176 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev); 2177 struct ab8500_codec_platform_data codec_pdata; 2178 int status; 2179 2180 dev_dbg(dev, "%s: Enter.\n", __func__); 2181 2182 ab8500_codec_of_probe(dev, np, &codec_pdata); 2183 2184 status = ab8500_audio_setup_mics(component, &codec_pdata.amics); 2185 if (status < 0) { 2186 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status); 2187 return status; 2188 } 2189 status = ab8500_audio_set_ear_cmv(component, codec_pdata.ear_cmv); 2190 if (status < 0) { 2191 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n", 2192 __func__, status); 2193 return status; 2194 } 2195 2196 status = ab8500_audio_init_audioblock(component); 2197 if (status < 0) { 2198 dev_err(dev, "%s: failed to init audio-block (%d)!\n", 2199 __func__, status); 2200 return status; 2201 } 2202 2203 /* Override HW-defaults */ 2204 snd_soc_component_write(component, AB8500_ANACONF5, 2205 BIT(AB8500_ANACONF5_HSAUTOEN)); 2206 snd_soc_component_write(component, AB8500_SHORTCIRCONF, 2207 BIT(AB8500_SHORTCIRCONF_HSZCDDIS)); 2208 2209 snd_soc_dapm_disable_pin(dapm, "ANC Configure Input"); 2210 2211 mutex_init(&drvdata->ctrl_lock); 2212 2213 return status; 2214 } 2215 2216 static const struct snd_soc_component_driver ab8500_component_driver = { 2217 .probe = ab8500_codec_probe, 2218 .controls = ab8500_ctrls, 2219 .num_controls = ARRAY_SIZE(ab8500_ctrls), 2220 .dapm_widgets = ab8500_dapm_widgets, 2221 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets), 2222 .dapm_routes = ab8500_dapm_routes, 2223 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes), 2224 .idle_bias_on = 1, 2225 .use_pmdown_time = 1, 2226 .endianness = 1, 2227 }; 2228 2229 static int ab8500_codec_driver_probe(struct platform_device *pdev) 2230 { 2231 int status; 2232 struct ab8500_codec_drvdata *drvdata; 2233 2234 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__); 2235 2236 /* Create driver private-data struct */ 2237 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata), 2238 GFP_KERNEL); 2239 if (!drvdata) 2240 return -ENOMEM; 2241 drvdata->sid_status = SID_UNCONFIGURED; 2242 dev_set_drvdata(&pdev->dev, drvdata); 2243 2244 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev, 2245 &ab8500_codec_regmap); 2246 if (IS_ERR(drvdata->regmap)) { 2247 status = PTR_ERR(drvdata->regmap); 2248 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n", 2249 __func__, status); 2250 return status; 2251 } 2252 2253 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__); 2254 status = devm_snd_soc_register_component(&pdev->dev, 2255 &ab8500_component_driver, 2256 ab8500_codec_dai, 2257 ARRAY_SIZE(ab8500_codec_dai)); 2258 if (status < 0) 2259 dev_err(&pdev->dev, 2260 "%s: Error: Failed to register codec (%d).\n", 2261 __func__, status); 2262 2263 return status; 2264 } 2265 2266 static struct platform_driver ab8500_codec_platform_driver = { 2267 .driver = { 2268 .name = "ab8500-codec", 2269 }, 2270 .probe = ab8500_codec_driver_probe, 2271 }; 2272 module_platform_driver(ab8500_codec_platform_driver); 2273 2274 MODULE_DESCRIPTION("ASoC AB8500 codec driver"); 2275 MODULE_LICENSE("GPL v2"); 2276