1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip S/PDIF RX Controller 4 // 5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/spinlock.h> 15 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 20 /* 21 * ---- S/PDIF Receiver Controller Register map ---- 22 */ 23 #define SPDIFRX_CR 0x00 /* Control Register */ 24 #define SPDIFRX_MR 0x04 /* Mode Register */ 25 26 #define SPDIFRX_IER 0x10 /* Interrupt Enable Register */ 27 #define SPDIFRX_IDR 0x14 /* Interrupt Disable Register */ 28 #define SPDIFRX_IMR 0x18 /* Interrupt Mask Register */ 29 #define SPDIFRX_ISR 0x1c /* Interrupt Status Register */ 30 #define SPDIFRX_RSR 0x20 /* Status Register */ 31 #define SPDIFRX_RHR 0x24 /* Holding Register */ 32 33 #define SPDIFRX_CHSR(channel, reg) \ 34 (0x30 + (channel) * 0x30 + (reg) * 4) /* Channel x Status Registers */ 35 36 #define SPDIFRX_CHUD(channel, reg) \ 37 (0x48 + (channel) * 0x30 + (reg) * 4) /* Channel x User Data Registers */ 38 39 #define SPDIFRX_WPMR 0xE4 /* Write Protection Mode Register */ 40 #define SPDIFRX_WPSR 0xE8 /* Write Protection Status Register */ 41 42 #define SPDIFRX_VERSION 0xFC /* Version Register */ 43 44 /* 45 * ---- Control Register (Write-only) ---- 46 */ 47 #define SPDIFRX_CR_SWRST BIT(0) /* Software Reset */ 48 49 /* 50 * ---- Mode Register (Read/Write) ---- 51 */ 52 /* Receive Enable */ 53 #define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0) 54 #define SPDIFRX_MR_RXEN_DISABLE (0 << 0) /* SPDIF Receiver Disabled */ 55 #define SPDIFRX_MR_RXEN_ENABLE (1 << 0) /* SPDIF Receiver Enabled */ 56 57 /* Validity Bit Mode */ 58 #define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1) 59 #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \ 60 (0 << 1) /* Load sample regardless of validity bit value */ 61 #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \ 62 (1 << 1) /* Load sample only if validity bit is 0 */ 63 64 /* Data Word Endian Mode */ 65 #define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2) 66 #define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2) /* Little Endian Mode */ 67 #define SPDIFRX_MR_ENDIAN_BIG (1 << 2) /* Big Endian Mode */ 68 69 /* Parity Bit Mode */ 70 #define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3) 71 #define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3) /* Parity Check Enabled */ 72 #define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3) /* Parity Check Disabled */ 73 74 /* Sample Data Width */ 75 #define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4) 76 #define SPDIFRX_MR_DATAWIDTH(width) \ 77 (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK) 78 79 /* Packed Data Mode in Receive Holding Register */ 80 #define SPDIFRX_MR_PACK_MASK GENMASK(7, 7) 81 #define SPDIFRX_MR_PACK_DISABLED (0 << 7) 82 #define SPDIFRX_MR_PACK_ENABLED (1 << 7) 83 84 /* Start of Block Bit Mode */ 85 #define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8) 86 #define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8) 87 #define SPDIFRX_MR_SBMODE_DISCARD (1 << 8) 88 89 /* Consecutive Preamble Error Threshold Automatic Restart */ 90 #define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24) 91 #define SPDIFRX_MR_AUTORST_NOACTION (0 << 24) 92 #define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24) 93 94 /* 95 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ---- 96 */ 97 #define SPDIFRX_IR_RXRDY BIT(0) 98 #define SPDIFRX_IR_LOCKED BIT(1) 99 #define SPDIFRX_IR_LOSS BIT(2) 100 #define SPDIFRX_IR_BLOCKEND BIT(3) 101 #define SPDIFRX_IR_SFE BIT(4) 102 #define SPDIFRX_IR_PAR_ERR BIT(5) 103 #define SPDIFRX_IR_OVERRUN BIT(6) 104 #define SPDIFRX_IR_RXFULL BIT(7) 105 #define SPDIFRX_IR_CSC(ch) BIT((ch) + 8) 106 #define SPDIFRX_IR_SECE BIT(10) 107 #define SPDIFRX_IR_BLOCKST BIT(11) 108 #define SPDIFRX_IR_NRZ_ERR BIT(12) 109 #define SPDIFRX_IR_PRE_ERR BIT(13) 110 #define SPDIFRX_IR_CP_ERR BIT(14) 111 112 /* 113 * ---- Receiver Status Register (Read/Write) ---- 114 */ 115 /* Enable Status */ 116 #define SPDIFRX_RSR_ULOCK BIT(0) 117 #define SPDIFRX_RSR_BADF BIT(1) 118 #define SPDIFRX_RSR_LOWF BIT(2) 119 #define SPDIFRX_RSR_NOSIGNAL BIT(3) 120 #define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16) 121 #define SPDIFRX_RSR_IFS(reg) \ 122 (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16) 123 124 /* 125 * ---- Version Register (Read-only) ---- 126 */ 127 #define SPDIFRX_VERSION_MASK GENMASK(11, 0) 128 #define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16) 129 #define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16) 130 131 static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case SPDIFRX_MR: 135 case SPDIFRX_IMR: 136 case SPDIFRX_ISR: 137 case SPDIFRX_RSR: 138 case SPDIFRX_CHSR(0, 0): 139 case SPDIFRX_CHSR(0, 1): 140 case SPDIFRX_CHSR(0, 2): 141 case SPDIFRX_CHSR(0, 3): 142 case SPDIFRX_CHSR(0, 4): 143 case SPDIFRX_CHSR(0, 5): 144 case SPDIFRX_CHUD(0, 0): 145 case SPDIFRX_CHUD(0, 1): 146 case SPDIFRX_CHUD(0, 2): 147 case SPDIFRX_CHUD(0, 3): 148 case SPDIFRX_CHUD(0, 4): 149 case SPDIFRX_CHUD(0, 5): 150 case SPDIFRX_CHSR(1, 0): 151 case SPDIFRX_CHSR(1, 1): 152 case SPDIFRX_CHSR(1, 2): 153 case SPDIFRX_CHSR(1, 3): 154 case SPDIFRX_CHSR(1, 4): 155 case SPDIFRX_CHSR(1, 5): 156 case SPDIFRX_CHUD(1, 0): 157 case SPDIFRX_CHUD(1, 1): 158 case SPDIFRX_CHUD(1, 2): 159 case SPDIFRX_CHUD(1, 3): 160 case SPDIFRX_CHUD(1, 4): 161 case SPDIFRX_CHUD(1, 5): 162 case SPDIFRX_WPMR: 163 case SPDIFRX_WPSR: 164 case SPDIFRX_VERSION: 165 return true; 166 default: 167 return false; 168 } 169 } 170 171 static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg) 172 { 173 switch (reg) { 174 case SPDIFRX_CR: 175 case SPDIFRX_MR: 176 case SPDIFRX_IER: 177 case SPDIFRX_IDR: 178 case SPDIFRX_WPMR: 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg) 186 { 187 switch (reg) { 188 case SPDIFRX_ISR: 189 case SPDIFRX_RHR: 190 return true; 191 default: 192 return false; 193 } 194 } 195 196 static bool mchp_spdifrx_volatile_reg(struct device *dev, unsigned int reg) 197 { 198 switch (reg) { 199 case SPDIFRX_IMR: 200 case SPDIFRX_ISR: 201 case SPDIFRX_RSR: 202 case SPDIFRX_CHSR(0, 0): 203 case SPDIFRX_CHSR(0, 1): 204 case SPDIFRX_CHSR(0, 2): 205 case SPDIFRX_CHSR(0, 3): 206 case SPDIFRX_CHSR(0, 4): 207 case SPDIFRX_CHSR(0, 5): 208 case SPDIFRX_CHUD(0, 0): 209 case SPDIFRX_CHUD(0, 1): 210 case SPDIFRX_CHUD(0, 2): 211 case SPDIFRX_CHUD(0, 3): 212 case SPDIFRX_CHUD(0, 4): 213 case SPDIFRX_CHUD(0, 5): 214 case SPDIFRX_CHSR(1, 0): 215 case SPDIFRX_CHSR(1, 1): 216 case SPDIFRX_CHSR(1, 2): 217 case SPDIFRX_CHSR(1, 3): 218 case SPDIFRX_CHSR(1, 4): 219 case SPDIFRX_CHSR(1, 5): 220 case SPDIFRX_CHUD(1, 0): 221 case SPDIFRX_CHUD(1, 1): 222 case SPDIFRX_CHUD(1, 2): 223 case SPDIFRX_CHUD(1, 3): 224 case SPDIFRX_CHUD(1, 4): 225 case SPDIFRX_CHUD(1, 5): 226 case SPDIFRX_VERSION: 227 return true; 228 default: 229 return false; 230 } 231 } 232 233 static const struct regmap_config mchp_spdifrx_regmap_config = { 234 .reg_bits = 32, 235 .reg_stride = 4, 236 .val_bits = 32, 237 .max_register = SPDIFRX_VERSION, 238 .readable_reg = mchp_spdifrx_readable_reg, 239 .writeable_reg = mchp_spdifrx_writeable_reg, 240 .precious_reg = mchp_spdifrx_precious_reg, 241 .volatile_reg = mchp_spdifrx_volatile_reg, 242 .cache_type = REGCACHE_FLAT, 243 }; 244 245 #define SPDIFRX_GCLK_RATIO_MIN (12 * 64) 246 247 #define SPDIFRX_CS_BITS 192 248 #define SPDIFRX_UD_BITS 192 249 250 #define SPDIFRX_CHANNELS 2 251 252 /** 253 * struct mchp_spdifrx_ch_stat: MCHP SPDIFRX channel status 254 * @data: channel status bits 255 * @done: completion to signal channel status bits acquisition done 256 */ 257 struct mchp_spdifrx_ch_stat { 258 unsigned char data[SPDIFRX_CS_BITS / 8]; 259 struct completion done; 260 }; 261 262 /** 263 * struct mchp_spdifrx_user_data: MCHP SPDIFRX user data 264 * @data: user data bits 265 * @done: completion to signal user data bits acquisition done 266 */ 267 struct mchp_spdifrx_user_data { 268 unsigned char data[SPDIFRX_UD_BITS / 8]; 269 struct completion done; 270 }; 271 272 /** 273 * struct mchp_spdifrx_mixer_control: MCHP SPDIFRX mixer control data structure 274 * @ch_stat: array of channel statuses 275 * @user_data: array of user data 276 * @ulock: ulock bit status 277 * @badf: badf bit status 278 * @signal: signal bit status 279 */ 280 struct mchp_spdifrx_mixer_control { 281 struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS]; 282 struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS]; 283 bool ulock; 284 bool badf; 285 bool signal; 286 }; 287 288 /** 289 * struct mchp_spdifrx_dev: MCHP SPDIFRX device data structure 290 * @capture: DAI DMA configuration data 291 * @control: mixer controls 292 * @mlock: mutex to protect concurency b/w configuration and control APIs 293 * @dev: struct device 294 * @regmap: regmap for this device 295 * @pclk: peripheral clock 296 * @gclk: generic clock 297 * @trigger_enabled: true if enabled though trigger() ops 298 */ 299 struct mchp_spdifrx_dev { 300 struct snd_dmaengine_dai_dma_data capture; 301 struct mchp_spdifrx_mixer_control control; 302 struct mutex mlock; 303 struct device *dev; 304 struct regmap *regmap; 305 struct clk *pclk; 306 struct clk *gclk; 307 unsigned int trigger_enabled; 308 }; 309 310 static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev, 311 int channel) 312 { 313 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 314 u8 *ch_stat = &ctrl->ch_stat[channel].data[0]; 315 u32 val; 316 int i; 317 318 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) { 319 regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val); 320 *ch_stat++ = val & 0xFF; 321 *ch_stat++ = (val >> 8) & 0xFF; 322 *ch_stat++ = (val >> 16) & 0xFF; 323 *ch_stat++ = (val >> 24) & 0xFF; 324 } 325 } 326 327 static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev, 328 int channel) 329 { 330 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 331 u8 *user_data = &ctrl->user_data[channel].data[0]; 332 u32 val; 333 int i; 334 335 for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) { 336 regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val); 337 *user_data++ = val & 0xFF; 338 *user_data++ = (val >> 8) & 0xFF; 339 *user_data++ = (val >> 16) & 0xFF; 340 *user_data++ = (val >> 24) & 0xFF; 341 } 342 } 343 344 static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) 345 { 346 struct mchp_spdifrx_dev *dev = dev_id; 347 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 348 u32 sr, imr, pending; 349 irqreturn_t ret = IRQ_NONE; 350 int ch; 351 352 regmap_read(dev->regmap, SPDIFRX_ISR, &sr); 353 regmap_read(dev->regmap, SPDIFRX_IMR, &imr); 354 pending = sr & imr; 355 dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr, 356 pending); 357 358 if (!pending) 359 return IRQ_NONE; 360 361 if (pending & SPDIFRX_IR_BLOCKEND) { 362 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 363 mchp_spdifrx_channel_user_data_read(dev, ch); 364 complete(&ctrl->user_data[ch].done); 365 } 366 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 367 ret = IRQ_HANDLED; 368 } 369 370 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 371 if (pending & SPDIFRX_IR_CSC(ch)) { 372 mchp_spdifrx_channel_status_read(dev, ch); 373 complete(&ctrl->ch_stat[ch].done); 374 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(ch)); 375 ret = IRQ_HANDLED; 376 } 377 } 378 379 if (pending & SPDIFRX_IR_OVERRUN) { 380 dev_warn(dev->dev, "Overrun detected\n"); 381 ret = IRQ_HANDLED; 382 } 383 384 return ret; 385 } 386 387 static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd, 388 struct snd_soc_dai *dai) 389 { 390 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 391 int ret = 0; 392 393 switch (cmd) { 394 case SNDRV_PCM_TRIGGER_START: 395 case SNDRV_PCM_TRIGGER_RESUME: 396 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 397 mutex_lock(&dev->mlock); 398 /* Enable overrun interrupts */ 399 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_OVERRUN); 400 401 /* Enable receiver. */ 402 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 403 SPDIFRX_MR_RXEN_ENABLE); 404 dev->trigger_enabled = true; 405 mutex_unlock(&dev->mlock); 406 break; 407 case SNDRV_PCM_TRIGGER_STOP: 408 case SNDRV_PCM_TRIGGER_SUSPEND: 409 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 410 mutex_lock(&dev->mlock); 411 /* Disable overrun interrupts */ 412 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_OVERRUN); 413 414 /* Disable receiver. */ 415 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 416 SPDIFRX_MR_RXEN_DISABLE); 417 dev->trigger_enabled = false; 418 mutex_unlock(&dev->mlock); 419 break; 420 default: 421 ret = -EINVAL; 422 } 423 424 return ret; 425 } 426 427 static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream, 428 struct snd_pcm_hw_params *params, 429 struct snd_soc_dai *dai) 430 { 431 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 432 u32 mr = 0; 433 int ret; 434 435 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 436 __func__, params_rate(params), params_format(params), 437 params_width(params), params_channels(params)); 438 439 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 440 dev_err(dev->dev, "Playback is not supported\n"); 441 return -EINVAL; 442 } 443 444 if (params_channels(params) != SPDIFRX_CHANNELS) { 445 dev_err(dev->dev, "unsupported number of channels: %d\n", 446 params_channels(params)); 447 return -EINVAL; 448 } 449 450 switch (params_format(params)) { 451 case SNDRV_PCM_FORMAT_S16_BE: 452 case SNDRV_PCM_FORMAT_S20_3BE: 453 case SNDRV_PCM_FORMAT_S24_3BE: 454 case SNDRV_PCM_FORMAT_S24_BE: 455 mr |= SPDIFRX_MR_ENDIAN_BIG; 456 fallthrough; 457 case SNDRV_PCM_FORMAT_S16_LE: 458 case SNDRV_PCM_FORMAT_S20_3LE: 459 case SNDRV_PCM_FORMAT_S24_3LE: 460 case SNDRV_PCM_FORMAT_S24_LE: 461 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params)); 462 break; 463 default: 464 dev_err(dev->dev, "unsupported PCM format: %d\n", 465 params_format(params)); 466 return -EINVAL; 467 } 468 469 mutex_lock(&dev->mlock); 470 if (dev->trigger_enabled) { 471 dev_err(dev->dev, "PCM already running\n"); 472 ret = -EBUSY; 473 goto unlock; 474 } 475 476 /* GCLK is enabled by runtime PM. */ 477 clk_disable_unprepare(dev->gclk); 478 479 ret = clk_set_min_rate(dev->gclk, params_rate(params) * 480 SPDIFRX_GCLK_RATIO_MIN + 1); 481 if (ret) { 482 dev_err(dev->dev, 483 "unable to set gclk min rate: rate %u * ratio %u + 1\n", 484 params_rate(params), SPDIFRX_GCLK_RATIO_MIN); 485 /* Restore runtime PM state. */ 486 clk_prepare_enable(dev->gclk); 487 goto unlock; 488 } 489 ret = clk_prepare_enable(dev->gclk); 490 if (ret) { 491 dev_err(dev->dev, "unable to enable gclk: %d\n", ret); 492 goto unlock; 493 } 494 495 dev_dbg(dev->dev, "GCLK range min set to %d\n", 496 params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1); 497 498 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr); 499 500 unlock: 501 mutex_unlock(&dev->mlock); 502 503 return ret; 504 } 505 506 #define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000 507 508 #define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 509 SNDRV_PCM_FMTBIT_U16_BE | \ 510 SNDRV_PCM_FMTBIT_S20_3LE | \ 511 SNDRV_PCM_FMTBIT_S20_3BE | \ 512 SNDRV_PCM_FMTBIT_S24_3LE | \ 513 SNDRV_PCM_FMTBIT_S24_3BE | \ 514 SNDRV_PCM_FMTBIT_S24_LE | \ 515 SNDRV_PCM_FMTBIT_S24_BE \ 516 ) 517 518 static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol, 519 struct snd_ctl_elem_info *uinfo) 520 { 521 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 522 uinfo->count = 1; 523 524 return 0; 525 } 526 527 static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev, 528 int channel, 529 struct snd_ctl_elem_value *uvalue) 530 { 531 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 532 struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel]; 533 int ret = 0; 534 535 mutex_lock(&dev->mlock); 536 537 ret = pm_runtime_resume_and_get(dev->dev); 538 if (ret < 0) 539 goto unlock; 540 541 /* 542 * We may reach this point with both clocks enabled but the receiver 543 * still disabled. To void waiting for completion and return with 544 * timeout check the dev->trigger_enabled. 545 * 546 * To retrieve data: 547 * - if the receiver is enabled CSC IRQ will update the data in software 548 * caches (ch_stat->data) 549 * - otherwise we just update it here the software caches with latest 550 * available information and return it; in this case we don't need 551 * spin locking as the IRQ is disabled and will not be raised from 552 * anywhere else. 553 */ 554 555 if (dev->trigger_enabled) { 556 reinit_completion(&ch_stat->done); 557 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel)); 558 /* Check for new data available */ 559 ret = wait_for_completion_interruptible_timeout(&ch_stat->done, 560 msecs_to_jiffies(100)); 561 /* Valid stream might not be present */ 562 if (ret <= 0) { 563 dev_dbg(dev->dev, "channel status for channel %d timeout\n", 564 channel); 565 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_CSC(channel)); 566 ret = ret ? : -ETIMEDOUT; 567 goto pm_runtime_put; 568 } else { 569 ret = 0; 570 } 571 } else { 572 /* Update software cache with latest channel status. */ 573 mchp_spdifrx_channel_status_read(dev, channel); 574 } 575 576 memcpy(uvalue->value.iec958.status, ch_stat->data, 577 sizeof(ch_stat->data)); 578 579 pm_runtime_put: 580 pm_runtime_put_autosuspend(dev->dev); 581 unlock: 582 mutex_unlock(&dev->mlock); 583 return ret; 584 } 585 586 static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol, 587 struct snd_ctl_elem_value *uvalue) 588 { 589 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 590 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 591 592 return mchp_spdifrx_cs_get(dev, 0, uvalue); 593 } 594 595 static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol, 596 struct snd_ctl_elem_value *uvalue) 597 { 598 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 599 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 600 601 return mchp_spdifrx_cs_get(dev, 1, uvalue); 602 } 603 604 static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol, 605 struct snd_ctl_elem_value *uvalue) 606 { 607 memset(uvalue->value.iec958.status, 0xff, 608 sizeof(uvalue->value.iec958.status)); 609 610 return 0; 611 } 612 613 static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, 614 int channel, 615 struct snd_ctl_elem_value *uvalue) 616 { 617 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 618 struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel]; 619 int ret = 0; 620 621 mutex_lock(&dev->mlock); 622 623 ret = pm_runtime_resume_and_get(dev->dev); 624 if (ret < 0) 625 goto unlock; 626 627 /* 628 * We may reach this point with both clocks enabled but the receiver 629 * still disabled. To void waiting for completion to just timeout we 630 * check here the dev->trigger_enabled flag. 631 * 632 * To retrieve data: 633 * - if the receiver is enabled we need to wait for blockend IRQ to read 634 * data to and update it for us in software caches 635 * - otherwise reading the SPDIFRX_CHUD() registers is enough. 636 */ 637 638 if (dev->trigger_enabled) { 639 reinit_completion(&user_data->done); 640 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND); 641 ret = wait_for_completion_interruptible_timeout(&user_data->done, 642 msecs_to_jiffies(100)); 643 /* Valid stream might not be present. */ 644 if (ret <= 0) { 645 dev_dbg(dev->dev, "user data for channel %d timeout\n", 646 channel); 647 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); 648 ret = ret ? : -ETIMEDOUT; 649 goto pm_runtime_put; 650 } else { 651 ret = 0; 652 } 653 } else { 654 /* Update software cache with last available data. */ 655 mchp_spdifrx_channel_user_data_read(dev, channel); 656 } 657 658 memcpy(uvalue->value.iec958.subcode, user_data->data, 659 sizeof(user_data->data)); 660 661 pm_runtime_put: 662 pm_runtime_put_autosuspend(dev->dev); 663 unlock: 664 mutex_unlock(&dev->mlock); 665 return ret; 666 } 667 668 static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol, 669 struct snd_ctl_elem_value *uvalue) 670 { 671 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 672 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 673 674 return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue); 675 } 676 677 static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol, 678 struct snd_ctl_elem_value *uvalue) 679 { 680 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 681 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 682 683 return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue); 684 } 685 686 static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol, 687 struct snd_ctl_elem_info *uinfo) 688 { 689 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 690 uinfo->count = 1; 691 uinfo->value.integer.min = 0; 692 uinfo->value.integer.max = 1; 693 694 return 0; 695 } 696 697 static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol, 698 struct snd_ctl_elem_value *uvalue) 699 { 700 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 701 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 702 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 703 u32 val; 704 int ret; 705 bool ulock_old = ctrl->ulock; 706 707 mutex_lock(&dev->mlock); 708 709 ret = pm_runtime_resume_and_get(dev->dev); 710 if (ret < 0) 711 goto unlock; 712 713 /* 714 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 715 * and the receiver is disabled. Thus we take into account the 716 * dev->trigger_enabled here to return a real status. 717 */ 718 if (dev->trigger_enabled) { 719 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 720 ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK); 721 } else { 722 ctrl->ulock = 0; 723 } 724 725 uvalue->value.integer.value[0] = ctrl->ulock; 726 727 pm_runtime_put_autosuspend(dev->dev); 728 unlock: 729 mutex_unlock(&dev->mlock); 730 731 return ulock_old != ctrl->ulock; 732 } 733 734 static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol, 735 struct snd_ctl_elem_value *uvalue) 736 { 737 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 738 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 739 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 740 u32 val; 741 int ret; 742 bool badf_old = ctrl->badf; 743 744 mutex_lock(&dev->mlock); 745 746 ret = pm_runtime_resume_and_get(dev->dev); 747 if (ret < 0) 748 goto unlock; 749 750 /* 751 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 752 * and the receiver is disabled. Thus we take into account the 753 * dev->trigger_enabled here to return a real status. 754 */ 755 if (dev->trigger_enabled) { 756 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 757 ctrl->badf = !!(val & SPDIFRX_RSR_BADF); 758 } else { 759 ctrl->badf = 0; 760 } 761 762 pm_runtime_put_autosuspend(dev->dev); 763 unlock: 764 mutex_unlock(&dev->mlock); 765 766 uvalue->value.integer.value[0] = ctrl->badf; 767 768 return badf_old != ctrl->badf; 769 } 770 771 static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol, 772 struct snd_ctl_elem_value *uvalue) 773 { 774 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 775 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 776 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 777 u32 val = ~0U, loops = 10; 778 int ret; 779 bool signal_old = ctrl->signal; 780 781 mutex_lock(&dev->mlock); 782 783 ret = pm_runtime_resume_and_get(dev->dev); 784 if (ret < 0) 785 goto unlock; 786 787 /* 788 * To get the signal we need to have receiver enabled. This 789 * could be enabled also from trigger() function thus we need to 790 * take care of not disabling the receiver when it runs. 791 */ 792 if (!dev->trigger_enabled) { 793 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 794 SPDIFRX_MR_RXEN_ENABLE); 795 796 /* Wait for RSR.ULOCK bit. */ 797 while (--loops) { 798 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 799 if (!(val & SPDIFRX_RSR_ULOCK)) 800 break; 801 usleep_range(100, 150); 802 } 803 804 regmap_update_bits(dev->regmap, SPDIFRX_MR, SPDIFRX_MR_RXEN_MASK, 805 SPDIFRX_MR_RXEN_DISABLE); 806 } else { 807 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 808 } 809 810 pm_runtime_put_autosuspend(dev->dev); 811 812 unlock: 813 mutex_unlock(&dev->mlock); 814 815 if (!(val & SPDIFRX_RSR_ULOCK)) 816 ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL); 817 else 818 ctrl->signal = 0; 819 uvalue->value.integer.value[0] = ctrl->signal; 820 821 return signal_old != ctrl->signal; 822 } 823 824 static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol, 825 struct snd_ctl_elem_info *uinfo) 826 { 827 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 828 uinfo->count = 1; 829 uinfo->value.integer.min = 0; 830 uinfo->value.integer.max = 192000; 831 832 return 0; 833 } 834 835 static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol, 836 struct snd_ctl_elem_value *ucontrol) 837 { 838 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 839 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 840 unsigned long rate; 841 u32 val; 842 int ret; 843 844 mutex_lock(&dev->mlock); 845 846 ret = pm_runtime_resume_and_get(dev->dev); 847 if (ret < 0) 848 goto unlock; 849 850 /* 851 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled 852 * and the receiver is disabled. Thus we take into account the 853 * dev->trigger_enabled here to return a real status. 854 */ 855 if (dev->trigger_enabled) { 856 regmap_read(dev->regmap, SPDIFRX_RSR, &val); 857 /* If the receiver is not locked, ISF data is invalid. */ 858 if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) { 859 ucontrol->value.integer.value[0] = 0; 860 goto pm_runtime_put; 861 } 862 } else { 863 /* Reveicer is not locked, IFS data is invalid. */ 864 ucontrol->value.integer.value[0] = 0; 865 goto pm_runtime_put; 866 } 867 868 rate = clk_get_rate(dev->gclk); 869 870 ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val)); 871 872 pm_runtime_put: 873 pm_runtime_put_autosuspend(dev->dev); 874 unlock: 875 mutex_unlock(&dev->mlock); 876 return ret; 877 } 878 879 static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = { 880 /* Channel status controller */ 881 { 882 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 883 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 884 " Channel 1", 885 .access = SNDRV_CTL_ELEM_ACCESS_READ | 886 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 887 .info = mchp_spdifrx_info, 888 .get = mchp_spdifrx_cs1_get, 889 }, 890 { 891 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 892 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT) 893 " Channel 2", 894 .access = SNDRV_CTL_ELEM_ACCESS_READ | 895 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 896 .info = mchp_spdifrx_info, 897 .get = mchp_spdifrx_cs2_get, 898 }, 899 { 900 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 901 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK), 902 .access = SNDRV_CTL_ELEM_ACCESS_READ, 903 .info = mchp_spdifrx_info, 904 .get = mchp_spdifrx_cs_mask, 905 }, 906 /* User bits controller */ 907 { 908 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 909 .name = "IEC958 Subcode Capture Default Channel 1", 910 .access = SNDRV_CTL_ELEM_ACCESS_READ | 911 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 912 .info = mchp_spdifrx_info, 913 .get = mchp_spdifrx_subcode_ch1_get, 914 }, 915 { 916 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 917 .name = "IEC958 Subcode Capture Default Channel 2", 918 .access = SNDRV_CTL_ELEM_ACCESS_READ | 919 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 920 .info = mchp_spdifrx_info, 921 .get = mchp_spdifrx_subcode_ch2_get, 922 }, 923 /* Lock status */ 924 { 925 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 926 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked", 927 .access = SNDRV_CTL_ELEM_ACCESS_READ | 928 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 929 .info = mchp_spdifrx_boolean_info, 930 .get = mchp_spdifrx_ulock_get, 931 }, 932 /* Bad format */ 933 { 934 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 935 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format", 936 .access = SNDRV_CTL_ELEM_ACCESS_READ | 937 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 938 .info = mchp_spdifrx_boolean_info, 939 .get = mchp_spdifrx_badf_get, 940 }, 941 /* Signal */ 942 { 943 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 944 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal", 945 .access = SNDRV_CTL_ELEM_ACCESS_READ | 946 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 947 .info = mchp_spdifrx_boolean_info, 948 .get = mchp_spdifrx_signal_get, 949 }, 950 /* Sampling rate */ 951 { 952 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 953 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate", 954 .access = SNDRV_CTL_ELEM_ACCESS_READ | 955 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 956 .info = mchp_spdifrx_rate_info, 957 .get = mchp_spdifrx_rate_get, 958 }, 959 }; 960 961 static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai) 962 { 963 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 964 struct mchp_spdifrx_mixer_control *ctrl = &dev->control; 965 int ch; 966 967 snd_soc_dai_init_dma_data(dai, NULL, &dev->capture); 968 969 /* Software reset the IP */ 970 regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST); 971 972 /* Default configuration */ 973 regmap_write(dev->regmap, SPDIFRX_MR, 974 SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 | 975 SPDIFRX_MR_SBMODE_DISCARD | 976 SPDIFRX_MR_AUTORST_NOACTION | 977 SPDIFRX_MR_PACK_DISABLED); 978 979 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) { 980 init_completion(&ctrl->ch_stat[ch].done); 981 init_completion(&ctrl->user_data[ch].done); 982 } 983 984 /* Add controls */ 985 snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls, 986 ARRAY_SIZE(mchp_spdifrx_ctrls)); 987 988 return 0; 989 } 990 991 static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai) 992 { 993 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai); 994 995 /* Disable interrupts */ 996 regmap_write(dev->regmap, SPDIFRX_IDR, GENMASK(14, 0)); 997 998 return 0; 999 } 1000 1001 static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = { 1002 .probe = mchp_spdifrx_dai_probe, 1003 .remove = mchp_spdifrx_dai_remove, 1004 .trigger = mchp_spdifrx_trigger, 1005 .hw_params = mchp_spdifrx_hw_params, 1006 }; 1007 1008 static struct snd_soc_dai_driver mchp_spdifrx_dai = { 1009 .name = "mchp-spdifrx", 1010 .capture = { 1011 .stream_name = "Capture", 1012 .channels_min = SPDIFRX_CHANNELS, 1013 .channels_max = SPDIFRX_CHANNELS, 1014 .rates = MCHP_SPDIF_RATES, 1015 .formats = MCHP_SPDIF_FORMATS, 1016 }, 1017 .ops = &mchp_spdifrx_dai_ops, 1018 }; 1019 1020 static const struct snd_soc_component_driver mchp_spdifrx_component = { 1021 .name = "mchp-spdifrx", 1022 .legacy_dai_naming = 1, 1023 }; 1024 1025 static const struct of_device_id mchp_spdifrx_dt_ids[] = { 1026 { 1027 .compatible = "microchip,sama7g5-spdifrx", 1028 }, 1029 { /* sentinel */ } 1030 }; 1031 MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids); 1032 1033 static int mchp_spdifrx_runtime_suspend(struct device *dev) 1034 { 1035 struct mchp_spdifrx_dev *spdifrx = dev_get_drvdata(dev); 1036 1037 regcache_cache_only(spdifrx->regmap, true); 1038 clk_disable_unprepare(spdifrx->gclk); 1039 clk_disable_unprepare(spdifrx->pclk); 1040 1041 return 0; 1042 } 1043 1044 static int mchp_spdifrx_runtime_resume(struct device *dev) 1045 { 1046 struct mchp_spdifrx_dev *spdifrx = dev_get_drvdata(dev); 1047 int ret; 1048 1049 ret = clk_prepare_enable(spdifrx->pclk); 1050 if (ret) 1051 return ret; 1052 1053 ret = clk_prepare_enable(spdifrx->gclk); 1054 if (ret) 1055 goto disable_pclk; 1056 1057 regcache_cache_only(spdifrx->regmap, false); 1058 regcache_mark_dirty(spdifrx->regmap); 1059 ret = regcache_sync(spdifrx->regmap); 1060 if (ret) { 1061 regcache_cache_only(spdifrx->regmap, true); 1062 clk_disable_unprepare(spdifrx->gclk); 1063 disable_pclk: 1064 clk_disable_unprepare(spdifrx->pclk); 1065 } 1066 1067 return ret; 1068 } 1069 1070 static const struct dev_pm_ops mchp_spdifrx_pm_ops = { 1071 RUNTIME_PM_OPS(mchp_spdifrx_runtime_suspend, mchp_spdifrx_runtime_resume, 1072 NULL) 1073 }; 1074 1075 static int mchp_spdifrx_probe(struct platform_device *pdev) 1076 { 1077 struct mchp_spdifrx_dev *dev; 1078 struct resource *mem; 1079 struct regmap *regmap; 1080 void __iomem *base; 1081 int irq; 1082 int err; 1083 u32 vers; 1084 1085 /* Get memory for driver data. */ 1086 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1087 if (!dev) 1088 return -ENOMEM; 1089 1090 /* Map I/O registers. */ 1091 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 1092 if (IS_ERR(base)) 1093 return PTR_ERR(base); 1094 1095 regmap = devm_regmap_init_mmio(&pdev->dev, base, 1096 &mchp_spdifrx_regmap_config); 1097 if (IS_ERR(regmap)) 1098 return PTR_ERR(regmap); 1099 1100 /* Request IRQ. */ 1101 irq = platform_get_irq(pdev, 0); 1102 if (irq < 0) 1103 return irq; 1104 1105 err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0, 1106 dev_name(&pdev->dev), dev); 1107 if (err) 1108 return err; 1109 1110 /* Get the peripheral clock */ 1111 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 1112 if (IS_ERR(dev->pclk)) { 1113 err = PTR_ERR(dev->pclk); 1114 dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n", 1115 err); 1116 return err; 1117 } 1118 1119 /* Get the generated clock */ 1120 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 1121 if (IS_ERR(dev->gclk)) { 1122 err = PTR_ERR(dev->gclk); 1123 dev_err(&pdev->dev, 1124 "failed to get the PMC generated clock: %d\n", err); 1125 return err; 1126 } 1127 1128 /* 1129 * Signal control need a valid rate on gclk. hw_params() configures 1130 * it propertly but requesting signal before any hw_params() has been 1131 * called lead to invalid value returned for signal. Thus, configure 1132 * gclk at a valid rate, here, in initialization, to simplify the 1133 * control path. 1134 */ 1135 clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1); 1136 1137 mutex_init(&dev->mlock); 1138 1139 dev->dev = &pdev->dev; 1140 dev->regmap = regmap; 1141 platform_set_drvdata(pdev, dev); 1142 1143 pm_runtime_enable(dev->dev); 1144 if (!pm_runtime_enabled(dev->dev)) { 1145 err = mchp_spdifrx_runtime_resume(dev->dev); 1146 if (err) 1147 goto pm_runtime_disable; 1148 } 1149 1150 dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR; 1151 dev->capture.maxburst = 1; 1152 1153 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1154 if (err) { 1155 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 1156 goto pm_runtime_suspend; 1157 } 1158 1159 err = devm_snd_soc_register_component(&pdev->dev, 1160 &mchp_spdifrx_component, 1161 &mchp_spdifrx_dai, 1); 1162 if (err) { 1163 dev_err(&pdev->dev, "fail to register dai\n"); 1164 goto pm_runtime_suspend; 1165 } 1166 1167 regmap_read(regmap, SPDIFRX_VERSION, &vers); 1168 dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK); 1169 1170 return 0; 1171 1172 pm_runtime_suspend: 1173 if (!pm_runtime_status_suspended(dev->dev)) 1174 mchp_spdifrx_runtime_suspend(dev->dev); 1175 pm_runtime_disable: 1176 pm_runtime_disable(dev->dev); 1177 return err; 1178 } 1179 1180 static void mchp_spdifrx_remove(struct platform_device *pdev) 1181 { 1182 struct mchp_spdifrx_dev *dev = platform_get_drvdata(pdev); 1183 1184 pm_runtime_disable(dev->dev); 1185 if (!pm_runtime_status_suspended(dev->dev)) 1186 mchp_spdifrx_runtime_suspend(dev->dev); 1187 } 1188 1189 static struct platform_driver mchp_spdifrx_driver = { 1190 .probe = mchp_spdifrx_probe, 1191 .remove = mchp_spdifrx_remove, 1192 .driver = { 1193 .name = "mchp_spdifrx", 1194 .of_match_table = mchp_spdifrx_dt_ids, 1195 .pm = pm_ptr(&mchp_spdifrx_pm_ops), 1196 }, 1197 }; 1198 1199 module_platform_driver(mchp_spdifrx_driver); 1200 1201 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1202 MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver"); 1203 MODULE_LICENSE("GPL v2"); 1204