1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces 4 // 5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries 6 // 7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 8 9 #include <dt-bindings/sound/microchip,pdmc.h> 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/core.h> 19 #include <sound/dmaengine_pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/tlv.h> 22 23 /* 24 * ---- PDMC Register map ---- 25 */ 26 #define MCHP_PDMC_CR 0x00 /* Control Register */ 27 #define MCHP_PDMC_MR 0x04 /* Mode Register */ 28 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */ 29 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */ 30 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */ 31 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */ 32 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */ 33 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */ 34 #define MCHP_PDMC_VER 0x50 /* Version Register */ 35 36 /* 37 * ---- Control Register (Write-only) ---- 38 */ 39 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */ 40 41 /* 42 * ---- Mode Register (Read/Write) ---- 43 */ 44 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0) 45 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK) 46 47 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16) 48 #define MCHP_PDMC_MR_OSR64 (1 << 16) 49 #define MCHP_PDMC_MR_OSR128 (2 << 16) 50 #define MCHP_PDMC_MR_OSR256 (3 << 16) 51 52 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20) 53 54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24) 55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24) 56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24) 57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24) 58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24) 59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24) 60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24) 61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24) 62 63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28) 64 65 /* 66 * ---- Configuration Register (Read/Write) ---- 67 */ 68 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6)) 69 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2) 70 71 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22)) 72 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16) 73 74 /* 75 * ---- Interrupt Enable/Disable/Mask/Status Registers ---- 76 */ 77 #define MCHP_PDMC_IR_RXRDY BIT(0) 78 #define MCHP_PDMC_IR_RXEMPTY BIT(1) 79 #define MCHP_PDMC_IR_RXFULL BIT(2) 80 #define MCHP_PDMC_IR_RXCHUNK BIT(3) 81 #define MCHP_PDMC_IR_RXUDR BIT(4) 82 #define MCHP_PDMC_IR_RXOVR BIT(5) 83 84 /* 85 * ---- Version Register (Read-only) ---- 86 */ 87 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0) 88 89 #define MCHP_PDMC_MAX_CHANNELS 4 90 #define MCHP_PDMC_DS_NO 2 91 #define MCHP_PDMC_EDGE_NO 2 92 93 struct mic_map { 94 int ds_pos; 95 int clk_edge; 96 }; 97 98 struct mchp_pdmc_chmap { 99 struct snd_pcm_chmap_elem *chmap; 100 struct mchp_pdmc *dd; 101 struct snd_pcm *pcm; 102 struct snd_kcontrol *kctl; 103 }; 104 105 struct mchp_pdmc { 106 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS]; 107 struct device *dev; 108 struct snd_dmaengine_dai_dma_data addr; 109 struct regmap *regmap; 110 struct clk *pclk; 111 struct clk *gclk; 112 u32 pdmcen; 113 u32 suspend_irq; 114 u32 startup_delay_us; 115 int mic_no; 116 int sinc_order; 117 bool audio_filter_en; 118 }; 119 120 static const char *const mchp_pdmc_sinc_filter_order_text[] = { 121 "1", "2", "3", "4", "5" 122 }; 123 124 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = { 125 1, 2, 3, 4, 5, 126 }; 127 128 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = { 129 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text), 130 .texts = mchp_pdmc_sinc_filter_order_text, 131 .values = mchp_pdmc_sinc_filter_order_values, 132 }; 133 134 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol, 135 struct snd_ctl_elem_value *uvalue) 136 { 137 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 138 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 139 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 140 unsigned int item; 141 142 item = snd_soc_enum_val_to_item(e, dd->sinc_order); 143 uvalue->value.enumerated.item[0] = item; 144 145 return 0; 146 } 147 148 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol, 149 struct snd_ctl_elem_value *uvalue) 150 { 151 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 152 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 153 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 154 unsigned int *item = uvalue->value.enumerated.item; 155 unsigned int val; 156 157 if (item[0] >= e->items) 158 return -EINVAL; 159 160 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 161 if (val == dd->sinc_order) 162 return 0; 163 164 dd->sinc_order = val; 165 166 return 1; 167 } 168 169 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol, 170 struct snd_ctl_elem_value *uvalue) 171 { 172 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 173 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 174 175 uvalue->value.integer.value[0] = !!dd->audio_filter_en; 176 177 return 0; 178 } 179 180 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol, 181 struct snd_ctl_elem_value *uvalue) 182 { 183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 184 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component); 185 bool af = uvalue->value.integer.value[0] ? true : false; 186 187 if (dd->audio_filter_en == af) 188 return 0; 189 190 dd->audio_filter_en = af; 191 192 return 1; 193 } 194 195 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 196 { 197 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 198 199 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 200 uinfo->count = info->dd->mic_no; 201 uinfo->value.integer.min = 0; 202 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */ 203 return 0; 204 } 205 206 static inline struct snd_pcm_substream * 207 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx) 208 { 209 struct snd_pcm_substream *s; 210 211 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next) 212 if (s->number == idx) 213 return s; 214 return NULL; 215 } 216 217 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream, 218 struct mchp_pdmc_chmap *ch_info) 219 { 220 struct snd_pcm_chmap_elem *map; 221 222 for (map = ch_info->chmap; map->channels; map++) { 223 if (map->channels == substream->runtime->channels) 224 return map; 225 } 226 return NULL; 227 } 228 229 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol, 230 struct snd_ctl_elem_value *ucontrol) 231 { 232 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 233 struct mchp_pdmc *dd = info->dd; 234 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 235 struct snd_pcm_substream *substream; 236 const struct snd_pcm_chmap_elem *map; 237 int i; 238 u32 cfgr_val = 0; 239 240 if (!info->chmap) 241 return -EINVAL; 242 substream = mchp_pdmc_chmap_substream(info, idx); 243 if (!substream) 244 return -ENODEV; 245 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no); 246 if (!substream->runtime) 247 return 0; /* no channels set */ 248 249 map = mchp_pdmc_chmap_get(substream, info); 250 if (!map) 251 return -EINVAL; 252 253 for (i = 0; i < map->channels; i++) { 254 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 255 map->map[i] - SNDRV_CHMAP_FL; 256 257 /* make sure the reported channel map is the real one, so write the map */ 258 if (dd->channel_mic_map[map_idx].ds_pos) 259 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 260 if (dd->channel_mic_map[map_idx].clk_edge) 261 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 262 263 ucontrol->value.integer.value[i] = map->map[i]; 264 } 265 266 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 267 268 return 0; 269 } 270 271 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol, 272 struct snd_ctl_elem_value *ucontrol) 273 { 274 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 275 struct mchp_pdmc *dd = info->dd; 276 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 277 struct snd_pcm_substream *substream; 278 struct snd_pcm_chmap_elem *map; 279 u32 cfgr_val = 0; 280 int i; 281 282 if (!info->chmap) 283 return -EINVAL; 284 substream = mchp_pdmc_chmap_substream(info, idx); 285 if (!substream) 286 return -ENODEV; 287 288 map = mchp_pdmc_chmap_get(substream, info); 289 if (!map) 290 return -EINVAL; 291 292 for (i = 0; i < map->channels; i++) { 293 int map_idx; 294 295 map->map[i] = ucontrol->value.integer.value[i]; 296 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO : 297 map->map[i] - SNDRV_CHMAP_FL; 298 299 /* configure IP for the desired channel map */ 300 if (dd->channel_mic_map[map_idx].ds_pos) 301 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 302 if (dd->channel_mic_map[map_idx].clk_edge) 303 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 304 } 305 306 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val); 307 308 return 0; 309 } 310 311 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol) 312 { 313 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 314 315 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL; 316 kfree(info); 317 } 318 319 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, 320 unsigned int size, unsigned int __user *tlv) 321 { 322 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol); 323 const struct snd_pcm_chmap_elem *map; 324 unsigned int __user *dst; 325 int c, count = 0; 326 327 if (!info->chmap) 328 return -EINVAL; 329 if (size < 8) 330 return -ENOMEM; 331 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) 332 return -EFAULT; 333 size -= 8; 334 dst = tlv + 2; 335 for (map = info->chmap; map->channels; map++) { 336 int chs_bytes = map->channels * 4; 337 338 if (size < 8) 339 return -ENOMEM; 340 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) || 341 put_user(chs_bytes, dst + 1)) 342 return -EFAULT; 343 dst += 2; 344 size -= 8; 345 count += 8; 346 if (size < chs_bytes) 347 return -ENOMEM; 348 size -= chs_bytes; 349 count += chs_bytes; 350 for (c = 0; c < map->channels; c++) { 351 if (put_user(map->map[c], dst)) 352 return -EFAULT; 353 dst++; 354 } 355 } 356 if (put_user(count, tlv + 1)) 357 return -EFAULT; 358 return 0; 359 } 360 361 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = { 362 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put), 363 { 364 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 365 .name = "SINC Filter Order", 366 .info = snd_soc_info_enum_double, 367 .get = mchp_pdmc_sinc_order_get, 368 .put = mchp_pdmc_sinc_order_put, 369 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum, 370 }, 371 }; 372 373 static int mchp_pdmc_close(struct snd_soc_component *component, 374 struct snd_pcm_substream *substream) 375 { 376 return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls, 377 ARRAY_SIZE(mchp_pdmc_snd_controls)); 378 } 379 380 static int mchp_pdmc_open(struct snd_soc_component *component, 381 struct snd_pcm_substream *substream) 382 { 383 int i; 384 385 /* remove controls that can't be changed at runtime */ 386 for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) { 387 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i]; 388 struct snd_ctl_elem_id id; 389 int err; 390 391 if (component->name_prefix) 392 snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix, 393 control->name); 394 else 395 strscpy(id.name, control->name, sizeof(id.name)); 396 397 id.numid = 0; 398 id.iface = control->iface; 399 id.device = control->device; 400 id.subdevice = control->subdevice; 401 id.index = control->index; 402 err = snd_ctl_remove_id(component->card->snd_card, &id); 403 if (err < 0) 404 dev_err(component->dev, "%d: Failed to remove %s\n", err, 405 control->name); 406 } 407 408 return 0; 409 } 410 411 static const struct snd_soc_component_driver mchp_pdmc_dai_component = { 412 .name = "mchp-pdmc", 413 .controls = mchp_pdmc_snd_controls, 414 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls), 415 .open = &mchp_pdmc_open, 416 .close = &mchp_pdmc_close, 417 .legacy_dai_naming = 1, 418 .trigger_start = SND_SOC_TRIGGER_ORDER_LDC, 419 }; 420 421 static const unsigned int mchp_pdmc_1mic[] = {1}; 422 static const unsigned int mchp_pdmc_2mic[] = {1, 2}; 423 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3}; 424 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4}; 425 426 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = { 427 { 428 .list = mchp_pdmc_1mic, 429 .count = ARRAY_SIZE(mchp_pdmc_1mic), 430 }, 431 { 432 .list = mchp_pdmc_2mic, 433 .count = ARRAY_SIZE(mchp_pdmc_2mic), 434 }, 435 { 436 .list = mchp_pdmc_3mic, 437 .count = ARRAY_SIZE(mchp_pdmc_3mic), 438 }, 439 { 440 .list = mchp_pdmc_4mic, 441 .count = ARRAY_SIZE(mchp_pdmc_4mic), 442 }, 443 }; 444 445 static int mchp_pdmc_startup(struct snd_pcm_substream *substream, 446 struct snd_soc_dai *dai) 447 { 448 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 449 450 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); 451 452 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 453 &mchp_pdmc_chan_constr[dd->mic_no - 1]); 454 455 return 0; 456 } 457 458 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) 459 { 460 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 461 462 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr); 463 464 return 0; 465 } 466 467 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 468 { 469 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK; 470 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 471 472 /* IP needs to be bitclock master */ 473 if (fmt_master != SND_SOC_DAIFMT_BP_FP && 474 fmt_master != SND_SOC_DAIFMT_BP_FC) 475 return -EINVAL; 476 477 /* IP supports only PDM interface */ 478 if (fmt_format != SND_SOC_DAIFMT_PDM) 479 return -EINVAL; 480 481 return 0; 482 } 483 484 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr) 485 { 486 if (audio_filter_en) { 487 switch (osr) { 488 case 64: 489 return MCHP_PDMC_MR_OSR64; 490 case 128: 491 return MCHP_PDMC_MR_OSR128; 492 case 256: 493 return MCHP_PDMC_MR_OSR256; 494 } 495 } else { 496 switch (osr) { 497 case 8: 498 return MCHP_PDMC_MR_SINC_OSR_8; 499 case 16: 500 return MCHP_PDMC_MR_SINC_OSR_16; 501 case 32: 502 return MCHP_PDMC_MR_SINC_OSR_32; 503 case 64: 504 return MCHP_PDMC_MR_SINC_OSR_64; 505 case 128: 506 return MCHP_PDMC_MR_SINC_OSR_128; 507 case 256: 508 return MCHP_PDMC_MR_SINC_OSR_256; 509 } 510 } 511 return 0; 512 } 513 514 static inline int mchp_pdmc_period_to_maxburst(int period_size) 515 { 516 if (!(period_size % 8)) 517 return 8; 518 if (!(period_size % 4)) 519 return 4; 520 if (!(period_size % 2)) 521 return 2; 522 return 1; 523 } 524 525 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = { 526 { .channels = 1, 527 .map = { SNDRV_CHMAP_MONO } }, 528 { .channels = 2, 529 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 530 { .channels = 3, 531 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 532 SNDRV_CHMAP_RL } }, 533 { .channels = 4, 534 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 535 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 536 { } 537 }; 538 539 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream, 540 struct snd_pcm_hw_params *params, 541 struct snd_soc_dai *dai) 542 { 543 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 544 struct snd_soc_component *comp = dai->component; 545 unsigned long gclk_rate = 0; 546 unsigned long best_diff_rate = ~0UL; 547 unsigned int channels = params_channels(params); 548 unsigned int osr = 0, osr_start; 549 unsigned int fs = params_rate(params); 550 u32 mr_val = 0; 551 u32 cfgr_val = 0; 552 int i; 553 int ret; 554 555 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", 556 __func__, params_rate(params), params_format(params), 557 params_width(params), params_channels(params)); 558 559 if (channels > dd->mic_no) { 560 dev_err(comp->dev, "more channels %u than microphones %d\n", 561 channels, dd->mic_no); 562 return -EINVAL; 563 } 564 565 dd->pdmcen = 0; 566 for (i = 0; i < channels; i++) { 567 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i); 568 if (dd->channel_mic_map[i].ds_pos) 569 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i); 570 if (dd->channel_mic_map[i].clk_edge) 571 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i); 572 } 573 574 for (osr_start = dd->audio_filter_en ? 64 : 8; 575 osr_start <= 256 && best_diff_rate; osr_start *= 2) { 576 long round_rate; 577 unsigned long diff_rate; 578 579 round_rate = clk_round_rate(dd->gclk, 580 (unsigned long)fs * 16 * osr_start); 581 if (round_rate < 0) 582 continue; 583 diff_rate = abs((fs * 16 * osr_start) - round_rate); 584 if (diff_rate < best_diff_rate) { 585 best_diff_rate = diff_rate; 586 osr = osr_start; 587 gclk_rate = fs * 16 * osr; 588 } 589 } 590 if (!gclk_rate) { 591 dev_err(comp->dev, "invalid sampling rate: %u\n", fs); 592 return -EINVAL; 593 } 594 595 /* CLK is enabled by runtime PM. */ 596 clk_disable_unprepare(dd->gclk); 597 598 /* set the rate */ 599 ret = clk_set_rate(dd->gclk, gclk_rate); 600 clk_prepare_enable(dd->gclk); 601 if (ret) { 602 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", 603 gclk_rate, ret); 604 return ret; 605 } 606 607 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr); 608 609 mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order); 610 611 dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream)); 612 mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst); 613 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); 614 615 snd_soc_component_update_bits(comp, MCHP_PDMC_MR, 616 MCHP_PDMC_MR_OSR_MASK | 617 MCHP_PDMC_MR_SINCORDER_MASK | 618 MCHP_PDMC_MR_SINC_OSR_MASK | 619 MCHP_PDMC_MR_CHUNK_MASK, mr_val); 620 621 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val); 622 623 return 0; 624 } 625 626 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd) 627 { 628 u32 tmp, steps = 16; 629 630 /* 631 * PDMC doesn't wait for microphones' startup time thus the acquisition 632 * may start before the microphones are ready leading to poc noises at 633 * the beginning of capture. To avoid this, we need to wait 50ms (in 634 * normal startup procedure) or 150 ms (worst case after resume from sleep 635 * states) after microphones are enabled and then clear the FIFOs (by 636 * reading the RHR 16 times) and possible interrupts before continuing. 637 * Also, for this to work the DMA needs to be started after interrupts 638 * are enabled. 639 */ 640 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5); 641 642 while (steps--) 643 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp); 644 645 /* Clear interrupts. */ 646 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp); 647 } 648 649 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, 650 int cmd, struct snd_soc_dai *dai) 651 { 652 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 653 struct snd_soc_component *cpu = dai->component; 654 #ifdef DEBUG 655 u32 val; 656 #endif 657 658 switch (cmd) { 659 case SNDRV_PCM_TRIGGER_RESUME: 660 case SNDRV_PCM_TRIGGER_START: 661 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 662 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 663 MCHP_PDMC_MR_PDMCEN_MASK, 664 dd->pdmcen); 665 666 mchp_pdmc_noise_filter_workaround(dd); 667 668 /* Enable interrupts. */ 669 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq | 670 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 671 dd->suspend_irq = 0; 672 break; 673 case SNDRV_PCM_TRIGGER_SUSPEND: 674 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq); 675 fallthrough; 676 case SNDRV_PCM_TRIGGER_STOP: 677 /* Disable overrun and underrun error interrupts */ 678 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq | 679 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); 680 fallthrough; 681 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 682 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, 683 MCHP_PDMC_MR_PDMCEN_MASK, 0); 684 break; 685 default: 686 return -EINVAL; 687 } 688 689 #ifdef DEBUG 690 regmap_read(dd->regmap, MCHP_PDMC_MR, &val); 691 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val); 692 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val); 693 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val); 694 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val); 695 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val); 696 #endif 697 698 return 0; 699 } 700 701 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd) 702 { 703 struct mchp_pdmc_chmap *info; 704 struct snd_kcontrol_new knew = { 705 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 706 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 707 SNDRV_CTL_ELEM_ACCESS_TLV_READ | 708 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, 709 .info = mchp_pdmc_chmap_ctl_info, 710 .get = mchp_pdmc_chmap_ctl_get, 711 .put = mchp_pdmc_chmap_ctl_put, 712 .tlv.c = mchp_pdmc_chmap_ctl_tlv, 713 }; 714 int err; 715 716 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl)) 717 return -EBUSY; 718 info = kzalloc(sizeof(*info), GFP_KERNEL); 719 if (!info) 720 return -ENOMEM; 721 info->pcm = pcm; 722 info->dd = dd; 723 info->chmap = mchp_pdmc_std_chmaps; 724 knew.name = "Capture Channel Map"; 725 knew.device = pcm->device; 726 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count; 727 info->kctl = snd_ctl_new1(&knew, info); 728 if (!info->kctl) { 729 kfree(info); 730 return -ENOMEM; 731 } 732 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free; 733 err = snd_ctl_add(pcm->card, info->kctl); 734 if (err < 0) 735 return err; 736 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl; 737 return 0; 738 } 739 740 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd, 741 struct snd_soc_dai *dai) 742 { 743 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai); 744 int ret; 745 746 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd); 747 if (ret < 0) 748 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret); 749 750 return ret; 751 } 752 753 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = { 754 .probe = mchp_pdmc_dai_probe, 755 .set_fmt = mchp_pdmc_set_fmt, 756 .startup = mchp_pdmc_startup, 757 .hw_params = mchp_pdmc_hw_params, 758 .trigger = mchp_pdmc_trigger, 759 .pcm_new = &mchp_pdmc_pcm_new, 760 }; 761 762 static struct snd_soc_dai_driver mchp_pdmc_dai = { 763 .capture = { 764 .stream_name = "Capture", 765 .channels_min = 1, 766 .channels_max = 4, 767 .rate_min = 8000, 768 .rate_max = 192000, 769 .rates = SNDRV_PCM_RATE_KNOT, 770 .formats = SNDRV_PCM_FMTBIT_S24_LE, 771 }, 772 .ops = &mchp_pdmc_dai_ops, 773 }; 774 775 /* PDMC interrupt handler */ 776 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id) 777 { 778 struct mchp_pdmc *dd = dev_id; 779 u32 isr, msr, pending; 780 irqreturn_t ret = IRQ_NONE; 781 782 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr); 783 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr); 784 785 pending = isr & msr; 786 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n", 787 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending); 788 if (!pending) 789 return IRQ_NONE; 790 791 if (pending & MCHP_PDMC_IR_RXUDR) { 792 dev_warn(dd->dev, "underrun detected\n"); 793 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR); 794 ret = IRQ_HANDLED; 795 } 796 if (pending & MCHP_PDMC_IR_RXOVR) { 797 dev_warn(dd->dev, "overrun detected\n"); 798 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR); 799 ret = IRQ_HANDLED; 800 } 801 802 return ret; 803 } 804 805 /* regmap configuration */ 806 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg) 807 { 808 switch (reg) { 809 case MCHP_PDMC_MR: 810 case MCHP_PDMC_CFGR: 811 case MCHP_PDMC_IMR: 812 case MCHP_PDMC_ISR: 813 case MCHP_PDMC_RHR: 814 case MCHP_PDMC_VER: 815 return true; 816 default: 817 return false; 818 } 819 } 820 821 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg) 822 { 823 switch (reg) { 824 case MCHP_PDMC_CR: 825 case MCHP_PDMC_MR: 826 case MCHP_PDMC_CFGR: 827 case MCHP_PDMC_IER: 828 case MCHP_PDMC_IDR: 829 return true; 830 default: 831 return false; 832 } 833 } 834 835 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg) 836 { 837 switch (reg) { 838 case MCHP_PDMC_ISR: 839 case MCHP_PDMC_RHR: 840 return true; 841 default: 842 return false; 843 } 844 } 845 846 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg) 847 { 848 switch (reg) { 849 case MCHP_PDMC_RHR: 850 case MCHP_PDMC_ISR: 851 return true; 852 default: 853 return false; 854 } 855 } 856 857 static const struct regmap_config mchp_pdmc_regmap_config = { 858 .reg_bits = 32, 859 .reg_stride = 4, 860 .val_bits = 32, 861 .max_register = MCHP_PDMC_VER, 862 .readable_reg = mchp_pdmc_readable_reg, 863 .writeable_reg = mchp_pdmc_writeable_reg, 864 .precious_reg = mchp_pdmc_precious_reg, 865 .volatile_reg = mchp_pdmc_volatile_reg, 866 .cache_type = REGCACHE_FLAT, 867 }; 868 869 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) 870 { 871 struct device_node *np = dd->dev->of_node; 872 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0}; 873 int i; 874 int ret; 875 876 if (!np) { 877 dev_err(dd->dev, "device node not found\n"); 878 return -EINVAL; 879 } 880 881 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos"); 882 if (dd->mic_no < 0) { 883 dev_err(dd->dev, "failed to get microchip,mic-pos: %d", 884 dd->mic_no); 885 return dd->mic_no; 886 } 887 if (!dd->mic_no || dd->mic_no % 2 || 888 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) { 889 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d", 890 dd->mic_no); 891 return -EINVAL; 892 } 893 894 dd->mic_no /= 2; 895 896 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no); 897 898 /* 899 * by default, we consider the order of microphones in 900 * microchip,mic-pos to be the same with the channel mapping; 901 * 1st microphone channel 0, 2nd microphone channel 1, etc. 902 */ 903 for (i = 0; i < dd->mic_no; i++) { 904 int ds; 905 int edge; 906 907 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2, 908 &ds); 909 if (ret) { 910 dev_err(dd->dev, 911 "failed to get value no %d value from microchip,mic-pos: %d", 912 i * 2, ret); 913 return ret; 914 } 915 if (ds >= MCHP_PDMC_DS_NO) { 916 dev_err(dd->dev, 917 "invalid DS index in microchip,mic-pos array: %d", 918 ds); 919 return -EINVAL; 920 } 921 922 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1, 923 &edge); 924 if (ret) { 925 dev_err(dd->dev, 926 "failed to get value no %d value from microchip,mic-pos: %d", 927 i * 2 + 1, ret); 928 return ret; 929 } 930 931 if (edge != MCHP_PDMC_CLK_POSITIVE && 932 edge != MCHP_PDMC_CLK_NEGATIVE) { 933 dev_err(dd->dev, 934 "invalid edge in microchip,mic-pos array: %d", edge); 935 return -EINVAL; 936 } 937 if (mic_ch[ds][edge]) { 938 dev_err(dd->dev, 939 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array", 940 ds, edge); 941 return -EINVAL; 942 } 943 mic_ch[ds][edge] = true; 944 dd->channel_mic_map[i].ds_pos = ds; 945 dd->channel_mic_map[i].clk_edge = edge; 946 } 947 948 dd->startup_delay_us = 150000; 949 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us); 950 951 return 0; 952 } 953 954 /* used to clean the channel index found on RHR's MSB */ 955 static int mchp_pdmc_process(struct snd_pcm_substream *substream, 956 int channel, unsigned long hwoff, 957 unsigned long bytes) 958 { 959 struct snd_pcm_runtime *runtime = substream->runtime; 960 u8 *dma_ptr = runtime->dma_area + hwoff + 961 channel * (runtime->dma_bytes / runtime->channels); 962 u8 *dma_ptr_end = dma_ptr + bytes; 963 unsigned int sample_size = samples_to_bytes(runtime, 1); 964 965 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size) 966 *dma_ptr = 0; 967 968 return 0; 969 } 970 971 static struct snd_dmaengine_pcm_config mchp_pdmc_config = { 972 .process = mchp_pdmc_process, 973 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 974 }; 975 976 static int mchp_pdmc_runtime_suspend(struct device *dev) 977 { 978 struct mchp_pdmc *dd = dev_get_drvdata(dev); 979 980 regcache_cache_only(dd->regmap, true); 981 982 clk_disable_unprepare(dd->gclk); 983 clk_disable_unprepare(dd->pclk); 984 985 return 0; 986 } 987 988 static int mchp_pdmc_runtime_resume(struct device *dev) 989 { 990 struct mchp_pdmc *dd = dev_get_drvdata(dev); 991 int ret; 992 993 ret = clk_prepare_enable(dd->pclk); 994 if (ret) { 995 dev_err(dd->dev, 996 "failed to enable the peripheral clock: %d\n", ret); 997 return ret; 998 } 999 ret = clk_prepare_enable(dd->gclk); 1000 if (ret) { 1001 dev_err(dd->dev, 1002 "failed to enable generic clock: %d\n", ret); 1003 goto disable_pclk; 1004 } 1005 1006 regcache_cache_only(dd->regmap, false); 1007 regcache_mark_dirty(dd->regmap); 1008 ret = regcache_sync(dd->regmap); 1009 if (ret) { 1010 regcache_cache_only(dd->regmap, true); 1011 clk_disable_unprepare(dd->gclk); 1012 disable_pclk: 1013 clk_disable_unprepare(dd->pclk); 1014 } 1015 1016 return ret; 1017 } 1018 1019 static int mchp_pdmc_probe(struct platform_device *pdev) 1020 { 1021 struct device *dev = &pdev->dev; 1022 struct mchp_pdmc *dd; 1023 struct resource *res; 1024 void __iomem *io_base; 1025 u32 version; 1026 int irq; 1027 int ret; 1028 1029 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL); 1030 if (!dd) 1031 return -ENOMEM; 1032 1033 dd->dev = &pdev->dev; 1034 ret = mchp_pdmc_dt_init(dd); 1035 if (ret < 0) 1036 return ret; 1037 1038 irq = platform_get_irq(pdev, 0); 1039 if (irq < 0) 1040 return irq; 1041 1042 dd->pclk = devm_clk_get(dev, "pclk"); 1043 if (IS_ERR(dd->pclk)) { 1044 ret = PTR_ERR(dd->pclk); 1045 dev_err(dev, "failed to get peripheral clock: %d\n", ret); 1046 return ret; 1047 } 1048 1049 dd->gclk = devm_clk_get(dev, "gclk"); 1050 if (IS_ERR(dd->gclk)) { 1051 ret = PTR_ERR(dd->gclk); 1052 dev_err(dev, "failed to get GCK: %d\n", ret); 1053 return ret; 1054 } 1055 1056 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1057 if (IS_ERR(io_base)) { 1058 ret = PTR_ERR(io_base); 1059 dev_err(dev, "failed to remap register memory: %d\n", ret); 1060 return ret; 1061 } 1062 1063 dd->regmap = devm_regmap_init_mmio(dev, io_base, 1064 &mchp_pdmc_regmap_config); 1065 if (IS_ERR(dd->regmap)) { 1066 ret = PTR_ERR(dd->regmap); 1067 dev_err(dev, "failed to init register map: %d\n", ret); 1068 return ret; 1069 } 1070 1071 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0, 1072 dev_name(&pdev->dev), dd); 1073 if (ret < 0) { 1074 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", 1075 irq, ret); 1076 return ret; 1077 } 1078 1079 /* by default audio filter is enabled and the SINC Filter order 1080 * will be set to the recommended value, 3 1081 */ 1082 dd->audio_filter_en = true; 1083 dd->sinc_order = 3; 1084 1085 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR; 1086 platform_set_drvdata(pdev, dd); 1087 1088 pm_runtime_enable(dd->dev); 1089 if (!pm_runtime_enabled(dd->dev)) { 1090 ret = mchp_pdmc_runtime_resume(dd->dev); 1091 if (ret) 1092 return ret; 1093 } 1094 1095 /* register platform */ 1096 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); 1097 if (ret) { 1098 dev_err(dev, "could not register platform: %d\n", ret); 1099 goto pm_runtime_suspend; 1100 } 1101 1102 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, 1103 &mchp_pdmc_dai, 1); 1104 if (ret) { 1105 dev_err(dev, "could not register CPU DAI: %d\n", ret); 1106 goto pm_runtime_suspend; 1107 } 1108 1109 /* print IP version */ 1110 regmap_read(dd->regmap, MCHP_PDMC_VER, &version); 1111 dev_info(dd->dev, "hw version: %#lx\n", 1112 version & MCHP_PDMC_VER_VERSION); 1113 1114 return 0; 1115 1116 pm_runtime_suspend: 1117 if (!pm_runtime_status_suspended(dd->dev)) 1118 mchp_pdmc_runtime_suspend(dd->dev); 1119 pm_runtime_disable(dd->dev); 1120 1121 return ret; 1122 } 1123 1124 static void mchp_pdmc_remove(struct platform_device *pdev) 1125 { 1126 struct mchp_pdmc *dd = platform_get_drvdata(pdev); 1127 1128 if (!pm_runtime_status_suspended(dd->dev)) 1129 mchp_pdmc_runtime_suspend(dd->dev); 1130 1131 pm_runtime_disable(dd->dev); 1132 } 1133 1134 static const struct of_device_id mchp_pdmc_of_match[] = { 1135 { 1136 .compatible = "microchip,sama7g5-pdmc", 1137 }, { 1138 /* sentinel */ 1139 } 1140 }; 1141 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); 1142 1143 static const struct dev_pm_ops mchp_pdmc_pm_ops = { 1144 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1145 RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, 1146 NULL) 1147 }; 1148 1149 static struct platform_driver mchp_pdmc_driver = { 1150 .driver = { 1151 .name = "mchp-pdmc", 1152 .of_match_table = of_match_ptr(mchp_pdmc_of_match), 1153 .pm = pm_ptr(&mchp_pdmc_pm_ops), 1154 }, 1155 .probe = mchp_pdmc_probe, 1156 .remove_new = mchp_pdmc_remove, 1157 }; 1158 module_platform_driver(mchp_pdmc_driver); 1159 1160 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture"); 1161 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>"); 1162 MODULE_LICENSE("GPL v2"); 1163