1 /* 2 * Driver for Atmel I2S controller 3 * 4 * Copyright (C) 2015 Atmel Corporation 5 * 6 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/module.h> 23 #include <linux/device.h> 24 #include <linux/slab.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 #include <linux/clk.h> 28 #include <linux/mfd/syscon.h> 29 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/initval.h> 34 #include <sound/soc.h> 35 #include <sound/dmaengine_pcm.h> 36 37 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8 38 39 /* 40 * ---- I2S Controller Register map ---- 41 */ 42 #define ATMEL_I2SC_CR 0x0000 /* Control Register */ 43 #define ATMEL_I2SC_MR 0x0004 /* Mode Register */ 44 #define ATMEL_I2SC_SR 0x0008 /* Status Register */ 45 #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */ 46 #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */ 47 #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */ 48 #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */ 49 #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */ 50 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */ 51 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */ 52 #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */ 53 54 /* 55 * ---- Control Register (Write-only) ---- 56 */ 57 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */ 58 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */ 59 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ 60 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ 61 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */ 62 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */ 63 #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */ 64 65 /* 66 * ---- Mode Register (Read/Write) ---- 67 */ 68 #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0) 69 #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0) 70 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0) 71 72 #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2) 73 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2) 74 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2) 75 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2) 76 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2) 77 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2) 78 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2) 79 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2) 80 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2) 81 82 #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6) 83 #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6) 84 #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */ 85 #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6) 86 #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6) 87 88 /* Left audio samples duplicated to right audio channel */ 89 #define ATMEL_I2SC_MR_RXMONO BIT(8) 90 91 /* Receiver uses one DMA channel ... */ 92 #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9) 93 #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */ 94 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */ 95 96 /* I2SDO output of I2SC is internally connected to I2SDI input */ 97 #define ATMEL_I2SC_MR_RXLOOP BIT(10) 98 99 /* Left audio samples duplicated to right audio channel */ 100 #define ATMEL_I2SC_MR_TXMONO BIT(12) 101 102 /* Transmitter uses one DMA channel ... */ 103 #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13) 104 #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */ 105 #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */ 106 107 /* x sample transmitted when underrun */ 108 #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14) 109 #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */ 110 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */ 111 112 /* Audio Clock to I2SC Master Clock ratio */ 113 #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16) 114 #define ATMEL_I2SC_MR_IMCKDIV(div) \ 115 (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK) 116 117 /* Master Clock to fs ratio */ 118 #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24) 119 #define ATMEL_I2SC_MR_IMCKFS(fs) \ 120 (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK) 121 122 /* Master Clock mode */ 123 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30) 124 /* 0: No master clock generated (selected clock drives I2SCK pin) */ 125 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30) 126 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */ 127 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30) 128 129 /* Slot Width */ 130 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */ 131 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */ 132 #define ATMEL_I2SC_MR_IWS BIT(31) 133 134 /* 135 * ---- Status Registers ---- 136 */ 137 #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */ 138 #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */ 139 #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */ 140 141 #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */ 142 #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */ 143 #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */ 144 145 /* Receive Overrun Channel */ 146 #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8) 147 #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8)) 148 149 /* Transmit Underrun Channel */ 150 #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20) 151 #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20)) 152 153 /* 154 * ---- Interrupt Enable/Disable/Mask Registers ---- 155 */ 156 #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY 157 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR 158 #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY 159 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR 160 161 static const struct regmap_config atmel_i2s_regmap_config = { 162 .reg_bits = 32, 163 .reg_stride = 4, 164 .val_bits = 32, 165 .max_register = ATMEL_I2SC_VERSION, 166 }; 167 168 struct atmel_i2s_gck_param { 169 int fs; 170 unsigned long mck; 171 int imckdiv; 172 int imckfs; 173 }; 174 175 #define I2S_MCK_12M288 12288000UL 176 #define I2S_MCK_11M2896 11289600UL 177 178 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ 179 static const struct atmel_i2s_gck_param gck_params[] = { 180 /* mck = 12.288MHz */ 181 { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */ 182 { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ 183 { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ 184 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ 185 { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */ 186 { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */ 187 { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */ 188 {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */ 189 190 /* mck = 11.2896MHz */ 191 { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */ 192 { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */ 193 { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */ 194 { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */ 195 {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */ 196 }; 197 198 struct atmel_i2s_dev; 199 200 struct atmel_i2s_caps { 201 int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np); 202 }; 203 204 struct atmel_i2s_dev { 205 struct device *dev; 206 struct regmap *regmap; 207 struct clk *pclk; 208 struct clk *gclk; 209 struct clk *aclk; 210 struct snd_dmaengine_dai_dma_data playback; 211 struct snd_dmaengine_dai_dma_data capture; 212 unsigned int fmt; 213 const struct atmel_i2s_gck_param *gck_param; 214 const struct atmel_i2s_caps *caps; 215 }; 216 217 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id) 218 { 219 struct atmel_i2s_dev *dev = dev_id; 220 unsigned int sr, imr, pending, ch, mask; 221 irqreturn_t ret = IRQ_NONE; 222 223 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 224 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr); 225 pending = sr & imr; 226 227 if (!pending) 228 return IRQ_NONE; 229 230 if (pending & ATMEL_I2SC_INT_RXOR) { 231 mask = ATMEL_I2SC_SR_RXOR; 232 233 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 234 if (sr & ATMEL_I2SC_SR_RXORCH(ch)) { 235 mask |= ATMEL_I2SC_SR_RXORCH(ch); 236 dev_err(dev->dev, 237 "RX overrun on channel %d\n", ch); 238 } 239 } 240 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 241 ret = IRQ_HANDLED; 242 } 243 244 if (pending & ATMEL_I2SC_INT_TXUR) { 245 mask = ATMEL_I2SC_SR_TXUR; 246 247 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 248 if (sr & ATMEL_I2SC_SR_TXURCH(ch)) { 249 mask |= ATMEL_I2SC_SR_TXURCH(ch); 250 dev_err(dev->dev, 251 "TX underrun on channel %d\n", ch); 252 } 253 } 254 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 255 ret = IRQ_HANDLED; 256 } 257 258 return ret; 259 } 260 261 #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000 262 263 #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 264 SNDRV_PCM_FMTBIT_S16_LE | \ 265 SNDRV_PCM_FMTBIT_S18_3LE | \ 266 SNDRV_PCM_FMTBIT_S20_3LE | \ 267 SNDRV_PCM_FMTBIT_S24_3LE | \ 268 SNDRV_PCM_FMTBIT_S24_LE | \ 269 SNDRV_PCM_FMTBIT_S32_LE) 270 271 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 272 { 273 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 274 275 dev->fmt = fmt; 276 return 0; 277 } 278 279 static int atmel_i2s_prepare(struct snd_pcm_substream *substream, 280 struct snd_soc_dai *dai) 281 { 282 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 283 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 284 unsigned int rhr, sr = 0; 285 286 if (is_playback) { 287 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 288 if (sr & ATMEL_I2SC_SR_RXRDY) { 289 /* 290 * The RX Ready flag should not be set. However if here, 291 * we flush (read) the Receive Holding Register to start 292 * from a clean state. 293 */ 294 dev_dbg(dev->dev, "RXRDY is set\n"); 295 regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr); 296 } 297 } 298 299 return 0; 300 } 301 302 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs) 303 { 304 int i, best; 305 306 if (!dev->gclk || !dev->aclk) { 307 dev_err(dev->dev, "cannot generate the I2S Master Clock\n"); 308 return -EINVAL; 309 } 310 311 /* 312 * Find the best possible settings to generate the I2S Master Clock 313 * from the PLL Audio. 314 */ 315 dev->gck_param = NULL; 316 best = INT_MAX; 317 for (i = 0; i < ARRAY_SIZE(gck_params); ++i) { 318 const struct atmel_i2s_gck_param *gck_param = &gck_params[i]; 319 int val = abs(fs - gck_param->fs); 320 321 if (val < best) { 322 best = val; 323 dev->gck_param = gck_param; 324 } 325 } 326 327 return 0; 328 } 329 330 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream, 331 struct snd_pcm_hw_params *params, 332 struct snd_soc_dai *dai) 333 { 334 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 335 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 336 unsigned int mr = 0; 337 int ret; 338 339 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 340 case SND_SOC_DAIFMT_I2S: 341 mr |= ATMEL_I2SC_MR_FORMAT_I2S; 342 break; 343 344 default: 345 dev_err(dev->dev, "unsupported bus format\n"); 346 return -EINVAL; 347 } 348 349 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 350 case SND_SOC_DAIFMT_CBS_CFS: 351 /* codec is slave, so cpu is master */ 352 mr |= ATMEL_I2SC_MR_MODE_MASTER; 353 ret = atmel_i2s_get_gck_param(dev, params_rate(params)); 354 if (ret) 355 return ret; 356 break; 357 358 case SND_SOC_DAIFMT_CBM_CFM: 359 /* codec is master, so cpu is slave */ 360 mr |= ATMEL_I2SC_MR_MODE_SLAVE; 361 dev->gck_param = NULL; 362 break; 363 364 default: 365 dev_err(dev->dev, "unsupported master/slave mode\n"); 366 return -EINVAL; 367 } 368 369 switch (params_channels(params)) { 370 case 1: 371 if (is_playback) 372 mr |= ATMEL_I2SC_MR_TXMONO; 373 else 374 mr |= ATMEL_I2SC_MR_RXMONO; 375 break; 376 case 2: 377 break; 378 default: 379 dev_err(dev->dev, "unsupported number of audio channels\n"); 380 return -EINVAL; 381 } 382 383 switch (params_format(params)) { 384 case SNDRV_PCM_FORMAT_S8: 385 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS; 386 break; 387 388 case SNDRV_PCM_FORMAT_S16_LE: 389 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS; 390 break; 391 392 case SNDRV_PCM_FORMAT_S18_3LE: 393 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS; 394 break; 395 396 case SNDRV_PCM_FORMAT_S20_3LE: 397 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS; 398 break; 399 400 case SNDRV_PCM_FORMAT_S24_3LE: 401 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS; 402 break; 403 404 case SNDRV_PCM_FORMAT_S24_LE: 405 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS; 406 break; 407 408 case SNDRV_PCM_FORMAT_S32_LE: 409 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS; 410 break; 411 412 default: 413 dev_err(dev->dev, "unsupported size/endianness for audio samples\n"); 414 return -EINVAL; 415 } 416 417 return regmap_write(dev->regmap, ATMEL_I2SC_MR, mr); 418 } 419 420 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev, 421 bool enabled) 422 { 423 unsigned int mr, mr_mask; 424 unsigned long aclk_rate; 425 int ret; 426 427 mr = 0; 428 mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK | 429 ATMEL_I2SC_MR_IMCKFS_MASK | 430 ATMEL_I2SC_MR_IMCKMODE_MASK); 431 432 if (!enabled) { 433 /* Disable the I2S Master Clock generator. */ 434 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR, 435 ATMEL_I2SC_CR_CKDIS); 436 if (ret) 437 return ret; 438 439 /* Reset the I2S Master Clock generator settings. */ 440 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, 441 mr_mask, mr); 442 if (ret) 443 return ret; 444 445 /* Disable/unprepare the PMC generated clock. */ 446 clk_disable_unprepare(dev->gclk); 447 448 /* Disable/unprepare the PLL audio clock. */ 449 clk_disable_unprepare(dev->aclk); 450 return 0; 451 } 452 453 if (!dev->gck_param) 454 return -EINVAL; 455 456 aclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1); 457 458 /* Fist change the PLL audio clock frequency ... */ 459 ret = clk_set_rate(dev->aclk, aclk_rate); 460 if (ret) 461 return ret; 462 463 /* 464 * ... then set the PMC generated clock rate to the very same frequency 465 * to set the gclk parent to aclk. 466 */ 467 ret = clk_set_rate(dev->gclk, aclk_rate); 468 if (ret) 469 return ret; 470 471 /* Prepare and enable the PLL audio clock first ... */ 472 ret = clk_prepare_enable(dev->aclk); 473 if (ret) 474 return ret; 475 476 /* ... then prepare and enable the PMC generated clock. */ 477 ret = clk_prepare_enable(dev->gclk); 478 if (ret) 479 return ret; 480 481 /* Update the Mode Register to generate the I2S Master Clock. */ 482 mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv); 483 mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs); 484 mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK; 485 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr); 486 if (ret) 487 return ret; 488 489 /* Finally enable the I2S Master Clock generator. */ 490 return regmap_write(dev->regmap, ATMEL_I2SC_CR, 491 ATMEL_I2SC_CR_CKEN); 492 } 493 494 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 495 struct snd_soc_dai *dai) 496 { 497 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 498 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 499 bool is_master, mck_enabled; 500 unsigned int cr, mr; 501 int err; 502 503 switch (cmd) { 504 case SNDRV_PCM_TRIGGER_START: 505 case SNDRV_PCM_TRIGGER_RESUME: 506 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 507 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN; 508 mck_enabled = true; 509 break; 510 case SNDRV_PCM_TRIGGER_STOP: 511 case SNDRV_PCM_TRIGGER_SUSPEND: 512 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 513 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS; 514 mck_enabled = false; 515 break; 516 default: 517 return -EINVAL; 518 } 519 520 /* Read the Mode Register to retrieve the master/slave state. */ 521 err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr); 522 if (err) 523 return err; 524 is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER; 525 526 /* If master starts, enable the audio clock. */ 527 if (is_master && mck_enabled) 528 err = atmel_i2s_switch_mck_generator(dev, true); 529 if (err) 530 return err; 531 532 err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr); 533 if (err) 534 return err; 535 536 /* If master stops, disable the audio clock. */ 537 if (is_master && !mck_enabled) 538 err = atmel_i2s_switch_mck_generator(dev, false); 539 540 return err; 541 } 542 543 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = { 544 .prepare = atmel_i2s_prepare, 545 .trigger = atmel_i2s_trigger, 546 .hw_params = atmel_i2s_hw_params, 547 .set_fmt = atmel_i2s_set_dai_fmt, 548 }; 549 550 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai) 551 { 552 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 553 554 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture); 555 return 0; 556 } 557 558 static struct snd_soc_dai_driver atmel_i2s_dai = { 559 .probe = atmel_i2s_dai_probe, 560 .playback = { 561 .channels_min = 1, 562 .channels_max = 2, 563 .rates = ATMEL_I2S_RATES, 564 .formats = ATMEL_I2S_FORMATS, 565 }, 566 .capture = { 567 .channels_min = 1, 568 .channels_max = 2, 569 .rates = ATMEL_I2S_RATES, 570 .formats = ATMEL_I2S_FORMATS, 571 }, 572 .ops = &atmel_i2s_dai_ops, 573 .symmetric_rates = 1, 574 }; 575 576 static const struct snd_soc_component_driver atmel_i2s_component = { 577 .name = "atmel-i2s", 578 }; 579 580 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev, 581 struct device_node *np) 582 { 583 struct clk *muxclk; 584 int err; 585 586 if (!dev->gclk) 587 return 0; 588 589 /* muxclk is optional, so we return error for probe defer only */ 590 muxclk = devm_clk_get(dev->dev, "muxclk"); 591 if (IS_ERR(muxclk)) { 592 err = PTR_ERR(muxclk); 593 if (err == -EPROBE_DEFER) 594 return -EPROBE_DEFER; 595 dev_warn(dev->dev, 596 "failed to get the I2S clock control: %d\n", err); 597 return 0; 598 } 599 600 return clk_set_parent(muxclk, dev->gclk); 601 } 602 603 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = { 604 .mck_init = atmel_i2s_sama5d2_mck_init, 605 }; 606 607 static const struct of_device_id atmel_i2s_dt_ids[] = { 608 { 609 .compatible = "atmel,sama5d2-i2s", 610 .data = (void *)&atmel_i2s_sama5d2_caps, 611 }, 612 613 { /* sentinel */ } 614 }; 615 616 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids); 617 618 static int atmel_i2s_probe(struct platform_device *pdev) 619 { 620 struct device_node *np = pdev->dev.of_node; 621 const struct of_device_id *match; 622 struct atmel_i2s_dev *dev; 623 struct resource *mem; 624 struct regmap *regmap; 625 void __iomem *base; 626 int irq; 627 int err = -ENXIO; 628 unsigned int pcm_flags = 0; 629 unsigned int version; 630 631 /* Get memory for driver data. */ 632 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 633 if (!dev) 634 return -ENOMEM; 635 636 /* Get hardware capabilities. */ 637 match = of_match_node(atmel_i2s_dt_ids, np); 638 if (match) 639 dev->caps = match->data; 640 641 /* Map I/O registers. */ 642 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 643 base = devm_ioremap_resource(&pdev->dev, mem); 644 if (IS_ERR(base)) 645 return PTR_ERR(base); 646 647 regmap = devm_regmap_init_mmio(&pdev->dev, base, 648 &atmel_i2s_regmap_config); 649 if (IS_ERR(regmap)) 650 return PTR_ERR(regmap); 651 652 /* Request IRQ. */ 653 irq = platform_get_irq(pdev, 0); 654 if (irq < 0) 655 return irq; 656 657 err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, 658 dev_name(&pdev->dev), dev); 659 if (err) 660 return err; 661 662 /* Get the peripheral clock. */ 663 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 664 if (IS_ERR(dev->pclk)) { 665 err = PTR_ERR(dev->pclk); 666 dev_err(&pdev->dev, 667 "failed to get the peripheral clock: %d\n", err); 668 return err; 669 } 670 671 /* Get audio clocks to generate the I2S Master Clock (I2S_MCK) */ 672 dev->aclk = devm_clk_get(&pdev->dev, "aclk"); 673 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 674 if (IS_ERR(dev->aclk) && IS_ERR(dev->gclk)) { 675 if (PTR_ERR(dev->aclk) == -EPROBE_DEFER || 676 PTR_ERR(dev->gclk) == -EPROBE_DEFER) 677 return -EPROBE_DEFER; 678 /* Master Mode not supported */ 679 dev->aclk = NULL; 680 dev->gclk = NULL; 681 } else if (IS_ERR(dev->gclk)) { 682 err = PTR_ERR(dev->gclk); 683 dev_err(&pdev->dev, 684 "failed to get the PMC generated clock: %d\n", err); 685 return err; 686 } else if (IS_ERR(dev->aclk)) { 687 err = PTR_ERR(dev->aclk); 688 dev_err(&pdev->dev, 689 "failed to get the PLL audio clock: %d\n", err); 690 return err; 691 } 692 693 dev->dev = &pdev->dev; 694 dev->regmap = regmap; 695 platform_set_drvdata(pdev, dev); 696 697 /* Do hardware specific settings to initialize I2S_MCK generator */ 698 if (dev->caps && dev->caps->mck_init) { 699 err = dev->caps->mck_init(dev, np); 700 if (err) 701 return err; 702 } 703 704 /* Enable the peripheral clock. */ 705 err = clk_prepare_enable(dev->pclk); 706 if (err) 707 return err; 708 709 /* Get IP version. */ 710 regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version); 711 dev_info(&pdev->dev, "hw version: %#x\n", version); 712 713 /* Enable error interrupts. */ 714 regmap_write(dev->regmap, ATMEL_I2SC_IER, 715 ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR); 716 717 err = devm_snd_soc_register_component(&pdev->dev, 718 &atmel_i2s_component, 719 &atmel_i2s_dai, 1); 720 if (err) { 721 dev_err(&pdev->dev, "failed to register DAI: %d\n", err); 722 clk_disable_unprepare(dev->pclk); 723 return err; 724 } 725 726 /* Prepare DMA config. */ 727 dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR; 728 dev->playback.maxburst = 1; 729 dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR; 730 dev->capture.maxburst = 1; 731 732 if (of_property_match_string(np, "dma-names", "rx-tx") == 0) 733 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX; 734 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags); 735 if (err) { 736 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 737 clk_disable_unprepare(dev->pclk); 738 return err; 739 } 740 741 return 0; 742 } 743 744 static int atmel_i2s_remove(struct platform_device *pdev) 745 { 746 struct atmel_i2s_dev *dev = platform_get_drvdata(pdev); 747 748 clk_disable_unprepare(dev->pclk); 749 750 return 0; 751 } 752 753 static struct platform_driver atmel_i2s_driver = { 754 .driver = { 755 .name = "atmel_i2s", 756 .of_match_table = of_match_ptr(atmel_i2s_dt_ids), 757 }, 758 .probe = atmel_i2s_probe, 759 .remove = atmel_i2s_remove, 760 }; 761 module_platform_driver(atmel_i2s_driver); 762 763 MODULE_DESCRIPTION("Atmel I2S Controller driver"); 764 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 765 MODULE_LICENSE("GPL v2"); 766