1 /* 2 * Driver for Atmel I2S controller 3 * 4 * Copyright (C) 2015 Atmel Corporation 5 * 6 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/init.h> 22 #include <linux/module.h> 23 #include <linux/device.h> 24 #include <linux/slab.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 #include <linux/clk.h> 28 #include <linux/mfd/syscon.h> 29 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/initval.h> 34 #include <sound/soc.h> 35 #include <sound/dmaengine_pcm.h> 36 37 #define ATMEL_I2SC_MAX_TDM_CHANNELS 8 38 39 /* 40 * ---- I2S Controller Register map ---- 41 */ 42 #define ATMEL_I2SC_CR 0x0000 /* Control Register */ 43 #define ATMEL_I2SC_MR 0x0004 /* Mode Register */ 44 #define ATMEL_I2SC_SR 0x0008 /* Status Register */ 45 #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */ 46 #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */ 47 #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */ 48 #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */ 49 #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */ 50 #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */ 51 #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */ 52 #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */ 53 54 /* 55 * ---- Control Register (Write-only) ---- 56 */ 57 #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */ 58 #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */ 59 #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ 60 #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ 61 #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */ 62 #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */ 63 #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */ 64 65 /* 66 * ---- Mode Register (Read/Write) ---- 67 */ 68 #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0) 69 #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0) 70 #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0) 71 72 #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2) 73 #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2) 74 #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2) 75 #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2) 76 #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2) 77 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2) 78 #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2) 79 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2) 80 #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2) 81 82 #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6) 83 #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6) 84 #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */ 85 #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6) 86 #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6) 87 88 /* Left audio samples duplicated to right audio channel */ 89 #define ATMEL_I2SC_MR_RXMONO BIT(8) 90 91 /* Receiver uses one DMA channel ... */ 92 #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9) 93 #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */ 94 #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */ 95 96 /* I2SDO output of I2SC is internally connected to I2SDI input */ 97 #define ATMEL_I2SC_MR_RXLOOP BIT(10) 98 99 /* Left audio samples duplicated to right audio channel */ 100 #define ATMEL_I2SC_MR_TXMONO BIT(12) 101 102 /* Transmitter uses one DMA channel ... */ 103 #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13) 104 #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */ 105 #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */ 106 107 /* x sample transmitted when underrun */ 108 #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14) 109 #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */ 110 #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */ 111 112 /* Audio Clock to I2SC Master Clock ratio */ 113 #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16) 114 #define ATMEL_I2SC_MR_IMCKDIV(div) \ 115 (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK) 116 117 /* Master Clock to fs ratio */ 118 #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24) 119 #define ATMEL_I2SC_MR_IMCKFS(fs) \ 120 (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK) 121 122 /* Master Clock mode */ 123 #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30) 124 /* 0: No master clock generated (selected clock drives I2SCK pin) */ 125 #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30) 126 /* 1: master clock generated (internally generated clock drives I2SMCK pin) */ 127 #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30) 128 129 /* Slot Width */ 130 /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */ 131 /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */ 132 #define ATMEL_I2SC_MR_IWS BIT(31) 133 134 /* 135 * ---- Status Registers ---- 136 */ 137 #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */ 138 #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */ 139 #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */ 140 141 #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */ 142 #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */ 143 #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */ 144 145 /* Receive Overrun Channel */ 146 #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8) 147 #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8)) 148 149 /* Transmit Underrun Channel */ 150 #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20) 151 #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20)) 152 153 /* 154 * ---- Interrupt Enable/Disable/Mask Registers ---- 155 */ 156 #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY 157 #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR 158 #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY 159 #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR 160 161 static const struct regmap_config atmel_i2s_regmap_config = { 162 .reg_bits = 32, 163 .reg_stride = 4, 164 .val_bits = 32, 165 .max_register = ATMEL_I2SC_VERSION, 166 }; 167 168 struct atmel_i2s_gck_param { 169 int fs; 170 unsigned long mck; 171 int imckdiv; 172 int imckfs; 173 }; 174 175 #define I2S_MCK_12M288 12288000UL 176 #define I2S_MCK_11M2896 11289600UL 177 178 /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ 179 static const struct atmel_i2s_gck_param gck_params[] = { 180 /* mck = 12.288MHz */ 181 { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */ 182 { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ 183 { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ 184 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ 185 { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */ 186 { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */ 187 { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */ 188 {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */ 189 190 /* mck = 11.2896MHz */ 191 { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */ 192 { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */ 193 { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */ 194 { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */ 195 {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */ 196 }; 197 198 struct atmel_i2s_dev; 199 200 struct atmel_i2s_caps { 201 int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np); 202 }; 203 204 struct atmel_i2s_dev { 205 struct device *dev; 206 struct regmap *regmap; 207 struct clk *pclk; 208 struct clk *gclk; 209 struct snd_dmaengine_dai_dma_data playback; 210 struct snd_dmaengine_dai_dma_data capture; 211 unsigned int fmt; 212 const struct atmel_i2s_gck_param *gck_param; 213 const struct atmel_i2s_caps *caps; 214 }; 215 216 static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id) 217 { 218 struct atmel_i2s_dev *dev = dev_id; 219 unsigned int sr, imr, pending, ch, mask; 220 irqreturn_t ret = IRQ_NONE; 221 222 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 223 regmap_read(dev->regmap, ATMEL_I2SC_IMR, &imr); 224 pending = sr & imr; 225 226 if (!pending) 227 return IRQ_NONE; 228 229 if (pending & ATMEL_I2SC_INT_RXOR) { 230 mask = ATMEL_I2SC_SR_RXOR; 231 232 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 233 if (sr & ATMEL_I2SC_SR_RXORCH(ch)) { 234 mask |= ATMEL_I2SC_SR_RXORCH(ch); 235 dev_err(dev->dev, 236 "RX overrun on channel %d\n", ch); 237 } 238 } 239 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 240 ret = IRQ_HANDLED; 241 } 242 243 if (pending & ATMEL_I2SC_INT_TXUR) { 244 mask = ATMEL_I2SC_SR_TXUR; 245 246 for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { 247 if (sr & ATMEL_I2SC_SR_TXURCH(ch)) { 248 mask |= ATMEL_I2SC_SR_TXURCH(ch); 249 dev_err(dev->dev, 250 "TX underrun on channel %d\n", ch); 251 } 252 } 253 regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); 254 ret = IRQ_HANDLED; 255 } 256 257 return ret; 258 } 259 260 #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000 261 262 #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 263 SNDRV_PCM_FMTBIT_S16_LE | \ 264 SNDRV_PCM_FMTBIT_S18_3LE | \ 265 SNDRV_PCM_FMTBIT_S20_3LE | \ 266 SNDRV_PCM_FMTBIT_S24_3LE | \ 267 SNDRV_PCM_FMTBIT_S24_LE | \ 268 SNDRV_PCM_FMTBIT_S32_LE) 269 270 static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 271 { 272 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 273 274 dev->fmt = fmt; 275 return 0; 276 } 277 278 static int atmel_i2s_prepare(struct snd_pcm_substream *substream, 279 struct snd_soc_dai *dai) 280 { 281 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 282 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 283 unsigned int rhr, sr = 0; 284 285 if (is_playback) { 286 regmap_read(dev->regmap, ATMEL_I2SC_SR, &sr); 287 if (sr & ATMEL_I2SC_SR_RXRDY) { 288 /* 289 * The RX Ready flag should not be set. However if here, 290 * we flush (read) the Receive Holding Register to start 291 * from a clean state. 292 */ 293 dev_dbg(dev->dev, "RXRDY is set\n"); 294 regmap_read(dev->regmap, ATMEL_I2SC_RHR, &rhr); 295 } 296 } 297 298 return 0; 299 } 300 301 static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs) 302 { 303 int i, best; 304 305 if (!dev->gclk) { 306 dev_err(dev->dev, "cannot generate the I2S Master Clock\n"); 307 return -EINVAL; 308 } 309 310 /* 311 * Find the best possible settings to generate the I2S Master Clock 312 * from the PLL Audio. 313 */ 314 dev->gck_param = NULL; 315 best = INT_MAX; 316 for (i = 0; i < ARRAY_SIZE(gck_params); ++i) { 317 const struct atmel_i2s_gck_param *gck_param = &gck_params[i]; 318 int val = abs(fs - gck_param->fs); 319 320 if (val < best) { 321 best = val; 322 dev->gck_param = gck_param; 323 } 324 } 325 326 return 0; 327 } 328 329 static int atmel_i2s_hw_params(struct snd_pcm_substream *substream, 330 struct snd_pcm_hw_params *params, 331 struct snd_soc_dai *dai) 332 { 333 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 334 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 335 unsigned int mr = 0; 336 int ret; 337 338 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 339 case SND_SOC_DAIFMT_I2S: 340 mr |= ATMEL_I2SC_MR_FORMAT_I2S; 341 break; 342 343 default: 344 dev_err(dev->dev, "unsupported bus format\n"); 345 return -EINVAL; 346 } 347 348 switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { 349 case SND_SOC_DAIFMT_CBS_CFS: 350 /* codec is slave, so cpu is master */ 351 mr |= ATMEL_I2SC_MR_MODE_MASTER; 352 ret = atmel_i2s_get_gck_param(dev, params_rate(params)); 353 if (ret) 354 return ret; 355 break; 356 357 case SND_SOC_DAIFMT_CBM_CFM: 358 /* codec is master, so cpu is slave */ 359 mr |= ATMEL_I2SC_MR_MODE_SLAVE; 360 dev->gck_param = NULL; 361 break; 362 363 default: 364 dev_err(dev->dev, "unsupported master/slave mode\n"); 365 return -EINVAL; 366 } 367 368 switch (params_channels(params)) { 369 case 1: 370 if (is_playback) 371 mr |= ATMEL_I2SC_MR_TXMONO; 372 else 373 mr |= ATMEL_I2SC_MR_RXMONO; 374 break; 375 case 2: 376 break; 377 default: 378 dev_err(dev->dev, "unsupported number of audio channels\n"); 379 return -EINVAL; 380 } 381 382 switch (params_format(params)) { 383 case SNDRV_PCM_FORMAT_S8: 384 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS; 385 break; 386 387 case SNDRV_PCM_FORMAT_S16_LE: 388 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS; 389 break; 390 391 case SNDRV_PCM_FORMAT_S18_3LE: 392 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS; 393 break; 394 395 case SNDRV_PCM_FORMAT_S20_3LE: 396 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS; 397 break; 398 399 case SNDRV_PCM_FORMAT_S24_3LE: 400 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS; 401 break; 402 403 case SNDRV_PCM_FORMAT_S24_LE: 404 mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS; 405 break; 406 407 case SNDRV_PCM_FORMAT_S32_LE: 408 mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS; 409 break; 410 411 default: 412 dev_err(dev->dev, "unsupported size/endianness for audio samples\n"); 413 return -EINVAL; 414 } 415 416 return regmap_write(dev->regmap, ATMEL_I2SC_MR, mr); 417 } 418 419 static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev, 420 bool enabled) 421 { 422 unsigned int mr, mr_mask; 423 unsigned long gclk_rate; 424 int ret; 425 426 mr = 0; 427 mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK | 428 ATMEL_I2SC_MR_IMCKFS_MASK | 429 ATMEL_I2SC_MR_IMCKMODE_MASK); 430 431 if (!enabled) { 432 /* Disable the I2S Master Clock generator. */ 433 ret = regmap_write(dev->regmap, ATMEL_I2SC_CR, 434 ATMEL_I2SC_CR_CKDIS); 435 if (ret) 436 return ret; 437 438 /* Reset the I2S Master Clock generator settings. */ 439 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, 440 mr_mask, mr); 441 if (ret) 442 return ret; 443 444 /* Disable/unprepare the PMC generated clock. */ 445 clk_disable_unprepare(dev->gclk); 446 447 return 0; 448 } 449 450 if (!dev->gck_param) 451 return -EINVAL; 452 453 gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1); 454 455 ret = clk_set_rate(dev->gclk, gclk_rate); 456 if (ret) 457 return ret; 458 459 ret = clk_prepare_enable(dev->gclk); 460 if (ret) 461 return ret; 462 463 /* Update the Mode Register to generate the I2S Master Clock. */ 464 mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv); 465 mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs); 466 mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK; 467 ret = regmap_update_bits(dev->regmap, ATMEL_I2SC_MR, mr_mask, mr); 468 if (ret) 469 return ret; 470 471 /* Finally enable the I2S Master Clock generator. */ 472 return regmap_write(dev->regmap, ATMEL_I2SC_CR, 473 ATMEL_I2SC_CR_CKEN); 474 } 475 476 static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 477 struct snd_soc_dai *dai) 478 { 479 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 480 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 481 bool is_master, mck_enabled; 482 unsigned int cr, mr; 483 int err; 484 485 switch (cmd) { 486 case SNDRV_PCM_TRIGGER_START: 487 case SNDRV_PCM_TRIGGER_RESUME: 488 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 489 cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN; 490 mck_enabled = true; 491 break; 492 case SNDRV_PCM_TRIGGER_STOP: 493 case SNDRV_PCM_TRIGGER_SUSPEND: 494 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 495 cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS; 496 mck_enabled = false; 497 break; 498 default: 499 return -EINVAL; 500 } 501 502 /* Read the Mode Register to retrieve the master/slave state. */ 503 err = regmap_read(dev->regmap, ATMEL_I2SC_MR, &mr); 504 if (err) 505 return err; 506 is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER; 507 508 /* If master starts, enable the audio clock. */ 509 if (is_master && mck_enabled) 510 err = atmel_i2s_switch_mck_generator(dev, true); 511 if (err) 512 return err; 513 514 err = regmap_write(dev->regmap, ATMEL_I2SC_CR, cr); 515 if (err) 516 return err; 517 518 /* If master stops, disable the audio clock. */ 519 if (is_master && !mck_enabled) 520 err = atmel_i2s_switch_mck_generator(dev, false); 521 522 return err; 523 } 524 525 static const struct snd_soc_dai_ops atmel_i2s_dai_ops = { 526 .prepare = atmel_i2s_prepare, 527 .trigger = atmel_i2s_trigger, 528 .hw_params = atmel_i2s_hw_params, 529 .set_fmt = atmel_i2s_set_dai_fmt, 530 }; 531 532 static int atmel_i2s_dai_probe(struct snd_soc_dai *dai) 533 { 534 struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 535 536 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture); 537 return 0; 538 } 539 540 static struct snd_soc_dai_driver atmel_i2s_dai = { 541 .probe = atmel_i2s_dai_probe, 542 .playback = { 543 .channels_min = 1, 544 .channels_max = 2, 545 .rates = ATMEL_I2S_RATES, 546 .formats = ATMEL_I2S_FORMATS, 547 }, 548 .capture = { 549 .channels_min = 1, 550 .channels_max = 2, 551 .rates = ATMEL_I2S_RATES, 552 .formats = ATMEL_I2S_FORMATS, 553 }, 554 .ops = &atmel_i2s_dai_ops, 555 .symmetric_rates = 1, 556 }; 557 558 static const struct snd_soc_component_driver atmel_i2s_component = { 559 .name = "atmel-i2s", 560 }; 561 562 static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev, 563 struct device_node *np) 564 { 565 struct clk *muxclk; 566 int err; 567 568 if (!dev->gclk) 569 return 0; 570 571 /* muxclk is optional, so we return error for probe defer only */ 572 muxclk = devm_clk_get(dev->dev, "muxclk"); 573 if (IS_ERR(muxclk)) { 574 err = PTR_ERR(muxclk); 575 if (err == -EPROBE_DEFER) 576 return -EPROBE_DEFER; 577 dev_warn(dev->dev, 578 "failed to get the I2S clock control: %d\n", err); 579 return 0; 580 } 581 582 return clk_set_parent(muxclk, dev->gclk); 583 } 584 585 static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = { 586 .mck_init = atmel_i2s_sama5d2_mck_init, 587 }; 588 589 static const struct of_device_id atmel_i2s_dt_ids[] = { 590 { 591 .compatible = "atmel,sama5d2-i2s", 592 .data = (void *)&atmel_i2s_sama5d2_caps, 593 }, 594 595 { /* sentinel */ } 596 }; 597 598 MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids); 599 600 static int atmel_i2s_probe(struct platform_device *pdev) 601 { 602 struct device_node *np = pdev->dev.of_node; 603 const struct of_device_id *match; 604 struct atmel_i2s_dev *dev; 605 struct resource *mem; 606 struct regmap *regmap; 607 void __iomem *base; 608 int irq; 609 int err = -ENXIO; 610 unsigned int pcm_flags = 0; 611 unsigned int version; 612 613 /* Get memory for driver data. */ 614 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 615 if (!dev) 616 return -ENOMEM; 617 618 /* Get hardware capabilities. */ 619 match = of_match_node(atmel_i2s_dt_ids, np); 620 if (match) 621 dev->caps = match->data; 622 623 /* Map I/O registers. */ 624 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 625 base = devm_ioremap_resource(&pdev->dev, mem); 626 if (IS_ERR(base)) 627 return PTR_ERR(base); 628 629 regmap = devm_regmap_init_mmio(&pdev->dev, base, 630 &atmel_i2s_regmap_config); 631 if (IS_ERR(regmap)) 632 return PTR_ERR(regmap); 633 634 /* Request IRQ. */ 635 irq = platform_get_irq(pdev, 0); 636 if (irq < 0) 637 return irq; 638 639 err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, 640 dev_name(&pdev->dev), dev); 641 if (err) 642 return err; 643 644 /* Get the peripheral clock. */ 645 dev->pclk = devm_clk_get(&pdev->dev, "pclk"); 646 if (IS_ERR(dev->pclk)) { 647 err = PTR_ERR(dev->pclk); 648 dev_err(&pdev->dev, 649 "failed to get the peripheral clock: %d\n", err); 650 return err; 651 } 652 653 /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */ 654 dev->gclk = devm_clk_get(&pdev->dev, "gclk"); 655 if (IS_ERR(dev->gclk)) { 656 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER) 657 return -EPROBE_DEFER; 658 /* Master Mode not supported */ 659 dev->gclk = NULL; 660 } 661 dev->dev = &pdev->dev; 662 dev->regmap = regmap; 663 platform_set_drvdata(pdev, dev); 664 665 /* Do hardware specific settings to initialize I2S_MCK generator */ 666 if (dev->caps && dev->caps->mck_init) { 667 err = dev->caps->mck_init(dev, np); 668 if (err) 669 return err; 670 } 671 672 /* Enable the peripheral clock. */ 673 err = clk_prepare_enable(dev->pclk); 674 if (err) 675 return err; 676 677 /* Get IP version. */ 678 regmap_read(dev->regmap, ATMEL_I2SC_VERSION, &version); 679 dev_info(&pdev->dev, "hw version: %#x\n", version); 680 681 /* Enable error interrupts. */ 682 regmap_write(dev->regmap, ATMEL_I2SC_IER, 683 ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR); 684 685 err = devm_snd_soc_register_component(&pdev->dev, 686 &atmel_i2s_component, 687 &atmel_i2s_dai, 1); 688 if (err) { 689 dev_err(&pdev->dev, "failed to register DAI: %d\n", err); 690 clk_disable_unprepare(dev->pclk); 691 return err; 692 } 693 694 /* Prepare DMA config. */ 695 dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR; 696 dev->playback.maxburst = 1; 697 dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR; 698 dev->capture.maxburst = 1; 699 700 if (of_property_match_string(np, "dma-names", "rx-tx") == 0) 701 pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX; 702 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, pcm_flags); 703 if (err) { 704 dev_err(&pdev->dev, "failed to register PCM: %d\n", err); 705 clk_disable_unprepare(dev->pclk); 706 return err; 707 } 708 709 return 0; 710 } 711 712 static int atmel_i2s_remove(struct platform_device *pdev) 713 { 714 struct atmel_i2s_dev *dev = platform_get_drvdata(pdev); 715 716 clk_disable_unprepare(dev->pclk); 717 718 return 0; 719 } 720 721 static struct platform_driver atmel_i2s_driver = { 722 .driver = { 723 .name = "atmel_i2s", 724 .of_match_table = of_match_ptr(atmel_i2s_dt_ids), 725 }, 726 .probe = atmel_i2s_probe, 727 .remove = atmel_i2s_remove, 728 }; 729 module_platform_driver(atmel_i2s_driver); 730 731 MODULE_DESCRIPTION("Atmel I2S Controller driver"); 732 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 733 MODULE_LICENSE("GPL v2"); 734